Oxide semiconductor, method for manufacturing same, p-type oxide semiconductor, and power device

Abstract

The present invention relates to a method for manufacturing an oxide semiconductor, the method comprising: ion-implanting a transition metal ion in the vicinity of the surface of a gallium oxide-containing semiconductor layer; and heat-treating the ion-implanted semiconductor layer in an oxygen-containing atmosphere.

Description

Oxide semiconductor and manufacturing method thereof, p-type oxide semiconductor, and power device

[0001] The present invention relates to an oxide semiconductor and a method for producing the same, a p-type oxide semiconductor, and a power device.

[0002] Gallium oxide has a wide band gap and high breakdown voltage, making it a promising semiconductor material for power devices.

[0003] Patent Document 1 describes a semiconductor element having a structure in which an n-type gallium oxide layer, a p-type nickel oxide layer, and an electrode layer are stacked.

[0004] Japanese Patent Application Publication No. 2023-10539

[0005] Many semiconductor elements require a p-type region in their structure. For example, a p-type region is necessary to realize a pin diode, a FET (field effect transistor), a bipolar transistor, etc. However, it is difficult to make gallium oxide p-type. Various methods for forming p-type gallium oxide have been proposed, but each method has various issues and has not yet been put to practical use.

[0006] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing an oxide semiconductor that can form a p-type layer in a semiconductor layer made of a gallium oxide-based semiconductor, and also to provide an oxide semiconductor having a semiconductor layer made of a gallium oxide-based semiconductor and a p-type layer.

[0007] One aspect of the present invention is as follows: [1] A method for producing an oxide semiconductor, comprising: implanting transition metal ions into a surface vicinity of a semiconductor layer containing gallium oxide; and heat-treating the ion-implanted semiconductor layer in an oxygen-containing atmosphere. [2] The method for producing an oxide semiconductor according to [1], wherein the heat treatment further comprises forming a p-type layer made of a p-type transition metal oxide near the surface of the semiconductor layer, and forming an intermediate layer between the semiconductor layer and the p-type layer, the intermediate layer containing a mixed crystal of the gallium oxide and the transition metal oxide. [3] The method for producing an oxide semiconductor according to [1] or [2], wherein the transition metal includes one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu. [4] The method for producing an oxide semiconductor according to any one of [1] to [3], wherein the transition metal includes Ni. [5] The method for producing an oxide semiconductor according to any one of [1] to [4], wherein the heat treatment is performed by rapid thermal annealing or annealing. [6] The method for producing an oxide semiconductor according to any one of [1] to [4], wherein plasma is generated using an oxygen-containing gas to radicalize oxygen, and the heat treatment is performed in the oxygen radicals that have been formed. [7] The method for producing an oxide semiconductor according to any one of [1] to [4], wherein the heat treatment includes a first heat treatment in which plasma is generated using an oxygen-containing gas to radicalize oxygen, and the heat treatment is performed in the oxygen radicals that have been formed, and a second heat treatment by rapid thermal annealing or annealing after the first heat treatment.

[0008] Other aspects of the present invention are as follows. [8] An oxide semiconductor comprising: a semiconductor layer containing n-type or undoped gallium oxide; a p-type layer located on the semiconductor layer and being an oxide of a transition metal and exhibiting p-type conductivity; and an intermediate layer located between the semiconductor layer and the p-type layer and containing a mixed crystal of the gallium oxide and an oxide of the transition metal. [9] The oxide semiconductor according to [8], wherein the transition metal includes one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu.

[10] The oxide semiconductor according to [8] or [9], wherein the transition metal includes Ni.

[0009] Further aspects of the present invention are as follows.

[11] A p-type oxide semiconductor containing a mixed crystal of gallium oxide and an oxide of a transition metal.

[12] The p-type oxide semiconductor according to

[11] , wherein the transition metal includes one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu.

[13] The p-type oxide semiconductor according to

[11] or

[12] , wherein the transition metal includes Ni.

[14] A power device having at least one semiconductor selected from the group consisting of the oxide semiconductor according to any one of [8] to

[10] and the p-type oxide semiconductor according to any one of

[11] to

[13] .

[0010] According to the above aspect, it is possible to provide a method for manufacturing an oxide semiconductor that can form a p-type layer on a semiconductor layer containing gallium oxide, and also to provide a new oxide semiconductor, a p-type oxide semiconductor, and a power device.

[0011] FIG. 1 is a diagram illustrating a method for manufacturing an oxide semiconductor according to Embodiment 1, and (a) to (c) of FIG. 1 are diagrams illustrating the layer configuration of a semiconductor layer in each step. FIG. 2 is a diagram illustrating the method for manufacturing an oxide semiconductor according to Embodiment 1, and is a flowchart illustrating each step. FIG. 3 is a diagram illustrating the IV characteristics of a semiconductor layer. FIG. 4 is a graph illustrating the IV characteristics of a substrate before ion implantation. FIG. 5 is a graph illustrating the IV characteristics of a substrate after ion implantation and before heat treatment. FIG. 6 is a graph illustrating the IV characteristics of a substrate after ion implantation and heat treatment by RTA. FIG. 7 is a graph illustrating the IV characteristics of a substrate after ion implantation and heat treatment by MBE. FIG. 8 is a graph illustrating the IV characteristics of Examples 3 to 5, where FIG. 8(a) is the reverse characteristic (Vr-Ir) for Example 3, FIG. 8(b) is the reverse characteristic (Vr-Ir) for Example 4, and FIG. 8(c) is the reverse characteristic (Vr-Ir) for Example 5. FIG. 9 is a graph showing the IV characteristics of Examples 3 to 5, where FIG. 9(a) shows the forward characteristics (Vf-If) for Example 3, FIG. 9(b) shows the forward characteristics (Vf-If) for Example 4, and FIG. 9(c) shows the forward characteristics (Vf-If) for Example 5.

[0012] The method for manufacturing an oxide semiconductor according to this embodiment includes an ion implantation step of implanting transition metal ions into the vicinity of the surface of a semiconductor layer containing gallium oxide, and a heat treatment step of heat treating the semiconductor layer implanted in the ion implantation step in an atmosphere containing oxygen.

[0013] The heat treatment step may be a step of forming a p-type layer made of a p-type transition metal oxide near the surface of the semiconductor layer, and further forming an intermediate layer containing a mixed crystal of gallium oxide and a transition metal oxide between the semiconductor layer and the p-type layer.

[0014] The transition metal may include one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu, and the transition metal may particularly include Ni.

[0015] The heat treatment step may be performed by rapid thermal annealing (RTA) or conventional annealing, or may be performed by rapid thermal annealing. Unlike conventional annealing, rapid thermal annealing is a method of rapid heating by infrared irradiation, and the temperature increase rate is, for example, 45°C / sec or higher. The temperature decrease rate after RTA may be 0.5°C / sec to 3.0°C / sec, preferably 1.0°C / sec to 2.0°C / sec. The heat treatment step may also be performed in the oxygen radicals generated by generating plasma using an oxygen-containing gas to radicalize oxygen. The heat treatment step may also be a combination of the above methods. Specifically, the heat treatment step preferably includes a first heat treatment step in which plasma is generated using an oxygen-containing gas to radicalize oxygen and the first heat treatment step is performed in the oxygen radicals generated by the first heat treatment step, and a second heat treatment step by rapid thermal annealing or annealing after the first heat treatment step. It is more preferable that the second heat treatment step be performed by rapid thermal annealing.

[0016] The oxide semiconductor according to this embodiment includes a semiconductor layer containing n-type or undoped gallium oxide, a p-type layer located on the semiconductor layer and made of a transition metal oxide, and exhibiting p-type conductivity, and an intermediate layer located between the semiconductor layer and the p-type layer and containing a mixed crystal of gallium oxide and a transition metal oxide.

[0017] In the oxide semiconductor, the transition metal may include one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu. The transition metal may particularly include Ni.

[0018] The p-type oxide semiconductor according to this embodiment contains a mixed crystal of gallium oxide and an oxide of a transition metal.

[0019] In the p-type oxide semiconductor, the transition metal may include one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu. The transition metal may particularly include Ni.

[0020] 1 and 2 are diagrams illustrating a method for manufacturing an oxide semiconductor according to embodiment 1. Fig. 1 is a diagram schematically illustrating the layer structure of a semiconductor layer in each step of the manufacturing process. Fig. 2 is a flowchart illustrating the manufacturing process.

[0021] The ion implantation step is a step of implanting ions of a transition metal into the vicinity of the surface of a semiconductor layer containing gallium oxide. ２ O ３ A semiconductor layer 10 made of a gallium oxide-based semiconductor is prepared. The semiconductor layer 10 is not limited to gallium oxide, and may be any gallium oxide-based semiconductor in which a portion of the gallium is replaced with aluminum, indium, or the like. The gallium oxide is preferably n-type or semi-insulating. Here, the n-type impurity is, for example, Sn or Si. The n-type impurity concentration may be any concentration, for example, 1×10 １３ ~1 x 10 ２０ / cm ３ The semiconductor layer 10 may be undoped.

[0022] The semiconductor layer 10 may be a substrate itself, or may be a layer grown on a growth substrate by a method such as CVD (Chemical Vapor Deposition), MOCVD (Metal Organic Chemical Vapor Deposition), or MBE (Molecular Beam Epitaxy). Examples of the growth substrate include sapphire, gallium oxide, gallium nitride, aluminum nitride, and indium nitride. The thickness of the semiconductor layer 10 may be any desired value. For example, the thickness is preferably 0.1 to 50 μm, more preferably 0.5 to 50 μm, even more preferably 0.8 to 30 μm, and particularly preferably 1 to 20 μm. From the viewpoint of application to power devices and the like, the thickness of the semiconductor layer 10 is preferably 0.1 μm or more, more preferably 0.5 μm or more, even more preferably 0.8 μm or more, and particularly preferably 1 μm or more. Although there is no particular upper limit, from the viewpoint of the film formation rate and film quality, the thickness of the semiconductor layer 10 is preferably 50 μm or less, more preferably 30 μm or less, and even more preferably 20 μm or less. The thickness can be measured using a scanning electron microscope or the like.

[0023] The crystalline phase of the gallium oxide in the semiconductor layer 10 is arbitrary. Five types of crystalline phases of gallium oxide are known: α-type, β-type, γ-type, δ-type, and ε-type, and any of them may be used. However, from the viewpoint of ease of formation, α-type and β-type are preferred. Furthermore, the plane orientation of the principal surface of the semiconductor layer 10 may also be arbitrary. For example, a β-type gallium oxide substrate whose principal surface is the (010) plane, (001) plane, or (-201) plane may be used.

[0024] Next, transition metal ions, such as Ni (nickel) ions, are implanted near the surface of the semiconductor layer 10 (step S1 in FIG. 2). The peak position where the Ni ion concentration is maximum may be any position near the surface of the semiconductor layer 10. The vicinity of the surface of the semiconductor layer 10 may be, for example, the outermost surface of the semiconductor layer 10, a position at a depth of 0 to 10 μm from the outermost surface, or a position at a depth of 20 nm to 10 μm from the outermost surface. The vicinity of the surface may also be a position from the surface of the semiconductor layer 10 to a depth of ½ or less of the thickness of the semiconductor layer 10. The half-width of the peak of the implanted ion concentration is, for example, 20 to 200 nm.

[0025] The implantation energy and dose of the ion implantation may be set so that the peak position, half width, and Ni concentration at the peak of the ion implantation are within the above ranges. For example, the implantation energy is 100 eV to 10 MeV, and the dose is 1×10 １１ ~1 x 10 １９ / cm ２ When implanting ions, it is advisable to adjust the implantation direction so that the channeling phenomenon does not occur.

[0026] This ion implantation forms an ion-implanted layer 11 to a predetermined depth from the surface of the semiconductor layer 10. For example, the ion-implanted layer 11 extends to a depth of 50 to 200 nm from the surface of the semiconductor layer 10. The ion-implanted layer 11 is an amorphous layer containing Ni, Ga, and O, and is a layer having a large amount of damage.

[0027] The average concentration of the transition metal in the thickness direction of the ion-implanted layer 11 is preferably smaller than the Ga concentration in the semiconductor layer 10. This facilitates recovery of crystallinity in the subsequent heat treatment step, and makes it easier to form the p-type layer 13 and intermediate layer 12 described below. For example, the average concentration of the transition metal is 1×10 １５ ~1 x 10 ２１ / cm ３ The concentration of the transition metal at the injection peak is preferably, for example, 1×10 １７ ~1 x 10 ２１ / cm ３ It is more preferable that the average Ni concentration is within the above range.

[0028] In the ion implantation step, a transition metal other than Ni may be ion-implanted. The transition metal preferably includes one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu. The transition metal may be an element that forms a deep level with respect to gallium oxide, and the oxide may exhibit p-type conductivity. In particular, it is preferable to include Ni or Cu, which are easily capable of obtaining p-type conductivity, and it is particularly preferable to include Ni. Furthermore, multiple types of elements may be ion-implanted.

[0029] Ion implantation may be performed multiple times, and by performing multiple implantations under different conditions, the distribution of the transition metal can be adjusted. Ion implantation may be performed at room temperature, or may be performed while heating the semiconductor layer 10. Damage to the semiconductor layer 10 can be suppressed by performing ion implantation while heating.

[0030] Following the ion implantation step, a heat treatment step is performed. The heat treatment step involves heat treating the ion-implanted semiconductor layer in an oxygen-containing atmosphere (step S2 in FIG. 2). The ion-implanted semiconductor layer includes the semiconductor layer 10 and the ion-implanted layer 11. Here, the oxygen-containing atmosphere may be an atmosphere containing only oxygen, or a mixed atmosphere containing oxygen and an inert gas. Examples of the inert gas include rare gases such as argon, nitrogen, etc. In the case of a mixed atmosphere, it is preferable that the oxygen content be 50% by volume or more. This allows for more efficient p-type conversion and formation of a p-type layer.

[0031] Any heat treatment method may be used, but the following method is particularly preferred, which allows for more efficient conversion to p-type and formation of a p-type layer.

[0032] The first method is a method in which heat treatment is performed by RTA (rapid thermal annealing). This is a method in which heating is performed by infrared irradiation. The heat treatment temperature is preferably 200 to 1100°C, more preferably 250 to 1050°C, and even more preferably 650 to 1000°C. Here, the heat treatment temperature is preferably 200°C or higher, more preferably 250°C or higher, even more preferably 650°C or higher, and may be 900°C or higher, and is preferably 1100°C or lower, more preferably 1050°C or lower, and even more preferably 1000°C or lower. The heat treatment time is preferably 10 to 500 minutes, more preferably 30 to 400 minutes, and even more preferably 60 to 300 minutes. Here, the heat treatment time is preferably 10 minutes or longer, more preferably 30 minutes or longer, even more preferably 60 minutes or longer, and is preferably 500 minutes or shorter, more preferably 400 minutes or shorter, and even more preferably 300 minutes or shorter. If the heat treatment temperature and heat treatment time are within these ranges, it is possible to efficiently form the p-type layer 13 and intermediate layer 12 described below. A suitable combination of the heat treatment temperature and heat treatment time in RTA is 900 to 1000° C. and 10 to 500 minutes.

[0033] Another method involves generating a plasma using an oxygen-containing gas to radicalize the oxygen, and then performing heat treatment in the resulting oxygen radicals. In this case, heat treatment is preferably performed in a vacuum. For example, heat treatment can be performed using a vacuum heating device such as a molecular beam epitaxy (MBE) device. This heat treatment method allows for efficient formation of the p-type layer 13 and intermediate layer 12, described below. Furthermore, the heat treatment temperature can be lowered compared to RTA, thereby further suppressing thermal damage to the semiconductor layer 10. The heat treatment temperature is preferably 100 to 500°C, more preferably 150 to 450°C, and even more preferably 200 to 400°C. Here, the heat treatment temperature is preferably 100°C or higher, more preferably 150°C or higher, and even more preferably 200°C or higher, and is preferably 500°C or lower, more preferably 450°C or lower, and even more preferably 400°C or lower. The heat treatment time is preferably 10 to 500 minutes, more preferably 20 to 400 minutes, and even more preferably 30 to 300 minutes. Here, the heat treatment time is preferably 10 minutes or more, more preferably 20 minutes or more, even more preferably 30 minutes or more, and is preferably 500 minutes or less, more preferably 400 minutes or less, and even more preferably 300 minutes or less. A suitable combination of heat treatment temperature and heat treatment time when performing heat treatment in oxygen radicals is 100 to 500°C and 10 to 500 minutes. As mentioned above, the heat treatment may be performed in two stages. For example, the first heat treatment may be performed in radicalized oxygen radicals, and then the second heat treatment may be performed by RTA.

[0034] In the heat treatment step, it is preferable to form a p-type layer 13 containing a p-type transition metal oxide near the surface of the semiconductor layer 10, and to further form an intermediate layer 12 containing a mixed crystal of gallium oxide and a transition metal oxide between the semiconductor layer 10 and the p-type layer 13. Here, the transition metal oxide is preferably nickel oxide. The formation of the p-type layer 13 and the intermediate layer 12 by heat treatment is believed to be due to the following mechanism.

[0035] Ion implantation near the surface of the semiconductor layer 10 forms an ion-implanted layer 11 near the surface of the semiconductor layer 10. The ion-implanted layer 11 has numerous crystal damages and amorphous regions. When heat treatment is performed, the transition metal in the ion-implanted layer 11 diffuses to repair the damage. Because the heat treatment is performed in an oxygen-containing atmosphere, oxygen also penetrates into the semiconductor layer 10 and repairs the damage. This causes atomic rearrangement in the ion-implanted layer 11. As a result, a p-type layer 13 containing a transition metal oxide is formed near the surface of the semiconductor layer 10. The diffusion of the transition metal creates a concentration distribution of the transition metal in the thickness direction of the oxide semiconductor, resulting in the formation of an intermediate layer 12 containing a mixed crystal of gallium oxide and a transition metal oxide between the semiconductor layer 10 and the p-type layer 13. The transition metal is preferably Ni, and the transition metal oxide is preferably nickel oxide.

[0036] The p-type layer 13 contains a transition metal oxide, preferably nickel oxide. Nickel oxide exhibits p-type even when undoped. This is because, in the case of a crystal layer in which oxygen is in an excess state and Ni vacancies exist, an acceptor level is formed in the valence band. The hole concentration of the p-type layer 13 is, for example, 1×10 １７ ~1 x 10 １９ / cm ３ In order to further increase the hole concentration, ions of Li or the like may be implanted in addition to transition metals such as Ni.

[0037] The thickness of the p-type layer 13 depends on the concentration distribution of the transition metal and the heat treatment conditions, but is, for example, 10 to 200 nm.

[0038] The intermediate layer 12 is a mixed crystal of gallium oxide and a transition metal oxide. When the transition metal oxide is nickel oxide, the mixed crystal is Ni ｘ Ga ｙ O ３ Here, the Ni composition x increases toward the p-type layer 13, and the Ga composition y decreases toward the p-type layer 13. The average Ni composition x in the thickness direction is, for example, 0.1 to 0.5. The average Ga composition y in the thickness direction is, for example, 1.5 to 1.9.

[0039] The intermediate layer 12 is considered to be a low-concentration p-type semiconductor having a lower hole concentration than the p-type layer 13. The hole concentration of the intermediate layer 12 is, for example, 1×10 １６ ~1 x 10 １８ / cm ３ is.

[0040] The thickness of the intermediate layer 12 depends on the concentration distribution of the transition metal and the heat treatment conditions, but is, for example, 10 to 100 nm.

[0041] In this manner, in this embodiment, the diffusion of transition metals by heat treatment is utilized, and therefore, an intermediate layer 12, which is a mixed crystal layer of gallium oxide and transition metal oxide, is formed between the semiconductor layer 10 and the p-type layer 13.

[0042] The presence of the p-type intermediate layer 12, which has a lower concentration than the p-type layer, improves the physical and temporal stability of the device structure. For example, the intermediate layer 12 gradually changes the crystal structure from the p-type layer 13 to the semiconductor layer 10, resulting in less crystal distortion and physical, thermal, and temporal stability. Furthermore, because the intermediate layer 12 is formed by heat treatment, it has few vacancies, preventing electric field concentration in the vacancies and breakdown during voltage application. Furthermore, because the intermediate layer 12 can be considered a low-concentration p-type layer or a high-resistance layer close to intrinsic, it spreads a depletion layer between the p-type layer 13 and the semiconductor layer 10, alleviating the electric field and also serving as a layer capable of forward charge conduction, similar to the intrinsic semiconductor layer (i-layer) of a pin diode. Even if such a p-layer contains a small amount of Ga, its basic function is not impaired, and its thickness can be as thin as, for example, about 0.1 μm. This is in line with the concept of the transparent p-emitter layer that has been utilized in Si power semiconductors (Nakagawa, et al., New Anode Design Concept of 600V Thin Wafer PT-IGBT with Very Low Dose P-buffer and Transparent P-emitter, ISPSD 2003, etc.).

[0043] FIG. 3 is a diagram schematically illustrating the IV characteristics of the semiconductor layer. Specifically, it is a diagram schematically illustrating the IV characteristics when a voltage is applied with the surface of the p-type layer 13 as the anode and the back surface of the semiconductor layer 10 as the cathode. In FIG. 3, A shows the IV characteristics after heat treatment, B shows the IV characteristics before ion implantation, and C shows the IV characteristics before heat treatment after ion implantation. As shown in FIG. 3, the IV characteristics after ion implantation and before heat treatment are not significantly different from those before ion implantation. This is because the intermediate layer 12 and p-type layer 13 have not yet been formed. On the other hand, after heat treatment, the breakdown voltage is significantly improved. Furthermore, the forward voltage is also slightly lower. This is because the intermediate layer 12 and p-type layer 13 are formed, forming a pn junction with the n-type semiconductor layer 10.

[0044] As described above, according to the method for producing an oxide semiconductor according to this embodiment, the intermediate layer 12, which is preferably p-type, and the p-type layer 13 can be formed in the semiconductor layer 10 containing gallium oxide. In particular, since the intermediate layer 12 is formed, a structure that is stable over time can be obtained.

[0045] The pn junction structure obtained by the oxide semiconductor manufacturing method of this embodiment can be formed entirely or selectively on a substrate, and therefore can be employed in the structures of various semiconductor elements such as pn diodes and FETs. In particular, an oxide semiconductor having a stacked structure of a semiconductor layer 10, an intermediate layer 12, and a p-type layer 13, or a power device having a p-type oxide semiconductor (intermediate layer 12), can be realized. That is, an oxide semiconductor according to one aspect of this embodiment includes a semiconductor layer made of an n-type or undoped gallium oxide-based semiconductor, a p-type layer located on the semiconductor layer and made of a transition metal oxide and exhibiting p-type conductivity, and an intermediate layer located between the semiconductor layer and the p-type layer and made of a mixed crystal of gallium oxide and an oxide of the transition metal. Here, the transition metal preferably includes one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu, and more preferably includes Ni. Furthermore, a p-type oxide semiconductor according to another aspect of this embodiment is a mixed crystal of gallium oxide and an oxide of a transition metal. The transition metal preferably includes one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu, and more preferably includes Ni.

[0046] In this embodiment, the p-type layer 13 is formed near the surface of the n-type semiconductor layer 10, leaving an n-type portion. However, if the semiconductor layer 10 is thinned or if transition metal ions are implanted not only near the surface of the semiconductor layer 10 but also into a deep region, the entire semiconductor layer 10 can be made into the intermediate layer 12 and p-type layer 13, with no n-type region remaining.

[0047] In this embodiment, ions are implanted into the entire surface vicinity of the semiconductor layer 10, and the intermediate layer 12 and the p-type layer 13 are formed over the entire surface, but the intermediate layer 12 and the p-type layer 13 may be formed in limited areas within the surface. For example, ions may be implanted after forming a mask on a partial area of ​​the surface of the semiconductor layer 10. Alternatively, the intermediate layer 12 and the p-type layer 13 may be formed in limited areas by heating a portion of the semiconductor layer 10 with a laser or the like.

[0048] Next, the test method according to this embodiment and the results thereof will be described.

[0049] Example 1 and Example 2 First, an n-type gallium oxide substrate having a thickness of 1 mm was prepared. The crystal phase was β-type, the principal surface had a (001) plane orientation, the n-type impurity was Sn, and the n-type impurity concentration was 1×10 １８ / cm ２ Then, Ni ions were implanted into the surface of the substrate. The ion implantation was performed at 180 keV and a dose of 8.4×10 １２ / cm ２ The injection peak was set at a depth of 80 nm from the substrate surface.

[0050] Next, heat treatment was performed in a 100% oxygen atmosphere. The heat treatment was performed by RTA for Example 1, and in an MBE apparatus for Example 2. Specifically, the heat treatment temperature was 500°C and the heat treatment time was 60 minutes for Example 1. For Example 2, plasma was generated using an oxygen-containing gas, and the heat treatment was performed in oxygen radicals generated by converting the oxygen into plasma. The heat treatment temperature was 300°C and the heat treatment time was 60 minutes.

[0051] In the above manufacturing process, the IV characteristics were measured with the front side (ion implantation side) of the substrate as the anode and the back side as the cathode at each stage before ion implantation, before heat treatment after ion implantation, and after heat treatment by RTA or MBE.

[0052] 4 to 7 are graphs showing the measured IV characteristics: Fig. 4 is the graph before ion implantation, Fig. 5 is the graph after ion implantation and before heat treatment, Fig. 6 is the graph after heat treatment by RTA (Example 1), and Fig. 7 is the graph after heat treatment by MBE (Example 2).

[0053] As shown in Figures 4 and 5, there was little change in the IV characteristics before ion implantation and before heat treatment after ion implantation. Furthermore, the IV characteristics were roughly symmetrical between forward bias and reverse bias. These results demonstrate that a p-type layer cannot be obtained simply by implanting transition metal ions near the surface of the semiconductor layer.

[0054] On the other hand, as shown in Figures 6 and 7, the heat treatment process significantly improved the breakdown voltage and breakdown voltage in both the RTA and MBE heat treatments. It was also found that the forward conduction performance was improved. These results indicated that a pn junction structure was formed by the heat treatment, and confirmed that a p-type layer was formed near the surface of the substrate.

[0055] Examples 3 to 5 First, a substrate was prepared by laminating a 10 μm high-resistivity n-type epitaxial layer having a resistivity of 100 Ω cm on a 600 μm thick low-resistivity n-type gallium oxide substrate (resistivity: 0.01 Ω cm or less). The crystalline phase of the substrate was β-type, the principal surface had a (001) plane orientation, the n-type impurity was Sn, and the n-type impurity concentration was 1×10 １８ / cm ２ Then, Ni ions were implanted into the surface of the high-resistivity epitaxial growth layer of the substrate. The ion implantation was performed at 180 keV and a dose of 8.4×10 １２ / cm ２ The ion implantation was performed at 300° C. in Example 3, and at room temperature in Examples 4 and 5, so that the implantation peak was at a depth of 80 nm from the substrate surface.

[0056] Next, each of the ion-implanted substrates was subjected to a heat treatment in a 100% oxygen atmosphere. The first heat treatment was performed in an MBE apparatus. Specifically, plasma was generated using an oxygen-containing gas, and the heat treatment was performed in the oxygen radicals generated by converting the oxygen into plasma. The heat treatment temperature was 300°C, and the heat treatment time was 60 minutes.

[0057] Next, for Examples 4 and 5, an RTA heat treatment was further performed in oxygen as a second heat treatment under different conditions. Specifically, in Example 4, the heat treatment temperature was 500° C. and the RTA heat treatment time was 10 minutes, and in Example 5, the heat treatment temperature was 950° C. and the RTA heat treatment time was 10 minutes. Note that the second heat treatment (RTA heat treatment) was not performed for Example 3.

[0058] For the devices of Examples 3 to 5 that had undergone the above manufacturing process, a 1 mm diameter Ni vapor-deposited film was formed as the anode on the epitaxial growth layer side, and a Ti vapor-deposited film was formed as the cathode on the back side, and then sintering was carried out in nitrogen at 400°C for 1 minute. The IV characteristics were measured using the front side (ion implantation side) of the substrate epitaxial growth layer as the anode and the back side as the cathode.

[0059] 8 and 9 are graphs showing the IV characteristics of Examples 3 to 5. Specifically, FIGS. 8(a) to 8(c) show the reverse characteristics (Vr-Ir) of Examples 3 to 5, respectively, and FIGS. 9(a) to 9(c) show the forward characteristics (Vf-If) of Examples 3 to 5, respectively.

[0060] As can be seen from the results in Figures 8(a) to 8(c), there was no significant difference in the reverse characteristics (Vr-Ir) due to the difference in the heat treatment method in the oxygen-containing atmosphere, and all results were good. On the other hand, as shown in Figures 9(a) to 9(c), with regard to the forward characteristics (Vf-If), compared to Example 3, which was heat treated only by MBE, Examples 4 and 5, which were heat treated in two stages, namely, the first heat treatment by MBE and the second heat treatment by RTA, showed significantly improved conduction performance. Furthermore, compared to Example 4, in which the heat treatment temperature for the second heat treatment, RTA, was 500°C, the conduction performance of Example 5, in which the heat treatment was performed at 950°C, was significantly improved.

[0061] Although the present invention has been described in detail and with reference to specific embodiments, various changes and modifications may be made without departing from the spirit and scope of the present invention, the contents of which are incorporated herein by reference. This application is based on a Japanese patent application (Patent Application No. 2023-096531) filed on June 12, 2023, the contents of which are incorporated herein by reference.

[0062] 10: Semiconductor layer 11: Ion implantation layer 12: Intermediate layer 13: P-type layer

Claims

1. A method for producing an oxide semiconductor, comprising: implanting transition metal ions into a surface vicinity of a semiconductor layer containing gallium oxide; and heat-treating the semiconductor layer into which the ions have been implanted in an atmosphere containing oxygen.

2. The method for producing an oxide semiconductor according to claim 1, wherein, in the heat treatment, a p-type layer made of a p-type transition metal oxide is formed in the vicinity of the surface of the semiconductor layer, and an intermediate layer containing a mixed crystal of the gallium oxide and the transition metal oxide is further formed between the semiconductor layer and the p-type layer.

3. The method for producing an oxide semiconductor according to claim 1, wherein the transition metal includes one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu.

4. The method for producing an oxide semiconductor according to claim 1, wherein the transition metal includes Ni.

5. The method for producing an oxide semiconductor according to any one of claims 1 to 4, wherein the heat treatment is carried out by rapid thermal annealing or annealing.

6. A method for producing an oxide semiconductor according to any one of claims 1 to 4, wherein a plasma is generated using a gas containing oxygen to convert the oxygen into radicals, and the heat treatment is carried out in the oxygen radicals.

7. The method for producing an oxide semiconductor according to any one of claims 1 to 4, wherein the heat treatment comprises: a first heat treatment in which plasma is generated using a gas containing oxygen to radicalize oxygen, and the heat treatment is performed in the oxygen radicals; and a second heat treatment by rapid thermal annealing or annealing after the first heat treatment.

8. An oxide semiconductor having: a semiconductor layer containing n-type or undoped gallium oxide; a p-type layer located on the semiconductor layer and which is an oxide of a transition metal and exhibits p-type conductivity; and an intermediate layer located between the semiconductor layer and the p-type layer and which contains a mixed crystal of the gallium oxide and an oxide of the transition metal.

9. The oxide semiconductor according to claim 8, wherein the transition metal includes one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu.

10. The oxide semiconductor according to claim 8, wherein the transition metal includes Ni.

11. A p-type oxide semiconductor comprising a mixed crystal of gallium oxide and an oxide of a transition metal.

12. The p-type oxide semiconductor according to claim 11, wherein the transition metal includes one or more selected from the group consisting of Ni, Fe, Co, Ti, V, Cr, Mn, and Cu.

13. The p-type oxide semiconductor according to claim 11, wherein the transition metal includes Ni.

14. A power device comprising at least one semiconductor selected from the group consisting of the oxide semiconductor according to any one of claims 8 to 10 and the p-type oxide semiconductor according to any one of claims 11 to 13.

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