Power semiconductor module and power conversion device comprising same

Abstract

An embodiment relates to a power semiconductor module and a power conversion device comprising same. The power semiconductor module according to an embodiment may comprise: a power semiconductor device; a first wiring layer and a second wiring layer disposed on the lower side and the upper side, respectively, of the power semiconductor device; and a first mold surrounding the side surfaces of the power semiconductor device. The power semiconductor device can include a (1-1)st power semiconductor device and a (1-2)st power semiconductor device that arranged to be adjacent to each other. The first wiring layer can include a (1-1)st wiring layer electrically connected to the drain electrodes of the (1-1)st power semiconductor device and the (1-2)st power semiconductor device. The second wiring layer can be electrically connected to a gate electrode and a source electrode of the (1-1)st power semiconductor device and the (1-2)st power semiconductor device. The second wiring layer can include a common gate wiring electrically connected to a first gate electrode of the (1-1)st power semiconductor device and a second gate electrode of the (1-2)st power semiconductor device.

Description

Power semiconductor module and power conversion device including the same

[0001] The embodiment relates to a power semiconductor module and a power conversion device including the same.

[0002] Power semiconductors are one of the key elements that determine the efficiency, speed, durability, and reliability of power electronics systems.

[0003] With the recent development of the power electronics industry, research is actively being conducted on WBG (Wide Bandgap) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) to replace the existing silicon (Si) power semiconductors that have reached their physical limits.

[0004] WBG power semiconductor devices have a bandgap energy approximately three times that of Si power semiconductor devices, resulting in lower intrinsic carrier concentration, higher breakdown field (approximately 4 to 20 times), higher thermal conductivity (approximately 3 to 13 times), and larger electron saturation velocity (approximately 2 to 2.5 times).

[0005] These characteristics enable operation in high-temperature, high-voltage environments, high switching speeds, and low switching losses. Among these, gallium nitride (GaN) power semiconductor devices can be used in low-voltage systems, while silicon carbide (SiC) power semiconductor devices are suitable for high-voltage systems.

[0006] Meanwhile, according to the conventional internal technology regarding SiC power semiconductors, there is a problem in which the power semiconductor elements crack during the process of bonding the individual power semiconductor elements to a predetermined heat dissipation substrate.

[0007] In addition, in conventional internal technology, there is a problem in that voids are generated because the mold material is not properly filled during the molding process after bonding individual power semiconductor elements to the heat sink substrate.

[0008] In addition, in the conventional internal technology, there is a problem of poor electrical interconnection occurring between the electrodes of the power semiconductor elements and the conductive layer pattern of the heat dissipation substrate during the process of bonding individual power semiconductor elements to the heat dissipation substrate.

[0009] In addition, according to conventional internal technology, multiple semiconductor modules, each including multiple power semiconductor elements, can be manufactured as a single unit module, but there is a problem in that the entire manufactured unit module must be discarded when a failure occurs in the final module test.

[0010]

[0011] Meanwhile, multiple power semiconductor devices included in a power semiconductor module are connected in series or parallel. In this case, when each power semiconductor device is turned off, stray inductance is formed in the corresponding power semiconductor device. The longer the electrical connection path between the power semiconductor devices, the greater the stray inductance.

[0012] Stray inductance impedes current flow and thus hinders high-power output, so it must be minimized or eliminated. In particular, as stray inductance increases, momentary voltage overshoot occurs. If this overshoot exceeds the withstand voltage of the power semiconductor device, it can damage the device or increase switching losses. Therefore, technological solutions that can minimize or eliminate stray inductance are urgently needed.

[0013] One of the technical challenges of the embodiment is to solve the problem of power semiconductor devices being cracked during the process of bonding individual power semiconductor devices to a predetermined heat dissipation substrate.

[0014] In addition, one of the technical challenges of the embodiment is to solve the problem of voids occurring when the mold material is not properly filled during the molding process after bonding individual power semiconductor devices to a heat sink substrate.

[0015] In addition, one of the technical challenges of the embodiment is to solve the problem of poor electrical interconnection between the electrodes of the power semiconductor device and the conductive layer pattern of the heat dissipation substrate during the process of bonding the individual power semiconductor device to the heat dissipation substrate.

[0016] In addition, one of the technical challenges of the embodiment is to solve the problem of discarding the entire manufactured unit module when a failure occurs in the final module test after a plurality of semiconductor modules are manufactured into one unit module.

[0017] In addition, one of the technical challenges of the embodiment is to solve the problem of stray inductance occurring due to an increase in the current path in a power semiconductor module.

[0018] The technical tasks of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0019] A power semiconductor module according to an embodiment may include a power semiconductor element (100a, 100b), a first wiring layer (210) and a second wiring layer (220) respectively arranged on the lower and upper sides of the power semiconductor element (100a, 100b), and a first mold (201) surrounding a side surface of the power semiconductor element (100a, 100b).

[0020] The above power semiconductor element (100a) may include a first-first power semiconductor element (100a1) and a first-second power semiconductor element (100a2) that are arranged adjacently.

[0021] The above first wiring layer (210) may include a 1-1 wiring layer (210a) electrically connected to the drain electrodes of the 1-1 power semiconductor element (100a1) and the 1-2 power semiconductor element (100a2).

[0022] The second wiring layer (220) can be electrically connected to the gate electrode and source electrode of the first-first power semiconductor element (100a1) and the first-second power semiconductor element (100a2).

[0023] The second wiring layer (220) may include a common gate wiring (220g) electrically connected to the first gate electrode (165g1) of the first-first power semiconductor element (100a1) and the second gate electrode (165g2) of the first-second power semiconductor element (100a2).

[0024] The second wiring layer (220) may include a first source wiring (220s1) and a second source wiring (220s2) that are electrically connected to the first source electrode (145s1) of the first-first power semiconductor element (100a1) and the second source electrode (145s2) of the first-second power semiconductor element (100a2), respectively.

[0025] The above power semiconductor element (100a) may include a first source via (245b1) that is disposed on an interlayer insulating layer (230) and electrically connects the first source electrode (145s1) of the first-first power semiconductor element (100a1) and the first source wiring (220s1). For example, the interlayer insulating layer (230) may be disposed above or below the power semiconductor element (100a).

[0026] The above power semiconductor element (100a) may include a second source via (245b2) that is disposed on the interlayer insulating layer (230) and electrically connects the second source electrode (145s2) of the first-second power semiconductor element (100a2) and the second source wiring (220s2).

[0027] The above power semiconductor element (100a) may include a common gate via (245a) that is disposed on the interlayer insulating layer (230) and electrically connects the first gate electrode (165g1) and the second gate electrode (165g2) of the first-first power semiconductor element (100a1) and the first-second power semiconductor element (100a2) to the common gate wiring (220g).

[0028] The first gate electrode (165g1) of the 1-1 power semiconductor element (100a1) and the second gate electrode (165g2) of the 1-2 power semiconductor element (100a2) are arranged to face each other, and the first gate electrode (165g1) and the second gate electrode (165g2) can be electrically connected to the common gate wiring (220g).

[0029] The second wiring layer (220) may include a common source wiring (220sc) electrically connected to the first source electrode (145s1) of the first-first power semiconductor element (100a1) and the second source electrode (145s2) of the first-second power semiconductor element (100a2).

[0030]

[0031] According to another embodiment, a power semiconductor module may include a third power semiconductor element (100c1, 100c2), a first wiring layer (210) and a second wiring layer (220) respectively disposed on the lower and upper sides of the third power semiconductor element (100c1, 100c2), and a first mold (201) surrounding a side surface of the third power semiconductor element (100c1, 100c2).

[0032] The above third power semiconductor element may include a 3-1 power semiconductor element (100c1) and a 3-2 power semiconductor element (100c2) that are arranged adjacently.

[0033] The above first wiring layer (210) may include a 1-1 wiring layer (210a) electrically connected to the drain electrodes of the 3-1 power semiconductor element (100c1) and the 3-2 power semiconductor element (100c2).

[0034] The above second wiring layer (220) can be electrically connected to the gate electrode and source electrode of the 3-1 power semiconductor element (100c1) and the 3-2 power semiconductor element (100c2).

[0035] The second wiring layer (220) may include a first gate wiring (220g1) and a second gate wiring (220g2) that are electrically connected to the first gate electrode (165g1) of the 3-1 power semiconductor element (100c1) and the second gate electrode (165g2) of the 3-2 power semiconductor element (100c2), respectively.

[0036] The above first gate wiring (220g1) and the above second gate wiring (220g2) can be connected by a gate bridge wiring (220gb).

[0037] The second wiring layer (220) may include a common source wiring (220s) electrically connected to the first source electrode (145s1) of the 3-1 power semiconductor element (100c1) and the second source electrode (145s2) of the 3-2 power semiconductor element (100c2).

[0038] The first gate wiring (220g1), the second gate wiring (220g2), and the common source wiring (220s) may be exposed by the interlayer insulating layer (230).

[0039] The above gate bridge wiring (220gb) can be covered by the interlayer insulating layer.

[0040] The first gate wiring (220g1) and the second gate wiring (220g2) of the second wiring layer (220) can be arranged at the corners of the 3-1 power semiconductor element (100c1) and the 3-2 power semiconductor element (100c2).

[0041] The first gate wiring (220g1) may be arranged at the upper left corner of the 3-1 power semiconductor element (100c1), and the second gate wiring (220g2) may be arranged at the upper right corner of the 3-2 power semiconductor element (100c2).

[0042] The third power semiconductor element (100c) may be disposed on an interlayer insulating layer (230) and may include a first source via (245b1) electrically connecting the first source electrode (145s1) of the third-first power semiconductor element (100c1) and the common source wiring (220s). For example, the interlayer insulating layer (230) may be disposed above or below the third power semiconductor element (100c).

[0043] The third power semiconductor element (100c) may include a second source via (245b2) that is disposed on the interlayer insulating layer (230) and electrically connects the second source electrode (145s2) of the third-second power semiconductor element (100c2) and the common source wiring (220s).

[0044] A power conversion device according to an embodiment may include any one of the power semiconductor modules described above.

[0045] According to the power semiconductor module and the power conversion device including the same according to the embodiment, the problem of power semiconductor elements being cracked during the process of bonding individual power semiconductor elements to a predetermined heat dissipation substrate can be solved.

[0046] For example, the embodiment has a technical effect that allows multiple power semiconductor devices to be sub-modules using a wiring layer, and that the wiring layer is adhered to a heat dissipation substrate in the sub-module state, thereby solving the problem of power semiconductor devices being cracked.

[0047] In addition, according to an embodiment, a first mold layer, for example, an inner mold layer, is disposed around a power semiconductor element and a wiring layer is present, so that the first mold layer prevents the power semiconductor element from being pressed, and at the same time, the wiring layer acts as an additional buffer, thereby solving the problem of the power semiconductor element being cracked.

[0048] In addition, according to the embodiment, the problem of voids occurring when the mold material is not properly filled during the molding process after bonding individual power semiconductor elements to a heat sink substrate can be solved.

[0049] For example, the embodiment has a technical effect that can solve the problem of voids occurring inside because internal molding is performed at the sub-module stage using a wiring layer.

[0050] In addition, according to the embodiment, it is possible to solve the problem of poor electrical interconnection between the electrodes of the power semiconductor device and the conductive layer pattern of the heat dissipation substrate during the process of bonding the individual power semiconductor device to the heat dissipation substrate.

[0051] For example, the embodiment performs sub-modularization using a wiring layer, and since the wiring layer in the sub-module state is adhered to the conductive layer pattern of the heat-dissipating substrate, there is a technical effect that can solve the problem of poor electrical interconnection between the electrodes of the power semiconductor element and the conductive layer pattern of the heat-dissipating substrate.

[0052] In addition, according to an embodiment, the problem of discarding the entire manufactured unit module when a failure occurs in the final module test after a plurality of semiconductor modules are manufactured into one unit module can be solved.

[0053] For example, the embodiment has the technical effect of reducing costs and increasing mass production by serially or parallelly sub-moduleizing multiple power semiconductor devices according to module specifications and performing pre-tests on the sub-modules so that only failed sub-modules can be discarded.

[0054] In addition, the second power semiconductor sub-module (PM) according to the second embodiment has a technical effect of being able to secure a wide second gate electrode area (GA). For example, the second gate electrode area (GA) can secure a side width (L) that is four times or more larger than that of the first gate area or the second gate area, and accordingly, the second gate electrode area (GA) has a special technical effect of being able to secure a gate electrode area that is 16 times (LxL) or larger than that of the internal technology.

[0055] In conventional internal technology, there is a problem of poor adhesion due to the gate pad having a small size, for example, 1.0x1.0mm. However, by increasing the gate pad size while making a sub-module according to an embodiment, adhesion becomes better, thereby solving the problem of poor electrical interconnection.

[0056] In addition, according to the embodiment, there is a technical effect of solving the problem of stray inductance occurring due to an increase in the current path in a power semiconductor module, thereby preventing switching loss of power semiconductor elements and enabling high-precision switching control.

[0057] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0058] Figure 1 is a circuit diagram illustrating a power conversion device (1000) according to an embodiment.

[0059] Figure 2a is a first cross-sectional view of a power semiconductor device (100) according to an embodiment.

[0060] Figure 2b is a second cross-sectional view of a power semiconductor device (100) according to an embodiment.

[0061] Figure 3a is a first cross-sectional view of a power semiconductor module (500) according to an embodiment.

[0062] FIG. 3b is a detailed view of the first arm (200) in the power semiconductor module (500) illustrated in FIG. 3a.

[0063] FIG. 4a is a specific cross-sectional view of a first power semiconductor element (100a) according to a first embodiment of the first arm (200) illustrated in FIG. 3b.

[0064] FIG. 4b is a plan view of a first power semiconductor element (100a) according to the first embodiment illustrated in FIG. 4a.

[0065] FIG. 4c and FIG. 4d are detailed views of the first power semiconductor element (100a) according to the first embodiment illustrated in FIG. 4a.

[0066] Figure 5a is a detailed plan view of a first power semiconductor element (100a) according to the first embodiment.

[0067] FIG. 5b is a detailed plan view of the 1-2 power semiconductor element (PM) according to the first embodiment.

[0068] Fig. 6a is a cross-sectional view of a third power semiconductor element (100c) according to the second embodiment.

[0069] FIG. 6b is a plan view of a third power semiconductor element (100c) according to the second embodiment illustrated in FIG. 6a.

[0070] Figures 6c and 6d are detailed views of the third power semiconductor element (100c) illustrated in Figure 6a.

[0071] Figure 7a is an example of the layout between the power semiconductor and the heat dissipation substrate metal layer in the internal technology.

[0072] Fig. 7b is an example of a layout between power semiconductors and a heat dissipation substrate metal layer to which a third power semiconductor element (100c) according to the second embodiment is applied.

[0073] Figure 7c is a plan view of a third power semiconductor element (100c) according to the second embodiment.

[0074] Fig. 8 is a second cross-sectional view of a power semiconductor module (500) according to an embodiment.

[0075] Hereinafter, an invention according to an embodiment for solving the above problem will be described in more detail with reference to the drawings.

[0076] The suffixes "module" and "part" used in the following description are given solely for the convenience of writing this specification and do not impart any particularly significant meaning or role to the components themselves. Therefore, the terms "module" and "part" may be used interchangeably.

[0077] Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

[0078] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0079] In this application, it should be understood that terms such as “include,” “have,” or “comprising” are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0080]

[0081] In an embodiment, the power semiconductor device is used in an inverter or converter, such as a computer, home appliance, automobile, solar power, or smart grid. In an embodiment, the power semiconductor device may include a single power semiconductor module or multiple power semiconductor modules. Furthermore, the power semiconductor module may include multiple power semiconductor elements.

[0082] The following examples describe an automotive inverter for driving a motor as a power semiconductor device. However, the power semiconductor devices of the examples can be applied to inverters, converters, etc. in various technical fields described above. Here, the automotive vehicle includes a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an electric vehicle (EV), a fuel cell electric vehicle (PCEV), etc. In the description of the following examples, the terms switching element and power semiconductor element may be used interchangeably.

[0083]

[0084] (Example)

[0085] Figure 1 is a circuit diagram illustrating a power conversion device (1000) according to an embodiment.

[0086] A power conversion device (1000) according to an embodiment can receive DC power from a battery or a fuel cell, convert it into AC power, and supply AC power to a predetermined load. For example, the power conversion device (1000) according to an embodiment can include an inverter, and can receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor (M), and the motor (M) can provide power to an electric vehicle, a fuel cell vehicle, etc.

[0087] A power conversion device (1000) according to an embodiment may include a power semiconductor device (100). The power semiconductor device (100) may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and may include an IGBT (Insulated Gate Bipolar Transistor).

[0088] For example, the power conversion device (1000) may include a plurality of power semiconductor elements (100a, 100b, 100c, 100d, 100e, 100f) and may include a plurality of diodes (not shown). Each of the plurality of diodes may be embedded in the power semiconductor elements (100a, 100b, 100c, 100d, 100e, 100f) in the form of an internal diode, but is not limited thereto, and may be arranged separately.

[0089] The embodiment can convert DC power into AC power through on-off control for a plurality of power semiconductor elements (100a to 100f). For example, the power conversion device (1000) according to the embodiment can supply positive power to the motor (M) by turning on the first power semiconductor element (100a) and turning off the second power semiconductor element (100b) in a first time section of one cycle, and can supply negative power to the motor (M) by turning off the first power semiconductor element (100a) and turning on the second power semiconductor element (100b) in a second time section of one cycle.

[0090] In an embodiment, a group of power semiconductor devices arranged in series on the high-voltage line and the low-voltage line of the input side may be referred to as an arm. For example, a first power semiconductor device (100a) and a second power semiconductor device (100b) may constitute a first arm, a third power semiconductor device (100c) and a fourth power semiconductor device (100d) may constitute a second arm, and a fifth power semiconductor device (100e) and a sixth power semiconductor device (100f) may constitute a third arm.

[0091] In the above arm, the upper power semiconductor element and the lower power semiconductor element can be controlled so as not to be turned on simultaneously. For example, in the first arm, the first power semiconductor element (100a) and the second power semiconductor element (100b) can be turned on and off alternately without being turned on simultaneously.

[0092] Each power semiconductor element (100a to 100f) can receive a high voltage while in an off state. For example, when the second power semiconductor element (100b) is turned off while the first power semiconductor element (100a) is turned on, the input voltage can be applied as is to the second power semiconductor element (100b). The voltage input to the second power semiconductor element (100b) can be a relatively high voltage, and the withstand voltage of each power semiconductor element (100a to 100f) can be designed to be at a high level so as to withstand such a high voltage.

[0093] Each power semiconductor element (100a to 100f) can conduct a high current when turned on. The motor (M) is driven by a relatively high current, and this high current can be supplied to the motor (M) through the turned-on power semiconductor element.

[0094] A high voltage applied to each power semiconductor element (100a to 100f) may cause high switching loss. A high current flowing through the power semiconductor element (100a to 100f) may cause high conduction loss. To dissipate the heat generated by such loss, the power semiconductor elements (100a to 100f) may be packaged into a power semiconductor module including a heat dissipation means.

[0095] The power semiconductor device (100) of the embodiment may be a silicon carbide (SiC) power semiconductor device, and may be capable of operating in a high temperature, high voltage environment and may have a high switching speed and low switching loss.

[0096]

[0097] Meanwhile, the power conversion device (1000) according to the embodiment may include a plurality of power semiconductor modules.

[0098] For example, a plurality of power semiconductor devices (100a to 100f) illustrated in FIG. 1 may be packaged into one power semiconductor module, or the power semiconductor devices constituting each arm may be packaged into one power semiconductor module.

[0099] For example, the first power semiconductor element (100a), the second power semiconductor element (100b), the third power semiconductor element (100c), the fourth power semiconductor element (100d), the fifth power semiconductor element (100e), and the sixth power semiconductor element (100f) illustrated in FIG. 1 can be packaged into one power semiconductor module.

[0100] Additionally, to increase the current capacity, additional power semiconductor devices may be placed in parallel with each power semiconductor device (100a to 100f). In this case, the number of power semiconductor devices included in the power semiconductor module may exceed six.

[0101] The power conversion device (1000) according to the embodiment may include, in addition to the transistor-type power semiconductor elements (100a to 100f), a diode-type power semiconductor element. For example, a first diode (not shown) may be arranged in parallel with a first power semiconductor element (100a), and a second diode (not shown) may be arranged in parallel with a second power semiconductor element (100b). In addition, these diodes may also be packaged together in a single power semiconductor module. In addition, the diodes may be arranged in the form of internal diodes in each power semiconductor element.

[0102]

[0103] Next, the power semiconductor devices that make up each arm can be packaged into a single power semiconductor module.

[0104] For example, the first power semiconductor element (100a) and the second power semiconductor element (100b) constituting the first arm may be packaged as a first power semiconductor module, the third power semiconductor element (100c) and the fourth power semiconductor element (100d) constituting the second arm may be packaged as a second power semiconductor module, and the fifth power semiconductor element (100e) and the sixth power semiconductor element (100f) constituting the third arm may be packaged as a third power semiconductor module.

[0105] In addition, in order to increase the current capacity, there may be additional power semiconductor elements arranged in parallel with each power semiconductor element (100a to 100f), in which case the number of power semiconductor elements included in each power semiconductor module may be more than two. In addition to the transistor-type power semiconductor elements (100a to 100f), each arm may also include a diode-type power semiconductor element (not shown), and these diodes may also be packaged together in one power semiconductor module. In addition, the diode may be arranged in the form of an internal diode in each power semiconductor element.

[0106]

[0107] Next, FIG. 2a is a first cross-sectional view of a power semiconductor device (100) according to an embodiment.

[0108] Referring to FIG. 2A, a power semiconductor device (100) according to an embodiment may include a substrate (110), a first conductivity type epilayer (120), a second conductivity type well (130), a first conductivity type source region (140), a gate insulating layer (150), a gate electrode (160), and a drain electrode (105). The first conductivity type may be N type, and the second conductivity type may be P type, but is not limited thereto.

[0109] For example, the power semiconductor device (100) may include a first conductive epi layer (120) formed on a predetermined substrate (110), a second conductive well (130) formed on the first conductive epi layer (120), a first conductive source region (140) formed on the second conductive well (130), a gate insulating layer (150) and a gate electrode (160) formed on the first conductive source region (140), and a drain electrode (105) disposed under the substrate (110).

[0110] The above substrate (110) and the first conductive epi layer (120) may include SiC (Silicon Carbide).

[0111]

[0112] Next, FIG. 2b is a second cross-sectional view of a power semiconductor device (100) according to an embodiment, and is a schematic diagram based on the first cross-sectional view illustrated in FIG. 2a.

[0113] A power semiconductor device (100) according to an embodiment may include a source electrode (145s), a gate electrode (165g) disposed on an upper side of a predetermined semiconductor epi layer (120), and a drain electrode (105) disposed on a lower side of the semiconductor epi layer (120).

[0114] In the form of a MOSFET, the source electrode (145s) or the gate electrode (165g) may include an Al series metal, and the drain electrode (105) may include a Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, or NiV / Ag, V(vanadium) / Ni / Ag, etc., but is not limited thereto.

[0115]

[0116] Next, FIG. 3a is a first cross-sectional view of a power semiconductor module (500) according to an embodiment.

[0117] A power semiconductor module (500) according to an embodiment may include a first substrate (410), a second substrate (420), a first arm (200), a first conductive frame (310), and a second conductive frame (320). In the embodiment, the 'conductive frame' may also be referred to as a 'lead frame', but is not limited thereto.

[0118] The above first arm (200) may include a plurality of power semiconductor elements (100a, 100b).

[0119] For example, the first arm (200) may include a first power semiconductor element (100a) and a second power semiconductor element (100b). Referring briefly to FIG. 2b, the first or second power semiconductor element (100a, 100b) may include a semiconductor epilayer (120), a source electrode (145s), a gate electrode (165g), and a drain electrode (105).

[0120] Referring again to FIG. 3a, the first power semiconductor element (100a) and the second power semiconductor element (100b) can form one arm (200).

[0121] For example, the electrodes of the first power semiconductor element (100a) and the second power semiconductor element (100b) may be arranged in opposite directions. For example, the source electrode and the gate electrode of the first power semiconductor element (100a) may be arranged upward, and the drain electrode may be arranged downward.

[0122] In addition, the source electrode and the gate electrode of the second power semiconductor element (100b) may be arranged downward, and the drain electrode may be arranged upward. In this arrangement structure, the first power semiconductor element (100a) and the second power semiconductor element (100b) may form one arm.

[0123]

[0124] Meanwhile, the first power semiconductor element (100a) and the second power semiconductor element (100b) can be electrically connected in parallel.

[0125] For example, in the embodiment, the electrodes of the first power semiconductor element (100a) and the second power semiconductor element (100b) may be arranged in the same direction. For example, the source electrode and the gate electrode of the first power semiconductor element (100a) may be arranged upward, and the drain electrode may be arranged downward.

[0126] Additionally, the source electrode and the gate electrode of the second power semiconductor element (100b) may be arranged on the upper side, and the drain electrode may be arranged on the lower side. In this arrangement structure, the first power semiconductor element (100a) and the second power semiconductor element (100b) may be electrically connected in parallel.

[0127]

[0128] Next, FIG. 3b is a detailed drawing of the first arm (200) in the power semiconductor module (500) illustrated in FIG. 3a.

[0129] A first arm (200) according to an embodiment may include a plurality of power semiconductor elements (100a, 100b) arranged between a first wiring layer (210) and a second wiring layer (220) and a first mold (201) surrounding side surfaces of the plurality of power semiconductor elements (100a, 100b). In the embodiment, the 'first mold' may be referred to as an 'inner mold', but is not limited thereto.

[0130] The above first wiring layer (210) may include a first-first wiring layer (210a) and a first-second wiring layer (210b).

[0131] The above 1-1 wiring layer (210a) can be electrically connected to the drain electrode of the first power semiconductor element (100a), and the 1-2 wiring layer (210b) can be electrically connected to the source electrode and gate electrode of the second power semiconductor element (100b).

[0132] The above second wiring layer (220) may include a 2-1 wiring layer (220a) and a 2-2 wiring layer (220b).

[0133] The above 2-1 wiring layer (220a) can be electrically connected to the gate electrode of the first power semiconductor element (100a), and the above 2-2 wiring layer (220b) can be electrically connected to the source electrode of the first power semiconductor element (100a) and the drain electrode of the second power semiconductor element (100b).

[0134] The above first mold (201), for example, the inner mold, can perform the function of protecting a plurality of power semiconductor elements (100a, 100b) from oxides and fixing the plurality of power semiconductor elements (100a, 100b).

[0135]

[0136] In the embodiment, the first power semiconductor element (100a) and the second power semiconductor element (100b) may be a power semiconductor sub-module including a plurality of power semiconductor elements.

[0137] For example, referring to FIG. 4a for a moment, the first power semiconductor device (100a) according to the first embodiment may include a plurality of power semiconductor devices. For example, the first power semiconductor device (100a) according to the first embodiment may include a first-first power semiconductor device (100a1) and a first-second power semiconductor device (100a2). Accordingly, the first power semiconductor device (100a) according to the first embodiment may be a power semiconductor sub-module including a plurality of power semiconductor devices.

[0138] The second power semiconductor element (100b) may also include a plurality of power semiconductor elements. For example, the second power semiconductor element (100b) may be a power semiconductor sub-module including a 2-1 power semiconductor element (not shown) and a 2-2 power semiconductor element (not shown).

[0139]

[0140] Referring again to FIGS. 3a and 3b, according to the embodiment, a plurality of power semiconductor devices can be made into sub-modules using wiring layers (210, 220), and since the wiring layers are bonded to the heat dissipation substrate in the sub-module state, the power semiconductor devices are protected by the first mold (201), thereby providing a technical effect of solving the problem of the power semiconductor devices being cracked.

[0141] In addition, according to the embodiment, since internal molding is performed by the first mold (201) at the sub-module stage using the wiring layer (210, 220), there is a technical effect that can solve the problem of voids occurring inside.

[0142] In addition, according to the embodiment, sub-modularization is performed using a wiring layer (210, 220), and since the wiring layer in the sub-module state is adhered to the conductive layer pattern of the heat-dissipating substrate, there is a technical effect that can solve the problem of poor electrical interconnection between the electrodes of the power semiconductor element and the conductive layer pattern of the heat-dissipating substrate.

[0143] In addition, according to an embodiment, a power semiconductor sub-module can be manufactured by performing singulation on an internally molded module, and the power semiconductor sub-module can include a plurality of power semiconductor elements. For example, the electrodes of each power semiconductor element can be packaged in a parallel configuration facing the same direction, or the electrodes of each element can be packaged in a configuration in which they are arranged in opposite directions to form each arm.

[0144] In addition, according to an embodiment, a plurality of power semiconductor devices are serially or parallelly sub-modules according to module specifications, and in addition, the embodiment can perform a pre-test on each power semiconductor sub-module.

[0145] Accordingly, there is a technical effect that can reduce costs and increase mass production by allowing only failed sub-modules to be discarded through pre-testing of the sub-modules.

[0146]

[0147] Next, FIG. 4a is a specific cross-sectional view of the first power semiconductor element (100a) according to the first embodiment of the first arm (200) illustrated in FIG. 3b.

[0148] Fig. 4b is a plan view of the first power semiconductor device (100a) according to the first embodiment illustrated in Fig. 4a. Fig. 4a is also a cross-sectional view taken along line A1-A1' of the first power semiconductor device (100a) according to the first embodiment illustrated in Fig. 4b.

[0149]

[0150] Referring to FIGS. 4A and 4B, the first power semiconductor device (100a) according to the first embodiment may include a plurality of power semiconductor devices. For example, the first power semiconductor device (100a) according to the first embodiment may include a first-first power semiconductor device (100a1) and a first-second power semiconductor device (100a2). Accordingly, the first power semiconductor device (100a) according to the first embodiment may be a power semiconductor sub-module including a plurality of power semiconductor devices.

[0151] Likewise, the second power semiconductor device (100b) illustrated in FIG. 3b may also include a plurality of power semiconductor devices. For example, the second power semiconductor device (100b) may include a 2-1 power semiconductor device (not shown) and a 2-2 power semiconductor device (not shown). Accordingly, the second power semiconductor device (100b) according to the first embodiment may be a power semiconductor sub-module including a plurality of power semiconductor devices.

[0152] Hereinafter, the first power semiconductor element (100a) according to the first embodiment will be described.

[0153] Referring to FIG. 4a, the 1-1 power semiconductor element (100a1) may include a first source electrode (145s1) and a first gate electrode (165g1) disposed on a predetermined semiconductor epilayer. In addition, the 1-2 power semiconductor element (100a2) may also include a second source electrode (145s2) and a second gate electrode (165g2) disposed on a predetermined semiconductor epilayer.

[0154] Next, the first power semiconductor element (100a) may include a first wiring layer (210a) electrically connected to the drain electrodes of the first-first power semiconductor element (100a1) and the first-second power semiconductor element (100a2).

[0155] Additionally, the first power semiconductor element (100a) may include a second wiring layer (220) electrically connected to the gate electrode and source electrode of the first-first power semiconductor element (100a1) and the first-second power semiconductor element (100a2).

[0156] For example, the second wiring layer (220) may include a common gate wiring (220g) electrically connected to the first gate electrode (165g1) of the first-first power semiconductor element (100a1) and the second gate electrode (165g2) of the first-second power semiconductor element (100a2).

[0157] In addition, the second wiring layer (220) may include a first source wiring (220s1) and a second source wiring (220s2) that are electrically connected to the first source electrode (145s1) of the first-first power semiconductor element (100a1) and the second source electrode (145s2) of the first-second power semiconductor element (100a2), respectively.

[0158]

[0159] Next, FIGS. 4c and 4d are detailed drawings of the first power semiconductor element (100a) according to the first embodiment illustrated in FIG. 4a.

[0160] Referring to FIG. 4c, the 1-1 power semiconductor element (100a1) may include a first source electrode (145s1), a first gate electrode (165g1) disposed on an upper side of a first semiconductor epi layer (120a1), and a first drain electrode (105a1) disposed on a lower side of the first semiconductor epi layer (120a1).

[0161] In addition, the first-second power semiconductor element (100a2) may also include a second source electrode (145s2), a second gate electrode (165g2) disposed on the upper side of the second semiconductor epi layer (120a2), and a second drain electrode (105a2) disposed on the lower side of the second semiconductor epi layer (120a2).

[0162]

[0163] Next, referring to FIG. 4d, the first power semiconductor element (100a) may include a first source via (245b1) that is disposed on an interlayer insulating layer (230) and electrically connects the first source electrode (145s1) of the first-1 power semiconductor element (100a1) to the first source wiring (220s1). For example, the interlayer insulating layer (230) may be disposed above or below the first power semiconductor element (100a).

[0164] In addition, the first power semiconductor element (100a) according to the first embodiment may include a second source via (245b2) that is disposed on the interlayer insulating layer (230) and electrically connects the second source electrode (145s2) of the first-second power semiconductor element (100a2) and the second source wiring (220s2).

[0165] In addition, the first power semiconductor element (100a) according to the first embodiment may include a gate via (245a) that is disposed on the interlayer insulating layer (230) and electrically connects the first gate electrode (165g1) and the second gate electrode (165g2) of the first-first power semiconductor element (100a1) and the first-second power semiconductor element (100a2) to a common gate wiring (220g). The gate via (245a) may be a common gate via.

[0166]

[0167] Next, FIG. 5a is a detailed plan view of a first power semiconductor element (100a) according to the first embodiment, showing a gate electrode area (GA).

[0168] Referring to FIG. 5a, the first power semiconductor element (100a) includes a first-first power semiconductor element (100a1) and a first-second power semiconductor element (100a2), and may include a second wiring layer (220) electrically connected to the gate electrode and source electrode of the first-first power semiconductor element (100a1) and the first-second power semiconductor element (100a2).

[0169] For example, the second wiring layer (220) may include a common gate wiring (220g) electrically connected to the first gate electrode (165g1) of the first-first power semiconductor element (100a1) and the second gate electrode (165g2) of the first-second power semiconductor element (100a2).

[0170] In addition, the second wiring layer (220) may include a first source wiring (220s1) and a second source wiring (220s2) that are electrically connected to the first source electrode (145s1) of the first-first power semiconductor element (100a1) and the second source electrode (145s2) of the first-second power semiconductor element (100a2), respectively.

[0171]

[0172] The first power semiconductor device (100a) according to the first embodiment has a technical effect of being able to secure a wide gate electrode area (GA) by arranging the first gate electrode (165g1) of the first-first power semiconductor device (100a1) and the second gate electrode (165g2) of the first-second power semiconductor device (100a2) so that they are adjacent to each other and facing each other, and electrically connecting them with a common gate wiring (220g).

[0173] For example, the horizontal width (M) of the gate electrode area (GA) can be secured to be about 3 times or more the horizontal width (m) of each of the first gate electrode (165g1) and the second gate electrode (165g2), and the vertical width (L) can also be secured to be about 1.5 times or more the internal technology width (l). Accordingly, compared to the internal technology, the gate electrode area (GA) has a gate electrode area of ​​4.5 times or more, which has a special technological effect of improving electrical characteristics along with submodular characteristics.

[0174]

[0175] Next, FIG. 5b is a plan view of a 1-2 power semiconductor device (PM) according to the first embodiment, and shows a gate contact area (GA).

[0176] Referring to FIG. 5b, the 1-2 power semiconductor element (PM) includes a 1-1 power semiconductor element (100a1) and a 1-2 power semiconductor element (100a2), and may include a second wiring layer (220) electrically connected to the gate electrode and source electrode of the 1-1 power semiconductor element (100a1) and the 1-2 power semiconductor element (100a2).

[0177] For example, the second wiring layer (220) may include a common gate wiring (220gc) electrically connected to the first gate electrode (165g1) of the first-first power semiconductor element (100a1) and the second gate electrode (165g2) of the first-second power semiconductor element (100a2).

[0178] In addition, the second wiring layer (220) may include a common source wiring (220sc) electrically connected to the first source electrode (145s1) of the first-first power semiconductor element (100a1) and the second source electrode (145s2) of the first-second power semiconductor element (100a2).

[0179] The first source electrode (145s1) of the above-mentioned 1-1 power semiconductor element (100a1) and the second source electrode (145s2) of the above-mentioned 1-2 power semiconductor element (100a2) may include a single or multiple source electrodes, but are not limited thereto.

[0180]

[0181] The 1-2 power semiconductor element (PM) has a technical effect of being able to secure a wide gate electrode area (GA) by positioning the first gate electrode (165g1) of the 1-1 power semiconductor element (100a1) and the second gate electrode (165g2) of the 1-2 power semiconductor element (100a2) at an edge so that they are adjacent to each other and electrically connecting them with a common gate wiring (220gc).

[0182] For example, the horizontal and vertical widths (L) of the gate electrode area (GA) can be secured to be at least four times the widths (m) of the first gate electrode (165g1) and the second gate electrode (165g2), and accordingly, compared to the internal technology, the gate electrode area (GA) can be secured to be at least 16 times (4x4), which has a special technical effect of improving electrical characteristics as well as a sub-modular effect.

[0183]

[0184] Next, FIG. 6a is a cross-sectional view of a third power semiconductor device (100c) according to a second embodiment, which is an additional embodiment of the first power semiconductor device (100a) according to the first embodiment illustrated in FIG. 3b.

[0185] Fig. 6b is a plan view of a third power semiconductor device (100c) according to the second embodiment illustrated in Fig. 6a. Fig. 6a is also a cross-sectional view taken along line A2-A2' of the third power semiconductor device (100c) according to the second embodiment illustrated in Fig. 6b.

[0186]

[0187] Referring to FIGS. 6A and 6B, the third power semiconductor device (100c) according to the second embodiment may include a plurality of power semiconductor devices. For example, the third power semiconductor device (100c) may include a 3-1 power semiconductor device (100c1) and a 3-2 power semiconductor device (100c2).

[0188] Referring to FIG. 6A, the 3-1 power semiconductor element (100c1) may include a first source electrode (145s1) and a first gate electrode (165g1) disposed on a predetermined semiconductor epilayer. In addition, the 3-2 power semiconductor element (100c2) may also include a second source electrode (145s2) and a second gate electrode (165g2) disposed on a predetermined semiconductor epilayer.

[0189] Next, the third power semiconductor element (100c) may include a first-first wiring layer (210a) electrically connected to the drain electrodes of the third-first power semiconductor element (100c1) and the third-second power semiconductor element (100c2).

[0190] Additionally, the third power semiconductor element (100c) may include a second wiring layer (220) electrically connected to the gate electrode and source electrode of the third-first power semiconductor element (100c1) and the third-second power semiconductor element (100c2).

[0191] For example, the second wiring layer (220) may include a first gate wiring (220g1) and a second gate wiring (220g2) that are electrically connected to the first gate electrode (165g1) of the 3-1 power semiconductor element (100c1) and the second gate electrode (165g2) of the 3-2 power semiconductor element (100c2), respectively.

[0192] Referring to FIG. 6b, the first gate wiring (220g1) and the second gate wiring (220g2) can be connected by a gate bridge wiring (220gb).

[0193] Additionally, the second wiring layer (220) may include a common source wiring (220s) electrically connected to the first source electrode (145s1) of the 3-1 power semiconductor element (100c1) and the second source electrode (145s2) of the 3-2 power semiconductor element (100c2).

[0194] According to the example, in the modularization process, the first gate wiring (220g1), the second gate wiring (220g2) and the common source wiring (220s) may be exposed on the interlayer insulating layer (230), but the gate bridge wiring (220gb) may not be exposed.

[0195] In an embodiment, the first gate wiring (220g1) and the second gate wiring (220g2) of the second wiring layer (220) can be arranged at the corners of the 3-1 power semiconductor element (100c1) and the 3-2 power semiconductor element (100c2).

[0196] Additionally, the first gate wiring (220g1) and the second gate wiring (220g2) can be arranged so that the 3-1 power semiconductor element (100c1) and the 3-2 power semiconductor element (100c2) face each other but are spaced apart from each other.

[0197] For example, the first gate wiring (220g1) may be placed at the upper left corner of the 3-1 power semiconductor element (100c1). On the other hand, the second gate wiring (220g2) may be placed at the upper right corner of the 3-2 power semiconductor element (100c2).

[0198]

[0199] Next, FIG. 6c and FIG. 6d are detailed drawings of the third power semiconductor element (100c) illustrated in FIG. 6a.

[0200] Referring to FIG. 6c, the 3-1 power semiconductor element (100c1) may include a first source electrode (145s1), a first gate electrode (165g1) disposed on the upper side of the first semiconductor epi layer (120a1), and a first drain electrode (105a1) disposed on the lower side of the first semiconductor epi layer (120a1).

[0201] In addition, the 3-2 power semiconductor element (100c2) may also include a second source electrode (145s2), a second gate electrode (165g2) disposed on the upper side of the second semiconductor epi layer (120a2), and a second drain electrode (105a2) disposed on the lower side of the second semiconductor epi layer (120a2).

[0202] Next, referring to FIG. 6d, the third power semiconductor element (100c) may be disposed on an interlayer insulating layer (230) and may include a first source via (245b1) electrically connecting the first source electrode (145s1) of the third-first power semiconductor element (100c1) and the common source wiring (220s). For example, the interlayer insulating layer (230) may be disposed above or below the third power semiconductor element (100c).

[0203] Additionally, the third power semiconductor element (100c) may be disposed on the interlayer insulating layer (230) and may include a second source via (245b2) electrically connecting the second source electrode (145s2) of the third-second power semiconductor element (100c2) and the common source wiring (220s).

[0204] In addition, the third power semiconductor element (100c) is disposed on the interlayer insulating layer (230) and may include a first gate via (245a) and a second gate via (245a) that electrically connect the first gate electrode (165g1) and the second gate electrode (165g2) of the third-first power semiconductor element (100c1) and the third-second power semiconductor element (100c2) to the first gate wiring (220g1) and the second gate wiring (220g2), respectively.

[0205]

[0206] Next, Fig. 7a is an example of a layout diagram (RA) between a power semiconductor and a heat dissipation substrate metal layer in an internal technology.

[0207] One of the technical challenges of the embodiment is to solve the problem of stray inductance occurring due to an increase in current path in a power semiconductor module.

[0208] Referring to FIG. 7a, the first to eighth power semiconductor elements (100r1, 100r2, 100r3, 100r4, 100r5, 100r6, 100r7, 100r8) can be electrically connected to the gate pattern (420g) of the heat dissipation substrate.

[0209] For example, the gate pattern (420g) of the heat dissipation substrate is connected to both the high side and low side MOSFET gate electrodes.

[0210] The gate pattern (420g) of the above heat dissipation substrate may include first to fourth gate patterns (420g1, 420g2, 420g3, 420g4).

[0211] For example, the first gate pattern (420g1) is connected to the gate electrodes of the first power semiconductor element (100r1) and the third power semiconductor element (100r3), respectively. In addition, the second gate pattern (420g2) is connected to the gate electrodes of the second power semiconductor element (100r2) and the fourth power semiconductor element (100r4), respectively.

[0212] In addition, the third gate pattern (420g3) is connected to the gate electrodes of the fifth power semiconductor element (100r5) and the seventh power semiconductor element (100r7), respectively. In addition, the fourth gate pattern (420g4) is connected to the gate electrodes of the sixth power semiconductor element (100r6) and the eighth power semiconductor element (100r8), respectively.

[0213]

[0214] However, the second gate pattern (420g2) and the third gate pattern (420g3) located in the middle of the power semiconductor module cause stray inductance (SI) to occur, which impedes the flow of current.

[0215] That is, as shown in Fig. 7a, the longer the electrical connection path between power semiconductor elements, the greater the stray inductance.

[0216] Stray inductance impedes current flow and thus hinders high-power output, so it must be minimized or eliminated. In particular, as stray inductance increases, momentary voltage overshoot occurs. If this overshoot exceeds the withstand voltage of the power semiconductor device, it can damage the device or increase switching losses. Therefore, technological solutions that can minimize or eliminate stray inductance are urgently needed.

[0217]

[0218] FIG. 7b is an example of a layout between power semiconductors and a heat dissipation substrate metal layer to which a third power semiconductor element (100c) according to the second embodiment is applied, and FIG. 7c is a plan view of the third power semiconductor element (100c) according to the second embodiment.

[0219] First, referring to FIG. 7c, the second wiring layer (220) may include a first gate wiring (220g1) and a second gate wiring (220g2) that are electrically connected to the first gate electrode (165g1) of the 3-1 power semiconductor element (100c1) and the second gate electrode (165g2) of the 3-2 power semiconductor element (100c2).

[0220] At this time, the first gate wiring (220g1) and the second gate wiring (220g2) can be connected through the gate bridge wiring (220gb).

[0221] Additionally, the second wiring layer (220) may include a common source wiring (220s) electrically connected to the first source electrode (145s1) of the 3-1 power semiconductor element (100c1) and the second source electrode (145s2) of the 3-2 power semiconductor element (100c2).

[0222] According to the third power semiconductor device (100c) according to the second embodiment, the first gate wiring (220g1) and the second gate wiring (220g2) and the common source wiring (220s) that are symmetrically arranged in the modularization process may be exposed to the outside, but the gate bridge wiring (220gb) may not be exposed.

[0223] In an embodiment, the first gate wiring (220g1) and the second gate wiring (220g2) of the second wiring layer (220) can be arranged at the corners of the 3-1 power semiconductor element (100c1) and the 3-2 power semiconductor element (100c2).

[0224] For example, the first gate wiring (220g1) may be placed at the upper left corner of the 3-1 power semiconductor element (100c1). On the other hand, the second gate wiring (220g2) may be placed at the upper right corner of the 3-2 power semiconductor element (100c2).

[0225]

[0226] Referring again to FIG. 7b, the first to eighth power semiconductor elements (100c1, 100c2, 100c3, 100c4, 100c5, 100c6, 100c7, 100c8) to which the third power semiconductor element (100c) according to the second embodiment is applied can be electrically connected to the gate pattern (420g) of the heat dissipation substrate in a sub-module state.

[0227] For example, the first and second power semiconductor elements (100c1, 100c2) can constitute a first sub-module. In addition, the third and fourth power semiconductor elements (100c3, 100c4) can constitute a second sub-module. In addition, the fifth and sixth power semiconductor elements (100c5, 100c6) can constitute a third sub-module. In addition, the seventh and eighth power semiconductor elements (100c7, 100c8) can constitute a fourth sub-module.

[0228]

[0229] In the embodiment, the gate pattern (420g) of the heat dissipation substrate is connected to both the high side and low side MOSFET gate electrodes, and the gate pattern (420g) of the heat dissipation substrate may include a first gate pattern (420g1) and a fourth gate pattern (420g4).

[0230] According to the third power semiconductor element (100c) according to the second embodiment, the first gate wiring (220g1) may be arranged at the upper left corner of the 3-1 power semiconductor element (100c1), and the second gate wiring (220g2) may be arranged at the upper right corner of the 3-2 power semiconductor element (100c2). At this time, the first gate wiring (220g1) and the second gate wiring (220g2) may be connected via a gate bridge wiring (220gb).

[0231] Accordingly, as shown in Fig. 7b, since the gate wiring is designed symmetrically, there is a special technical effect that can connect one first gate pattern (420g1) to the four gate wirings on the left, right, top, and bottom of the first sub-module and the second sub-module through rotation of the sub-module.

[0232] Additionally, there is a special technical effect that allows the four gate wirings on the left, right, top and bottom for the third and fourth sub-modules to be connected to one fourth gate pattern (420g4).

[0233] Accordingly, the second gate pattern (420g2) and the third gate pattern (420g3) illustrated in FIG. 7a can be omitted, thereby providing a special technical effect of preventing the occurrence of stray inductance (SI) by shortening the electrical connection path.

[0234]

[0235] Next, FIG. 8 is a second cross-sectional view of a power semiconductor module (500) according to an embodiment, and is a detailed view of the power semiconductor module (500) according to the embodiment illustrated in FIG. 3a.

[0236] In the embodiment, the first and second substrates (410, 420) may be placed on the lower and upper sides of the power semiconductor module (500), respectively.

[0237] For example, the first substrate (410) may be placed on the lower side of the power semiconductor module (500) and may be bonded to the lower side of the power semiconductor module (500) through a predetermined adhesive member (not shown). The adhesive member may be a Sn-Ag series adhesive member or a Ag series adhesive member. Alternatively, the first substrate (410) may be bonded to the lower side of the power semiconductor module (500) through soldering or sintering.

[0238] The second substrate (420) may be placed on the upper side of the power semiconductor module (500) and may adopt the technical features of the first substrate (410) described above.

[0239] The above first substrate (410) may include a first metal layer (410a), a first insulating layer (410b), and a second metal layer (410c).

[0240] The first insulating layer (410b) can electrically insulate the first metal layer (410a) and the second metal layer (410c). The first insulating layer (410b) can include a ceramic material with high thermal conductivity.

[0241] The first metal layer (410a) has one side in contact with the first insulating layer (410b) and can dissipate heat to the other side. A heat dissipation means including a cooling medium may be disposed adjacent to the other side of the first metal layer (410a).

[0242] A wiring pattern is formed on the second metal layer (410c) and the wiring pattern can be electrically connected to the first arm (200).

[0243] For example, the second metal layer (410c) may include a second-first metal layer (410c1) and a second-second metal layer (410c2) that are electrically separated, and may be electrically connected to the first power semiconductor element (100a) and the second power semiconductor element (100b), respectively. The first metal layer (410a) and the second metal layer (410c) may include a Cu-based metal, but are not limited thereto.

[0244] Additionally, the second substrate (420) may include a third metal layer (420a), a second insulating layer (420b), and a fourth metal layer (420c). The second substrate (420) may adopt the technical features of the first substrate (410).

[0245] For example, the second insulating layer (420b) can electrically insulate the third metal layer (420a) and the fourth metal layer (420c). The second insulating layer (420b) can include a ceramic material with high thermal conductivity.

[0246] A wiring pattern is formed on the third metal layer (420a), and the wiring pattern can be electrically connected to the first arm (200). For example, the third metal layer (420a) can be electrically connected to the first power semiconductor element (100a) and the second power semiconductor element (100b).

[0247] The fourth metal layer (420c) has one side in contact with the second insulating layer (420b) and can dissipate heat to the other side. A heat dissipation means including a cooling medium may be disposed adjacent to the other side of the fourth metal layer (420c).

[0248]

[0249] One side of each of the first conductive frame (310) and the second conductive frame (320) can be electrically connected to the first arm (200), and the other side of each can be connected to an external connection terminal. The external connection terminal can include an input power source, a motor, or an inverter controller.

[0250] For example, the first conductive frame (300) and the second conductive frame (320) can be electrically connected to the first arm (200) through the first substrate (410) and the second substrate (420).

[0251] For example, the first conductive frame (310) may include a first-first conductive frame (310a) electrically connected to a second-first metal layer (410c1) of a first substrate (410), and a first-second conductive frame (310b) electrically connected to a third metal layer (420a) of a second substrate (420).

[0252] In addition, the second conductive frame (320) may include a second-first conductive frame (320a) electrically connected to the second-second metal layer (410c2) of the first substrate (410), and a second-second conductive frame (320b) electrically connected to the third metal layer (420a) of the second substrate (420).

[0253] Next, the first arm (200) of the embodiment may include a first mold (201) surrounding the side surfaces of a plurality of power semiconductor elements (100a, 100b).

[0254] In addition, the power semiconductor module (500) according to the embodiment may include a second mold (502) surrounding the outer surface of the first arm (200). In the embodiment, the 'second mold' may be referred to as an 'outer mold', but is not limited thereto.

[0255] The above first mold (201) or the above second mold (502) may include, but is not limited to, EMC (Epoxy Molding Compound).

[0256]

[0257] According to the embodiment, since the first internal molding is performed through the first mold (201) in the sub module stage using the first and second wiring layers (210, 220), there is a technical effect that can solve the problem of voids occurring inside.

[0258] In addition, according to an embodiment, a plurality of power semiconductor devices are made into sub-modules using a wiring layer, and in the sub-module state, the wiring layer is bonded to the first substrate (410) and the second substrate (420) and the power semiconductor devices are protected by the first mold (201), so there is a technical effect that can solve the problem of the power semiconductor devices being cracked.

[0259] In addition, the embodiment proceeds with sub-module formation using a wiring layer, and since the wiring layer in the sub-module state is adhered to the first and second substrates (410, 420), there is a technical effect that can solve the problem of poor electrical interconnection between the electrodes of the power semiconductor element and the conductive layer patterns of the first and second substrates (410, 420).

[0260] In addition, the embodiment has the technical effect of being able to control the number of power semiconductor devices mounted by serially or parallelly forming sub-modules according to module specifications, and being able to discard only failed sub-modules through pre-testing of the sub-modules, thereby reducing costs and increasing mass production.

[0261] In addition, the second power semiconductor sub-module (PM) according to the second embodiment has a technical effect of being able to secure a wide second gate electrode area (GA). For example, the second gate electrode area (GA) can secure a side width (L) that is four times or more larger than that of the first gate area or the second gate area, and accordingly, the second gate electrode area (GA) has a special technical effect of being able to secure a gate electrode area that is 16 times (LxL) or larger than that of the internal technology.

[0262] In addition, according to the embodiment, there is a technical effect of solving the problem of stray inductance occurring due to an increase in the current path in a power semiconductor module, thereby preventing switching loss of power semiconductor elements and enabling high-precision switching control.

[0263]

[0264] According to an embodiment, a plurality of power semiconductor devices are made into sub-modules using a wiring layer, and in the sub-module state, the wiring layer is bonded to a first substrate (410) and a second substrate (420) and the power semiconductor devices are protected by a first mold (201), so there is a technical effect that can solve the problem of the power semiconductor devices being cracked.

[0265] In addition, the embodiment proceeds with sub-module formation using a wiring layer, and since the wiring layer in the sub-module state is adhered to the first and second substrates (410, 420), there is a technical effect that can solve the problem of poor electrical interconnection between the electrodes of the power semiconductor element and the conductive layer patterns of the first and second substrates (410, 420).

[0266] In addition, the second power semiconductor sub-module (PM) according to the second embodiment has a technical effect of being able to secure a wide second gate electrode area (GA). For example, the second gate electrode area (GA) can secure a side width (L) that is four times or more larger than that of the first gate area or the second gate area, and accordingly, the second gate electrode area (GA) has a special technical effect of being able to secure a gate electrode area that is 16 times (LxL) or larger than that of the internal technology.

[0267] In addition, according to the embodiment, there is a technical effect of solving the problem of stray inductance occurring due to an increase in the current path in a power semiconductor module, thereby preventing switching loss of power semiconductor elements and enabling high-precision switching control.

[0268] Although the present invention has been described above with reference to embodiments thereof, it will be readily understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

[0269] The power conversion device according to the embodiment can be used in inverters or converters of computers, home appliances, automobiles, solar power, smart grids, etc. In the embodiment, the power conversion device can include one power semiconductor module or a plurality of power semiconductor modules. In addition, the power conversion device according to the embodiment can be applied to an inverter for an automobile for driving a motor. The power conversion device of the embodiment can be applied to inverters or converters of the various technical fields described above. Here, the automobile includes a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an electric vehicle (EV), a fuel cell electric vehicle (PCEV), etc.

Claims

1. Power semiconductor devices; A first wiring layer and a second wiring layer respectively arranged on the lower and upper sides of the power semiconductor device; and A first mold surrounding a side surface of the power semiconductor device; The above power semiconductor element includes a first-first power semiconductor element and a first-second power semiconductor element that are arranged adjacently, The first wiring layer includes a first wiring layer electrically connected to the drain electrodes of the first-first power semiconductor element and the first-second power semiconductor element, A power semiconductor module in which the second wiring layer is electrically connected to the gate electrode and source electrode of the first-first power semiconductor element and the first-second power semiconductor element.

2. In paragraph 1, The above second wiring layer is, A power semiconductor module comprising a common gate wiring electrically connected to a first gate electrode of the first-1 power semiconductor element and a second gate electrode of the first-2 power semiconductor element.

3. In paragraph 2, The above second wiring layer is, A power semiconductor module comprising a first source wire and a second source wire electrically connected to a first source electrode of the first-1 power semiconductor element and a second source electrode of the first-2 power semiconductor element, respectively.

4. In paragraph 3, The above power semiconductor device A power semiconductor module comprising a first source via disposed on an interlayer insulating layer and electrically connecting a first source electrode of the first-first power semiconductor element and the first source wiring.

5. In paragraph 4, The above power semiconductor device A power semiconductor module comprising a second source via disposed on the interlayer insulating layer and electrically connecting the second source electrode of the first-second power semiconductor element and the second source wiring.

6. Third power semiconductor device; A first wiring layer and a second wiring layer respectively arranged on the lower and upper sides of the third power semiconductor element; and A first mold surrounding a side surface of the third power semiconductor element; The third power semiconductor element includes a third-1 power semiconductor element and a third-2 power semiconductor element that are arranged adjacently, The first wiring layer includes a first wiring layer electrically connected to the drain electrodes of the third-first power semiconductor element and the third-second power semiconductor element, The second wiring layer is electrically connected to the gate electrode and source electrode of the 3-1 power semiconductor element and the 3-2 power semiconductor element, A power semiconductor module, wherein the second wiring layer includes a first gate wiring and a second gate wiring that are electrically connected to the first gate electrode of the 3-1 power semiconductor element and the second gate electrode of the 3-2 power semiconductor element, respectively.

7. In paragraph 6, A power semiconductor module, wherein the first gate wiring and the second gate wiring are connected by a gate bridge wiring.

8. In paragraph 7, A power semiconductor module, wherein the second wiring layer includes a common source wiring electrically connected to the first source electrode of the 3-1 power semiconductor element and the second source electrode of the 3-2 power semiconductor element.

9. In paragraph 8, The first gate wiring, the second gate wiring, and the common source wiring are exposed by an interlayer insulating layer, A power semiconductor module, wherein the above gate bridge wiring is covered by the interlayer insulating layer.

10. A power conversion device comprising a power semiconductor module according to any one of claims 1 to 9.

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