Circuit board, and semiconductor package comprising same

Abstract

An embodiment of the present invention provides a circuit board comprising: a first insulating layer; a first circuit pattern layer disposed on at least one of the upper surface and the lower surface of the first insulating layer and including a first metal; a first nano particle in contact with the surface of the first circuit pattern layer and including a second metal; and a second insulating layer covering the first circuit pattern layer, wherein the second metal has higher electronegativity than the first metal.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages, and more particularly to circuit boards and semiconductor packages having improved bonding strength between an insulating layer (substrate) and an electrode layer.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantities. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of the circuit board, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of the circuit board. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] Additionally, to reduce signal loss due to the skin effect in circuit patterns, pattern widths are being reduced and illumination is being lowered. However, in these cases, physical anchoring poses a limitation, as it reduces adhesive strength.

[0007] An embodiment of the present invention provides a circuit board having improved reliability including nanoparticles arranged on a circuit pattern layer and a semiconductor package including the same.

[0008] In addition, the embodiment can provide a circuit board with improved bonding strength between an insulating layer and an electrode layer and a semiconductor package including the same.

[0009] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which reduce signal loss according to illumination by having nanoparticles arranged on a circuit pattern layer and arranged corresponding to the structure of the crystal grain size of the circuit pattern layer.

[0010] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0011] A circuit board according to an embodiment of the present invention comprises: a first insulating layer; a first circuit pattern layer disposed on at least one of an upper surface and a lower surface of the first insulating layer and including a first metal; first nanoparticles in contact with a surface of the first circuit pattern layer and including a second metal; and a second insulating layer covering the first circuit pattern layer, wherein the second metal has a higher electronegativity than the first metal.

[0012] The first circuit pattern layer includes a first surface in contact with the first insulating layer; a second surface in contact with the second insulating layer and facing the first surface; and a third surface which is a side surface disposed between the first surface and the second surface; and the first nanoparticle can be in contact with the first surface and the third surface.

[0013] The amount of the first nanoparticles per unit area on the first surface may be greater than the amount of the first nanoparticles per unit area on the third surface.

[0014] The first circuit pattern layer may include a first region adjacent to the second insulating layer; and a second region adjacent to the first insulating layer.

[0015] The amount of the first nanoparticles per unit area of ​​the third surface in the first region may be greater than the amount of the first nanoparticles per unit area of ​​the third surface in the second region.

[0016] The first region may have a larger grain size than the second region.

[0017] The first region may have smaller grain boundaries than the second region.

[0018] The above first nanoparticles can be formed by an oxidation-reduction reaction between the second metal and the first metal of the first circuit pattern layer.

[0019] The second insulating layer includes an opening exposing the first circuit pattern layer, and the first nanoparticles can overlap with the opening in the stacking direction.

[0020] The first or third side may have a rough structure.

[0021] An embodiment of the present invention implements a circuit board having improved reliability including nanoparticles arranged on a circuit pattern layer and a semiconductor package including the same.

[0022] In addition, the embodiment can implement a circuit board with improved bonding strength between an insulating layer and an electrode layer and a semiconductor package including the same.

[0023] In addition, the embodiment can implement a circuit board and a semiconductor package including the same that reduces signal loss according to illumination by having nanoparticles arranged on a circuit pattern layer and arranged corresponding to the structure of the crystal grain size of the circuit pattern layer.

[0024] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0025] Figure 1 is a diagram showing the configuration of a circuit board according to an embodiment of the present invention.

[0026] Figure 2 is a drawing of a circuit board according to the first embodiment,

[0027] Figure 3 is an enlarged view of a portion of Figure 2,

[0028] Figure 4 is a drawing explaining the formation of a circuit pattern layer and nano particles according to an embodiment.

[0029] FIG. 5 is a drawing explaining the structure of a circuit pattern layer and nanoparticles in a circuit board according to an embodiment.

[0030] Figures 6a and 6b are SEM (Scanning Electron Microscopy) images of a circuit pattern layer without nanoparticles.

[0031] Figures 6c and 6d are SEM images of a circuit pattern layer in which nanoparticles exist.

[0032] Figure 7a shows the SEM results for the surface of the circuit pattern layer and the EDS (Energy Dispersive Spectrometer) results for points without nanoparticles.

[0033] Figure 7b shows the SEM results for the surface of the circuit pattern layer and the EDS results for the points where nanoparticles exist.

[0034] Figure 8 is an XPS result for nanoparticles and circuit pattern layers in a circuit board according to an embodiment.

[0035] Figure 9 is an SEM photograph of a circuit pattern layer according to the concentration of the second metal.

[0036] Figure 10 is the result of a test explaining the effect of improving the reliability of a circuit board according to an embodiment.

[0037] Fig. 11 is a drawing showing the manufacturing sequence of a circuit board according to an embodiment;

[0038] Fig. 12 is a plan view of a circuit board according to the first embodiment;

[0039] Figure 13 is an enlarged view of K1 in Figure 11,

[0040] Figure 14 is an enlarged view of K2 in Figure 11,

[0041] Fig. 15 is a drawing of a circuit board according to the second embodiment,

[0042] Fig. 16 is a drawing of a circuit board according to the third embodiment,

[0043] Fig. 17 is a drawing of a circuit board according to the fourth embodiment;

[0044] Fig. 18 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0045] Fig. 19 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0046] Fig. 20 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0047] Fig. 21 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0048] Fig. 22 is a cross-sectional view showing a semiconductor package according to the fifth embodiment.

[0049] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0050] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0051] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0052] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0053] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0054] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0055] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0056] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may contain various semiconductor elements.

[0057] The semiconductor device may include active components and / or passive components. The active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above-mentioned components.

[0058] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0059] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0060] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0061] Figure 1 is a conceptual diagram of a circuit board according to an embodiment.

[0062] First, the circuit board includes an insulating layer (110) and wiring (120). Referring to FIG. 1, the insulating layer (110) includes an upper surface for mounting a semiconductor element, a lower surface (110B) corresponding to the upper surface and for connecting the circuit board (CB) to a main board, etc., and may have a structure in which a plurality of insulating layers (111, 112) are laminated between the upper surface and the lower surface. The upper insulating layer (112) constituting the upper surface of the circuit board and the lower insulating layer (112) constituting the lower surface of the circuit board may be referred to as an outer laminated region, and the region laminated between the upper insulating layer and the lower insulating layer may be referred to as an inner laminated region.

[0063] The wiring (120) is arranged for electrical connection between the main board, etc. and the semiconductor element (SD), and includes a circuit pattern (or circuit pattern layer), pad, and via electrode. The wiring may correspond to an electrode portion or electrode. In addition, the circuit pattern may be designed in various forms for signal and / or power transmission with the semiconductor element (SD), and is arranged within each vertically stacked insulating layer (110).

[0064] Via electrodes (121b, 122b) are arranged to penetrate a portion of each insulating layer for vertical connection between circuit patterns arranged on each vertically stacked insulating layer. That is, the insulating layer may include via holes (V1, V2) for arrangement of the via electrodes. In addition, the via electrodes may have a wider width than the circuit patterns for impedance optimization or heat dissipation, but the present invention is not limited thereto and may be freely designed.

[0065] The pads (121a, 122a) may include an outer pad (122a) arranged in an outer laminated region and an inner pad (121a) arranged in an inner laminated region. The outer pad (122a) functions to be bonded to a semiconductor device (SD) and / or a main board (CB). Currently, it can be bonded with solder, wire, conductive adhesive, etc., but may be arranged with a width larger than the width of the circuit pattern to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process. The inner pad (121a) functions to connect the via electrode and the circuit pattern. When the via electrode is arranged with a width wider than the circuit pattern, a pad with a width wider than the circuit pattern is provided for positional alignment during the manufacturing process of the via electrode to be arranged on each circuit pattern. Accordingly, each via electrode may have an upper surface that is flush with the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is flush with the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0066] The circuit board may further include a protective layer (113). The protective layer (113) may function to protect the pad from external moisture or contaminants, and may be formed of a solder resist, for example, to prevent a short circuit problem when bonding the semiconductor element and / or the main board and the circuit board. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (113) may be formed of a material that has insulating properties for electrical connection. Accordingly, the protective layer (113) may be referred to as an 'insulating layer' and may be a component of the above-described insulating layer (110).

[0067] And the insulating layer (112) or protective layer (113) located in the outer laminated area of ​​the circuit board may have an opening (OP). It may be electrically connected to other semiconductor elements or a circuit board, etc., through the opening (OP).

[0068] Circuit boards can be divided into package boards and interposers based on their function. The package board serves the function of mounting semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, to improve the yield of circuit boards with a high number of layers, the yield of the circuit board can be improved by separating them into an interposer and a package board. In addition, as the terminal density of semiconductor devices increases, it can be difficult to implement pads on the package board with an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package board can act as a buffer between the size of the pad and the fine pattern size of the terminals of the semiconductor devices.

[0069] The package substrate and interposer described above can be classified into core substrates and coreless substrates, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0070] The insulating layer of the circuit board is formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The aforementioned optional insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, a reinforcing material such as glass fiber or aramid fiber can be included.

[0071] FIG. 2 is a drawing of a circuit board according to the first embodiment, FIG. 3 is an enlarged view of a portion of FIG. 2, FIG. 4 is a drawing explaining the formation of a circuit pattern layer and nano particles according to the embodiment, and FIG. 5 is a drawing explaining the structure of a circuit pattern layer and nano particles in a circuit board according to the embodiment.

[0072] Referring to FIG. 2, a circuit board (100A) according to an embodiment may include an insulating layer (110), an electrode portion (120), and nano particles (130). In each embodiment, the insulating layer and the electrode portion may be applied as described above in FIG. 1, except for the description below.

[0073] A circuit board (100A) according to an embodiment may include a circuit pattern and nanoparticles (130) arranged on pads. In the circuit board according to an embodiment of the present invention, the circuit pattern layer may be a concept including the circuit pattern and pads described in FIG. 1. In addition, in the embodiment, the nanoparticles (130) may be arranged on the circuit pattern layer.

[0074] The insulating layer (110) may be formed of an insulating material. The insulating layer (110) may be formed of at least one layer. When the insulating layer (110) has a multi-layer structure, the insulating layers (110) of the multiple layers may include the same insulating material, but are not limited thereto. For example, at least one insulating layer (110) among the multiple layers of insulating layers (110) may include an insulating material different from at least one other insulating layer (110).

[0075] The insulating layer (110) of the circuit board (100) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100) may include glass or plastic. For example, the insulating layer (110) of the circuit board may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the substrate may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the substrate may include an optically isotropic film. For example, the insulating layer (110) of the substrate may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), photoisotropic polycarbonate (PC), or photoisotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the substrate may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the substrate may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0076] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0077] In one embodiment, the insulating layer (110) may include a core layer or a coreless layer including a reinforcing member. Here, the core layer may refer to an insulating layer including a reinforcing member and having a thickness in the lamination direction (X-axis direction) exceeding 30 μm. In addition, the insulating layer may include a plurality of layers that are respectively disposed on the upper and lower portions of the core layer and do not include a reinforcing member. In this case, the circuit board may be a core board. The reinforcing member may also be referred to as reinforcing fiber or glass fiber.

[0078] Reinforcing member may mean a glass fiber material extending along the horizontal direction of the insulation layer and may have a different meaning from the spaced filler.

[0079] In another embodiment, the insulating layer (110) of the substrate may be a coreless substrate that does not include a core layer. For example, the insulating layer (110) of the substrate may include an organic material that does not include a reinforcing member that has excellent processability, enables slimming of the substrate, and enables miniaturization of the electrode layer of the substrate. For example, the insulating layer (110) of the substrate may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0080] As an example, the insulating layer (110) may include a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113). The second insulating layer (112) may be disposed on the first insulating layer (111), and the third insulating layer (113) may be positioned on the second insulating layer (112).

[0081] The first insulating layer (111) may include an insulating material as an inner layer laminated region in the circuit board (100A). The first insulating layer (111) may be composed of multiple layers, and the multiple layers may be composed of the same or different materials. The boundary surface of the first insulating layer (111) and the second insulating layer (112) on top may or may not be distinguished depending on the analysis method. In addition, the third insulating layer (113) may be a protective layer or a resist layer.

[0082] Additionally, the first insulating layer (111) may be positioned between the upper and lower second insulating layers (112). The second insulating layer (112) may be positioned on the upper and lower surfaces of the first insulating layer (111).

[0083] In the circuit board (110A), the outer layer laminated region may include a second insulating layer (112). Furthermore, in the circuit board (110A), the outer layer laminated region may further include a third insulating layer (113). That is, the outer layer laminated region is a region other than the inner layer laminated region, and may correspond to a region other than the first insulating layer (111).

[0084] Furthermore, the third insulating layer (113) may be positioned on the upper surface of the second insulating layer (112) or the lower surface of the second insulating layer (112). The following description will be based on the lamination direction (X-axis direction).

[0085] Additionally, as described above, in the outer laminated region, the third insulating layer (113) may be a resist layer. For example, the third insulating layer (113) of the substrate may be a resist layer disposed on the uppermost side of the substrate.

[0086] The third insulating layer (113) may be a solder resist layer containing an organic polymer material. For example, the third insulating layer (113) of the circuit board may contain a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. In an embodiment, the third insulating layer (113) may be any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0087] Additionally, the third insulating layer (113) located on the upper side may have an opening (OP). Through the opening (OP), it may be electrically connected to other semiconductor elements, circuit boards, etc. However, if the second insulating layer is on the outside of the circuit board and there is no third insulating layer (113), the second insulating layer may have an opening.

[0088] In addition, as a variation, both the second insulating layer (112) and the third insulating layer (113) may be an insulating layer disposed on the inside of the substrate or a resist layer disposed on the outside. Such a resist layer may have a function of preventing solder flow during solder bonding by having a low solder wettability characteristic, or may have a function of preventing moisture or contaminants from the outside from penetrating into the inside of the circuit board.

[0089] And the electrode layer (120) may include a first electrode layer (121) and a second electrode layer (122). The first electrode layer (121) may include a first circuit pattern layer (121a) and a first through-electrode (121b). The second electrode layer (122) may include a second circuit pattern layer (122a) and a second through-electrode (122b). Each circuit pattern layer may mean including a pad and / or trace of the electrode layer and a circuit pattern. The through-electrode may mean a via electrode connected to the circuit pattern layer. For example, the through-electrode may be disposed between a plurality of circuit pattern layers disposed on different layers.

[0090] The first circuit pattern layer (121a) can be arranged on the upper and lower surfaces of the first insulating layer (111). The first through-electrode (121b) can penetrate the first insulating layer (111) and come into contact with the first circuit pattern layer (121a).

[0091] The second circuit pattern layer (122a) can be arranged on the upper and lower surfaces of the second insulating layer (112). The second through-electrode (122b) can penetrate the second insulating layer (112) and come into contact with the second circuit pattern layer (122a).

[0092] Nanoparticles (130) may be positioned on each circuit pattern layer of the electrode layer (120). Specifically, the electrode layer (120) may include first nanoparticles (131) and second nanoparticles (132). The first nanoparticles (131) may be positioned on the first circuit pattern layer (121a). Accordingly, the first nanoparticles (131) may be positioned between the first circuit pattern layer (121a) and the second insulating layer (112). In addition, the first nanoparticles (131) may be positioned between the first circuit pattern layer (121a) and the second through-electrode (122b). And the second nanoparticles (132) may be positioned between the second circuit pattern layer (122a) and the third insulating layer (113). In addition, the second nanoparticles (132) may be positioned in the openings (OP) on the second circuit pattern layer (122a).

[0093] And the first insulating layer (111) and the second insulating layer (112) may include vias or through holes (V1, V2). The through holes may include a first through hole (V1) penetrating the first insulating layer (111) and a second through hole (V2) penetrating the second insulating layer (112). And through electrodes may be positioned in the through holes (V1, V2) as described above. For example, a first through electrode (121b) may be positioned in the first through hole (V1). A second through electrode (122b) may be positioned in the second through hole (V2).

[0094] In addition, the second insulating layer (112) can cover at least a portion of the first circuit pattern layer (121a). At this time, the first nanoparticle (131) can also be positioned within the second through hole (V2) of the second insulating layer (112). Accordingly, the first nanoparticle (131) can overlap not only the second insulating layer (112) but also the second through hole (V2 (or the second through electrode) in the stacking direction (X-axis direction).

[0095] Furthermore, the first through hole (V1) or the first through electrode (121b) may overlap with the first nano particle (131) or the second nano particle (132) on the upper side in the stacking direction (X-axis direction).

[0096] In addition, the third insulating layer (113) may cover at least a portion of the second circuit pattern layer (122a). The third insulating layer (113) may include an opening (OP) for electrical connection with a semiconductor element, an interposer, etc. The second circuit pattern layer (122a) may be exposed by the opening (OP). Furthermore, the second nanoparticles (132) described later may also be exposed by the opening (OP). That is, the second nanoparticles (132) may be positioned within the openings (OP) of the third insulating layer (113). Accordingly, the openings (OP) overlap the second nanoparticles (132) in the stacking direction (X-axis direction), so that the bonding strength and conductivity with a material such as solder may be further improved.

[0097] In addition, when the opening (OP) and the first and second through holes overlap along the stacking direction, the nano particles may overlap with the opening and the first and second through holes. For example, when the first circuit pattern layer (122a) and the second circuit pattern layer (122a) are positioned to overlap with the first through hole (V1) and the opening (OP) in the stacking direction, the first nano particle (131) may at least partially overlap with the second nano particle (132), the opening (OP), the second through hole (V2), and the first through hole (V1) in the stacking direction.

[0098] The first nanoparticle (131) and the second nanoparticle (132) come into contact with the first and second circuit pattern layers (121a, 122a) and the second and third insulating layers (112, 113), thereby improving the bonding force or adhesion between the first and second circuit pattern layers (121a, 122a) and the second and third insulating layers (112, 113).

[0099] Referring further to FIG. 3, a circuit pattern layer (121a (122a)) may be arranged on the upper surface (US) of each insulating layer (111 (112)). The lower surface (S1 (S3)) of the circuit pattern layer (121a (122a)) may be in contact with the upper surface of the lower insulating layer (111 (112)). In addition, the upper insulating layer (112 (113)) may cover the circuit pattern layer (121a (122a)) and the nanoparticles (131 (132)).

[0100] The circuit pattern layer (121a (122a)) may be formed of a material having electrical conductivity. For example, the circuit pattern layer (121a (122a)) may be a wiring that transmits an electrical signal. The circuit pattern layer (121a (122a)) may be formed of a first metal that is a metal material having high electrical conductivity. The circuit pattern layer (121a (122a)) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the circuit pattern layer (121a (122a)) may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the circuit pattern layer (121a (122a)) can be formed of copper (Cu) which has high electrical conductivity and is inexpensive.

[0101] The insulating layer (111 (112)) may include a through hole or via or an opening. The circuit pattern layer (121a (122a)) may be electrically connected to a circuit pattern layer disposed on a different surface or layer through the through hole of the insulating layer (111 (112)). The description of this circuit pattern layer may be equally applied to the circuit pattern layer described below.

[0102] The nanoparticle (131 (132)) may be in contact with the surface of the circuit pattern layer (121a (122a)). For example, the nanoparticle (131 (132)) may be located on the surface of the circuit pattern layer (121a (122a)). And the nanoparticle (131 (132)) may include a second metal. In other words, the nanoparticle (131 (132)) may be made of a second metal, and the second metal may have a higher electronegativity than the first metal. In other words, the second metal may have a lower oxidation degree than the first metal.

[0103] As an example, the nanoparticles (131 (132)) may be positioned on the upper surface (S2 (S4)) and the side surface (S0 (S5)) of the circuit pattern layer (121a (122a)). The nanoparticles (131 (132)) may be positioned on the upper and side surfaces of the circuit pattern layer (121a (122a)) and may be covered by the upper insulating layer (112 (113)). There may be a plurality of nanoparticles (131 (132)). The nanoparticles may have a round or circular shape with a diameter of 2 nm to 30 nm.

[0104] Nanoparticles (131 (132)) are positioned between the upper insulating layer (112 (113)) and the circuit pattern layer (121a (122a)), and can improve the bonding strength between the upper insulating layer (112 (113)) and the circuit pattern layer (121a (122a)). By this configuration, the reliability of the circuit board according to the embodiment can be improved.

[0105] Furthermore, the nanoparticles (131 (132)) may overlap with the circuit pattern layer (121a (122a)) in the stacking direction (X-axis direction). In addition, the nanoparticles (131 (132)) may overlap with each insulating layer in the stacking direction. In addition, the nanoparticles (131 (132)) may overlap with the circuit pattern layer (121a (122a)) or the upper insulating layer (112 (113)) in the horizontal direction (direction perpendicular to the stacking direction) in the drawing. In addition, the nanoparticles (131 (132)) may be positioned in the via hole or opening (OP) of the upper insulating layer (112 (113)). Therefore, the nanoparticles (131 (132)) may at least partially overlap with the via hole or opening (OP) of the upper insulating layer (112 (113)).

[0106] In addition, the circuit pattern layer (121a (122a)) may have a rough structure on a surface (top surface S2 (S4) and side surface S0 (S5)) other than the surface in contact with the lower insulating layer (111 (112)). That is, the circuit pattern layer (121a (122a)) may have a protrusion (PT) arranged on the surface. In other words, the surface of the circuit pattern layer (121a (122a)) may have a predetermined roughness. For example, the circuit pattern layer (121a (122a)) may have a roughness (Ra) of several μm or less on the surface. In addition, the surface area of ​​the upper surface of the circuit pattern layer (121a (122a)) may increase, so that the bonding area for the insulating layer in contact with the circuit pattern layer may increase. As a result, the bonding strength between the circuit pattern layer and the insulating layer may increase, thereby providing a circuit board with improved reliability.

[0107] And the upper surface (S2 (S4)) of the circuit pattern layer (121a (122a)) may correspond to the first surface. And the side surface (S0 (S5)) of the circuit pattern layer (122a) may correspond to the third surface. In addition, the lower surface (S1 (S3)) of the circuit pattern layer (122a) may correspond to the second surface.

[0108] Referring further to FIG. 4, the following describes the contents of each insulating layer, nanoparticle, and circuit pattern layer based on the second insulating layer (112), the third insulating layer (113), the second nanoparticle (132), and the second circuit pattern layer (122a).

[0109] The second nanoparticles (132) may be positioned on the upper portion of the second circuit pattern layer (122a). The second nanoparticles (132) may be positioned in multiple regions corresponding to the surface shape of the second circuit pattern layer (122a).

[0110] The second nanoparticle (132) according to the embodiment may be formed by a corrosion solution or etchant on the circuit pattern layer (122a'). That is, the second nanoparticle according to the embodiment may be a result of etching the circuit pattern layer (122a') with an etchant.

[0111] More specifically, the second nanoparticles (132) may be made of a second metal as described above. The etchant may also be made of the second metal. In this case, the etchant may include ions of the second metal.

[0112] The second nanoparticle (132) can be formed by an oxidation-reduction reaction between the second metal (ion) of the etchant and the first metal of the circuit pattern layer (122a').

[0113] For example, the second nanoparticle (132) or the second metal may be made of silver (Ag). And the second circuit pattern layer (122a) or the first metal may be made of copper (Cu).

[0114] And when an etchant containing silver ions is applied to a circuit pattern layer (122a) made of copper (Cu), nanoparticles (silver nanoparticles) can be formed on the surface of the circuit pattern layer through an oxidation-reduction reaction according to Equations 1 to 3 below.

[0115] [Formula 1]

[0116]

[0117] [Formula 2]

[0118]

[0119] [Formula 3]

[0120]

[0121] Equation 3 can be the overall reaction equation combining Equations 1 and 2. And Cu(s) corresponds to the circuit pattern layer, and 2Ag + corresponds to etchant, and 2Ag(s) can correspond to nanoparticles.

[0122] Furthermore, silver nanoparticles exhibit high electrical conductivity, allowing them to maintain the electrical performance of the circuit pattern layer. Furthermore, the second metal (silver) has a lower oxidation rate than the first metal (copper), preventing electrical performance degradation due to oxides and reliability issues caused by oxide separation. In other words, the second metal can provide physically stable, enhanced reliability.

[0123] Furthermore, the second metal (e.g., silver) can form a coordination bond with a highly electronegative reactive group within the insulating layer, thereby providing improved compatibility between materials.

[0124] In addition, since the nanoparticles have a round shape and are positioned on the protrusions or uneven structures, the nanoparticles and the circuit pattern portion can provide an enhanced surface area when bonded to the second insulating layer. Accordingly, the nanoparticles and the circuit pattern portion can be bonded to the second insulating layer with enhanced adhesion. In addition, the nanoparticles and the circuit pattern portion have an enhanced surface area to volume ratio, and can form a stronger bond with highly electronegative carboxyl groups and the like within the second insulating layer.

[0125] In addition, nanoparticles can be evenly distributed and positioned or formed on the surface of the circuit pattern layer without lumps, thereby providing higher adhesion or bonding strength while maintaining the roughness of the surface of the circuit pattern layer.

[0126] The description of the second nanoparticles and the second circuit pattern layer can be equally applied to the first nanoparticles and the first circuit pattern layer.

[0127] Referring to FIG. 5, the circuit pattern layer (122a) may have a smaller crystal grain size from the lower surface (S3) to the upper surface (S4). This is because crystal growth starts from the upper surface of the first insulating layer. As an example, the circuit pattern layer (122a) may include a first region (AR1) and a second region (AR2). The first region (AR1) is a region spaced apart from the second insulating layer (112) and adjacent to the third insulating layer (113). The second region (AR2) may be an region adjacent to the second insulating layer (112). Alternatively, the first region (AR1) and the second region (AR2) may be respective regions that are divided (e.g., bisected) in the stacking direction of the circuit pattern layer (122a).

[0128] Since the grain size of the first region (AR1) is smaller than that of the second region (AR2), the grain boundaries (or grain boundaries, gaps) of the first region (AR1) may be larger than those of the second region (AR2). In other words, the number of grain boundaries and grains per unit volume of the first region (AR1) may be larger than that of the second region (AR2).

[0129] Accordingly, the first region (AR1) may be formed with a greater roughness than the second region (AR2), and may have more grain boundaries than the second region (AR2), and thus may have a higher relative energy than the second region. In addition, the first surface or top surface (S4) may have more grain boundaries than the side surface (S5) (or third surface).

[0130] And since the etchant diffuses into the grain boundaries, the amount (or ratio) of the second nanoparticles (132) per unit area (or volume, area) on the first surface may be greater than the amount (or ratio) per unit area (or volume, area) on the third surface.

[0131] Similarly, the amount (or ratio) of the second nanoparticles (132) per unit area (or volume, region) in the first region may be greater than the amount (or ratio) per unit area (or volume, region) in the second region.

[0132] Additionally, the amount (or ratio) of the second nanoparticles (132) to the area (or volume, area) may vary in response to the number (or ratio) of grain boundaries. For example, if the number (or ratio) of grain boundaries to the area (or volume, area) increases, the amount (or ratio) of the second nanoparticles (132) to the area (or volume, area) may increase.

[0133] Alternatively, the amount (or ratio) of the second nanoparticle (132) to the area (or volume, region) may vary in response to the surface energy. For example, if the surface energy increases (the surface energy increases from the second region to the first region or the surface energy increases from the side to the top), the amount (or ratio) of the second nanoparticle (132) to the area (or volume, region) may increase.

[0134] Accordingly, by improving the bonding strength between the second circuit pattern layer and the third insulating layer, the second nanoparticles (132) can provide the effect of improving the strength and performance of the circuit board. Each of the descriptions of the second circuit pattern layer, the second insulating layer, the third insulating layer, and the second nanoparticles can be applied to the first circuit pattern layer, the first insulating layer, the second insulating layer, and the first nanoparticles.

[0135] FIG. 6a and FIG. 6b are SEM (Scanning Electron Microscopy) images of a circuit pattern layer without nanoparticles, FIG. 6c and FIG. 6d are SEM images of a circuit pattern layer with nanoparticles, FIG. 7a is an SEM image of the surface of the circuit pattern layer and an EDS (Energy Dispersive Spectrometer) image of a point without nanoparticles, FIG. 7b is an SEM image of the surface of the circuit pattern layer and an EDS image of a point with nanoparticles, FIG. 8 is an XPS image of nanoparticles and a circuit pattern layer in a circuit board according to an embodiment, FIG. 9 is an SEM image of a circuit pattern layer according to the concentration of a second metal, and FIG. 10 is a result of a test explaining the reliability improvement effect of a circuit board according to an embodiment. The following images and results for each circuit pattern layer may be images and results analyzed in the absence of a second insulating layer.

[0136] Referring to FIGS. 6A and 6B, when etched with an etchant other than the second metal, the circuit pattern layer may have peaks / valleys due to the etchant. That is, the roughness may increase due to the etching.

[0137] In contrast, referring further to FIGS. 6c and 6d, nanoparticles (132) may be present on the circuit pattern layer when etched with an etchant having a second metal. As described above, the nanoparticles (132) have a round shape and may be variously located in mountains or valleys.

[0138] Referring to Fig. 7a, EDS (Energy Dispersive Spectrometer) results for points where nanoparticles exist in a circuit board according to an embodiment were obtained, with weight ratio and atomic ratio results as shown in Table 1 below.

[0139] ElementWeight%Atomic%C K5.3222.52O K0.732.31Cu L93.9575.17Totals100.00

[0140] Referring to Fig. 7b, EDS (Energy Dispersive Spectrometer) results for points where nanoparticles exist in a circuit board according to an embodiment were obtained, showing weight ratio and atomic ratio results as shown in Table 1 below.

[0141] ElementWeight%Atomic%C K5.6523.74O K0.983.11Cu L90.3371.73Ag L3.031.42Totals100.00

[0142] Looking at Tables 1 and 2 together, the presence or absence of nanoparticles on the circuit pattern portion can be determined through EDS for points where nanoparticles (132) exist. For example, when an electron beam is scanned on a circuit pattern layer and nanoparticles, electrons in atoms may absorb energy and become excited. At this time, as the excited electrons become stabilized, characteristic X-rays are emitted, and since the X-rays emitted at this time have a unique energy value for each substance, the depicted spectrum can be obtained by collecting the X-rays through a detector and classifying the X-rays. And based on the spectrum of the EDS, the weight ratio of the nanoparticles in the circuit board according to the embodiment may be smaller than that of carbon. Furthermore, the weight ratio of the nanoparticles may be smaller than that of copper. In addition, in terms of the atomic %), the nanoparticles may be smaller than that of copper. Furthermore, the atomic %) of the nanoparticles may be smaller than that of carbon and oxygen.

[0143] In addition, referring to FIG. 8, XPS (X-ray Photoelectron Spectroscopy) can be applied to nanoparticles and a circuit pattern layer in a circuit board according to an embodiment. That is, X-rays are used as a light source for nanoparticles and a circuit pattern layer in a circuit board, and binding energy can be measured through the kinetic energy of photoelectrons emitted from the surface of the nanoparticles and the circuit pattern layer as samples.

[0144] Table 3 below shows the results of XPS Quantitative Analysis for examples and comparative examples. Figure 8 and Table 3 show the results obtained with an X-ray beam size of 15 kV and 100 μm.

[0145] NosampleC 1O 1sN 1sCu 2pAg 3d1Example38.631.50.926.82.22Comparative Example37.736.22.223.9<0.1

[0146] Referring further to Table 3, etc., the embodiment (circuit pattern layer with nanoparticles) may have a larger amount of silver (Ag) than the comparative example (circuit pattern layer without nanoparticles). As such, in the circuit board according to the embodiment, the element ratio of nanoparticles may be smaller than that of carbon based on the spectrum and results of XPS. Referring further to Fig. 9, Fig. 9a is an SEM photograph when an etchant without a second metal is applied, and Figs. 9b to 9d are SEM photographs when the concentration of the second metal (e.g., silver) in the etchant is 0.05 ppm, 0.2 ppm, and 0.3 ppm, respectively.

[0147] In this way, the amount of nanoparticles in the circuit board according to the embodiment can increase in response to the concentration of the second metal (e.g., Ag) in the etchant. However, the difference in the size of the nanoparticles was found to be similar depending on the concentration.

[0148] Referring further to Fig. 10, Comparative Examples 1 and 2 are results obtained when the circuit pattern layer was etched with an etchant other than the second metal. The Examples are results obtained when the circuit pattern layer was etched with an etchant made of the second metal.

[0149] The roughness of the circuit pattern layer may be smaller in the presence of nanoparticles (the embodiment) than in the comparative example. By reducing this roughness, signal transmission can be facilitated in the circuit board according to the embodiment.

[0150] Furthermore, it can be seen that, despite the decrease in illuminance as described above, the peel strength for the second insulating layer increases or is maintained in the case of the example compared to the comparative example. Accordingly, it can be seen that the reliability of the circuit board is improved.

[0151] Fig. 11 is a drawing showing the manufacturing sequence of a circuit board according to an embodiment.

[0152] Referring to Fig. 11(a), in the embodiment, a second insulating layer (112) is prepared. The second insulating layer (112) may be a core layer or a coreless layer. Alternatively, it may be an insulating layer disposed on top of the inner layer laminate region as described above.

[0153] Although the description of this manufacturing sequence is based on the second insulating layer, if the first insulating layer described above is a core layer, the first insulating layer may be a copper clad laminate (CCL). Furthermore, a process may be performed to form a through hole penetrating the second insulating layer (112). Although not illustrated, the through hole may be formed and filled with a conductive material.

[0154] A circuit pattern layer (122a') may be laminated on the upper and lower surfaces of the second insulating layer (112). The circuit pattern layer (122a') may have various patterns using a dry film or the like.

[0155] Referring to Fig. 11(b), when etching is performed using an etchant including a second metal, a circuit pattern layer (122a) may be formed in a predetermined pattern on the second insulating layer (112). Accordingly, a portion of the second insulating layer (112) may be exposed or opened. In addition, the circuit pattern layer (122a) may have a predetermined roughness formed on the surface by etching or may have a protrusion (PT). In addition, nanoparticles (132) may exist on the surface of the circuit pattern layer (122a).

[0156] Referring to Fig. 11(c), a second insulating layer (113') may be formed on top of the nanoparticles (132) to cover the nanoparticles (132) and the circuit pattern layer (122a). Heat and pressure may be applied. Accordingly, the second insulating layer, the nanoparticles (132), the circuit pattern layer (122a), and the second insulating layer (112) may be bonded to each other. Depending on the position of the second insulating layer on the circuit board, it may be a solder resist layer or an insulating layer.

[0157] Fig. 12 is a plan view of a circuit board according to the first embodiment, Fig. 13 is an enlarged view of K1 in Fig. 11, and Fig. 14 is an enlarged view of K2 in Fig. 11.

[0158] In addition, as described above, the first circuit pattern layer (121a) according to the embodiment may include a first surface (S1), a second surface (S2), and a third surface (S0), which is a side surface. The first surface (S1) may be in contact with the first insulating layer (111). For example, the first through-electrode (121b) may be in contact with the first surface (S1) of the first circuit pattern layer (121a). The second surface (S2) may face the first surface (S1) and may be in contact with the second insulating layer (112). In addition, the third surface (S0) may be located between the first surface (S1) and the second surface (S2) and may correspond to the side surface of the first circuit pattern layer (121a).

[0159] As described above, the second surface (S2) and the third surface (S3) of the first circuit pattern layer (121a) may include a rough structure or a protrusion. In addition, the first nanoparticles (131) may be disposed on the second surface (S2) and the third surface (S3). For example, the first nanoparticles (131) may be disposed on the entire area including the area where the second through-electrode (122b) is disposed on the second surface (S2). In addition, the first nanoparticles (131) may also be disposed on the third surface (S3) that is in contact with the second insulating layer (112). As a result, the bonding strength between the second insulating layer (112) and the first electrode layer (121) may be further improved.

[0160] And the second circuit pattern layer (122a) may include a third surface (S3), a fourth surface (S4), and a fifth surface (S5). The third surface (S3) may be in contact with the second insulating layer (112). For example, the second through-electrode (122b) may be in contact with the third surface (S3) of the second circuit pattern layer (122a). The fourth surface (S4) may face the third surface (S3) and may be in contact with the third insulating layer (113). The fifth surface (S5) may be disposed between the third surface (S3) and the fourth surface (S4) and may correspond to a side surface of the second circuit pattern layer (122a).

[0161] Furthermore, the fourth surface (S4) and the fifth surface (S5) of the second circuit pattern layer (122a) may include a rough structure or a protrusion. The second nanoparticles (132) may be disposed on the fourth surface (S4) and the fifth surface (S5). Accordingly, the second nanoparticles (132) may be in contact with the fourth surface (S4) and the fifth surface (S5). For example, the second nanoparticles (132) may be disposed in the entire area including the area of ​​the opening (OP) on the fourth surface (S4). In addition, the second nanoparticles (132) may be disposed in an area in contact with the third insulating layer (113) on the fifth surface (S5). As a result, the bonding strength between the third insulating layer (113) and the second electrode layer (122) may be further enhanced.

[0162] Fig. 15 is a drawing of a circuit board according to the second embodiment.

[0163] Referring to FIG. 15, a circuit board (100B) according to the second embodiment may include an insulating layer (110), an electrode layer (120), and nano particles (130). Except for the contents described below, the description of the insulating layer, electrode layer, and nano particles described above may be applied to the insulating layer (110), the electrode layer (120), and the nano particles (130).

[0164] According to the present embodiment, only the second nanoparticle (132) may exist among the nanoparticles (130). That is, the first nanoparticle may not be present on the first circuit pattern layer (121a). And the nanoparticle (130) may be located on the second circuit pattern layer (122a).

[0165] By this configuration, the second nanoparticle (132) is placed between the third insulating layer (113) and the second circuit pattern layer or the second electrode layer (122), thereby improving the bonding strength between the third insulating layer (113) and the second circuit pattern layer or the second electrode layer (122).

[0166] In addition, the second nanoparticle (132) is also located within the opening (OP) of the third insulating layer (113), so that electrical connection with other elements can be easily achieved.

[0167] Fig. 16 is a drawing of a circuit board according to the third embodiment.

[0168] Referring to FIG. 16, a circuit board (100C) according to the third embodiment may include an insulating layer (110), an electrode layer (120), and nano particles (130). Except for the contents described below, the description of the insulating layer, electrode layer, and nano particles described above may be applied to the insulating layer (110), the electrode layer (120), and the nano particles (130).

[0169] According to the present embodiment, only the first nanoparticle (131) may be present among the nanoparticles (130). That is, the second nanoparticle may not be present on the second circuit pattern layer (122a). In addition, the nanoparticle (130) may be positioned on the first circuit pattern layer (121a).

[0170] By this configuration, the first nanoparticle (131) is placed between the second insulating layer (112) and the first circuit pattern layer or the first electrode layer (121), thereby improving the bonding strength between the second insulating layer (112) and the first circuit pattern layer or the first electrode layer (121).

[0171] Fig. 17 is a drawing of a circuit board according to the fourth embodiment.

[0172] A circuit board (100D) according to the fourth embodiment may include an insulating layer (110), an electrode layer (120), and nanoparticles (130). Except for the contents described below, the description of the insulating layer, electrode layer, and nanoparticles described above may be applied to the insulating layer (110), the electrode layer (120), and the nanoparticles (130).

[0173] According to the present embodiment, the nanoparticles (130) may include first nanoparticles (131) and second nanoparticles (132). The nanoparticles (130) according to the present embodiment may be positioned on the surfaces of the first circuit pattern layer (121a) and the second circuit pattern layer (122a) like the nanoparticles in the circuit board according to the first embodiment. That is, the nanoparticles (130) may be positioned to overlap or overlap between the first circuit pattern layer (121a) and the second insulating layer (112), between the first circuit pattern layer (121a) and the second through-electrode (122b), between the first or second circuit pattern layer (122a) and the third insulating layer (113), and with the opening (OP) of the third insulating layer (113) in the lamination direction. By this configuration, the first nanoparticle (131) and the second nanoparticle (132) can improve the bonding force between the second insulating layer (112) and the first circuit pattern layer (or the first electrode layer (121)) or the bonding force between the third insulating layer (113) and the second circuit pattern layer (or the second electrode layer (122)).

[0174] However, in the present embodiment, the nanoparticles (130) may be arranged in some areas on the surfaces of the first circuit pattern layer (121a) and the second circuit pattern layer (122a). As an example, the nanoparticles (130) may be positioned between the insulating layer and the circuit pattern layer corresponding to the quantity or area of ​​the circuit pattern layer or the through hole. For example, the nanoparticles (130) may be arranged between the insulating layer in contact with the electrode layer on which a plurality of circuit pattern layers are arranged. For example, when the number of circuit pattern layers or the area of ​​the circuit pattern layers is larger on the second electrode layer than on the first electrode layer, more nanoparticles may be arranged on the second electrode layer than on the first electrode layer to improve the bonding strength. This makes it possible to prevent a decrease in the bonding strength between the insulating layer and the circuit pattern layer depending on the arrangement of the circuit pattern layers.

[0175] Furthermore, a large number of nanoparticles can be arranged on an electrode layer with multiple through-electrodes. Accordingly, the bonding strength between the circuit pattern layer and the insulating layer can be enhanced.

[0176] FIG. 18 is a cross-sectional view showing a semiconductor package according to the first embodiment, FIG. 19 is a cross-sectional view showing a semiconductor package according to the second embodiment, FIG. 20 is a cross-sectional view showing a semiconductor package according to the third embodiment, FIG. 21 is a cross-sectional view showing a semiconductor package according to the fourth embodiment, and FIG. 22 is a cross-sectional view showing a semiconductor package according to the fifth embodiment.

[0177] In the various semiconductor packages described below, the circuit board described above may be located in some area or may correspond to one substrate.

[0178] Referring to FIG. 18, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor element (1300).

[0179] The first substrate (1100) may mean or include a 'package substrate' or a 'circuit substrate'. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate (1100).

[0180] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space in which at least one semiconductor element is mounted.

[0181] The first substrate (1100) may include at least one insulating layer and an electrode portion disposed on at least one insulating layer.

[0182] A second substrate (1200) may be placed on the first substrate (1100).

[0183] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0184] In Fig. 18, two semiconductor elements (1310, 1320) are illustrated as being arranged on a second substrate (1200), but this is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0185] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate (1100).

[0186] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate (1100) and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. Unlike passive devices, the characteristics of current and voltage may not be linear in the case of an active device, and the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first substrate (1100).

[0187] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for connection with the semiconductor element (1300) and the main board, respectively, there is a problem that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complicated. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor element (1300). In addition, the second substrate (1200) can include electrodes having a micro width and spacing corresponding to the terminals of the semiconductor element (1300).

[0188] The semiconductor device (1300) may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above-mentioned. And the memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0189] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0190] For example, a semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) may electrically connect the second substrate (1200) to the first substrate (1100) while bonding them thereto.

[0191] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0192] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate (1100). The third connector (1430) may electrically connect the first substrate (1100) to the main board while connecting them therebetween.

[0193] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0194] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a metal layer formed between the plurality of components by recrystallization.

[0195] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0196] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420) and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the insulating layer of the corresponding substrate. The protrusion may protrude outward from the first substrate (1100) or the second substrate (1200).

[0197] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0198] Additionally, looking further into FIG. 19, the semiconductor package of the second embodiment may further include a connecting member (1210).

[0199] The connecting member (1210) may be referred to as a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) may have a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device should have is generally too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0200] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0201] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be placed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements placed on the second substrate (1200).

[0202] Referring to FIG. 20, the semiconductor package of the third embodiment may include a second substrate (1200) and a semiconductor element (1300). At this time, the semiconductor package of the third embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0203] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0204] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0205] Referring to FIG. 21, the semiconductor package of the fourth embodiment may include a first substrate (1100) and a semiconductor element (1300).

[0206] At this time, the semiconductor package of the fourth embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0207] That is, the first substrate (1100) of the third embodiment can function as a package substrate while also connecting a semiconductor element (1300) and a main board. To this end, the first substrate (1100) can include a connecting member (1110) for connecting a plurality of semiconductor elements. The connecting member (1110) can be an organic bridge connecting a plurality of semiconductor elements.

[0208] Referring to FIG. 22, the semiconductor package of the fifth embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the fourth embodiment. To this end, a fourth connecting portion may be further arranged on one surface of the first substrate (1100).

[0209] In this way, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on the upper and lower sides, respectively. In this case, the third semiconductor element (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the semiconductor package of FIG. 19.

[0210] And a connecting member (1110) can be embedded in the first substrate (1100). The connecting member (1110) can horizontally connect the first and second semiconductor elements (1310, 1320).

[0211] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may further protrude from the first substrate (1100) toward the second semiconductor element (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, as a post. The conductive coupling portion (1450) may be positioned with a protruding structure on an electrode positioned on the uppermost side of the first substrate (1100).

[0212] A third semiconductor element (1330) may be placed on the conductive joint (1450). At this time, the third semiconductor element (1330) may be connected to the first substrate (1100) through the conductive joint (1450). In addition, a second connection (1420) may be placed between the first and second semiconductor elements (1310, 1320) and the third semiconductor element (1330).

[0213] Accordingly, the third semiconductor element (1330) can be electrically connected to the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0214] That is, the third semiconductor element (1330) can be connected to the first substrate (1100) through the conductive joint (1450), and can also be connected to the first and second semiconductor elements (1310, 1320) through the second connection (1420).

[0215] At this time, the third semiconductor element (1330) can receive a power signal and / or electric power through the conductive coupling portion (1450). In addition, the third semiconductor element (1330) can exchange communication signals with the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0216] The semiconductor package of the fifth embodiment can provide sufficient power for driving the third semiconductor element (1330) or enable smooth control of power operation by supplying a power signal and / or power to the third semiconductor element (1330) through the conductive coupling portion (1450).

[0217] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor element (1330). That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor element (1330). Furthermore, the embodiment can provide at least one of the power signal, power, and communication signal of the third semiconductor element (1330) through different paths via the conductive coupling portion (1450) and the second connection portion (1420). Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0218] Meanwhile, the third semiconductor element (1330) in the fifth embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be placed on the first substrate (1100). For example, the third semiconductor element (1330) may be a memory package including a memory chip. And the memory package may be coupled on the conductive joint (1450). At this time, the memory package may not be connected to the first and second semiconductor elements (1310, 1320).

[0219] Furthermore, the semiconductor package of the modified example may include a first substrate (1100) and first and second semiconductor elements (1310, 1320) disposed on the first substrate (1100) in FIG. 18. Furthermore, the semiconductor package may include a first connection portion (1410) disposed between the first substrate (1100) and the first and second semiconductor elements (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in FIG. 18.

[0220] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0221] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0222] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0223] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulation layer; A first circuit pattern layer disposed on at least one of the upper and lower surfaces of the first insulating layer and including a first metal; A first nano particle in contact with the surface of the first circuit pattern layer and including a second metal; and A second insulating layer covering the first circuit pattern layer; A circuit board wherein the second metal has a higher electronegativity than the first metal.

2. In paragraph 1, The above first circuit pattern layer is, A first surface in contact with the first insulating layer; A second surface in contact with the second insulating layer and facing the first surface; and A third side is disposed between the first side and the second side; The circuit board in which the first nano particle is in contact with the first surface and the third surface.

3. In paragraph 2, A circuit board wherein the amount of the first nanoparticle per unit area on the first surface is greater than the amount of the first nanoparticle per unit area on the third surface.

4. In paragraph 2, A circuit board comprising: a first region adjacent to the second insulating layer; and a second region adjacent to the first insulating layer.

5. In paragraph 4, A circuit board wherein the amount of the first nanoparticles per unit area of ​​the third surface in the first region is greater than the amount of the first nanoparticles per unit area of ​​the third surface in the second region.

6. In paragraph 4, The above first region is a circuit board having a larger grain size than the above second region.

7. In paragraph 4, A circuit board in which the first region has a smaller grain boundary than the second region.

8. In paragraph 1, A circuit board in which the first nanoparticles are formed by an oxidation-reduction reaction between the second metal and the first metal of the first circuit pattern layer.

9. In paragraph 1, The second insulating layer includes an opening exposing the first circuit pattern layer; The circuit board in which the first nanoparticle overlaps the opening in the stacking direction.

10. In paragraph 2, A circuit board having a first surface or a third surface having a concave-convex structure.

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