Semiconductor structure and manufacturing method therefor

Abstract

Embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate; a first conductive layer, located on the substrate and comprising a first sub-conductive structure, a second sub-conductive structure, and a second conductive structure which are arranged at intervals; a second conductive layer, located on the first conductive layer; an isolation structure, located between the first sub-conductive structure and the second sub-conductive structure, connected to the second conductive layer and used for electrically isolating the first sub-conductive structure from the second sub-conductive structure; and a contact plug, located between the second conductive structure and the second conductive layer, and used for electrically connecting the second conductive structure to the second conductive layer.

Description

Semiconductor structure and preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application with application number 202310763715.1, application date June 25, 2023, and invention name “Semiconductor structure and preparation method thereof”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0004] With the evolution of advanced dynamic random access memory (DRAM) processes, the core metal layer area continues to shrink as bitline / wordline (BL / WL) dimensions shrink. Unlike the repetitive line / space layout in the array area, the metal layer layout in the core area is relatively complex. The shrinking size increases manufacturing complexity and easily leads to bridging issues between metal layers.

[0005] Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.

[0007] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, comprising:

[0008] substrate;

[0009] a first conductive layer, located on the substrate, comprising a first sub-conductive structure, a second sub-conductive structure, and a second conductive structure that are spaced apart;

[0010] a second conductive layer, located on the first conductive layer;

[0011] an isolation structure, located between the first sub-conductive structure and the second sub-conductive structure and connected to the second conductive layer, for electrically isolating the first sub-conductive structure from the second sub-conductive structure;

[0012] A contact plug is located between the second conductive structure and the second conductive layer, and is used to electrically connect the second conductive structure and the second conductive layer.

[0013] In some embodiments, the top surface of the isolation structure is flush with the top surface of the contact plug, the bottom surface of the isolation structure is lower than the bottom surface of the contact plug, and the bottom surface of the isolation structure is not higher than the bottom surface of the first conductive layer.

[0014] In some embodiments, the isolation structure and the contact plug each include a conductive pillar and an insulating layer disposed around a sidewall of the conductive pillar.

[0015] In some embodiments, the semiconductor structure further comprises:

[0016] a first dielectric layer, located on the substrate, comprising a first sub-dielectric layer and a second sub-dielectric layer; wherein the first sub-dielectric layer is located on the sidewall and below the first conductive layer, and the second sub-dielectric layer covers the first conductive layer and the first sub-dielectric layer;

[0017] The second dielectric layer is located on the first dielectric layer.

[0018] In some embodiments, the sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is greater than or equal to a preset value;

[0019] The isolation structure penetrates the second dielectric layer and the second sub-dielectric layer and extends into the first sub-dielectric layer;

[0020] The contact plug penetrates the second dielectric layer and the second sub-dielectric layer and contacts the second conductive structure.

[0021] In some embodiments, the sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is less than a preset value;

[0022] The semiconductor structure further includes: a third dielectric layer located on the second dielectric layer;

[0023] The isolation structure penetrates the third dielectric layer, the second dielectric layer and the second sub-dielectric layer and extends into the first sub-dielectric layer;

[0024] The contact plug penetrates the third dielectric layer, the second dielectric layer, and the second sub-dielectric layer and contacts the second conductive structure.

[0025] In some embodiments, the first dielectric layer and the second dielectric layer are made of different materials; and the second dielectric layer and the third dielectric layer are made of different materials.

[0026] In some embodiments, the size of the isolation structure in the first horizontal direction is greater than the size of the contact plug in the first horizontal direction, and the size of the isolation structure in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure and the second sub-conductive structure in the second horizontal direction. The first horizontal direction is the arrangement direction of the first sub-conductive structure and the second sub-conductive structure, and the second horizontal direction is the extension direction of the first sub-conductive structure and the second sub-conductive structure.

[0027] In some embodiments, the substrate includes an active region and a gate structure located on the active region, and the active region includes a first source and drain region and a second source and drain region located on opposite sides of the gate structure;

[0028] The semiconductor structure further includes a first connecting pillar and a second connecting pillar, wherein the first connecting pillar electrically connects the first sub-conductive structure and the first source and drain region, and the second connecting pillar electrically connects the second sub-conductive structure and the second source and drain region.

[0029] According to a second aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising:

[0030] providing a substrate;

[0031] forming an initial first conductive layer on the substrate, wherein the initial first conductive layer includes a first conductive structure and a second conductive structure spaced apart from each other;

[0032] forming a first trench and a second trench in the same step, wherein the first trench penetrates the first conductive structure to divide the first conductive structure into a first sub-conductive structure and a second sub-conductive structure, and the second trench is located above the second conductive structure and exposes a portion of the surface of the second conductive structure; the first sub-conductive structure, the second sub-conductive structure, and the second conductive structure form a first conductive layer;

[0033] forming an isolation structure in the first trench;

[0034] forming a contact plug in the second trench;

[0035] A second conductive layer is formed on the isolation structure and the contact plug.

[0036] In some embodiments, the method further comprises:

[0037] Before forming the initial first conductive layer, forming a first sub-dielectric layer on the substrate, wherein the first sub-dielectric layer is located on the sidewall and below the initial first conductive layer;

[0038] forming a second sub-dielectric layer covering the initial first conductive layer and the first sub-dielectric layer, wherein the first sub-dielectric layer and the second sub-dielectric layer form a first dielectric layer;

[0039] A second dielectric layer is formed on the first dielectric layer.

[0040] In some embodiments, the sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is greater than or equal to a preset value;

[0041] The forming of the first trench and the second trench in the same step comprises:

[0042] Performing a first etching process, wherein the first trench penetrates the second dielectric layer and stops at the surface of the first dielectric layer, the second trench stops within the second dielectric layer, and the dimension of the first trench in the first horizontal direction is larger than the dimension of the second trench in the first horizontal direction, and the first horizontal direction is the arrangement direction of the first sub-conductive structure and the second sub-conductive structure;

[0043] performing a second etching process, wherein the first trench penetrates the second sub-dielectric layer and stops at the surface of the first conductive structure, and the second trench stops within the second dielectric layer, and the etching selectivities of the first dielectric layer and the second dielectric layer are different;

[0044] A third etching process is performed, the first trench penetrates the first conductive structure, and the second trench exposes a portion of the surface of the second conductive structure.

[0045] In some embodiments, the sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is less than a preset value;

[0046] The method further includes: forming a third dielectric layer on the second dielectric layer;

[0047] The forming of the first trench and the second trench in the same step comprises:

[0048] Performing a fourth etching process, wherein the first trench penetrates the third dielectric layer and stops at the surface of the second dielectric layer, the second trench stops within the third dielectric layer, and a dimension of the first trench in a first horizontal direction is larger than a dimension of the second trench in the first horizontal direction, and the first horizontal direction is an arrangement direction of the first sub-conductive structure and the second sub-conductive structure;

[0049] performing a fifth etching process, wherein the first trench penetrates the second dielectric layer and the second sub-dielectric layer and stops at the surface of the first conductive structure, and the second trench penetrates the third dielectric layer and stops within the second dielectric layer, and the etching selectivities of the second dielectric layer and the third dielectric layer are different;

[0050] A sixth etching process is performed, the first trench penetrates the first conductive structure, and the second trench exposes a portion of the surface of the second conductive structure.

[0051] In some embodiments, forming an isolation structure in the first trench and forming a contact plug in the second trench includes:

[0052] forming an insulating layer on sidewalls of the first trench and the second trench;

[0053] Conductive material is filled in the first trench and the second trench where the insulating layer is formed, so as to form an isolation structure in the first trench and a contact plug in the second trench.

[0054] In some embodiments, the substrate includes an active region and a gate structure located on the active region, and the active region includes a first source and drain region and a second source and drain region located on opposite sides of the gate structure;

[0055] forming an initial first conductive layer on the substrate, comprising:

[0056] A first connecting pillar and a second connecting pillar and an initial first conductive layer located on the first connecting pillar and the second connecting pillar are formed, wherein the first connecting pillar contacts the first source and drain region, and the second connecting pillar contacts the second source and drain region.

[0057] In the disclosed embodiment, the isolation structure, contact plug, and first conductive layer can be formed in the same process, which simplifies the process and saves costs; at the same time, the isolation structure electrically isolates the first sub-conductive structure from the second sub-conductive structure to avoid crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0059] FIG1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0060] FIG2 is a top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0061] FIG3 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure;

[0062] FIG4 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0063] 5a to 7f are schematic structural diagrams of the semiconductor structure provided by an embodiment of the present disclosure during the preparation process.

[0064] Description of reference numerals:

[0065] Substrate, 10; active region, 11; first source and drain region, 111; second source and drain region, 112; gate structure, 12; gate insulating layer, 121; first gate conductive layer, 122; second gate conductive layer, 123; third gate conductive layer, 124; cap layer, 125; gate spacer, 13;

[0066] First conductive layer, 20; first conductive structure, 21; first sub-conductive structure, 211; second sub-conductive structure, 212; second conductive structure, 22; initial first conductive layer pre-layer, 200'; initial first conductive layer, 200;

[0067] Second conductive layer, 30; Initial second conductive layer, 300;

[0068] Isolation structure, 41; contact plug, 42; conductive pillar, 401; insulating layer, 402;

[0069] First dielectric layer, 51; first sub-dielectric layer, 511; second sub-dielectric layer, 512; second dielectric layer, 52; third dielectric layer, 53;

[0070] First connecting post, 61; second connecting post, 62;

[0071] First groove, 71; second groove, 72;

[0072] A first isolation layer 81 ; a first mask layer 82 ; and a first pattern transfer layer 83 . DETAILED DESCRIPTION

[0073] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0074] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0075] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0076] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0077] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0078] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0079] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0080] In the related art, a first conductive layer is first formed using a self-aligned double patterning (SADP) technique, a dielectric layer is deposited, and then a contact plug and a second conductive layer are formed. This requires multiple processes, which increases costs.

[0081] Based on this, an embodiment of the present disclosure provides a semiconductor structure, and FIG1 is a schematic structural diagram of the semiconductor structure provided by an embodiment of the present disclosure.

[0082] Referring to FIG1 , the semiconductor structure includes:

[0083] substrate 10;

[0084] The first conductive layer 20 is located on the substrate 10 and includes a first sub-conductive structure 211, a second sub-conductive structure 212 and a second conductive structure 22 that are spaced apart.

[0085] A second conductive layer 30 is located on the first conductive layer 20;

[0086] an isolation structure 41 , located between the first sub-conductive structure 211 and the second sub-conductive structure 212 and connected to the second conductive layer 30 , for electrically isolating the first sub-conductive structure 211 from the second sub-conductive structure 212 ;

[0087] The contact plug 42 is located between the second conductive structure 22 and the second conductive layer 30 and is used to electrically connect the second conductive structure 22 and the second conductive layer 30 .

[0088] In the disclosed embodiment, the isolation structure, contact plug, and first conductive layer can be formed in the same process, which simplifies the process and saves costs; at the same time, the isolation structure electrically isolates the first sub-conductive structure from the second sub-conductive structure to avoid crosstalk.

[0089] In one embodiment, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator) substrate, etc. It may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), it may also be a stacked structure, such as Si / SiGe, etc., or it may be other epitaxial structures, such as SGOI (Silicon Germanium on Insulator), etc.

[0090] The substrate 10 includes an active region 11 and a gate structure 12 located on the active region 11. The active region 11 includes a first source / drain region 111 and a second source / drain region 112 located on opposite sides of the gate structure 12. The substrate also includes an isolation region (not shown) adjacent to the active region 11. The isolation region defines the substrate into multiple discrete active regions 11.

[0091] The gate structure 12 includes a gate insulating layer 121, a first gate conductive layer 122, a second gate conductive layer 123, a third gate conductive layer 124 and a capping layer 125 stacked in sequence from bottom to top, wherein the material of the gate insulating layer 121 includes but is not limited to oxide; the material of the first gate conductive layer 122 includes but is not limited to polysilicon; the material of the second gate conductive layer 123 includes but is not limited to titanium nitride; the material of the third gate conductive layer 124 includes but is not limited to metal tungsten; the material of the capping layer 125 includes but is not limited to oxide, nitride, metal oxide and nitrogen oxide, etc.

[0092] In one embodiment, the semiconductor structure further includes a gate spacer layer 13 . The gate spacer layer 13 covers the sidewalls of the gate structure 12 to insulate and isolate the gate structure 12 from the first connecting pillar 61 and the second connecting pillar 62 .

[0093] 1 , the first conductive layer 20 includes a first sub-conductive structure 211 , a second sub-conductive structure 212 , and a second conductive structure 22 that are spaced apart.

[0094] The material of the first conductive layer 20 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0095] In one embodiment, the semiconductor structure further includes: a first connecting pillar 61 and a second connecting pillar 62 , wherein the first connecting pillar 61 electrically connects the first sub-conductive structure 211 and the first source and drain region 111 , and the second connecting pillar 62 electrically connects the second sub-conductive structure 212 and the second source and drain region 112 .

[0096] In one embodiment, the semiconductor structure further includes: a first dielectric layer 51, located on the substrate 10, including a first sub-dielectric layer 511 and a second sub-dielectric layer 512; wherein the first sub-dielectric layer 511 is located on the sidewall and below the first conductive layer 20, and the second sub-dielectric layer 512 covers the first conductive layer 20 and the first sub-dielectric layer 511; and the second dielectric layer 52 is located on the first dielectric layer 51.

[0097] 1 , the second conductive layer 30 is located on the first conductive layer 20 . Specifically, the second conductive layer 30 is located on the second dielectric layer 52 .

[0098] The material of the second conductive layer 30 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0099] Continuing with FIG1 , the isolation structure 41 is located between the first sub-conductive structure 211 and the second sub-conductive structure 212 and is connected to the second conductive layer 30 , and is used to electrically isolate the first sub-conductive structure 211 from the second sub-conductive structure 212 ; the contact plug 42 is located between the second conductive structure 22 and the second conductive layer 30 , and is used to electrically connect the second conductive structure 22 to the second conductive layer 30 .

[0100] In some embodiments, the bottom surface of the contact plug 42 is flush with the top surface of the second conductive structure 22 , that is, the contact plug 42 does not extend into the second conductive structure 22 .

[0101] In some other embodiments, the bottom surface of the contact plug 42 is lower than the top surface of the second conductive structure 22 and higher than the bottom surface of the second conductive structure 22 , that is, the contact plug extends into the second conductive structure 22 but does not penetrate the second conductive structure 22 .

[0102] In one embodiment, the top surface of the isolation structure 41 is flush with the top surface of the contact plug 42 , the bottom surface of the isolation structure 41 is lower than the bottom surface of the contact plug 42 , and the bottom surface of the isolation structure 41 is no higher than the bottom surface of the first conductive layer 20 .

[0103] Specifically, in some embodiments, as shown in FIG1 , the bottom surface of the isolation structure 41 is lower than the bottom surface of the first conductive layer 20; in other embodiments, the bottom surface of the isolation structure 41 is flush with the bottom surface of the first conductive layer 20. Regardless of whether the bottom surface of the isolation structure 41 is lower than or flush with the bottom surface of the first conductive layer 20, as long as the isolation structure 41 can insulate and isolate the first sub-conductive structure 211 from the second sub-conductive structure 212, it will suffice.

[0104] In one embodiment, both the isolation structure 41 and the contact plug 42 include a conductive pillar 401 and an insulating layer 402 disposed around the sidewalls of the conductive pillar 401 .

[0105] The insulating layer 402 in the isolation structure 41 contacts the first and second sub-conductive structures 211 and 212, providing insulation and isolation. The conductive pillars 401 do not contact the first and second sub-conductive structures 211 and 212. Therefore, even though the isolation structure 41 includes the conductive pillars 401, the isolation structure 41 does not function as a conductor. Because the bottom and top surfaces of the conductive pillars 401 contact the second conductive structure 22 and the second conductive layer 30, respectively, and the insulating layer 402 is located on the sidewalls of the conductive pillars 401, the conductivity of the contact plugs 42 is not affected. Furthermore, the conductive pillars and insulating layer forming the isolation structure and contact plugs can be formed simultaneously in the same step, simplifying the process steps and reducing costs.

[0106] In some other embodiments, the isolation structure 41 may include only the insulating layer 402 , and the contact plug may include only the conductive pillar 401 .

[0107] As shown in FIG1 , the conductive pillar 401 may include a two-layer structure, namely a first conductive pillar (not labeled in the figure) and a diffusion barrier layer (not labeled in the figure) located between the first conductive pillar and the insulating layer. The diffusion barrier layer may also be located between the second conductive layer and the second dielectric layer. For example, the first conductive pillar may be made of a metal material such as tungsten or copper, and the diffusion barrier layer may be made of titanium nitride.

[0108] FIG2 is a top view of the semiconductor structure provided in an embodiment of the present disclosure. However, it should be explained that FIG2 is a top view after the second conductive layer, the second dielectric layer, and the second sub-dielectric layer are removed, mainly for the purpose of showing the positional relationship between the isolation structure 41 and the contact plug 42 and the first conductive layer 20.

[0109] In one embodiment, as shown in Figure 2, the size of the isolation structure 41 in the first horizontal direction is greater than the size of the contact plug 42 in the first horizontal direction, and the size of the isolation structure 41 in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure 211 and the second sub-conductive structure 212 in the second horizontal direction. The first horizontal direction is the arrangement direction of the first sub-conductive structure 211 and the second sub-conductive structure 212, and the second horizontal direction is the extension direction of the first sub-conductive structure 211 and the second sub-conductive structure 212.

[0110] The size of the isolation structure 41 in the first horizontal direction is larger than the size of the contact plug 42 in the first horizontal direction, that is, when etching the first trench and the second trench for forming the isolation structure 41 and the contact plug 42 respectively, the width of the first trench is larger than the width of the second trench. In this way, due to the etching load effect of the dielectric layer, the first trench with a larger width can be etched faster, that is, when the first trench penetrates the first conductive layer 20, the second trench stays on the surface or inside the first conductive layer 20, and does not penetrate the first conductive layer 20.

[0111] The size of the isolation structure 41 in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure 211 and the second sub-conductive structure 212 in the second horizontal direction. In this way, the isolation structure 41 can completely isolate the first sub-conductive structure 211 and the second sub-conductive structure 212 to achieve insulation isolation.

[0112] In some embodiments, the sum of the size of the second sub-dielectric layer 512 along the thickness direction of the substrate 10 and the size of the second dielectric layer 52 along the thickness direction of the substrate 10 is greater than or equal to a preset value;

[0113] The isolation structure 41 penetrates the second dielectric layer 52 and the second sub-dielectric layer 512 and extends into the first sub-dielectric layer 511 ;

[0114] The contact plug 42 penetrates the second dielectric layer 52 and the second sub-dielectric layer 512 and contacts the second conductive structure 22 .

[0115] When the sum of the dimensions of the second sub-dielectric layer 512 along the substrate thickness direction and the dimensions of the second dielectric layer 52 along the substrate thickness direction is greater than or equal to a preset value, the preset value is greater than one tenth of the height of the contact plug 42, for example, it can be 20 nm, indicating that the overall thickness of the dielectric layer is thick enough, so that there is sufficient margin to utilize the load effect to achieve the etching of the first trench and the second trench of different depths. When the first trench with a larger width etches through the second sub-dielectric layer, the second trench with a smaller width will not etch through the second sub-dielectric layer.

[0116] FIG3 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure. It should be explained that a substrate is not shown in FIG3 .

[0117] In some other embodiments, as shown in FIG3 , the sum of the size of the second sub-dielectric layer 512 along the thickness direction of the substrate 10 and the size of the second dielectric layer 52 along the thickness direction of the substrate 10 is less than a preset value;

[0118] The semiconductor structure further includes: a third dielectric layer 53 located on the second dielectric layer 52;

[0119] The isolation structure 41 penetrates the third dielectric layer 53 , the second dielectric layer 52 and the second sub-dielectric layer 512 and extends into the first sub-dielectric layer 511 ;

[0120] The contact plug 42 penetrates the third dielectric layer 53 , the second dielectric layer 52 and the second sub-dielectric layer 512 and contacts the second conductive structure 22 .

[0121] When the sum of the dimensions of the second sub-dielectric layer 512 along the substrate thickness direction and the dimensions of the second dielectric layer 52 along the substrate thickness direction is less than a preset value, it indicates that the sum of the thicknesses of the second sub-dielectric layer 512 and the second dielectric layer 52 is insufficient, and there is no way to utilize the load effect to achieve etching of the first trench and the second trench of different depths. Therefore, a third dielectric layer is added to increase the overall thickness of the dielectric layer (the sum of the second sub-dielectric layer, the second dielectric layer, and the third dielectric layer), thereby ensuring that there is sufficient margin to utilize the load effect to achieve etching of the first trench and the second trench of different depths.

[0122] In one embodiment, the first dielectric layer 51 and the second dielectric layer 52 are made of different materials; the second dielectric layer 52 and the third dielectric layer 53 are made of different materials.

[0123] The materials between the first dielectric layer 51 and the second dielectric layer 52, as well as between the second dielectric layer 52 and the third dielectric layer 53 are different. In this way, it can be ensured that the etching selectivity between the first dielectric layer 51 and the second dielectric layer 52, as well as the etching selectivity between the second dielectric layer 52 and the third dielectric layer 53 are different. Therefore, during the process of etching the first trench and the second trench, when the first trench penetrates the first conductive layer, the second trench can remain on the surface or inside the first conductive layer.

[0124] The material of the first dielectric layer 51 includes but is not limited to nitride, the material of the second dielectric layer 52 includes but is not limited to oxide, and the material of the third dielectric layer 53 includes but is not limited to nitride.

[0125] In some other embodiments, the first trench and the second trench may be formed separately and sequentially to more accurately control the depths of the first trench and the second trench. For example, the first trench may be etched first, then filled with a sacrificial material, and then the sacrificial material may be removed after the second trench is etched. Alternatively, the second trench may be etched first, then filled with a sacrificial material, and then the sacrificial material may be removed after the first trench is etched.

[0126] The present disclosure also provides a method for preparing a semiconductor structure. For details, please refer to FIG. 4 . As shown in FIG. 4 , the method includes the following steps:

[0127] Step 401: providing a substrate;

[0128] Step 402: forming an initial first conductive layer on a substrate, wherein the initial first conductive layer includes a first conductive structure and a second conductive structure spaced apart from each other;

[0129] Step 403: forming a first trench and a second trench in the same step, wherein the first trench penetrates the first conductive structure to divide the first conductive structure into a first sub-conductive structure and a second sub-conductive structure, and the second trench is located above the second conductive structure and exposes a portion of the surface of the second conductive structure; the first sub-conductive structure, the second sub-conductive structure, and the second conductive structure form a first conductive layer;

[0130] Step 404: forming an isolation structure in the first trench;

[0131] Step 405: forming a contact plug in the second trench;

[0132] Step 406 : Form a second conductive layer on the isolation structure and the contact plug.

[0133] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure will be further described in detail below with reference to specific embodiments.

[0134] 5a to 7f are schematic structural diagrams of the semiconductor structure provided by an embodiment of the present disclosure during the preparation process.

[0135] First, referring to FIG. 5 a , step 401 is performed to provide a substrate 10 .

[0136] In one embodiment, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator) substrate, etc. It may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), it may also be a stacked structure, such as Si / SiGe, etc., or it may be other epitaxial structures, such as SGOI (Silicon Germanium on Insulator), etc.

[0137] The substrate 10 includes an active region 11 and a gate structure 12 located on the active region 11. The active region 11 includes a first source / drain region 111 and a second source / drain region 112 located on opposite sides of the gate structure 12. The substrate 10 also includes isolation regions (not shown) that define the substrate into multiple discrete active regions 11.

[0138] The gate structure 12 includes a gate insulating layer 121, a first gate conductive layer 122, a second gate conductive layer 123, a third gate conductive layer 124 and a capping layer 125 stacked in sequence from bottom to top, wherein the material of the gate insulating layer 121 includes but is not limited to oxide; the material of the first gate conductive layer 122 includes but is not limited to polysilicon; the material of the second gate conductive layer 123 includes but is not limited to titanium nitride; the material of the third gate conductive layer 124 includes but is not limited to metal tungsten; the material of the capping layer 125 includes but is not limited to oxide, nitride, metal oxide and nitrogen oxide, etc.

[0139] In one embodiment, a gate spacer 13 is formed to cover the sidewalls of the gate structure 12 to insulate and isolate the gate structure 12 from the first connecting pillar 61 and the second connecting pillar 62 to be formed subsequently.

[0140] Next, referring to FIG. 5 a to FIG. 5 c , step 402 is performed to form an initial first conductive layer 200 on the substrate 10 . The initial first conductive layer 200 includes a first conductive structure 21 and a second conductive structure 22 that are spaced apart.

[0141] In one embodiment, an initial first conductive layer 200 is formed on the substrate 10, including: forming a first connecting pillar 61 and a second connecting pillar 62 and an initial first conductive layer 200 located on the first connecting pillar 61 and the second connecting pillar 62, the first connecting pillar 61 contacts the first source and drain region 111, and the second connecting pillar 62 contacts the second source and drain region 112.

[0142] Specifically, referring to Figures 5a and 5b, the method further includes: before forming the initial first conductive layer 200, forming an initial first conductive layer pre-layer 200' on the substrate 10, and forming a first isolation layer 81, a first mask layer 82, and a first pattern transfer layer 83 on the initial first conductive layer pre-layer 200'. The first isolation layer 81, the first mask layer 82, and the first pattern transfer layer 83 can serve as masks for the subsequent formation of the initial first conductive layer 200.

[0143] In actual operation, the initial first conductive layer pre-layer 200', the first isolation layer 81, the first mask layer 82 and the first pattern transfer layer 83 can be formed using one or more thin film deposition processes; specifically, the deposition process includes but is not limited to a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or a combination thereof.

[0144] The material of the first isolation layer 81 includes, but is not limited to, amorphous carbon (ACL), the material of the first mask layer 82 includes, but is not limited to, silicon oxynitride, and the material of the first pattern transfer layer 83 includes, but is not limited to, photoresist. The material of the initial first conductive layer pre-layer 200' includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0145] 5 c , the first pattern transfer layer 83 has a pattern structure. According to the pattern structure on the first pattern transfer layer 83 , the initial first conductive layer pre-layer 200 ′ is etched to form the initial first conductive layer 200 .

[0146] The initial first conductive layer 200 includes a first conductive structure 21 and a second conductive structure 22 . The first connecting pillar 61 and the second connecting pillar 62 are connected to the first conductive structure 21 .

[0147] Next, referring to Figure 5d and Figures 6a to 6f, as well as Figures 7a to 7f, steps 403 to 405 are performed to form a first trench 71 and a second trench 72 in the same step. The first trench 71 penetrates the first conductive structure 21 to divide the first conductive structure 21 into a first sub-conductive structure 211 and a second sub-conductive structure 212. The second trench 72 is located above the second conductive structure 22 and exposes part of the surface of the second conductive structure 22. The first sub-conductive structure 211, the second sub-conductive structure 212 and the second conductive structure 22 are formed into a first conductive layer 20. An isolation structure 41 is formed in the first trench 71. A contact plug 42 is formed in the second trench 72.

[0148] It should be noted that Figures 6a to 6f are schematic diagrams of a semiconductor structure during the fabrication process according to one embodiment, and Figures 7a to 7f are schematic diagrams of a semiconductor structure during the fabrication process according to another embodiment. The embodiment shown in Figures 6a to 6f will be described in detail below.

[0149] 6a , the method further includes: before forming the initial first conductive layer 200 , forming a first sub-dielectric layer 511 on the substrate 10 , wherein the first sub-dielectric layer 511 is located on the sidewalls and below the initial first conductive layer 200 ;

[0150] forming a second sub-dielectric layer 512 covering the initial first conductive layer 200 and the first sub-dielectric layer 511 , so that the first sub-dielectric layer 511 and the second sub-dielectric layer 512 form the first dielectric layer 51 ;

[0151] A second dielectric layer 52 is formed on the first dielectric layer 51 .

[0152] In one embodiment, the materials of the first dielectric layer 51 and the second dielectric layer 52 are different. The material of the first dielectric layer 51 includes but is not limited to nitride, and the material of the second dielectric layer 52 includes but is not limited to oxide.

[0153] Next, referring to FIG. 6 b to FIG. 6 d , the sum of the size of the second sub-dielectric layer 512 along the thickness direction of the substrate 10 and the size of the second dielectric layer 52 along the thickness direction of the substrate 10 is greater than or equal to a preset value;

[0154] The first trench 71 and the second trench 72 are formed in the same step, including:

[0155] 6 b , a first etching process is performed, whereby the first trench 71 penetrates the second dielectric layer 52 and stops at the surface of the first dielectric layer 51 , and the second trench 72 stops within the second dielectric layer 52 . Furthermore, the dimension of the first trench 71 in the first horizontal direction is larger than the dimension of the second trench 72 in the first horizontal direction. The first horizontal direction is the arrangement direction of the first sub-conductive structure 211 and the second sub-conductive structure 212 .

[0156] 6 c , a second etching process is performed. The first trench 71 penetrates the second sub-dielectric layer 512 and stops at the surface of the first conductive structure 21 . The second trench 72 stops in the second dielectric layer 52 . The etching selectivity ratios of the first dielectric layer 51 and the second dielectric layer 52 are different.

[0157] 6 d , a third etching process is performed, and the first trench 71 penetrates the first conductive structure 21 , and the second trench 72 exposes a portion of the surface of the second conductive structure 22 .

[0158] In this embodiment, when the sum of the dimensions of the second sub-dielectric layer 512 along the substrate thickness direction and the dimensions of the second dielectric layer 52 along the substrate thickness direction is greater than or equal to a preset value, it indicates that the overall thickness of the dielectric layer is thick enough, so that there is sufficient margin to utilize the load effect to achieve the etching of the first trench 71 and the second trench 72 of different depths. When the first trench 71 with a larger width etches through the second sub-dielectric layer 512, the second trench 72 with a smaller width will not etch through the second sub-dielectric layer 512.

[0159] Furthermore, the etching selectivity of the first dielectric layer 51 and the second dielectric layer 52 is different, so that when etching the first trench 71 and the second trench 72 , when the first trench 71 etches through the first conductive structure 21 , the second trench 72 can stay on the surface or inside the second conductive structure 22 .

[0160] Next, referring to FIG. 6e and FIG. 6f , an isolation structure 41 is formed in the first trench 71 and a contact plug 42 is formed in the second trench 72 , including:

[0161] forming an insulating layer 402 on sidewalls of the first trench 71 and the second trench 72;

[0162] Conductive material is filled in the first trench 71 and the second trench 72 formed with the insulating layer 402 to form an isolation structure 41 in the first trench 71 and a contact plug 42 in the second trench 72 .

[0163] Specifically, the insulating layer 402 is first formed on the sidewalls of the first trench 71 and the second trench 72 , and then the conductive pillar 401 covering the insulating layer 402 is formed.

[0164] The insulating layer 402 in the isolation structure 41 contacts the first sub-conductive structure 211 and the second sub-conductive structure 212, providing insulation and isolation. Therefore, even though the isolation structure 41 includes the conductive pillar 401, the isolation structure 41 does not function as a conductor. Because the bottom and top surfaces of the contact plug 42 are connected to the second conductive structure 22 and the second conductive layer 30, respectively, and the insulating layer 402 is located on the sidewall, the conductivity of the contact plug 42 is not affected. Furthermore, the conductive pillar and insulating layer can be formed in the isolation structure and contact plug in the same step, simplifying the process steps and reducing costs.

[0165] As shown in Figure 6f, the conductive column 401 may include a two-layer structure, namely a first conductive column (not marked in the figure) and a diffusion barrier layer (not marked in the figure) located between the first conductive column and the insulating layer, wherein the diffusion barrier layer may also cover the surface of the second dielectric layer.

[0166] In this embodiment, both the isolation structure 41 and the contact plug 42 include a conductive pillar 401 and an insulating layer 402 .

[0167] In some other embodiments, the isolation structure 41 may include only the insulating layer 402 , and the contact plug 42 may include only the conductive pillar 401 .

[0168] In some embodiments, the bottom surface of the contact plug 42 is flush with the top surface of the second conductive structure 22 , that is, the contact plug 42 does not extend into the second conductive structure 22 .

[0169] In some other embodiments, the bottom surface of the contact plug 42 is lower than the top surface of the second conductive structure 22 , that is, the contact plug 42 extends into the second conductive structure 22 .

[0170] In one embodiment, the top surface of the isolation structure 41 is flush with the top surface of the contact plug 42 , the bottom surface of the isolation structure 41 is lower than the bottom surface of the contact plug 42 , and the bottom surface of the isolation structure 41 is no higher than the bottom surface of the first conductive layer 20 .

[0171] Specifically, in some embodiments, as shown in FIG6f , the bottom surface of the isolation structure 41 is lower than the bottom surface of the first conductive layer 20; in other embodiments, the bottom surface of the isolation structure 41 is flush with the bottom surface of the first conductive layer 20. Regardless of whether the bottom surface of the isolation structure 41 is lower than or flush with the bottom surface of the first conductive layer 20, as long as the isolation structure 41 can insulate and isolate the first sub-conductive structure 211 from the second sub-conductive structure 212, it will be sufficient.

[0172] In one embodiment, as shown in Figure 2, the size of the isolation structure 41 in the first horizontal direction is greater than the size of the contact plug 42 in the first horizontal direction, and the size of the isolation structure 41 in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure 211 and the second sub-conductive structure 212 in the second horizontal direction. The first horizontal direction is the arrangement direction of the first sub-conductive structure 211 and the second sub-conductive structure 212, and the second horizontal direction is the extension direction of the first sub-conductive structure 211 and the second sub-conductive structure 212.

[0173] The size of the isolation structure 41 in the first horizontal direction is larger than the size of the contact plug 42 in the first horizontal direction, that is, when etching the first trench 71 and the second trench 72 for forming the isolation structure 41 and the contact plug 42 respectively, the width of the first trench 71 is larger than the width of the second trench 72. In this way, due to the etching load effect of the dielectric layer, the first trench 71 with a larger width can be etched faster, that is, when the first trench penetrates the first conductive layer 20, the second trench 72 stays on the surface or inside the first conductive layer 20, and does not penetrate the first conductive layer.

[0174] The size of the isolation structure 41 in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure 211 and the second sub-conductive structure 212 in the second horizontal direction. In this way, the isolation structure 41 can completely isolate the first sub-conductive structure 211 and the second sub-conductive structure 212 to achieve insulation isolation.

[0175] 6 f , while the conductive pillars 401 are being formed, an initial second conductive layer 300 is formed on the second dielectric layer 52 .

[0176] Next, the embodiments shown in FIG. 7 a to FIG. 7 f are described in detail.

[0177] The sum of the size of the second sub-dielectric layer 512 along the thickness direction of the substrate 10 and the size of the second dielectric layer 52 along the thickness direction of the substrate 10 is less than a preset value;

[0178] The method also includes:

[0179] 7a, a third dielectric layer 53 is formed on the second dielectric layer 52;

[0180] The first trench 71 and the second trench 72 are formed in the same step, including:

[0181] 7 b , a fourth etching process is performed. The first trench 71 penetrates the third dielectric layer 53 and stops at the surface of the second dielectric layer 52 . The second trench 72 stops within the third dielectric layer 53 . The dimension of the first trench 71 in the first horizontal direction is larger than the dimension of the second trench 72 in the first horizontal direction. The first horizontal direction is the arrangement direction of the first sub-conductive structure 211 and the second sub-conductive structure 212 .

[0182] 7 c , a fifth etching process is performed. The first trench 71 penetrates the second dielectric layer 52 and the second sub-dielectric layer 512 and stops at the surface of the first conductive structure 21. The second trench 72 penetrates the third dielectric layer 53 and stops within the second dielectric layer 52. The etching selectivities of the second dielectric layer 52 and the third dielectric layer 53 are different.

[0183] 7 d , a sixth etching process is performed, and the first trench 71 penetrates the first conductive structure 21 , and the second trench 72 exposes a portion of the surface of the second conductive structure 22 .

[0184] When the sum of the dimensions of the second sub-dielectric layer 512 along the substrate thickness direction and the dimensions of the second dielectric layer 52 along the substrate thickness direction is less than a preset value, it indicates that the sum of the thicknesses of the second sub-dielectric layer 512 and the second dielectric layer 52 is insufficient, and there is no way to utilize the load effect to achieve etching of the first trench and the second trench of different depths. Therefore, a third dielectric layer 53 is added to increase the overall thickness of the dielectric layer, thereby ensuring that there is sufficient margin to utilize the load effect to achieve etching of the first trench and the second trench of different depths.

[0185] In one embodiment, the first dielectric layer 51 and the second dielectric layer 52 are made of different materials; the second dielectric layer 52 and the third dielectric layer 53 are made of different materials. The material of the first dielectric layer 51 includes, but is not limited to, nitride, the material of the second dielectric layer 52 includes, but is not limited to, oxide, and the material of the third dielectric layer 53 includes, but is not limited to, nitride.

[0186] 7e and 7f , an isolation structure 41 is formed in the first trench 71, and a contact plug 42 is formed in the second trench 72. The steps for forming the isolation structure 41 and the contact plug 42 in this embodiment are the same as those in FIG. 6e and FIG. 6f , and are not repeated here.

[0187] Next, referring to FIG. 5 e , step 406 is performed to form a second conductive layer 30 on the isolation structure 41 and the contact plug 42 .

[0188] Specifically, a mask layer can be grown on the upper surface of the initial second conductive layer 300. This mask layer is then patterned to indicate the pattern of the second conductive layer to be etched. This mask layer can be patterned using a photolithography process. The mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask. When the mask layer is a photoresist mask, the mask layer is patterned through steps such as exposure, development, and stripping. The second conductive layer 30 is then etched according to the pattern of the second conductive layer 30 to be etched.

[0189] The material of the second conductive layer 30 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0190] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure. Industrial Applicability

[0191] In the disclosed embodiment, the isolation structure, contact plug, and first conductive layer can be formed in the same process, which simplifies the process and saves costs; at the same time, the isolation structure electrically isolates the first sub-conductive structure from the second sub-conductive structure to avoid crosstalk.

Claims

1. A semiconductor structure comprising: A substrate (10); A first conductive layer (20), located on the substrate (10), comprising a first sub-conductive structure (211), a second sub-conductive structure (212) and a second conductive structure (22) arranged at intervals; A second conductive layer (30) located on the first conductive layer (20); an isolation structure (41), located between the first sub-conductive structure (211) and the second sub-conductive structure (212) and connected to the second conductive layer (30), and used for electrically isolating the first sub-conductive structure (211) from the second sub-conductive structure (212); A contact plug (42) is located between the second conductive structure (22) and the second conductive layer (30) and is used to electrically connect the second conductive structure (22) and the second conductive layer (30).

2. The semiconductor structure according to claim 1, wherein: The top surface of the isolation structure (41) is flush with the top surface of the contact plug (42), the bottom surface of the isolation structure (41) is lower than the bottom surface of the contact plug (42), and the bottom surface of the isolation structure (41) is not higher than the bottom surface of the first conductive layer (20).

3. The semiconductor structure according to claim 1 or 2, wherein: The isolation structure (41) and the contact plug (42) both include a conductive column (401) and an insulating layer (402) disposed around the side wall of the conductive column (401).

4. The semiconductor structure according to any one of claims 1 to 3, wherein: The semiconductor structure further comprises: A first dielectric layer (51), located on the substrate (10), comprising a first sub-dielectric layer (511) and a second sub-dielectric layer (512); wherein the first sub-dielectric layer (511) is located on the side wall and below the first conductive layer (20), and the second sub-dielectric layer (512) covers the first conductive layer (20) and the first sub-dielectric layer (511); The second dielectric layer (52) is located on the first dielectric layer (51).

5. The semiconductor structure according to claim 4, wherein: The sum of the size of the second sub-dielectric layer (512) along the thickness direction of the substrate (10) and the size of the second dielectric layer (52) along the thickness direction of the substrate (10) is greater than or equal to a preset value; The isolation structure (41) penetrates the second dielectric layer (52) and the second sub-dielectric layer (512) and extends into the first sub-dielectric layer (511); The contact plug (42) penetrates the second dielectric layer (52) and the second sub-dielectric layer (512) and contacts the second conductive structure (22).

6. The semiconductor structure according to claim 4, wherein: The sum of the size of the second sub-dielectric layer (512) along the thickness direction of the substrate (10) and the size of the second dielectric layer (52) along the thickness direction of the substrate (10) is less than a preset value; The semiconductor structure further comprises: a third dielectric layer (53) located on the second dielectric layer (52); The isolation structure (41) penetrates the third dielectric layer (53), the second dielectric layer (52) and the second sub-dielectric layer (512) and extends into the first sub-dielectric layer (511); The contact plug (42) penetrates the third dielectric layer (53), the second dielectric layer (52) and the second sub-dielectric layer (512) and contacts the second conductive structure (22).

7. The semiconductor structure according to claim 6, wherein: The first dielectric layer (51) and the second dielectric layer (52) are made of different materials; the second dielectric layer (52) and the third dielectric layer (53) are made of different materials.

8. The semiconductor structure according to any one of claims 1 to 7, wherein: The size of the isolation structure (41) in the first horizontal direction is greater than the size of the contact plug (42) in the first horizontal direction, and the size of the isolation structure (41) in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure (211) and the second sub-conductive structure (212) in the second horizontal direction. The first horizontal direction is the arrangement direction of the first sub-conductive structure (211) and the second sub-conductive structure (212), and the second horizontal direction is the extension direction of the first sub-conductive structure (211) and the second sub-conductive structure (212).

9. The semiconductor structure according to any one of claims 1 to 7, wherein: The substrate (10) comprises an active region (11) and a gate structure (12) located on the active region (11), wherein the active region (11) comprises a first source-drain region (111) and a second source-drain region (112) located on opposite sides of the gate structure (12); The semiconductor structure further comprises: a first connecting pillar (61) and a second connecting pillar (62), wherein the first connecting pillar (61) electrically connects the first sub-conductive structure (211) and the first source-drain region (111), and the second connecting pillar (62) electrically connects the second sub-conductive structure (212) and the second source-drain region (112).

10. A method for preparing a semiconductor structure, comprising: Providing a substrate (10); Forming an initial first conductive layer (200) on the substrate (10), wherein the initial first conductive layer (200) comprises a first conductive structure (21) and a second conductive structure (22) which are arranged at intervals; A first groove (71) and a second groove (72) are formed in the same step, wherein the first groove (71) penetrates the first conductive structure (21) to divide the first conductive structure (21) into a first sub-conductive structure (211) and a second sub-conductive structure (212), and the second groove (72) is located above the second conductive structure (22) and exposes a portion of the surface of the second conductive structure (22); the first sub-conductive structure (211), the second sub-conductive structure (212) and the second conductive structure (22) form a first conductive layer (20); forming an isolation structure (41) in the first trench (71); forming a contact plug (42) in the second trench (72); A second conductive layer (30) is formed on the isolation structure (41) and the contact plug (42).

11. The method according to claim 10, wherein: The method further comprises: Before forming the initial first conductive layer (200), forming a first sub-dielectric layer (511) on the substrate (10), wherein the first sub-dielectric layer (511) is located on the side wall and below the initial first conductive layer (200); forming a second sub-dielectric layer (512) covering the initial first conductive layer (200) and the first sub-dielectric layer (511), wherein the first sub-dielectric layer (511) and the second sub-dielectric layer (512) form a first dielectric layer (51); A second dielectric layer (52) is formed on the first dielectric layer (51).

12. The method according to claim 11, wherein: The sum of the size of the second sub-dielectric layer (512) along the thickness direction of the substrate (10) and the size of the second dielectric layer (52) along the thickness direction of the substrate (10) is greater than or equal to a preset value; The forming of the first groove (71) and the second groove (72) in the same step comprises: A first etching process is performed, wherein the first groove (71) penetrates the second dielectric layer (52) and stops at the surface of the first dielectric layer (51), the second groove (72) stops in the second dielectric layer (52), and the size of the first groove (71) in a first horizontal direction is greater than the size of the second groove (72) in the first horizontal direction, and the first horizontal direction is the arrangement direction of the first sub-conductive structure (211) and the second sub-conductive structure (212); Performing a second etching process, wherein the first trench (71) penetrates the second sub-dielectric layer (512) and stops at the surface of the first conductive structure (21), and the second trench (72) stops in the second dielectric layer (52), and the etching selectivity ratios of the first dielectric layer (51) and the second dielectric layer (52) are different; A third etching process is performed, whereby the first trench (71) penetrates through the first conductive structure (21), and the second trench (72) exposes a portion of the surface of the second conductive structure (22).

13. The method according to claim 11, wherein: The sum of the size of the second sub-dielectric layer (512) along the thickness direction of the substrate (10) and the size of the second dielectric layer (52) along the thickness direction of the substrate (10) is less than a preset value; The method further comprises: forming a third dielectric layer (53) on the second dielectric layer (52); The forming of the first groove (71) and the second groove (72) in the same step comprises: A fourth etching process is performed, wherein the first trench (71) penetrates the third dielectric layer (53) and stops at the surface of the second dielectric layer (52), the second trench (72) stops in the third dielectric layer (53), and the size of the first trench (71) in a first horizontal direction is greater than the size of the second trench (72) in the first horizontal direction, and the first horizontal direction is the arrangement direction of the first sub-conductive structure (211) and the second sub-conductive structure (212); Performing a fifth etching process, wherein the first trench (71) penetrates the second dielectric layer (52) and the second sub-dielectric layer (512) and stops at the surface of the first conductive structure (21), the second trench (72) penetrates the third dielectric layer (53) and stops within the second dielectric layer (52), and the etching selectivity ratios of the second dielectric layer (52) and the third dielectric layer (53) are different; A sixth etching process is performed, whereby the first trench (71) penetrates the first conductive structure (21), and the second trench (72) exposes a portion of the surface of the second conductive structure (22).

14. The method according to any one of claims 10 to 13, wherein: Forming an isolation structure (41) in the first trench (71) and forming a contact plug (42) in the second trench (72), comprising: forming an insulating layer (402) on the side walls of the first trench (71) and the second trench (72); Conductive material is filled in the first trench (71) and the second trench (72) formed with the insulating layer (402) to form an isolation structure (41) in the first trench (71) and a contact plug (42) in the second trench (72).

15. The method according to any one of claims 10 to 14, wherein: The substrate (10) comprises an active region (11) and a gate structure (12) located on the active region (11), wherein the active region (11) comprises a first source-drain region (111) and a second source-drain region (112) located on opposite sides of the gate structure (12); Forming an initial first conductive layer (200) on the substrate (10), comprising: A first connecting pillar (61) and a second connecting pillar (62) and an initial first conductive layer (200) located on the first connecting pillar (61) and the second connecting pillar (62) are formed, wherein the first connecting pillar (61) contacts the first source and drain region (111), and the second connecting pillar (62) contacts the second source and drain region (112).

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