Display substrate and display panel

Abstract

Provided in the embodiments of the present disclosure are a display substrate and a display panel. The display substrate comprises a substrate, the substrate being provided with a display area and a peripheral area surrounding the display area; the display substrate comprises: a plurality of thin film transistors, each thin film transistor comprising a gate and an active pattern; each active pattern comprises a first connection part, a second connection part and a channel part connected therebetween, the channel part and the gate being arranged opposite to each other and insulated from each other; the gate of each thin film transistor is located on the side of the active pattern away from the substrate, the Hall mobility of the active pattern of each thin film transistor being greater than or equal to 20 cm2 / v.s; the display area and the peripheral area each comprise at least one thin film transistor.

Description

Display substrate and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display panel. Background Art

[0002] With the development of display technology, the use of display panels has become more and more widespread. Among them, the thin film transistor (TFT) array substrate is the main component of the current display panel device, which is used to provide a driving circuit to the display substrate. The traditional bottom gate thin film transistor has a large parasitic capacitance due to the large overlapping area between the gate and the source / drain, which leads to signal delay, and the channel length L of the produced thin film transistor is large, thus limiting its application. In related technologies, the Hall mobility of common metal oxide thin film transistors is about 10cm 2 / V·s, but in order to meet the increasingly higher demands of display substrates for resolution, refresh rate and narrow borders, higher requirements are also placed on the device characteristics of thin film transistors.

[0003] Summary of the Invention

[0004] Embodiments of the present disclosure provide a display substrate and a display panel.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising a substrate, on which a display area and a peripheral area surrounding the display area are provided, wherein the display substrate comprises:

[0006] a plurality of thin film transistors, each thin film transistor including a gate and an active pattern, each active pattern including a first connecting portion, a second connecting portion, and a channel portion connected therebetween, each channel portion being disposed opposite to the gate and insulated from the gate;

[0007] The gate of the thin film transistor is located on a side of the active pattern away from the substrate, and the Hall mobility of the active pattern of the thin film transistor is greater than or equal to 20 cm 2 / v·s;

[0008] The display area and the peripheral area respectively include at least one thin film transistor.

[0009] In some embodiments, the material of the active pattern is any one or more of a metal oxide semiconductor and a silicon semiconductor, and the morphology of the active pattern is any one or more of amorphous, partially crystalline, single crystal, and polycrystalline.

[0010] In some embodiments, the thin film transistor further includes: a light-shielding pattern, the light-shielding pattern is located on a side of the active pattern close to the substrate, and an orthographic projection of the light-shielding pattern on the substrate overlaps with an orthographic projection of the channel portion on the substrate.

[0011] In some embodiments, an orthographic projection of the light-shielding pattern on the substrate covers and exceeds an orthographic projection of the channel portion on the substrate.

[0012] In some embodiments, the display substrate includes: a first conductive layer, the first conductive layer being located on a side of the active pattern away from the substrate;

[0013] The thin film transistor further includes: a first electrode and a second electrode, wherein the first electrode and the second electrode are both located in the first conductive layer, the first electrode is connected to the first connecting portion, and the second electrode is connected to the second connecting portion;

[0014] The orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate do not overlap with the orthographic projection of the gate on the substrate.

[0015] In some embodiments, the plurality of thin film transistors include a plurality of first thin film transistors, and the first thin film transistors are located in the display area;

[0016] The display substrate further comprises: a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, wherein the data lines are located in the first conductive layer;

[0017] The plurality of gate lines and the plurality of data lines define a plurality of pixel units, the pixel units including the first thin film transistor and the corresponding pixel electrode, part of the gate line is reused as the gate of the first thin film transistor, the first electrode of the first thin film transistor is connected to the pixel electrode, and the second electrode of the first thin film transistor is connected to the data line.

[0018] In some embodiments, the gate electrode of the first thin film transistor and the light shielding pattern are insulated from each other.

[0019] In some embodiments, the active pattern of the first thin film transistor is projected onto the substrate in an L-shaped pattern, the first connecting portion and the channel portion both extend along the second direction, and the second connecting portion includes a portion extending along the first direction and a portion extending along the second direction.

[0020] In some embodiments, the plurality of thin film transistors include a plurality of second thin film transistors, and the second thin film transistors are located in the peripheral region;

[0021] The first electrode, the second electrode and the gate of the second thin film transistor are all conductive patterns extending along the second direction.

[0022] In some embodiments, the orthographic projection of the active pattern of the second thin film transistor on the substrate is a rectangular pattern, and the first connecting portion, the channel portion, and the second connecting portion are arranged in sequence along the first direction.

[0023] In some embodiments, the plurality of second thin film transistors include a plurality of first sub-transistors and a plurality of second sub-transistors.

[0024] Wherein, the light shielding pattern and the gate of the first sub-transistor are electrically connected;

[0025] The light shielding pattern and the gate of the second sub-transistor are insulated from each other.

[0026] In some embodiments, the first sub-transistor further includes: a first transfer electrode, the first transfer electrode is located in the first conductive layer, and the light-shielding pattern and the gate of the first sub-transistor are electrically connected through the first transfer electrode.

[0027] In some embodiments, the display substrate further comprises:

[0028] a buffer layer, located between the light-shielding pattern and the active pattern;

[0029] an interlayer dielectric layer, located between the active pattern and the first conductive layer, and located on a side of the gate away from the substrate;

[0030] The first transfer electrode is connected to the gate through a first via hole and is connected to the light shielding pattern through a second via hole, the first via hole is located on the interlayer dielectric layer, and the second via hole passes through the interlayer dielectric layer and the buffer layer.

[0031] The orthographic projections of the first via hole and the second via hole on the substrate do not overlap with the orthographic projection of the active pattern on the substrate.

[0032] In some embodiments, the first sub-transistor further includes: a second switching electrode, the second switching electrode is provided in the same layer as the pixel electrode, and the light-shielding pattern and the gate of the first sub-transistor are electrically connected via the second switching electrode.

[0033] In some embodiments, the display substrate further comprises:

[0034] a buffer layer, located between the light-shielding pattern and the active pattern;

[0035] an interlayer dielectric layer, located between the active pattern and the first conductive layer, and located on a side of the gate away from the substrate;

[0036] a passivation layer, located between the first conductive layer and the pixel electrode;

[0037] The second transfer electrode is connected to the gate through a third via hole and is connected to the light shielding pattern through a fourth via hole. The third via hole penetrates the interlayer dielectric layer and the passivation layer. The fourth via hole penetrates the interlayer dielectric layer, the passivation layer, and the buffer layer.

[0038] The orthographic projections of the third via hole and the fourth via hole on the substrate do not overlap with the orthographic projection of the active pattern on the substrate.

[0039] In some embodiments, the peripheral area includes a first peripheral sub-area, and the first peripheral sub-area includes a first area located on one side of the display area in the second direction.

[0040] The display substrate further includes: a plurality of multi-way selection circuits located in the first area, the multi-way selection circuits being electrically connected to the selection control signal line, the driving signal line provided by the source driver chip, and the n data lines, respectively, and configured to provide the data signals output by the source driver chip to the n data lines under the control of the selection control signal line;

[0041] The multiplexer selection circuit includes at least one second sub-transistor, part of the selection control signal line is multiplexed as the gate of the second sub-transistor, the first electrode of the second sub-transistor is connected to the drive signal line, and the second electrode of the second sub-transistor is connected to the data line corresponding to the multiplexer selection circuit to which it belongs.

[0042] In some embodiments, a plurality of the multiplexing circuits constitute a multiplexing unit.

[0043] In the same multiple-way selection unit, the first electrodes of different second sub-transistors corresponding to different multiple-way selection circuits are connected to the same driving signal line.

[0044] In some embodiments, the first peripheral sub-region further includes a second region, and the second region is located on a side of the display region away from the first region.

[0045] The display substrate further includes: an electrostatic protection circuit located in the second area, wherein the electrostatic protection circuit is configured to release static electricity generated on the display substrate.

[0046] The electrostatic protection circuit includes at least one second sub-transistor.

[0047] In some embodiments, the peripheral area further includes a second peripheral sub-area, the second peripheral sub-area includes a third area, and the third area is located on a side of the second area away from the display area.

[0048] The display substrate further includes a touch detection circuit located in the third area, and the touch detection circuit includes at least one of the first sub-transistors.

[0049] In some embodiments, the second peripheral sub-region further includes a fourth region, and the fourth region is located on both sides of the display region along the first direction.

[0050] The display substrate further includes a gate driving circuit configured to provide scanning signals to the gate lines row by row.

[0051] The gate driving circuit includes a plurality of the first sub-transistors.

[0052] In some embodiments, the width-to-length ratio of the channel portions corresponding to the first thin film transistor and the first sub-transistor respectively is 5 / 5 to 60 / 5.

[0053] In some embodiments, a width-to-length ratio of a channel portion of the second sub-transistor is 7.5 / 5 to 90 / 5.

[0054] In a second aspect, an embodiment of the present disclosure provides a display panel comprising the above-mentioned display substrate.

[0055] The display substrate provided in the embodiment of the present disclosure includes a plurality of thin film transistors. Since the active pattern act0 includes an oxide semiconductor material and the gate Gate is located on the side of the active pattern act0 away from the substrate 10, the thin film transistor is a top-gate thin film transistor, wherein the material of the active pattern act0 is a high-mobility metal oxide semiconductor material, and the Hall mobility is greater than or equal to 20cm 2 / v·s. Therefore, based on its material and structural characteristics, the thin film transistor provided by the embodiment of the present disclosure can achieve both improved mobility and stable performance. The improved mobility can achieve higher on-state current and facilitate the narrow-frame design of the display substrate. At the same time, thin film transistors with the same structure are prepared in the display area AA and the peripheral area NA, so that the corresponding stacked structures in multiple thin film transistors can be formed in the same preparation process, which is conducive to simplifying the preparation process and improving preparation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0057] FIG1 is a schematic diagram of a planar structure of a display substrate provided by an embodiment of the present disclosure.

[0058] FIG2 is a schematic diagram of a planar structure of a thin film transistor in a display area provided by an embodiment of the present disclosure.

[0059] FIG3 is a schematic diagram of the cross-sectional structure corresponding to the AA cutting line in FIG2 .

[0060] FIG4 is a schematic diagram of a planar structure of a thin film transistor in a peripheral region provided by an embodiment of the present disclosure.

[0061] FIG5 is a schematic diagram of a cross-sectional structure of a thin film transistor in a peripheral region provided by an embodiment of the present disclosure.

[0062] FIG6 a is a schematic diagram of a planar structure of a thin film transistor in another peripheral region provided by an embodiment of the present disclosure.

[0063] FIG6 b is a schematic cross-sectional view corresponding to the CC cutting line in FIG6 a .

[0064] FIG6 c is a schematic cross-sectional view corresponding to the BB section line in FIG6 a .

[0065] FIG7 a is a schematic diagram of a planar structure of a thin film transistor in another peripheral region provided by an embodiment of the present disclosure.

[0066] FIG7 b is a schematic cross-sectional view corresponding to the EE section line in FIG7 a .

[0067] FIG7 c is a schematic cross-sectional view corresponding to the DD section line in FIG7 a .

[0068] FIG8 is a schematic diagram of a planar structure of a thin film transistor in another peripheral region provided by an embodiment of the present disclosure.

[0069] Description of reference numerals:

[0070] Display substrate: substrate 10, second conductive layer 12, buffer layer BUF, active semiconductor layer Act, gate insulating layer GI, third conductive layer 13, interlayer dielectric layer ILD, first conductive layer 11, first sub-passivation layer PVX1, planarization layer PLN, fourth conductive layer 14, second sub-passivation layer PVX2 and fifth conductive layer 15, data line DL, gate line GL; pixel electrode PIX, common electrode COM, first transfer electrode Z1, second transfer electrode Z2;

[0071] Substrate: display area AA, peripheral area NA, first peripheral sub-area na1, second peripheral sub-area na2, first region q1, second region q2, third region q3, fourth region q4, binding area BA, first direction X, second direction Y;

[0072] Thin film transistor: active pattern act0, light shielding pattern S, first electrode / drain t1, second electrode / source t2, gate Gate; first connecting portion l1, second connecting portion l2, channel portion g;

[0073] A first via hole k1 , a second via hole k2 , a third via hole k3 , a fourth via hole k4 , a first sub-hole k11 , a second sub-hole k12 , a third sub-hole k13 , and a fourth sub-hole k14 . DETAILED DESCRIPTION

[0074] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0075] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0076] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0077] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0078] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0079] It should be noted that the "same-layer arrangement" in the embodiment of the present disclosure means that the two structures are formed by the same material layer through a composition process, so the two are in the same layer in terms of the stacking relationship; but this does not mean that the distance between the two and the substrate 10 must be the same.

[0080] With the development of display technology, the use of display panels has become more and more widespread. Among them, the thin film transistor (TFT) array substrate is the main component of the current display panel device, which is used to provide a driving circuit to the display substrate. The traditional bottom gate thin film transistor has a large parasitic capacitance due to the large overlapping area between the gate and the source / drain, which leads to signal delay, and the channel length L of the produced thin film transistor is large, thus limiting its application. In related technologies, the Hall mobility of common metal oxide thin film transistors is about 10cm 2 / V·s, but in order to meet the increasingly higher demands of display substrates for resolution, refresh rate and narrow borders, higher requirements are also placed on the device characteristics of thin film transistors.

[0081] FIG1 is a schematic diagram of the planar structure of a display substrate provided in an embodiment of the present disclosure, FIG2 is a schematic diagram of the planar structure of a thin film transistor in a display area provided in an embodiment of the present disclosure, and FIG3 is a schematic diagram of the cross-sectional structure corresponding to the AA cutting line in FIG2 .

[0082] In order to solve at least one or more of the above-mentioned technical problems, the present disclosure provides a display substrate, including a substrate 10, on which a display area AA and a peripheral area NA surrounding the display area AA are provided. The display substrate includes: a plurality of thin film transistors, each thin film transistor including a gate Gate and an active pattern act0, the active pattern act0 including a first connecting portion l1, a second connecting portion l2, and a channel portion g connected therebetween, the channel portion g being arranged opposite to the gate Gate and insulated from each other. The gate Gate of the thin film transistor is located on a side of the active pattern act0 away from the substrate 10, and the Hall mobility of the active pattern act0 of the thin film transistor is greater than or equal to 20 cm 2 / v·s; the display area AA and the peripheral area NA each include at least one of the above-mentioned thin film transistors.

[0083] The display substrate provided in the embodiment of the present disclosure includes a plurality of thin film transistors. Since the active pattern act0 includes an oxide semiconductor material and the gate Gate is located on the side of the active pattern act0 away from the substrate 10, the thin film transistor is a top-gate thin film transistor, wherein the material of the active pattern act0 is a high-mobility metal oxide semiconductor material, and the Hall mobility is greater than or equal to 20cm 2 / v·s. Therefore, based on its material and structural characteristics, the thin film transistor provided by the embodiment of the present disclosure can achieve both improved mobility and stable performance. The improved mobility can achieve higher on-state current and facilitate the narrow-frame design of the display substrate. At the same time, thin film transistors with the same structure are prepared in the display area AA and the peripheral area NA, so that the corresponding stacked structures in multiple thin film transistors can be formed in the same preparation process, which is conducive to simplifying the preparation process and improving preparation efficiency.

[0084] As shown in Figures 2 and 3, the display substrate includes: a substrate 10, a second conductive layer 12, a buffer layer BUF, an active semiconductor layer Act, a gate insulating layer GI, a third conductive layer 13, a buffer layer BUF, a first conductive layer 11, a first sub-passivation layer PVX1, a fourth conductive layer 14, a second sub-passivation layer PVX2, and a fifth conductive layer 15. The first conductive layer 11 includes the data line DL and the first electrode t1 and second electrode t2 of the thin-film transistor; the second conductive layer 12 includes the light-shielding pattern S of the thin-film transistor; the third conductive layer 13 includes the gate line GL and the gate Gate of the thin-film transistor; the fourth conductive layer 14 includes the common electrode COM; and the fifth conductive layer 15 includes the pixel electrode PIX. A planarization layer PLN may also be provided between the first sub-passivation layer PVX1 and the second sub-passivation layer PVX2.

[0085] The above-mentioned buffer layer BUF can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a composite film formed by alternating layers of silicon oxide films and silicon nitride films. The material of the gate insulating layer GI may include silicon oxynitride, silicon oxide, silicon nitride, silicon oxycarbide, silicon carbide nitride, aluminum oxide, aluminum nitride, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc., and the gate insulating layer GI can be formed as a single layer or multiple layers. The material of the interlayer insulating layer may include, for example, silicon compounds, metal oxides, etc. The material of the passivation layer PVX may include, for example, silicon oxynitride, silicon oxide, silicon nitride, etc. The planarization layer PLN can be made of an organic insulating material, for example, the organic insulating material includes resin materials such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, etc.

[0086] It should be noted that either the fourth conductive layer 14 or the fifth conductive layer 15 can comprise the common electrode COM and the other can comprise the pixel electrode PIX. The present disclosure does not limit the stacking relationship between the two. In the following embodiments, the structure shown in FIG. 3 is used as the basis, i.e., the pixel electrode PIX is located on the side of the common electrode COM away from the substrate 10 for further description.

[0087] In addition, as shown in Figure 1, the substrate of the display substrate in the embodiment of the present disclosure also includes a binding area BA, and a plurality of binding terminals are provided on the binding area BA. The binding terminals are configured to be connected to the driving chip and / or the flexible circuit board to provide driving signals to the pixel units in the display area.

[0088] Specifically, the graphic structure provided in each layer is described in detail in conjunction with the following embodiments.

[0089] In some embodiments, the active pattern act0 is located in the above-mentioned active semiconductor layer Act, and the material of the active pattern act0 includes a metal oxide semiconductor material, specifically including any one or more of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element doped metal oxide (RE-OS), wherein the rare earth element doped metal oxide may include lanthanide doped metal oxide (Ln-OS); the material of the active pattern act0 may also include a silicon material, specifically including any one or more of amorphous silicon, single crystal silicon, and polycrystalline silicon. The crystalline state of the active pattern act0 may be one or more of amorphous, partially crystalline, single crystal, and polycrystalline. In one example, the active pattern has high mobility and good optical stability, which can increase the Hall mobility of the corresponding thin film transistor to 20-25 cm 2 / (V·S) and maintain good characteristics.

[0090] The thin film transistor further includes a light shielding pattern S located on the side of the active pattern act0 close to the substrate 10, that is, the light shielding pattern S is located on the second conductive layer 12. The orthographic projection of the light shielding pattern S on the substrate 10 overlaps with the orthographic projection of the channel portion g on the substrate.

[0091] It should be understood that the size of the light-shielding pattern S is related to the stability requirements of the thin-film transistor characteristics. The larger the area of ​​the light-shielding pattern S, the more stable the characteristics of the thin-film transistor. Preferably, the orthographic projection of the light-shielding pattern S on the substrate 10 covers and exceeds the orthographic projection of the channel portion g on the substrate 10.

[0092] In one example, the material of the light-shielding pattern S can be a metal material, for example, the material of the light-shielding pattern S includes one or more alloys of molybdenum (Mo), copper (Cu), and titanium (Ti). In the disclosed embodiment, the light-shielding pattern S is configured to shield the channel portion g in the active pattern act0 from light, thereby reducing heat generation of the thin film transistor and preventing light from affecting the stability of the active pattern act0.

[0093] In some embodiments, the first conductive layer 11 of the display substrate is located on a side of the active pattern act0 away from the substrate 10. The thin film transistor further includes a first electrode t1 and a second electrode t2 located on the first conductive layer 11. The first electrode t1 is connected to the first connection portion l1, and the second electrode t2 is connected to the second connection portion l2. The orthographic projections of the first electrode t1 and the second electrode t2 on the substrate 10 do not overlap with the orthographic projection of the gate Gate on the substrate 10.

[0094] It should be noted that the first electrode t1 and the second electrode t2 of the thin film transistor refer to the drain and source of the thin film transistor. Correspondingly, the first connection portion l1 in the active pattern act0 is the drain connection portion, and the second connection portion l2 is the source connection portion. The source connection portion is connected to the source of the thin film transistor, and the drain connection portion is connected to the drain of the thin film transistor. Both the source connection portion and the drain connection portion can be doped with impurities (for example, N-type impurities or P-type impurities) with a higher impurity concentration than the impurity concentration of the channel portion g. The channel portion g is directly opposite to the gate Gate of the thin film transistor. When the voltage signal loaded on the gate Gate reaches a certain value, a carrier path is formed in the channel portion g, causing the source and drain of the thin film transistor to be conductive.

[0095] Furthermore, the thin film transistor in the embodiment of the present disclosure has a top-gate structure. Since there is no overlap between the gate and the source and drain, it has lower parasitic capacitance, which can reduce the delay of signal transmission. At the same time, the self-aligned manufacturing method can produce devices with shorter channels, thereby reducing the device size.

[0096] In some embodiments, the plurality of thin film transistors include a plurality of first thin film transistors, and the first thin film transistors are located in the display area AA. The display substrate further includes a plurality of gate lines GL extending along a first direction X and a plurality of data lines DL extending along a second direction Y, wherein the gate lines GL are located in the third conductive layer 13, and the data lines DL are located in the first conductive layer 11. The plurality of gate lines GL and the plurality of data lines DL define a plurality of pixel units, each of which includes a first thin film transistor and a corresponding pixel electrode PIX, wherein the pixel electrode PIX is located in the fifth conductive layer 15.

[0097] The gate line GL of the display substrate is partially reused as the gate Gate of the first thin film transistor. The first electrode t1 of the first thin film transistor is connected to the pixel electrode PIX, and the second electrode t2 of the first thin film transistor is connected to the data line DL. The pixel electrode PIX is located in the fifth conductive layer 15.

[0098] In some embodiments, the gate (Gate) of the first thin-film transistor and the light-shielding pattern (S) are insulated from each other. That is, the light-shielding pattern (S) of the first thin-film transistor is an independent metal pattern that is not connected to any other structure and therefore does not increase the parasitic capacitance of the first thin-film transistor. In the first thin-film transistor, the light-shielding pattern (S) serves solely as a light shield, preventing light from affecting the channel region of the active pattern (act0), thereby increasing the stability of the on-state current.

[0099] The first thin-film transistor provided in the display area AA in the embodiment of the present disclosure has a measured parasitic capacitance Cgs of 3.85 fF when the width-to-length ratio of the channel portion g of its active pattern act0 is 5 μm / 4 μm. Compared to conventional bottom-gate thin-film transistors in related art, its parasitic capacitance Cgs is 7.39 fF. Therefore, the parasitic capacitance Cgs of the first thin-film transistor in this solution is reduced by 1 / 2, which helps reduce the feed-through voltage of the pixel unit and the load capacitance on the scan line.

[0100] In some embodiments, as shown in Figure 3, the active pattern act0 of the first thin film transistor is projected onto the substrate 10 in an L-shaped shape, the first connection portion l1 and the channel portion g both extend along the second direction Y, and the second connection portion l2 includes a portion extending along the first direction X and a portion extending along the second direction Y.

[0101] FIG4 is a schematic diagram of a planar structure of a thin film transistor in a peripheral region according to an embodiment of the present disclosure, and FIG5 is a schematic diagram of a cross-sectional structure of a thin film transistor in a peripheral region according to an embodiment of the present disclosure.

[0102] In some embodiments, as shown in FIG4 and FIG5, the plurality of thin film transistors include a plurality of second thin film transistors, and the second thin film transistors are located in the peripheral area NA; the first electrode t1, the second electrode t2 and the gate Gate of the second thin film transistor are all conductive patterns extending along the second direction Y.

[0103] In the embodiment of the present disclosure, thin film transistors with the same structure are prepared in the display area AA and the peripheral area NA, so that the corresponding stacked structures in the multiple thin film transistors can be formed in the same preparation process, which is conducive to simplifying the preparation process and improving preparation efficiency.

[0104] In addition, as shown in FIG5 , a plurality of vias may be provided between the first electrode of the thin film transistor and the first connection portion on the active pattern, and between the second electrode and the second connection portion of the active pattern, so as to reduce parasitic capacitance on the thin film transistor.

[0105] In some embodiments, as shown in FIG4 , the orthographic projection of the active pattern act0 of the second thin film transistor on the substrate 10 is a rectangular pattern, and the first connection portion l1 , the channel portion g, and the second connection portion l2 are sequentially arranged along the first direction X. Referring to FIG2 and FIG4 , although the thin film transistors located in the display area AA and the peripheral area NA have the same stacked structure, the planar shapes of the active pattern act0 corresponding to the thin film transistors located in different areas are different.

[0106] In some embodiments, the plurality of second thin film transistors include a plurality of first sub-transistors and a plurality of second sub-transistors, wherein the light shielding pattern S and the gate Gate of the first sub-transistor are electrically connected; and the light shielding pattern S and the gate Gate of the second sub-transistor are insulated from each other.

[0107] In the embodiment of the present disclosure, the shading pattern S and the gate Gate of the above-mentioned first sub-transistor are electrically connected to form a dual-gate structure, that is, the shading pattern S is also reused as a bottom gate, and the shading pattern S and the gate Gate are electrically connected, thereby forming two conductive channels, increasing the on-state current, and effectively suppressing the negative drift of the threshold voltage, improving the carrier mobility, and thus facilitating narrow frame design.

[0108] Table 1 presents comparative data obtained through the preparation and testing of the first and second sub-transistors provided in the embodiments of the present disclosure. As shown in Table 1, when the channel portions g of the active pattern act0 corresponding to the first and second sub-transistors LS-0 and LS-F, respectively, have the same aspect ratio, and three different threshold voltages Vds are applied to the first and second sub-transistors LS-0 and LS-F, respectively, it can be seen that their on-state currents are similar. However, the Vth of the second sub-transistor LS-F exhibits a significant negative drift as the threshold voltage Vds increases. The formation of two conductive channels in the first sub-transistor LS-0 increases the on-state current, effectively suppressing the negative drift of the threshold voltage and improving carrier mobility, thus facilitating a narrow-frame design.

[0109] Table 1

[0110] Figure 6a is a schematic diagram of the planar structure of another thin-film transistor in the peripheral region according to an embodiment of the present disclosure, Figure 6b is a schematic diagram of a cross-section corresponding to the CC section in Figure 6a, and Figure 6c is a schematic diagram of a cross-section corresponding to the BB section in Figure 6a. Figure 7a is a schematic diagram of the planar structure of another thin-film transistor in the peripheral region according to an embodiment of the present disclosure, Figure 7b is a schematic diagram of a cross-section corresponding to the EE section in Figure 7a, and Figure 7c is a schematic diagram of a cross-section corresponding to the DD section in Figure 7a.

[0111] In some embodiments, in order to achieve electrical connection between the shading pattern S and the gate Gate in the first sub-transistor, the shading pattern S and the gate Gate are extended to a position where they do not overlap with the active pattern act0 in the thickness direction of the display substrate and are connected through vias.

[0112] In some embodiments, as shown in FIG6a , the first sub-transistor further includes a first transfer electrode Z1 . The first transfer electrode Z1 is located in the first conductive layer 11 , and the light-shielding pattern S and the gate Gate of the first sub-transistor are electrically connected via the first transfer electrode Z1 . In other words, the first transfer electrode Z1 is disposed on the same layer as the source / drain of the first sub-transistor.

[0113] In some embodiments, as shown in Figures 6b and 6c, the first transfer electrode Z1 is connected to the gate Gate through a first via k1, and is connected to the shading pattern S through a second via k2. The first via k1 is located on the interlayer dielectric layer ILD, and the second via k2 passes through the interlayer dielectric layer ILD and the buffer layer BUF; the orthographic projections of the first via k1 and the second via k2 on the substrate 10 do not overlap with the orthographic projection of the active pattern act0 on the substrate 10.

[0114] It should be understood that when forming the second via hole k2 , a separate mask is not used when etching the buffer material film. Instead, the same mask as that used for the interlayer dielectric material film is used, thereby saving one mask and reducing the preparation cost.

[0115] In other words, a first via k1 is first formed in the interlayer dielectric film, and then a secondary etching is performed to form a second via k2 that penetrates the buffer material film and the interlayer dielectric film. Because the buffer material film and the interlayer dielectric film use the same mask, the secondary etching of the interlayer dielectric film is equivalent to overetching. Since the active material film is located on the side of the interlayer dielectric layer ILD closest to the substrate 10, overetching the interlayer dielectric film carries the risk of damaging the active pattern act0.

[0116] As shown in Figure 5, the first conductive layer 11 is located on a side of the interlayer dielectric layer ILD away from the active semiconductor layer Act, and the active semiconductor layer Act is located between the interlayer dielectric layer ILD and the buffer layer BUF, while the first transfer electrode Z1 is located on the first conductive layer 11. In this case, when etching the second via k2, since the buffer layer BUF and the interlayer dielectric layer ILD need to be etched simultaneously, the active pattern act0 in the active semiconductor layer Act may be damaged.

[0117] In order to solve the above technical problems, as shown in FIG7a , in the display substrate provided by the embodiment of the present disclosure, the light shielding pattern S and the gate Gate in the first sub-transistor are connected via the second switching electrode Z2 , and the second switching electrode Z2 is provided in the same layer as the pixel electrode PIX.

[0118] In some embodiments, as shown in Figures 7b and 7c, the second transfer electrode Z2 is connected to the gate Gate through the third via k3, and is connected to the shading pattern S through the fourth via k4. The third via k3 penetrates the interlayer dielectric layer ILD and the passivation layer, and the fourth via k4 penetrates the interlayer dielectric layer ILD, the passivation layer and the buffer layer BUF; the orthographic projections of the third via k3 and the fourth via k4 on the substrate 10 do not overlap with the orthographic projection of the active pattern act0 on the substrate 10.

[0119] 5 , the passivation layer includes a first sub-passivation layer PVX1 and a second sub-passivation layer PVX2, wherein the first sub-passivation layer PVX1 is located on a side of the first conductive layer 11 away from the substrate 10, and the second sub-passivation layer PVX2 is located on a side of the first sub-passivation layer PVX1 away from the substrate 10. Furthermore, referring to FIG3 , in the display area AA of the display substrate, the first sub-passivation layer PVX1 is located between the pixel electrode PIX of the fifth conductive layer 15 and the drain electrode of the first conductive layer 11, and the second sub-passivation layer PVX2 is located between the pixel electrode PIX of the fifth conductive layer 15 and the common electrode COM of the fourth conductive layer 14.

[0120] It should be noted that the display substrate may further include a planarization layer PLN located between the first sub-passivation layer PVX1 and the second sub-passivation layer PVX2. In this case, the third via hole k3 and the fourth via hole k4 also penetrate the planarization layer PLN respectively.

[0121] It should be noted that the process of preparing the third via k3 includes two steps, namely, first forming a first sub-hole k11 on the interlayer dielectric material film, and then forming a third sub-hole k13 located above the first sub-hole k11 on the first passivation material film and the second passivation material film. In other words, the first sub-hole k11 and the third sub-hole k13 together constitute the third via k3.

[0122] Similarly, the process of forming the fourth via hole k4 also includes two steps, namely, first forming a second sub-hole k12 on the interlayer dielectric material film, and then forming a fourth sub-hole k14 connected to the second sub-hole k12 on the first passivation material film, the second passivation material film and the buffer material film. In other words, the second sub-hole k12 and the fourth sub-hole k14 together constitute the fourth via hole k4.

[0123] As can be seen, a separate mask is not used when forming the via hole in the buffer material film. Instead, the via hole is formed using the same masking process as the first and second passivation material films. In this case, the via hole formed in the buffer material film is formed through the second sub-hole k12. This means that the formation of the via hole in the buffer material film does not affect the interlayer dielectric layer ILD, preventing overetching of the interlayer dielectric film and thus avoiding damage to the active pattern act0.

[0124] The first sub-transistor provided in the embodiment of the present disclosure and located in the peripheral area NA has a light-shielding pattern S reused as a bottom gate to form a thin-film transistor with a dual-gate structure. Therefore, its source and drain will be affected by the positive gate voltage of the bottom gate and accumulate carriers, so that the resistance of the source and drain is greatly reduced, thereby reducing the heat generated by the first sub-transistor and reducing damage to the first sub-transistor.

[0125] FIG8 is a schematic diagram of a planar structure of a thin film transistor in another peripheral region provided by an embodiment of the present disclosure.

[0126] In some embodiments, the peripheral area NA includes a first peripheral sub-area na1, and the first peripheral sub-area na1 includes a first region located on one side of the display area AA in the second direction Y. The display substrate further includes: a plurality of multi-way selection circuits located in the first region, the multi-way selection circuits being electrically connected to the selection control signal line, the drive signal line provided by the source driver chip, and the n data lines DL, respectively, and being configured to provide data signals output by the source driver chip to the n data lines DL under the control of the selection control signal line.

[0127] As shown in Figure 8, the multiplexer circuit includes at least one second sub-transistor, and part of the selection control signal line MUX is multiplexed as the gate Gate of the second sub-transistor. The first electrode t1 of the second sub-transistor is connected to the drive signal line, and the second electrode t2 of the second sub-transistor is connected to the data line DL corresponding to the multiplexer circuit to which it belongs.

[0128] In some embodiments, as shown in FIG8 , a plurality of multiplexer circuits constitute a multiplexer unit. In the same multiplexer unit, the first electrodes t1 of different second sub-transistors corresponding to different multiplexer circuits are connected to the same driving signal line CL.

[0129] Specifically, a plurality of selection units may include multiple multi-way selection circuits, wherein one of the multi-way selection circuits may correspond to at least one second sub-transistor. When a multi-way selection circuit corresponds to multiple second sub-transistors, the light-shielding patterns S of the multiple second sub-transistors are independently configured, which helps the multi-way selection circuit maintain a good heat dissipation state and thus ensures device stability. Furthermore, the first electrodes t1 of the second sub-transistors corresponding to the multiple multi-way selection circuits included in a multi-way selection unit can be connected to the same drive signal line CL.

[0130] In some embodiments, as shown in Figure 1, the first peripheral sub-area na1 also includes a second area, the second area is located on the side of the display area AA away from the first area, and the display substrate also includes: an electrostatic protection circuit located in the second area, the electrostatic protection circuit is configured to release static electricity generated on the display substrate, and the electrostatic protection circuit includes at least one second sub-transistor.

[0131] The second sub-transistor in the electrostatic protection circuit located in the second region has the same structure as the transistor in FIG5 , and will not be described in detail here.

[0132] In some embodiments, as shown in Figure 1, the peripheral area NA also includes a second peripheral sub-area na2, the second peripheral sub-area na2 includes a third area, the third area is located on the side of the second area away from the display area AA, and the display substrate also includes: a touch detection circuit located in the third area, and the touch detection circuit includes at least one of the first sub-transistors.

[0133] In some embodiments, as shown in Figure 1, the second peripheral sub-area na2 also includes a fourth area, which is located on both sides of the display area AA along the first direction X. The display substrate also includes a gate drive circuit, and the gate drive circuit is configured to provide a scan signal to the gate line GL row by row. The gate drive circuit includes multiple first sub-transistors.

[0134] In the disclosed embodiment, the first sub-transistor of the active pattern act0 formed by a high-mobility metal oxide semiconductor material is applied to the gate drive circuit. Compared with the conventional oxide thin film transistor, the on-state current Ion is increased by about 8 times and 5 times respectively. Without changing the original circuit structure of the gate drive, the driving capability of the gate drive circuit can be greatly improved, the size of the thin film transistor in the gate drive circuit can be reduced, and a high-resolution unilateral drive design can be realized, saving the left and right borders of the panel, so that it presents an ultra-narrow border display appearance.

[0135] The touch detection circuit located in the third area and the first sub-transistor in the gate driving electrode located in the fourth area can be connected to the shading pattern S and the corresponding gate Gate through the first switching electrode Z1 shown in Figure 6a, or can be connected to the shading pattern S and the corresponding gate Gate through the second switching electrode Z2 shown in Figure 7a. The embodiments of the present disclosure are not limited to this.

[0136] Table 2 shows multiple sets of width-to-length ratio data for the first sub-transistor, the second sub-transistor (the first thin-film transistor) provided in the embodiment of the present disclosure, and comparative examples 1 and 2 in the same load circuit under different circumstances. Among them, comparative examples 1 and 2 are both bottom-gate thin-film transistors formed by the back channel etch (BCE) process, but the material of the active pattern act0 in comparative example 1 is the same as that in the embodiment of the present disclosure, and the material of the active pattern act0 in comparative example 2 is a conventional oxide material. It can be seen from Table 2 that in the same set of load circuits, that is, when achieving the same on-state current, the width-to-length ratio and overall size of the first sub-transistor and the second sub-transistor provided in the embodiment of the present disclosure are significantly smaller than those of the thin-film transistor in the comparative example, which is conducive to achieving a narrow-frame design.

[0137] Table 2

[0138] Based on the same inventive concept as above, an embodiment of the present disclosure further provides a method for preparing a display substrate, which is used to prepare the display substrate in any of the above embodiments.

[0139] The following describes in detail how the first thin film transistor (second sub-transistor), the first sub-transistor including the first switching electrode Z1, and the first sub-transistor including the second switching electrode Z2 are prepared in this application through specific examples.

[0140] Example 1

[0141] The first thin film transistor shown in FIG. 2 and FIG. 3 is formed by steps S11 to S20, specifically including:

[0142] In step S11 , a substrate 10 is provided, a light shielding pattern S is formed on the substrate 10 , a buffer layer BUF is formed on a side of the light shielding pattern S away from the substrate 10 , and a metal oxide semiconductor film is formed on a side of the buffer layer BUF away from the substrate 10 .

[0143] The substrate 10 is a glass substrate, but is not limited thereto. It may also be a PI substrate or other substrate. The buffer layer BUF prevents ions in the glass substrate or quartz substrate from migrating into the thin film transistor and affecting its performance. Specifically, the buffer layer BUF may be made of an oxide, a nitride, or an oxynitride compound.

[0144] Step S12: patterning the oxide semiconductor film to form an active pattern act0. Forming a gate insulating layer GI covering the active pattern act0 on the buffer layer BUF, and depositing a third metal film on the gate insulating layer GI.

[0145] In step S13 , a photoresist layer is formed on the gate insulating layer GI, and patterned to form a photoresist pattern to define the position of the gate.

[0146] In step S14, the third metal film is etched using the photoresist pattern as a first mask to form a gate.

[0147] In step S15 , the gate insulating layer GI is etched using the photoresist pattern and the gate Gate as a second mask to form a corresponding gate insulating pattern.

[0148] In step S16, the active pattern act0 is subjected to a conductorization process using the photoresist pattern, the gate Gate and the gate insulation pattern as a third mask, and the photoresist material is stripped after the conductorization process is completed.

[0149] In the active pattern act0 after the conductorization process, the first connection portion l1 and the second connection portion l2 become conductors, and the channel portion g maintains semiconductor characteristics.

[0150] Step S17 , forming an interlayer dielectric material film above the active pattern act0 and the gate Gate, and forming a source contact hole and a drain contact hole in the interlayer dielectric material film.

[0151] In step S18, a first metal film is formed on the interlayer dielectric layer ILD, and a first electrode t1 and a second electrode t2 of the first thin film transistor are formed by patterning, wherein the first electrode t1 is connected to the first connecting portion l1 through a drain contact hole, and the second electrode t2 is connected to the second connecting portion l2 through a source contact hole.

[0152] Step S19 , forming a first sub-passivation layer PVX1 on the interlayer dielectric layer ILD to cover the first electrode t1 and the second electrode t2 of the first thin film transistor.

[0153] Of course, after step S19, the process further includes forming a planar layer on the first sub-passivation layer PVX1, forming a common electrode COM on the planar layer, and then forming a second sub-passivation layer PVX2 on the planarization layer PLN to cover the common electrode COM; forming a via hole penetrating the second sub-passivation layer PVX2, the planarization layer PLN, and the first planarization layer PLN; and forming a pixel electrode PIX on the second sub-passivation layer PVX2, the pixel electrode PIX being connected to the first electrode t1 of the first thin film transistor through the via hole. In this way, the display substrate including the first thin film transistor is prepared.

[0154] Example 2

[0155] The first sub-transistor including the first transfer electrode Z1 is formed through steps S21 to S29, wherein steps S21 to S26 and step S29 are the same as steps S11 to S16 and step S19 in the first embodiment, and are not described here. Only the formation process of the first via hole k1 and the second via hole k2 is shown in detail, as follows:

[0156] In step S27, an interlayer dielectric material film is formed above the active pattern act0 and the gate Gate, and a first transfer mask is used to pattern the interlayer dielectric material film to form a first via k1, a source contact hole, and a drain contact hole. Furthermore, the first transfer mask is used again to pattern the interlayer dielectric material film to form a second via k2 that penetrates the interlayer dielectric material film and the buffer material film, thereby forming the final interlayer dielectric layer ILD and buffer layer BUF.

[0157] It should be noted that the first via k1 formed on the interlayer dielectric material film is configured to connect the first transfer electrode Z1 and the gate Gate, and the second via k2 is configured to connect the first transfer electrode Z1 and the light shielding pattern S. Furthermore, in the process of forming the second via k2, a separate mask is not used when etching the buffer material film, but the same mask as the interlayer dielectric material film is used, thereby saving one mask and reducing manufacturing costs.

[0158] Step S28 , forming a first metal thin film on the interlayer dielectric layer ILD, and forming a first transfer electrode Z1 , a first electrode t1 , and a second electrode t2 of a first thin film transistor through patterning.

[0159] The first electrode t1 is connected to the first connecting part l1 through the drain contact hole, and the second electrode t2 is connected to the second connecting part l2 through the source contact hole; the first transfer electrode Z1 is connected to the gate Gate through the first via k1 and to the shading pattern S through the second via k2, thereby realizing the connection between the gate Gate and the shading pattern S, so that the first sub-transistor forms a dual-gate structure.

[0160] Example 3:

[0161] The first sub-transistor including the second transfer electrode Z2 is formed through steps S31 to S39, wherein steps S31 to S26 and step S28 are the same as steps S11 to S16 and step S18 in the first embodiment, and are not described here. Only the formation process of the third via hole k3 and the fourth via hole k4 is shown in detail, as follows:

[0162] In step S27 , an interlayer dielectric material film is formed above the active pattern act0 and the gate Gate, and a second transfer mask is used to pattern the interlayer dielectric material film to form a first sub-hole k11 , a second sub-hole k12 , and a source contact hole and a drain contact hole.

[0163] In step S29, a first passivation material film and a second passivation material film are formed on the interlayer dielectric layer ILD, covering the first electrode t1 and the second electrode t2 of the first thin-film transistor. A third sub-hole k13 is formed through the first passivation material film and the second passivation material film, and a fourth sub-hole k14 is formed through the first passivation material film, the second passivation material film, and the buffer material film using a second transfer mask. The third sub-hole k13 is connected to the first sub-hole k11, and the fourth sub-hole k14 is connected to the second sub-hole k12.

[0164] In one example, the orthographic projection of the first sub-hole k11 on the substrate 10 partially overlaps with the orthographic projection of the third sub-hole k13 on the substrate 10; the orthographic projection of the second sub-hole k12 on the substrate 10 partially overlaps with the orthographic projection of the fourth sub-hole k14 on the substrate 10. Preferably, as shown in Figures 7b and 7c, the orthographic projection of the third sub-hole k13 on the substrate 10 covers the orthographic projection of the first sub-hole k11 on the substrate 10; and the orthographic projection of the fourth sub-hole k14 formed on the first passivation material film and the second passivation material film on the substrate 10 covers the orthographic projection of the second sub-hole k12 on the substrate 10.

[0165] It should be noted that the process of forming the third via k3 includes two steps, namely, first forming a first sub-hole k11 on the interlayer dielectric material film, and then forming a third sub-hole k13 located above the first sub-hole k11 on the first passivation material film and the second passivation material film. In other words, the first sub-hole k11 and the third sub-hole k13 together constitute the third via k3.

[0166] Similarly, the process of forming the fourth via k4 also includes two steps: first, forming a second sub-hole k12 in the interlayer dielectric material film, and then forming a fourth sub-hole k14 connecting to the second sub-hole k12 in the first passivation material film, the second passivation material film, and the buffer material film. In other words, the second sub-hole k12 and the fourth sub-hole k14 together constitute the fourth via k4. As can be seen from this, when forming the via in the buffer material film, a separate mask is not used. Instead, the via is formed in the same mask process as the first passivation material film and the second passivation material film, thereby saving a mask and reducing manufacturing costs.

[0167] In step S30, a fifth metal material film is formed on the second passivation material film, and a second transfer electrode Z2 is formed through patterning. The second transfer electrode Z2 is connected to the gate Gate through the third via k3 and to the shading pattern S through the fourth via k4, thereby realizing the connection between the gate Gate and the shading pattern S, so that the first sub-transistor forms a dual-gate structure.

[0168] An embodiment of the present disclosure further provides a display panel, comprising the above-mentioned display substrate.

[0169] The display panel may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., and the present disclosure does not limit this.

[0170] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, wherein: The display substrate comprises a substrate, on which a display area and a peripheral area surrounding the display area are arranged, and the display substrate comprises: A plurality of thin film transistors, each thin film transistor comprising a gate and an active pattern, each active pattern comprising a first connecting portion, a second connecting portion and a channel portion connected therebetween, each channel portion being arranged opposite to the gate and insulated from the gate; The gate of the thin film transistor is located on a side of the active pattern away from the substrate, and the Hall mobility of the active pattern of the thin film transistor is greater than or equal to 20 cm 2 / v·s; The display area and the peripheral area respectively include at least one thin film transistor.

2. The display substrate according to claim 1, wherein: The material of the active pattern is any one or more of metal oxide semiconductor and silicon semiconductor, and the morphology of the active pattern is any one or more of amorphous, partially crystalline, single crystal and polycrystalline.

3. The display substrate according to claim 1, wherein: The thin film transistor further includes a light shielding pattern, which is located on a side of the active pattern close to the substrate, and an orthographic projection of the light shielding pattern on the substrate overlaps with an orthographic projection of the channel portion on the substrate.

4. The display substrate according to claim 3, wherein: The orthographic projection of the light-shielding pattern on the substrate covers and exceeds the orthographic projection of the channel portion on the substrate.

5. The display substrate according to claim 3 or 4, wherein: The display substrate comprises: a first conductive layer, the first conductive layer being located on a side of the active pattern away from the substrate; The thin film transistor further includes: a first electrode and a second electrode, wherein the first electrode and the second electrode are both located in the first conductive layer, the first electrode is connected to the first connecting portion, and the second electrode is connected to the second connecting portion; The orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate do not overlap with the orthographic projection of the gate on the substrate.

6. The display substrate according to claim 5, wherein: The plurality of thin film transistors include a plurality of first thin film transistors, and the first thin film transistors are located in the display area; The display substrate further comprises: a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, wherein the data lines are located in the first conductive layer; The plurality of gate lines and the plurality of data lines define a plurality of pixel units, the pixel units include the first thin film transistor and a corresponding pixel electrode, a portion of the gate line is reused as a gate of the first thin film transistor, a first electrode of the first thin film transistor is connected to the pixel electrode, and a second electrode of the first thin film transistor is connected to the data line.

7. The display substrate according to claim 6, wherein: The gate electrode of the first thin film transistor and the light shielding pattern are insulated from each other.

8. The display substrate according to claim 6, wherein: The orthographic projection of the active pattern of the first thin film transistor on the substrate is an L-shaped pattern, the first connecting portion and the channel portion both extend along the second direction, and the second connecting portion includes a portion extending along the first direction and a portion extending along the second direction.

9. The display substrate according to claim 6, wherein: The plurality of thin film transistors include a plurality of second thin film transistors, and the second thin film transistors are located in the peripheral area; The first electrode, the second electrode and the gate electrode of the second thin film transistor are all conductive patterns extending along the second direction.

10. The display substrate according to claim 9, wherein: The orthographic projection of the active pattern of the second thin film transistor on the substrate is a rectangular pattern, and the first connecting portion, the channel portion and the second connecting portion are arranged in sequence along the first direction.

11. The display substrate according to claim 9, wherein: The plurality of second thin film transistors include a plurality of first sub-transistors and a plurality of second sub-transistors, Wherein, the light shielding pattern and the gate of the first sub-transistor are electrically connected; The light shielding pattern and the gate of the second sub-transistor are insulated from each other.

12. The display substrate according to claim 11, wherein: The first sub-transistor further includes: a first switching electrode, the first switching electrode is located in the first conductive layer, and the light shielding pattern and the gate of the first sub-transistor are electrically connected through the first switching electrode.

13. The display substrate according to claim 12, wherein: The display substrate further comprises: A buffer layer, located between the light shielding pattern and the active pattern; an interlayer dielectric layer, located between the active pattern and the first conductive layer, and located on a side of the gate away from the substrate; The first transfer electrode is connected to the gate through a first via hole and is connected to the light shielding pattern through a second via hole, the first via hole is located on the interlayer dielectric layer, and the second via hole penetrates the interlayer dielectric layer and the buffer layer. The orthographic projections of the first via hole and the second via hole on the substrate do not overlap with the orthographic projection of the active pattern on the substrate.

14. The display substrate according to claim 11, wherein: The first sub-transistor further includes: a second switching electrode, the second switching electrode is arranged in the same layer as the pixel electrode, and the light shielding pattern and the gate of the first sub-transistor are electrically connected through the second switching electrode.

15. The display substrate according to claim 14, wherein: The display substrate further comprises: A buffer layer, located between the light shielding pattern and the active pattern; an interlayer dielectric layer, located between the active pattern and the first conductive layer, and located on a side of the gate away from the substrate; A passivation layer, located between the first conductive layer and the pixel electrode; The second transfer electrode is connected to the gate through a third via hole and is connected to the light shielding pattern through a fourth via hole, the third via hole penetrates the interlayer dielectric layer and the passivation layer, and the fourth via hole penetrates the interlayer dielectric layer, the passivation layer and the buffer layer. The orthographic projections of the third via hole and the fourth via hole on the substrate do not overlap with the orthographic projection of the active pattern on the substrate.

16. The display substrate according to claim 11, wherein: The peripheral area includes a first peripheral sub-area, and the first peripheral sub-area includes a first area located on one side of the display area in the second direction. The display substrate further comprises: a plurality of multi-way selection circuits located in the first area, the multi-way selection circuits being electrically connected to the selection control signal line, the driving signal line provided by the source driving chip and the n data lines respectively, and being configured to provide the data signal output by the source driving chip to the n data lines under the control of the selection control signal line; The multi-way selection circuit includes at least one second sub-transistor, part of the selection control signal line is multiplexed as the gate of the second sub-transistor, the first electrode of the second sub-transistor is connected to the drive signal line, and the second electrode of the second sub-transistor is connected to the data line corresponding to the multi-way selection circuit to which it belongs.

17. The display substrate according to claim 16, wherein: A plurality of said multiplexer circuits constitute a multiplexer unit, In the same multiplexer selection unit, different multiplexer selection circuits correspond to different second sub-crystals. The first electrode of the tube is connected to the same driving signal line.

18. The display substrate according to claim 16, wherein: The first peripheral sub-area further includes a second area, and the second area is located on a side of the display area away from the first area. The display substrate further comprises: an electrostatic protection circuit located in the second area, the electrostatic protection circuit being configured to release static electricity generated on the display substrate, The electrostatic protection circuit includes at least one of the second sub-transistors.

19. The display substrate according to claim 18, wherein: The peripheral area further includes a second peripheral sub-area, the second peripheral sub-area includes a third area, and the third area is located on a side of the second area away from the display area. The display substrate further includes: a touch detection circuit located in the third area, and the touch detection circuit includes at least one of the first sub-transistors.

20. The display substrate according to claim 19, wherein: The second peripheral sub-area further includes a fourth area, and the fourth area is located on both sides of the display area along the first direction. The display substrate further comprises a gate driving circuit, wherein the gate driving circuit is configured to provide scanning signals to the gate lines row by row. The gate driving circuit includes a plurality of the first sub-transistors.

21. The display substrate according to claim 11, wherein: The width-to-length ratios of the channel portions corresponding to the first thin film transistor and the first sub-transistor are 5 / 5 to 60 / 5.

22. The display substrate according to claim 11, wherein: The width-to-length ratio of the channel portion of the second sub-transistor is 7.5 / 5 to 90 / 5.

23. A display panel, wherein: A display substrate comprising any one of claims 1-22.

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