Optimal current selection method for hybrid parallel integrated power supply

Abstract

The present invention provides an optimal current selection method for a hybrid parallel integrated power supply. The method comprises the following steps: step S1, selecting multiple power device combinations of Si IGBT and SiC MOSFET having different current ratios; step S2, performing cost analysis on the Si IGBT devices and SiC MOSFET devices having different current ratios; step S3, performing junction temperature analysis and comparison on the Si IGBT devices and the SiC MOSFET devices having different current ratios; step S4, comparing the efficiency of the hybrid parallel integrated power supply having multiple current ratios at different power levels and different SiC MOSFET switching frequencies; step S5, performing comparative analysis on EMI noise of the hybrid parallel integrated power supply, and studying the influence of different current ratios on the EMI noise of the hybrid parallel integrated power supply; step S6, studying the influence of different current ratios on device cost and junction temperature, and the efficiency and EMI noise of the hybrid parallel integrated power supply; step S7, selecting an optimal current ratio of the hybrid parallel integrated power supply.

Description

A method for selecting optimal current of hybrid parallel integrated power supply Technical Field

[0001] The present invention relates to the field of power electronics, and in particular to a method for selecting an optimal current of a hybrid parallel integrated power supply. Background Art

[0002] As a core component of shore power systems for energy conversion and system control, the inverter determines the stable, reliable, and efficient operation of the entire power system. Therefore, research on high-power, high-performance, and cost-effective integrated power supplies is urgent. Si IGBTs and SiC MOSFETs are the core components of hybrid parallel integrated power supplies, and their characteristics directly impact their performance. The high capacity and low cost of Si IGBT inverters, combined with the low losses, high switching frequency, and high harmonic suppression capabilities of SiC MOSFET inverters, have garnered considerable attention. However, comprehensive theoretical research on current matching in hybrid parallel inverters is lacking. Hybrid parallel integrated power supplies also face key technical challenges, including a lack of research on optimal current matching for devices and an immature power distribution optimization scheme.

[0003] The study analyzes the impact of different current ratios on device cost and junction temperature, as well as the efficiency and EMI noise of hybrid parallel integrated power supplies, and selects the optimal current ratio for the topology hybrid parallel integrated power supply.

[0004] The prior art patent, titled "An Inverter, Control Method, and Computer Device," with publication number CN110601523A, includes a sequentially connected DC source, a half-bridge inverter topology, a low-pass filter, and a load. The half-bridge inverter topology includes a hybrid device comprised of a SiIGBT and a high-frequency power device connected in parallel; the high-frequency power device includes, but is not limited to, a Si-based CoolMOS, SiC MOSFET, and GaN HEMT. This invention prevents excessive operating junction temperatures of power electronic devices and increases the lifespan of the inverter. However, it fails to demonstrate the advantages of a hybrid integrated power supply, as does the present invention, which requires high cost-effectiveness and high performance for a hybrid parallel integrated power supply.

[0005] Summary of the Invention

[0006] To solve the above technical problems, the present invention provides a method for selecting the optimal current of a hybrid parallel integrated power supply. The specific technical solution is as follows:

[0007] A method for selecting an optimal current of a hybrid parallel integrated power supply, the method comprising the following steps:

[0008] Step S1: selecting multiple power device combinations of Si IGBTs and SiC MOSFETs with different current ratios;

[0009] Step S2: performing cost analysis on Si IGBT devices and SiC MOSFET devices with different current ratios;

[0010] Step S3: performing junction temperature analysis and comparison on Si IGBT devices and SiC MOSFET devices with different current ratios;

[0011] Step S4: comparing the efficiency of hybrid parallel integrated power supplies with various current ratios at different power levels and different SiC MOSFET switching frequencies;

[0012] Step S5: performing comparative analysis on the EMI noise of the hybrid parallel integrated power supply, and studying the effects of different current ratios on the EMI noise of the hybrid parallel integrated power supply;

[0013] Step S6: Study the effects of different current ratios on device cost and junction temperature as well as efficiency and EMI noise of hybrid parallel integrated power supplies;

[0014] Step S7: Selecting the optimal current ratio of the hybrid parallel integrated power supply.

[0015] Furthermore, the current matching ratio in step S1 is defined as γ, where γ is the ratio of the rated current level of the Si IGBT to the rated current level of the SiC MOSFET under the operating condition of 100° C.:

[0016] Furthermore, the cost analysis method in step 2 is: summarizing the current levels and device costs of Si IGBT and SiC MOSFET device combinations, and fitting the data into a curve to derive market patterns and conduct comparative analysis.

[0017] Furthermore, the specific method in step S4 is: under a certain SiC MOSFET switching frequency, the hybrid parallel integrated power supply operates at different power levels, analyzes the impact of different current ratios on the efficiency of the hybrid parallel integrated power supply, and records the total device loss; under certain conditions of the hybrid parallel integrated power supply power level, increases the operating frequency of the SIC MOSFET under different current ratios, and analyzes the impact of the SIC MOSFET operating frequency on the power supply efficiency.

[0018] Furthermore, in step S5, the power devices used in the Si IGBT inverter and the SiC MOSFET inverter have the same rated current, and the current ratio of the hybrid parallel integrated power supply is 1:1. The EMI noise spectrum amplitudes of the SiC MOSFET parallel inverter and the Si IGBT parallel inverter within a certain resonant frequency range are compared.

[0019] Furthermore, the method for studying the influence of different current ratios on the EMI noise of the hybrid parallel integrated power supply in step S5 is: increasing the current ratio from 1:1 to 4:1, comparing and analyzing the noise voltage waveform and spectrum envelope of the hybrid parallel integrated power supply, observing the changes in turn-on ringing and turn-off ringing, and observing and comparing the EMI noise spectrum amplitude within a certain frequency range.

[0020] Furthermore, we can solve the formula: M=TPtyΔη-Δcos t (1-2)

[0021] The differential investment recovery period Y (years) of the hybrid parallel integrated power supply under different current ratios can be calculated by formula (1-1), that is, the additional device cost can be recovered within Y years, and the additional income M (￥) increased during the working life of the hybrid parallel integrated power supply can be calculated by formula (1-2), where P (kW) is the power level of the hybrid parallel integrated power supply, t (h) is the average annual working time of the hybrid parallel integrated power supply, y (￥ / W) is the device loss cost saved as the current ratio decreases, Δcost (￥) is the total device cost of the hybrid parallel integrated power supply that increases as the current ratio decreases, T is the working life of the hybrid parallel integrated power supply, and Δη is the change in the efficiency of the hybrid parallel integrated power supply as the current ratio decreases.

[0022] Beneficial effects of the present invention:

[0023] 1. This invention selects multiple device combinations with different current ratios and applies them to a hybrid parallel integrated power supply. The impact of current ratio on device cost, device junction temperature, hybrid parallel integrated power supply efficiency, and EMI noise is analyzed. It is concluded that as current ratio increases, total device cost decreases, device junction temperature increases, hybrid parallel integrated power supply efficiency decreases, and EMI noise increases.

[0024] 2. The present invention achieves efficiency improvement without causing significant EMI noise interference, which confirms the superiority of the hybrid parallel integrated power supply.

[0025] 3. The present invention calculates the differential investment payback period and additional income of the hybrid parallel integrated power supply under different current ratios, while considering the impact of the current ratio on the device junction temperature and EMI noise, and adopts the optimal current ratio of 2:1 to meet the requirements of high cost performance and high performance of the hybrid parallel integrated power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a flow chart of a method for optimal matching of hybrid parallel integrated power supplies.

[0027] Figure 2 shows a combination diagram of four power devices with different current ratios, including Si IGBTs and SCT series SiC MOSFETs.

[0028] Figure 3 shows the total cost of Si IGBT and SiC MOSFET device combinations under four current ratios.

[0029] Figure 4 is a comparison of device losses and device junction temperatures for Si IGBT and SiC MOSFET under four current ratios.

[0030] Figure 5 shows the efficiency diagram of the integrated power converter for four current ratios at power levels ranging from 1kW to 7kW.

[0031] Figure 6 shows the integrated power efficiency of SiC MOSFET for four current ratios at switching frequencies from 10kHz to 60kHz. DETAILED DESCRIPTION

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments derived by those skilled in the art based on the embodiments of the present invention without inventive effort shall fall within the scope of protection of the present invention.

[0033] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as limiting the present invention.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referenced. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0035] In the present invention, unless otherwise clearly specified or limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components.

[0036] Step S1: Select multiple power device combinations with different current ratios of Si IGBTs and SCT series SiC MOSFETs, where the current ratio is defined as γ, which is the ratio of the Si IGBT rated current level to the Si IGBT rated current level under 100°C operating conditions:

[0037] As shown in FIG2 , in this embodiment, current ratios of 1:1, 2:1, 3:1, and 4:1 are selected, and the sum of the rated currents of the Si IGBT device and the SiC MOSFET is close to 40A for comparison and explanation;

[0038] Step S2: Cost analysis is performed on Si IGBT devices and SiC MOSFET devices with different current ratios. The current levels and device costs of Si IGBT and SiC MOSFET device combinations are summarized, and the data is fitted into a curve to derive market trends and conduct comparative analysis, as shown in Figure 3.

[0039] Step S3: performing junction temperature analysis and comparison on Si IGBT devices and SiC MOSFET devices with different current ratios. In this embodiment, the experimental analysis is performed under the operating conditions of a power level of 6 kW and an operating frequency of 20 kHz. The junction temperatures of Si IGBT devices and SiC MOSFET devices with different current ratios are analyzed. The current ratios are 1:1, 2:1, 3:1, and 4:1. The junction temperature changes of the devices with different current ratios are observed. The maximum junction temperature does not exceed 126°C as an example for illustration, as shown in FIG4 .

[0040] Step S4: Comparing the efficiencies of hybrid parallel integrated power supplies with various current ratios at different power levels and different SiC MOSFET switching frequencies, as shown in FIG5 . In this embodiment, the specific method is to set the current ratios to 1:1, 2:1, 3:1, and 4:1 at a certain SiC MOSFET switching frequency, operate the hybrid parallel integrated power supply at different power levels, analyze the effects of different current ratios on the efficiency of the hybrid parallel integrated power supply, and record the total device loss. As shown in FIG6 , under certain conditions of the hybrid parallel integrated power supply power level, the current ratios are set to 1:1, 2:1, 3:1, and 4:1, increase the operating frequencies of the SIC MOSFETs under different current ratios, and analyze the effects of the SIC MOSFET operating frequencies on the power supply efficiency.

[0041] Step S5: performing a comparative analysis of the EMI noise of the hybrid parallel integrated power supply, and studying the effects of different current ratios on the EMI noise of the hybrid parallel integrated power supply; wherein the power devices used in the Si IGBT inverter and the SiC MOSFET inverter have the same rated current, and the current ratio of the hybrid parallel integrated power supply is 1:1, comparing the spectrum amplitude of the SiC MOSFET parallel inverter with the EMI noise spectrum amplitude of the Si IGBT parallel inverter within a certain resonant frequency range;

[0042] In this embodiment, the method for studying the impact of different current ratios on the EMI noise of the hybrid parallel integrated power supply is as follows: the current ratio is increased from 1:1 to 4:1, the noise voltage waveform and spectrum envelope of the hybrid parallel integrated power supply are compared and analyzed, the changes in turn-on ringing and turn-off ringing are observed, and the amplitude of the EMI noise spectrum within a certain frequency range is observed and compared.

[0043] Step S6: Study the impact of different current ratios on device cost and junction temperature as well as hybrid parallel integrated power supply efficiency and EMI noise.

[0044] Step S7: Selecting the optimal current ratio of the hybrid parallel integrated power supply.

[0045] First, statistics are made on the efficiency and total device cost of the hybrid parallel integrated power supply under certain power levels and operating frequencies. There is an optimal current ratio, which can balance the economic benefits saved by reducing device losses and improving the efficiency of the hybrid parallel integrated power supply with the increased total investment cost of its power devices. The hybrid parallel integrated power supply with this current ratio has the highest cost-effectiveness. The reduction in the total loss of power devices in the hybrid parallel integrated power supply means that the efficiency of the system can be improved, which can shorten the difference in investment recovery years and at the same time increase additional benefits within the working life of the hybrid parallel integrated power supply.

[0046] Solve the formula: M=TPtyΔη-Δcos t (1-2)

[0047] The differential investment recovery period Y (years) of the hybrid parallel integrated power supply under different current ratios can be calculated by formula (1-1), that is, the additional device cost can be recovered within Y years, and the additional income M (￥) increased during the working life of the hybrid parallel integrated power supply can be calculated by formula (1-2), where P (kW) is the power level of the hybrid parallel integrated power supply, t (h) is the average annual working time of the hybrid parallel integrated power supply, y (￥ / W) is the device loss cost saved as the current ratio decreases, Δcost (￥) is the total device cost of the hybrid parallel integrated power supply that increases as the current ratio decreases, T is the working life of the hybrid parallel integrated power supply, and Δη is the change in the efficiency of the hybrid parallel integrated power supply as the current ratio decreases.

[0048] The present invention solves the key technical difficulties faced by hybrid parallel integrated power supplies, such as the lack of research on optimal current ratios for devices and the immaturity of power distribution optimization schemes, by hybrid use of power devices and adoption of high switching frequencies, and by building an experimental platform for a parallel integrated power supply consisting of Si IGBTs and SiC MOSFET inverters. This provides a high-performance and cost-effective power supply solution.

[0049] The above is only a preferred embodiment of the present invention, and its description is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that several improvements and modifications can be made without departing from the concept of the present invention, which all fall within the scope of protection of the present invention.

Claims

1. A method for selecting optimal current of a hybrid parallel integrated power supply, characterized in that: The method comprises the following steps: Step S1: selecting multiple groups of power device combinations with different current ratios of Si IGBT and SiC MOSFET; Step S2: performing cost analysis on Si IGBT devices and SiC MOSFET devices with different current ratios; Step S3: performing junction temperature analysis and comparison on Si IGBT devices and SiC MOSFET devices with different current ratios; Step S4: comparing the efficiency of hybrid parallel integrated power supplies with various current ratios at different power levels and different SiC MOSFET switching frequencies; Step S5: performing comparative analysis on the EMI noise of the hybrid parallel integrated power supply, and studying the influence of different current ratios on the EMI noise of the hybrid parallel integrated power supply; Step S6: studying the influence of different current ratios on device cost and junction temperature as well as efficiency and EMI noise of hybrid parallel integrated power supply; Step S7: Selecting the optimal current ratio of the hybrid parallel integrated power supply.

2. The method for selecting the optimal current of a hybrid parallel integrated power supply according to claim 1, characterized in that: The current matching ratio in step S1 is defined as γ, where γ is the ratio of the rated current level of the Si IGBT to the rated current level of the SiC MOSFET under the working condition of 100° C.:

3. The method for selecting optimal current of a hybrid parallel integrated power supply according to claim 1, characterized in that: The cost analysis method in step 2 is: summarizing the current levels and device costs of Si IGBT and SiC MOSFET device combinations, and fitting the data into a curve to derive market rules and conduct comparative analysis.

4. The method for selecting optimal current of a hybrid parallel integrated power supply according to claim 1, characterized in that: The specific method in step S4 is: under a certain SiC MOSFET switching frequency, the hybrid parallel integrated power supply operates at different power levels, the influence of different current ratios on the efficiency of the hybrid parallel integrated power supply is analyzed, and the total device loss is recorded; under certain conditions of the power level of the hybrid parallel integrated power supply, the operating frequency of the SIC MOSFET under different current ratios is increased, and the influence of the SIC MOSFET operating frequency on the power supply efficiency is analyzed.

5. The method for selecting optimal current of a hybrid parallel integrated power supply according to claim 1, characterized in that: In the step S5, the power devices used by the Si IGBT inverter and the SiC MOSFET inverter have the same rated current, and the current ratio of the hybrid parallel integrated power supply is 1:1, and the EMI noise spectrum amplitudes of the SiC MOSFET parallel inverter and the Si IGBT parallel inverter are compared within a certain resonant frequency range.

6. The method for selecting optimal current of a hybrid parallel integrated power supply according to claim 1, characterized in that: The method for studying the influence of different current ratios on the EMI noise of the hybrid parallel integrated power supply in step S5 is: increasing the current ratio from 1:1 to 4:1, comparing and analyzing the noise voltage waveform and spectrum envelope of the hybrid parallel integrated power supply, observing the changes in turn-on ringing and turn-off ringing, and observing and comparing the EMI noise spectrum amplitude within a certain frequency range.

7. The method for selecting optimal current of a hybrid parallel integrated power supply according to claim 1, characterized in that: Solve the formula: M=TPtyΔη-Δcost (1-2) The differential investment recovery period Y (years) of the hybrid parallel integrated power supply under different current ratios can be calculated by formula (1-1), that is, the additional device cost can be recovered within Y years, and the additional income M (￥) increased within the working life of the hybrid parallel integrated power supply can be calculated by formula (1-2), where P (kW) is the power level of the hybrid parallel integrated power supply, t (h) is the annual average working time of the hybrid parallel integrated power supply, y (￥ / W) is the device loss cost saved as the current ratio decreases, Δcost (￥) is the total device cost of the hybrid parallel integrated power supply that increases as the current ratio decreases, T is the working life of the hybrid parallel integrated power supply, and Δη is the change in the efficiency of the hybrid parallel integrated power supply as the current ratio decreases.

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