Semiconductor structure and preparation method therefor, and functional chip and electronic device

Abstract

The embodiments of the present application relate to the technical field of semiconductor structures. Provided are a semiconductor structure and a preparation method therefor, and a functional chip and an electronic device. The preparation method for a semiconductor structure comprises: providing a semiconductor layer group, wherein the semiconductor layer group comprises a first dielectric layer, a semiconductor layer, a conductive structure and an electronic element; in a first direction, removing part of the semiconductor layer from one side of a second surface of the semiconductor layer to expose an end face of the side of the conductive structure away from the electronic element; forming a protection structure on the side of the conductive structure away from the first dielectric layer, wherein the orthographic projection of the protection structure on the semiconductor layer covers the orthographic projection of the exposed end face of the conductive structure on the semiconductor layer; and using the protection structure as a mask to etch, in the first direction, part of the semiconductor layer from one side of the second surface of the semiconductor layer. In the embodiments of the present application, by providing a protection structure, conductive metal particle residues can be reduced, thereby improving the electrical reliability of a semiconductor layer.

Description

Semiconductor structure and preparation method thereof, functional chip and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on June 27, 2023, with application number 202310770844.3 and application name “Semiconductor structure and its preparation method, functional chip and electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] Embodiments of the present application relate to the technical field of semiconductor structures, and in particular, to a semiconductor structure and a method for preparing the same, a functional chip, and an electronic device. Background Art

[0003] Chips typically include semiconductor structures, which can include semiconductor layers and conductive structures made of metal. In related technologies, when preparing semiconductor structures, the conductive structures can easily cause metal contamination of the semiconductor layers, affecting the electrical reliability of the semiconductor structures.

[0004] Summary of the Invention

[0005] Embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, a functional chip, and an electronic device for improving the electrical performance of the semiconductor structure.

[0006] In order to achieve the above objectives, the following technical solutions are provided:

[0007] In one aspect, embodiments of the present application provide a method for fabricating a semiconductor structure. The method includes providing a semiconductor layer assembly, the semiconductor layer assembly including a first dielectric layer, a semiconductor layer, a conductive structure, and an electronic component. The semiconductor layer includes a first surface and a second surface disposed opposite each other, the first dielectric layer being disposed adjacent to the first surface of the semiconductor layer, and the electronic component being disposed within the first dielectric layer. One end of the conductive structure is disposed within the first dielectric layer and electrically connected to the electronic component, while the other end of the conductive structure passes through the first surface of the semiconductor layer and extends into the semiconductor layer. A portion of the semiconductor layer is removed from one side of the second surface of the semiconductor layer along a first direction, exposing an end face of the conductive structure facing away from the electronic component. The first direction intersects the surface of the semiconductor layer. A protective structure is formed on the side of the conductive structure facing away from the first dielectric layer, the orthographic projection of the protective structure on the semiconductor layer covering the orthographic projection of the exposed end face of the conductive structure on the semiconductor layer. Using the protective structure as a mask, a portion of the semiconductor layer is etched from one side of the second surface of the semiconductor layer along the first direction. The protective structure is removed.

[0008] In an embodiment of the present application, a protective structure is formed on a side of the conductive structure away from the first dielectric layer. The orthographic projection of the protective structure on the semiconductor layer covers the orthographic projection of the exposed end face of the conductive structure (that is, the end face of the conductive structure away from the electronic component) on the semiconductor layer, so that the protective structure can shield and cover the end face of the conductive structure away from the electronic component.

[0009] In this way, the protective structure can be used as a mask. When etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction, the etching ion beam will not bombard the end face of the conductive structure away from the electronic component, thereby reducing the risk of the conductive structure splashing under the action of the etching ion beam when etching a portion of the semiconductor layer, causing metal particles to fall on the second surface of the semiconductor layer. This can reduce the residual conductive metal particles, reduce the metal contamination of the semiconductor layer caused by the conductive structure, and improve the electrical reliability of the semiconductor structure.

[0010] Furthermore, after etching a portion of the semiconductor layer, the protective structure is removed to prevent the protective structure from affecting subsequent processing techniques.

[0011] In some possible implementations, the semiconductor layer group further includes a second dielectric layer, which covers the conductive structure. Using the protective structure as a mask, etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction also includes: etching the first portion of the second dielectric layer. The first portion of the second dielectric layer covers the outer peripheral side of the conductive structure away from the end of one side of the electronic component, and is away from the conductive structure along the second direction. The second direction is parallel to the surface of the semiconductor layer. Such an arrangement can reduce the risk of adhesion between the semiconductor layer and the second dielectric layer, resulting in the semiconductor layer remaining on the surface of the second dielectric layer away from the conductive structure, thereby improving the reliability of the method for preparing the semiconductor structure. In addition, the remaining portion of the second dielectric layer (the second portion of the second dielectric layer) can protect the outer peripheral side of the conductive structure away from the end of one side of the electronic component. That is, the protective structure can protect the end face of the conductive structure away from the electronic component, and the remaining part of the second dielectric layer can protect the peripheral side of the end of the conductive structure away from the electronic component, thereby preventing the etching ion beam from bombarding the end of the conductive structure away from the electronic component (including the end face and the peripheral side) when etching the semiconductor layer, reducing the metal contamination of the semiconductor layer caused by the conductive structure, and improving the electrical reliability of the semiconductor structure.

[0012] In some possible implementations, the edge of the orthographic projection of the protective structure on the semiconductor layer is located between the orthographic projection of the surface of the second dielectric layer on the side away from the conductive structure and the orthographic projection of the surface of the second dielectric layer on the side closer to the conductive structure. This configuration allows the protective structure to protect the end surface of the conductive structure away from the electronic component and the second portion of the second dielectric layer. Furthermore, it allows the first portion of the second dielectric layer to be etched away, reducing the risk of adhesion between the semiconductor layer and the second dielectric layer, resulting in the semiconductor layer remaining on the surface of the second dielectric layer away from the conductive structure, thereby improving the reliability of the semiconductor structure fabrication method.

[0013] In some possible implementations, forming a protective structure on a side of the conductive structure remote from the first dielectric layer includes forming a photoresist layer on a side of the semiconductor layer remote from the first dielectric layer. The photoresist layer is patterned through exposure and development to form the protective structure. This arrangement eliminates the need for complex fabrication methods, improves the electrical performance of the semiconductor structure, simplifies the fabrication process for the semiconductor structure, and reduces fabrication costs.

[0014] In some implementations, before forming a photoresist layer on the side of the semiconductor layer facing away from the first dielectric layer, the method further includes: forming an isolation layer on one side of the second surface of the semiconductor layer, the isolation layer covering the exposed end faces of the semiconductor layer and the conductive structure. Before etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along a first direction using a protective structure as a mask, the method further includes: etching the portion of the semiconductor layer covered by the isolation layer using the protective structure as a mask. This configuration allows the isolation layer to isolate the photoresist layer from the end face of the conductive structure facing away from the electronic component, thereby preventing the photoresist layer from contacting the end face of the conductive structure facing away from the electronic component, thereby preventing the photoresist layer from contaminating the end face of the conductive structure facing away from the electronic component, and improving the electrical reliability of the semiconductor structure. Furthermore, before etching a portion of the semiconductor layer, the portion of the isolation layer covering the semiconductor layer is etched so that the semiconductor layer can be exposed, thereby preventing the isolation layer from affecting subsequent processes.

[0015] In some possible implementations, after removing the protective structure, the method further includes forming a third dielectric layer, the third dielectric layer covering the second surface of the semiconductor layer and encapsulating the end of the conductive structure protruding from the semiconductor layer. A portion of the third dielectric layer and the isolation layer are removed along the first direction to expose the end face of the conductive structure facing away from the electronic component. This arrangement allows the end face of the conductive structure facing away from the electronic component to be exposed, thereby enabling other components (e.g., external components or other semiconductor structures) to be electrically connected to the semiconductor structure via the conductive structure. Furthermore, the third dielectric layer can provide electrical isolation, thereby improving the reliability of the semiconductor structure when electrically connected to other components.

[0016] In some possible implementations, there are multiple conductive structures, and the multiple conductive structures include a first conductive structure and a second conductive structure. Before a portion of the semiconductor layer is removed from one side of the second surface of the semiconductor layer along a first direction to expose an end face of the conductive structure facing away from the electronic component, the distance between the end face of the first conductive structure facing away from the electronic component and the second surface of the semiconductor layer is unequal to the distance between the end face of the second conductive structure facing away from the electronic component and the second surface of the semiconductor layer. Removing a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction to expose the end face of the conductive structure facing away from the electronic component includes: removing a portion of the semiconductor layer and a portion of the conductive structure from one side of the second surface of the semiconductor layer along the first direction to expose the end faces of the first and second conductive structures facing away from the electronic component. The exposed end face of the first conductive structure and the exposed end face of the second conductive structure are flush. This arrangement enables other external components to be electrically connected to the first and second conductive structures, and enables different semiconductor structures to be electrically connected via the first and second conductive structures, meeting different requirements. In addition, the exposed end surface of the first conductive structure is flush with the exposed end surface of the second conductive structure, which can improve the structural regularity of the semiconductor structure and improve the processing convenience of the semiconductor structure in subsequent processes.

[0017] On the other hand, embodiments of the present application provide a semiconductor structure. The semiconductor structure includes a semiconductor layer group and a third dielectric layer. The semiconductor layer group includes a first dielectric layer, a semiconductor layer, a second dielectric layer, a conductive structure, and an electronic component. The semiconductor layer includes a first surface and a second surface disposed opposite each other. The first dielectric layer is disposed adjacent to the first surface of the semiconductor layer, and the electronic component is disposed within the first dielectric layer. One end of the conductive structure is disposed within the first dielectric layer and is electrically connected to the electronic component. The second dielectric layer covers the conductive structure. The third dielectric layer is disposed adjacent to the second surface of the semiconductor layer. The end of the conductive structure facing away from the electronic component passes through the semiconductor layer and the third dielectric layer, and the end surface of the conductive structure facing away from the electronic component is exposed to the third dielectric layer. The second dielectric layer includes a first subsection and a second subsection. The first subsection is disposed between the third dielectric layer and the conductive structure, and the second subsection is disposed between the semiconductor layer and the conductive structure. The thickness of the first subsection is less than that of the second subsection. This arrangement reduces the risk of the semiconductor layer adhering to the surface of the first subsection facing away from the conductive structure, thereby improving the electrical reliability of the semiconductor structure.

[0018] In another aspect, an embodiment of the present application provides a functional chip, comprising at least one semiconductor structure. The semiconductor structure is the semiconductor structure described above; or the semiconductor structure is manufactured according to the method for manufacturing the semiconductor structure described above.

[0019] The functional chip provided in the embodiments of the present application includes the semiconductor structure as described above; or, the semiconductor structure in the functional chip provided in the embodiments of the present application is manufactured according to the preparation method of the semiconductor structure as described above; therefore, the functional chip provided in the embodiments of the present application has all the above-mentioned beneficial effects, which will not be repeated here.

[0020] In some possible implementations, when the functional chip includes at least two semiconductor structures, the at least two semiconductor structures include a first semiconductor structure and a second semiconductor structure. The exposed end surface of the conductive structure in the first semiconductor structure is bonded to the exposed end surface of the conductive structure in the second semiconductor structure. This arrangement enables, when the first and second semiconductor structures are stacked, the electronic components in the first semiconductor structure to be electrically connected to the electronic components in the second semiconductor structure, thereby achieving interlayer interconnection of the bonded wafers and enabling the functional chip to become a 3D IC.

[0021] In another aspect, an embodiment of the present application provides an electronic device, which includes a bus and the aforementioned function chip, wherein the function chip is electrically connected to the bus.

[0022] The electronic device provided in the embodiment of the present application includes the functional chip as described above, and therefore has all the beneficial effects described above, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic block diagram of the structure of an electronic device provided in some embodiments of the present application;

[0024] FIG2 is a flowchart of steps of a method for preparing a semiconductor structure according to some embodiments of the present application;

[0025] FIG3 is a schematic structural diagram of a semiconductor layer group provided in some embodiments of the present application;

[0026] FIG4 is a schematic structural diagram of a semiconductor layer group provided in some other embodiments of the present application;

[0027] FIG5 is an electron microscope image of a semiconductor structure provided by some embodiments of the present application;

[0028] FIG6 is a schematic structural diagram of a semiconductor layer group provided in some other embodiments of the present application;

[0029] FIG7 is a schematic structural diagram of a semiconductor layer group provided in some other embodiments of the present application;

[0030] FIG8 is a schematic structural diagram of a semiconductor layer group provided in some other embodiments of the present application;

[0031] FIG9 is an electron microscope image of a conductive structure provided by some embodiments of the present application;

[0032] FIG10 is a schematic structural diagram of a semiconductor layer group provided in some other embodiments of the present application;

[0033] FIG11 is a schematic structural diagram of a semiconductor layer group provided in some other embodiments of the present application;

[0034] FIG12 is a schematic diagram of the structure of a functional chip provided in some embodiments of the present application;

[0035] FIG13 is a partial enlarged view of the M1 region in FIG9 ;

[0036] FIG14 is a schematic diagram showing a curve of the effective diffusion coefficient of copper varying with temperature;

[0037] FIG15 is a schematic diagram of the diffusion depth curves of different metals in the same medium;

[0038] FIG16 is a flowchart of steps of a method for preparing a semiconductor structure according to other embodiments of the present application;

[0039] FIG17 is a schematic structural diagram of a semiconductor layer group according to some other embodiments of the present application;

[0040] FIG18 is a schematic structural diagram of a semiconductor layer group according to some other embodiments of the present application;

[0041] FIG19 is a schematic structural diagram of a semiconductor layer group according to some other embodiments of the present application;

[0042] FIG20 is a partial enlarged view of the M2 region in FIG19 ;

[0043] FIG21 is a diagram illustrating the positional relationship between the edge of the orthographic projection of the protection structure on the semiconductor layer and the orthographic projection of the second dielectric layer on the semiconductor layer, provided by some embodiments of the present application;

[0044] FIG22 is a flowchart of steps of a method for preparing a semiconductor structure according to yet other embodiments of the present application;

[0045] FIG23 is a schematic structural diagram of a semiconductor layer group provided in yet other embodiments of the present application;

[0046] FIG24 is a schematic structural diagram of a semiconductor layer group provided in yet other embodiments of the present application;

[0047] FIG25 is a schematic structural diagram of a semiconductor layer group provided in yet other embodiments of the present application;

[0048] FIG26 is a schematic structural diagram of a semiconductor structure provided in some embodiments of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0052] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0053] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0054] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0055] FIG1 is a schematic block diagram of the structure of an electronic device provided in some embodiments of the present application.

[0056] As shown in FIG1 , an embodiment of the present application provides an electronic device 300. For example, the electronic device 300 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, etc.; the electronic device 300 may also be a personal computer (PC), a server, a workstation, etc.

[0057] In some examples, as shown in FIG. 1 , the electronic device 300 may include a bus 301 and a function chip 200 , and the function chip 200 may be electrically connected to the bus 301 .

[0058] It will be understood that bus 301 is a common communication trunk for transmitting information between different functional components of electronic device 300. Functional chip 200 is electrically connected to bus 301, enabling signals to be transmitted between the functional chip 200 and bus 301. In some examples, as shown in FIG1 , electronic device 300 may further include other functional components 302, which are electrically connected to bus 301. In this way, signals can be transmitted between functional chip 200 and other functional components 302 via bus 301, enabling electronic device 300 to implement different functions.

[0059] In some examples, the function chip 200 can implement at least one of a storage function and a computing function. In other examples, the function chip 200 can also implement functions other than storage and computing functions. It is understood that the embodiments of the present application do not further limit the functions that the function chip 200 can implement.

[0060] In some examples, the function chip 200 may be a 3D IC (Three-Dimensional Integrated Circuit). For example, the function chip 200 may be at least one of an application processor (AP), a graphics processing unit (GPU), a central processing unit (CPU), a random access memory (RAM), a read-only memory (ROM), a communication chip, and a power management chip. The electronic device 300 may include one function chip 200 or multiple function chips 200.

[0061] In some examples, the function chip 200 may include at least one semiconductor structure 100 . For example, the function chip 200 may include only one semiconductor structure 100 ; the function chip 200 may also include two, three, four, or more semiconductor structures 100 .

[0062] When the functional chip 200 includes multiple semiconductor structures 100, at least two of the multiple semiconductor structures 100 can be electrically connected. For example, the at least two semiconductor structures 100 can be electrically connected by bonding. Compared to electrically connecting the at least two semiconductor structures 100 via wires, electrically connecting the at least two semiconductor structures 100 via bonding reduces the wiring complexity of the functional chip 200 and can shorten the distance between the at least two electrically connected semiconductor structures 100.

[0063] Figure 2 is a flow chart of the steps of a method for preparing a semiconductor structure according to some embodiments of the present application. Figure 3 is a schematic diagram of the structure of a semiconductor layer assembly according to some embodiments of the present application. Figure 4 is a schematic diagram of the structure of a semiconductor layer assembly according to other embodiments of the present application. Figure 5 is an electron microscope image of a semiconductor structure according to some embodiments of the present application.

[0064] The following is an example of a method for preparing the semiconductor structure 100. In some examples, as shown in FIG2 , the method for preparing the semiconductor structure 100 includes:

[0065] Step S101 provides a semiconductor layer assembly, comprising a first dielectric layer, a semiconductor layer, a conductive structure, and an electronic component. The semiconductor layer comprises a first surface and a second surface disposed opposite each other, the first dielectric layer being disposed adjacent to the first surface of the semiconductor layer, and the electronic component being disposed within the first dielectric layer. One end of the conductive structure is disposed within the first dielectric layer and electrically connected to the electronic component, while the other end of the conductive structure passes through the first surface of the semiconductor layer and extends into the semiconductor layer.

[0066] For example, as shown in FIG3 , semiconductor layer assembly 110 may include a first dielectric layer 111, a semiconductor layer 112, a conductive structure 113, and an electronic component 114. The material of first dielectric layer 111 may be an oxide, such as silicon dioxide (chemical formula: SiO 2 ); alternatively, the material of first dielectric layer 111 may be a nitride, such as silicon nitride (chemical formula: SiN); alternatively, the material of first dielectric layer 111 may be one or more combinations of other high-k insulating materials.

[0067] For example, the first dielectric layer 111 may include multiple stacked sub-layers (see FIG3 ), and the electronic components 114 may be located in the multiple stacked sub-layers. The materials of different sub-layers may be the same or different.

[0068] In some examples, the material of the semiconductor layer 112 may include silicon (chemical formula: Si). For example, the semiconductor layer 112 may be pure silicon or doped silicon.

[0069] As shown in Figures 3 and 4, the semiconductor layer 112 may include a first surface P1 and a second surface P2 disposed opposite each other. The first surface P1 and the second surface P2 may be smooth planes. The first dielectric layer 111 is located on one side of the semiconductor layer 112 where the first surface P1 is located, and is disposed adjacent to the first surface P1. For example, the first dielectric layer 111 may be in contact with the first surface P1 of the semiconductor layer 112.

[0070] It is understandable that the electronic component 114 may be a component having functions such as storage, calculation, switching, digital-to-analog conversion, analog-to-digital conversion, etc. There may be multiple electronic components 114, and the functions of the multiple electronic components 114 may be the same or different.

[0071] As shown in Figures 3 and 4 , one end of the conductive structure 113 is located within the first dielectric layer 111 and is electrically connected to the electronic component 114, allowing signals to be transmitted between the electronic component 114 and the conductive structure 113. It is understood that the conductive structure 113 and the electronic component 114 can be directly electrically connected, or the conductive structure 113 and the electronic component 114 can be electrically connected via other conductive traces (e.g., conductive traces and metal interconnect structures, not shown in Figures 3 and 4 ).

[0072] In some examples, the conductive structures 113 and the electronic components 114 may be electrically connected in a one-to-one correspondence; in other examples, one conductive structure 113 may be electrically connected to multiple electronic components 114; or, multiple conductive structures 113 may be electrically connected to one electronic component 114.

[0073] As shown in Figures 3 and 4, the extension direction of the conductive structure 113 can intersect the surface of the semiconductor layer 112 (including the first surface P1 and the second surface P2), so that the other end of the conductive structure 113 can pass through the first surface P1 of the semiconductor layer 112 and extend into the semiconductor layer 112. For example, the extension direction of the conductive structure 113 can be perpendicular to the surface of the semiconductor layer 112.

[0074] In some examples, the conductive structure 113 can be formed using TSV (Through Silicon Via) technology. For example, a conductive via can be formed in the semiconductor layer 112 through the first surface P1 of the semiconductor layer 112, and the conductive structure 113 can be formed within the conductive via. The conductive structure 113 can be made of a metal material such as copper, aluminum, iron, or silver to improve the conductive performance of the conductive structure 113. It is understood that the embodiments of the present application do not further limit the material of the conductive structure 113.

[0075] 5 is a schematic cross-sectional view of the conductive structure 113 taken along a direction perpendicular to a surface (eg, first surface P1 or second surface P2) of the semiconductor layer 112. It is understood that in order to clearly illustrate the conductive structure 113, other structures of the semiconductor layer assembly 110 are not shown in FIG5 .

[0076] In some examples, the conductive structure 113 may be shaped like a cylinder, a cuboid, or a prism, so that the cross-section of the conductive structure 113 along a direction perpendicular to the surface of the semiconductor layer 112 may be rectangular. In other examples, the conductive structure 113 may also be other irregular shapes.

[0077] Taking the shape of the conductive structure 113 as a cylinder as an example, in some examples, the base diameter of the cylinder can be 5 μm (unit: micrometer) and the height of the cylinder can be 50 μm. In other examples, the conductive structure 113 can also have other sizes. It is understood that the embodiments of the present application do not further limit the shape and size of the conductive structure 113.

[0078] In some examples, as shown in FIG. 3 and FIG. 4 , the semiconductor layer group 110 may further include a second dielectric layer 115 , where the second dielectric layer 115 covers the conductive structure 113 .

[0079] For example, the second dielectric layer 115 can be located within the semiconductor layer 112 and cover the conductive structure 113. It is understood that the second dielectric layer 115 can serve as an electrical isolation layer. For example, the material of the second dielectric layer 115 can be an oxide (English name: oxide), such as silicon dioxide (chemical formula: SiO2); or, the material of the second dielectric layer 115 can be a nitride (English name: nitrides), such as silicon nitride (chemical formula: SiN); or, the material of the second dielectric layer 115 can be a combination of one or more other high dielectric constant insulating materials. The material of the second dielectric layer 115 can be the same as or different from the material of the first dielectric layer 111.

[0080] For example, after forming a conductive through hole on the semiconductor layer 112 , a second dielectric layer 115 can be formed on the inner wall of the conductive through hole, and then a conductive structure 113 can be formed on a side of the second dielectric layer 115 away from the semiconductor layer 112 , so that the second dielectric layer 115 can cover the conductive structure 113 .

[0081] Figure 6 is a schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application. Figure 7 is a schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application.

[0082] Referring again to FIG. 2 , after providing the semiconductor layer group 110 (ie, after step S101 ), the method for preparing the semiconductor structure 100 further includes:

[0083] Step S102 : removing a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along a first direction, exposing an end face of the conductive structure away from the electronic component. The first direction intersects the surface of the semiconductor layer.

[0084] In some examples, the first direction X may be perpendicular to the surface of the semiconductor layer 112 (including the first surface P1 and the second surface P2 ).

[0085] It can be understood that because the end of the conductive structure 113 away from the electronic component 114 passes through the first surface P1 of the semiconductor layer 112 and extends into the semiconductor layer 112, a portion of the semiconductor layer 112 is removed from the side of the second surface P2 of the semiconductor layer 112 along the first direction X, as shown in Figures 6 and 7, the end surface of the conductive structure 113 away from the electronic component 114 can be exposed. For example, the exposed end surface of the conductive structure 113 is flush with the second surface P2 of the semiconductor layer 112.

[0086] For example, the process of removing a portion of the semiconductor layer 112 from one side of the second surface P2 of the semiconductor layer 112 along the first direction X to expose the end face of the conductive structure 113 away from the electronic component 114 is called a back side via revealing process (full name: Backside Via Reveal, abbreviated in English: BVR).

[0087] It can be understood that the BVR process is used to expose the end face of the conductive structure 113 away from the electronic component 114, so that other external components can be electrically connected to the electronic component 114 through the conductive structure 113, or so that two different semiconductor structures 100 can be electrically connected through the conductive structure 113, thereby improving the electrical reliability of the semiconductor structure 100 in subsequent processing technology.

[0088] In some examples, a CMP (Chemical Mechanical Polishing) process can be used to thin the semiconductor layer 112 from an initial thickness (e.g., 75 μm) to a predetermined thickness to expose the end surface of the conductive structure 113 facing away from the electronic component 114. It is understood that using the CMP process to remove a portion of the semiconductor layer 112 not only exposes the end surface of the conductive structure 113 facing away from the electronic component 114, but also polishes and planarizes the second surface P2 of the semiconductor layer 112 and the end surface of the conductive structure 113 facing away from the electronic component 114, thereby improving the structural regularity of the semiconductor structure 100.

[0089] It is understood that when a portion of the semiconductor layer 112 is not removed, the second surface P2 is a surface opposite to the first surface P1. After a portion of the semiconductor layer 112 is removed from one side of the second surface P2 of the semiconductor layer 112 along the first direction X, the second surface P2 is a surface of the remaining semiconductor layer 112 opposite to the first surface P1.

[0090] For example, while removing a portion of the semiconductor layer 112 from one side of the second surface P2 of the semiconductor layer 112, the second dielectric layer 115 covering the end surface of the conductive structure 113 away from the electronic component 114 can be removed, as shown in Figures 6 and 7, so that the end surface of the conductive structure 113 away from the electronic component 114 can be exposed. It will be understood that in the embodiments of the present application, "simultaneously" refers to the same step or the same process, and is not limited to the same time.

[0091] In some examples, as shown in Figures 3 and 4 , before removing a portion of the semiconductor layer 112, a carrier wafer 118 may be provided. Carrier wafer 118 is located on a side of the first dielectric layer 111 away from the semiconductor layer 112. Carrier wafer 118 may be bonded to the first dielectric layer 111 using a material such as a bonding adhesive. It is understood that carrier wafer 118 can serve as a support, reducing the risk of semiconductor layer assembly 110 breaking when removing a portion of the semiconductor layer 112.

[0092] In other examples, the semiconductor layer assembly 110 may further include a functional film layer (not shown in the figures), which may be located on a side of the first dielectric layer 111 away from the semiconductor layer 112. It is understood that the functional film layer can provide support for the first dielectric layer 111 and the semiconductor layer 112. In this case, the carrier 118 may not be required, thereby simplifying the fabrication process of the semiconductor structure 100.

[0093] In some examples, after providing the semiconductor layer group 110, the semiconductor layer group 110 can be flipped so that the second surface P2 of the semiconductor layer 112 faces upward (toward the sky, see Figure 4), thereby improving the convenience of removing part of the semiconductor layer 112 from one side of the second surface P2 of the semiconductor layer 112.

[0094] In some examples, as shown in Figures 6 and 7, there may be multiple conductive structures 113. The number of conductive structures 113 may be the same as or different from the number of electronic components 114. The multiple conductive structures 113 may be arranged in an array.

[0095] In some examples, as shown in FIG4 , the plurality of conductive structures 113 may include a first conductive structure 113 a and a second conductive structure 113 b. Before a portion of the semiconductor layer 112 is removed from one side of the second surface P2 of the semiconductor layer 112 along the first direction X to expose the end surface of the conductive structure 113 facing away from the electronic component 114, a distance L1 between the end surface of the first conductive structure 113 a facing away from the electronic component 114 and the second surface P2 of the semiconductor layer 112 is not equal to a distance L2 between the end surface of the second conductive structure 113 b facing away from the electronic component 114 and the second surface P2 of the semiconductor layer 112.

[0096] It is understandable that there may be multiple first conductive structures 113a, multiple second conductive structures 113b, and the number of first conductive structures 113a and the number of second conductive structures 113b may be equal or unequal.

[0097] As shown in Figure 4, before a portion of the semiconductor layer 112 is removed to expose the end surface of the conductive structure 113 on the side away from the electronic component 114, the distance L1 between the end surface of the first conductive structure 113a on the side away from the electronic component 114 and the second surface P2 of the semiconductor layer 112 is not equal to the distance L2 between the end surface of the second conductive structure 113b on the side away from the electronic component 114 and the second surface P2 of the semiconductor layer 112. That is, the length of the portion of the first conductive structure 113a located in the semiconductor layer 112 along the first direction X is not equal to the length of the portion of the second conductive structure 113b located in the semiconductor layer 112 along the first direction X.

[0098] In some examples, as shown in Figure 4, the distance L1 between the end surface of the first conductive structure 113a away from the electronic component 114 and the second surface P2 of the semiconductor layer 112 may be greater than the distance L2 between the end surface of the second conductive structure 113b away from the electronic component 114 and the second surface P2 of the semiconductor layer 112; in other examples, the distance L1 between the end surface of the first conductive structure 113a away from the electronic component 114 and the second surface P2 of the semiconductor layer 112 may also be less than the distance L2 between the end surface of the second conductive structure 113b away from the electronic component 114 and the second surface P2 of the semiconductor layer 112.

[0099] It can be understood that by removing part of the semiconductor layer 112 from one side of the second surface P2 of the semiconductor layer 112 along the first direction X, the end surface of a conductive structure 113 (for example, the second conductive structure 113b) away from the electronic component 114 can be exposed, and the end surfaces of multiple conductive structures 113 (for example, the first conductive structure 113a and the second conductive structure 113b) away from the electronic component 114 can also be exposed.

[0100] For example, in step S102, a portion of the semiconductor layer is removed from one side of the second surface of the semiconductor layer along the first direction to expose an end surface of the conductive structure away from the electronic component, including:

[0101] Along the first direction, part of the semiconductor layer and part of the conductive structure are removed from one side of the second surface of the semiconductor layer to expose the end faces of the first conductive structure and the second conductive structure away from the electronic component; wherein the exposed end face of the first conductive structure is flush with the exposed end face of the second conductive structure.

[0102] It can be understood that since the distance L1 between the end surface of the first conductive structure 113a away from the electronic component 114 and the second surface P2 of the semiconductor layer 112 is not equal to the distance L2 between the end surface of the second conductive structure 113b away from the electronic component 114 and the second surface P2 of the semiconductor layer 112, a portion of the semiconductor layer 112 and a portion of the conductive structure 113 (for example, the second conductive structure 113b) along the first direction X can be removed from the side of the second surface P2 of the semiconductor layer 112, as shown in Figure 7, so that the end surface of the first conductive structure 113a away from the electronic component 114 and the end surface of the second conductive structure 113b away from the electronic component 114 can be exposed.

[0103] It can be understood that the end face of the first conductive structure 113a away from the electronic component 114 and the end face of the second conductive structure 113b away from the electronic component 114 can be exposed, so that other external components can be electrically connected to the first conductive structure 113a and the second conductive structure 113b, and different semiconductor structures 100 can be electrically connected through the first conductive structure 113a and the second conductive structure 113b to meet different needs.

[0104] In addition, the exposed end surface of the first conductive structure 113 a is flush with the exposed end surface of the second conductive structure 113 b , which can improve the structural regularity of the semiconductor structure 100 and enhance the processing convenience of the semiconductor structure 100 in subsequent processes.

[0105] In some examples, as shown in FIG6 and FIG7 , the end surfaces of the plurality of conductive structures 113 away from the electronic component 114 are flush, and the end surfaces of the plurality of conductive structures 113 away from the electronic component 114 are all flush with the second surface P2 of the semiconductor layer 112 .

[0106] Figure 8 is a schematic diagram of the structure of a semiconductor layer assembly provided in further embodiments of the present application. Figure 9 is an electron microscope image of a conductive structure provided in further embodiments of the present application. Figure 10 is a schematic diagram of the structure of a semiconductor layer assembly provided in further embodiments of the present application. Figure 11 is a schematic diagram of the structure of a semiconductor layer assembly provided in further embodiments of the present application. It will be understood that Figure 9 is an electron microscope image of the semiconductor layer 112 as viewed from the side of the second surface P2 of the semiconductor layer 112.

[0107] Referring again to FIG. 2 , after the end surface of the conductive structure 113 is exposed (ie, after step S102 ), the method for preparing the semiconductor structure 100 further includes:

[0108] Step S103 , etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction.

[0109] As shown in Figure 8, after the end face of the conductive structure 113 is exposed, a portion of the semiconductor layer 112 can be etched from the side of the second surface P2 of the semiconductor layer 112 along the first direction X, as shown in Figures 8 and 9, so that the end of the conductive structure 113 away from the electronic component 114 can protrude from the semiconductor layer 112.

[0110] For example, a dry etching process can be used to etch a portion of the semiconductor layer 112 along the first direction X from one side of the second surface P2 of the semiconductor layer 112; or a wet etching process can be used to etch a portion of the semiconductor layer 112 along the first direction X from one side of the second surface P2 of the semiconductor layer 112.

[0111] It can be understood that, as shown in Figure 8, since the second dielectric layer 115 covers the conductive structure 113, when the semiconductor layer 112 is etched so that the end of the conductive structure 113 away from the electronic component 114 protrudes from the semiconductor layer 112, the portion of the second dielectric layer 115 away from the electronic component 114 can also protrude from the semiconductor layer 112.

[0112] Step S104 : forming a third dielectric layer, wherein the third dielectric layer covers the second surface of the semiconductor layer and encapsulates the end of the conductive structure protruding from the semiconductor layer.

[0113] As shown in FIG. 10 , after the end of the conductive structure 113 protrudes from the semiconductor layer 112 , a third dielectric layer 116 may be formed. The third dielectric layer 116 covers the second surface P2 of the semiconductor layer 112 and encapsulates the end of the conductive structure 113 protruding from the semiconductor layer 112 .

[0114] It is understood that the third dielectric layer 116 can provide electrical isolation. For example, the material of the third dielectric layer 116 can be an oxide, such as silicon dioxide (chemical formula: SiO2); or, the material of the third dielectric layer 116 can be a nitride, such as silicon nitride (chemical formula: SiN); or, the material of the third dielectric layer 116 can be a combination of one or more other high-k insulating materials. The materials of the first dielectric layer 111, the second dielectric layer 115, and the third dielectric layer 116 can be the same or different.

[0115] Step S105 : removing a portion of the third dielectric layer along the first direction to expose the end surface of the conductive structure away from the electronic component.

[0116] As shown in FIG. 11 , after the third dielectric layer 116 is formed, a portion of the third dielectric layer 116 may be removed along the first direction X so that the end surface of the conductive structure 113 away from the electronic component 114 is exposed.

[0117] In some examples, a CMP process may be used to remove a portion of the third dielectric layer 116, thereby exposing the end surface of the conductive structure 113 away from the electronic component 114. For example, when removing a portion of the third dielectric layer 116, a portion of the conductive structure 113 along the first direction X may be removed to polish and planarize the surface of the third dielectric layer 116 away from the semiconductor layer 112 and the end surface of the conductive structure 113 away from the electronic component 114, thereby improving the structural regularity of the semiconductor structure 100.

[0118] It can be understood that the third dielectric layer 116 can play a role of electrical isolation, thereby improving the reliability of the semiconductor structure 100 when electrically connected to other components (such as external devices or other semiconductor structures 100).

[0119] FIG12 is a schematic diagram of the structure of a functional chip provided in some embodiments of the present application.

[0120] In other examples, as shown in FIG12 , when the functional chip 200 includes at least two semiconductor structures 100, the at least two semiconductor structures 100 may include a first semiconductor structure 100a and a second semiconductor structure 100b. The exposed end surface of the conductive structure 113 in the first semiconductor structure 100a may be bonded to the exposed end surface of the conductive structure 113 in the second semiconductor structure 100b.

[0121] It is understandable that the first semiconductor structure 100a and the second semiconductor structure 100b may be the same or different. The functions that the first semiconductor structure 100a can achieve may be the same or different from the functions that the second semiconductor structure 100b can achieve.

[0122] In some examples, as shown in FIG12 , electronic components 114 in semiconductor structure 100 (e.g., first semiconductor structure 100a or second semiconductor structure 100b) can be electrically connected to conductive structure 113 via conductive traces 141 and metal interconnect structures 142. For example, conductive traces 141, metal interconnect structures 142, and conductive structure 113 are made of the same material; in other examples, conductive traces 141, metal interconnect structures 142, and conductive structure 113 can be made of different materials.

[0123] In some examples, the semiconductor structure 100 (e.g., the second semiconductor structure 100b) may further include a buried oxide layer (BOX) 117. The buried oxide layer 117 may be located between the first dielectric layer 111 and the semiconductor layer 112 to provide electrical isolation. For example, the material of the buried oxide layer 117 may include silicon dioxide.

[0124] It can be understood that the exposed end face of the conductive structure 113 in the first semiconductor structure 100a (that is, the end face of the conductive structure 113 in the first semiconductor structure 100a away from the electronic component 114) is bonded to the exposed end face of the conductive structure 113 in the second semiconductor structure 100b (that is, the end face of the conductive structure 113 in the second semiconductor structure 100b away from the electronic component 114), so that when the first semiconductor structure 100a and the second semiconductor structure 100b are stacked, the electronic component 114 in the first semiconductor structure 100a can be electrically connected to the electronic component 114 in the second semiconductor structure 100b, thereby realizing interlayer interconnection of the bonded wafers and enabling the functional chip 200 to become a 3DIC.

[0125] FIG13 is a partial enlarged view of the M1 region in FIG9 .

[0126] The inventors of this application have discovered that the above implementation method has at least the following technical problems:

[0127] In related art, when the conductive structure 113 is formed using the TSV process, it can be divided into Via-First (Chinese name: first through hole), Via-Middle (Chinese name: middle through hole) and Via-Last (last through hole) according to different process sequences.

[0128] Via-First refers to the formation of the conductive structure 113 before the front-end process (full name in English: Front End Of The Line, English abbreviation: FEOL); Via-Middle refers to the formation of the conductive structure 113 after the front-end process and before the back-end process (full name in English: Back End Of The Line, English abbreviation: BEOL); Via-Last refers to the formation of the conductive structure 113 after the back-end process.

[0129] Of the three aforementioned methods, Via-First and Via-Middle are more common. Regardless of whether the Via-First or Via-Middle process is employed, a portion of the semiconductor layer 112 is removed from one side of the second surface P2 of the semiconductor layer 112 along the first direction X, exposing the end surface of the conductive structure 113 away from the electronic component 114, and then a portion of the semiconductor layer 112 is etched (see steps S102 and S103 in FIG. 2 ).

[0130] In this way, when etching a portion of the semiconductor layer 112, the end surface of the conductive structure 113 away from the electronic component 114 is exposed, allowing the etching ion beam to directly bombard the exposed end surface of the conductive structure 113. Under the bombardment of the ion beam, the conductive structure 113 will splash metal particles, which fall onto the second surface P2 of the semiconductor layer 112.

[0131] Taking the case where the conductive structure 113 is made of copper and the semiconductor layer 112 is made of silicon as an example, the etching ion beam will directly bombard the copper surface. Under the bombardment of the ion beam, copper particles 113c will splash out of the conductive structure 113. As shown in Figure 13, the copper particles 113c fall onto the second surface P2 of the semiconductor layer 112, causing a serious copper contamination problem (full name: Cu Contamination Issue) to the semiconductor layer 112. Subsequent cleaning processes are difficult to remove the copper contamination of the semiconductor layer 112. The copper particles 113c easily diffuse within the semiconductor layer 112, affecting the electrical reliability of the semiconductor structure 100.

[0132] Figure 14 is a schematic diagram of the effective diffusion coefficient of copper versus temperature. Figure 15 is a schematic diagram of the diffusion depth curves of different metals in the same medium.

[0133] In FIG14 , the vertical axis is the effective diffusion coefficient of copper (full name: Effective Copper Diffusion Coefficient), which can be the effective diffusion coefficient of copper in silicon, and the unit is square meters per second (cm 2 / s); the horizontal axis is temperature, the unit is 1000 / T(K -1 ); Different curves represent different experimental data.

[0134] As can be seen from Figure 14, the effective diffusion coefficient of copper atoms in silicon varies at different temperatures. However, the migration coefficient (effective diffusion coefficient) of copper atoms in silicon is high at all temperatures.

[0135] Table 1

[0136] Table 1 shows the self-diffusion coefficient D, frequency factor D0 and activation energy Q of different metals in silicon at the same temperature (300K, unit: Kelvin).

[0137] As can be seen from Table 1, compared with other metal elements, copper has a higher self-diffusion coefficient D in silicon. Taking the temperature condition of 300K as an example, the self-diffusion coefficient of copper in silicon is as high as 1.4x10 -41 cm 2 / s, which is more than ten orders of magnitude higher than other common metals such as Co, Ni, Pt, etc.

[0138] Figure 15 shows the depth profiles of Ru, Pb, and Cu in silicon after annealing at 400°C (degrees Celsius) for one hour in a nitrogen atmosphere. In Figure 15 , the y-axis represents metal concentration (atoma / cm3), and the abscissa represents depth (nm). Different curves represent different metals.

[0139] It can be seen from Figure 15 that under the same pollution concentration (metal concentration), the diffusion depth of copper is much higher than that of other metals (Ru and Pb).

[0140] It can be seen from the above data that after the copper particles fall onto the second surface P2 of the semiconductor layer 112 , they will quickly diffuse within the semiconductor layer 112 , affecting the electrical reliability of the semiconductor structure 100 .

[0141] Figure 16 is a flow chart of the steps of a method for fabricating a semiconductor structure according to other embodiments of the present application. Figure 17 is a schematic diagram of the structure of a semiconductor layer assembly according to still other embodiments of the present application. Figure 18 is a schematic diagram of the structure of a semiconductor layer assembly according to still other embodiments of the present application. Figure 19 is a schematic diagram of the structure of a semiconductor layer assembly according to still other embodiments of the present application. Figure 20 is a partial enlarged view of the M2 region in Figure 19.

[0142] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure.

[0143] As shown in FIG16 , the method for preparing a semiconductor structure includes:

[0144] Step S201 provides a semiconductor layer assembly, comprising a first dielectric layer, a semiconductor layer, a conductive structure, and an electronic component. The semiconductor layer comprises a first surface and a second surface disposed opposite each other, the first dielectric layer being disposed adjacent to the first surface of the semiconductor layer, and the electronic component being disposed within the first dielectric layer. One end of the conductive structure is disposed within the first dielectric layer and electrically connected to the electronic component, while the other end of the conductive structure passes through the first surface of the semiconductor layer and extends into the semiconductor layer.

[0145] Step S202 : removing a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along a first direction, exposing an end face of the conductive structure away from the electronic component. The first direction intersects the surface of the semiconductor layer.

[0146] It can be understood that step S201 is the same as step S101, and step S202 is the same as step S102. The above embodiments of the present application have already provided examples for step S101 and step S102, which will not be repeated here.

[0147] Step S203 , forming a protection structure on a side of the conductive structure away from the first dielectric layer, wherein the orthographic projection of the protection structure on the semiconductor layer covers the orthographic projection of the exposed end face of the conductive structure on the semiconductor layer.

[0148] It can be understood that the protective structure 121 is located on the side of the conductive structure 113 away from the first dielectric layer 111, and the orthographic projection of the protective structure 121 on the semiconductor layer 112 covers the orthographic projection of the exposed end face of the conductive structure 113 (that is, the end face of the conductive structure 113 away from the electronic component 114) on the semiconductor layer 112, so that the protective structure 121 can shield and cover the end face of the conductive structure 113 away from the electronic component 114.

[0149] In some examples, the orthographic projection of the protective structure 121 on the semiconductor layer 112 can completely cover the orthographic projection of the exposed end surface of the conductive structure 113 on the semiconductor layer 112; in other examples, the orthographic projection of the protective structure 121 on the semiconductor layer 112 can also partially cover the orthographic projection of the exposed end surface of the conductive structure 113 on the semiconductor layer 112.

[0150] In some examples, the orthographic projection of the protection structure 121 on the semiconductor layer 112 is aligned with the orthographic projection of the exposed end surface of the conductive structure 113 on the semiconductor layer 112 (overlay, OVL), and the distance between the center of the orthographic projection of the protection structure 121 on the semiconductor layer 112 and the center of the orthographic projection of the conductive structure 113 on the semiconductor layer 112 is less than 100 nm. This arrangement can reduce the deviation between the orthographic projection of the protection structure 121 on the semiconductor layer 112 and the orthographic projection of the exposed end surface of the conductive structure 113 on the semiconductor layer 112, thereby improving the reliability of the method for manufacturing the semiconductor structure 100.

[0151] For example, the shape of the protection structure 121 may be a cylinder, a frustum, a cone, a prism, a truncated pyramid, a cuboid, a cube, or other irregular shapes, etc. The embodiment of the present application does not further limit the shape of the protection structure 121 .

[0152] For example, when the protective structure 121 is shaped like a cylinder, the orthographic projection of the cylinder onto the semiconductor layer 112 is the orthographic projection of the cylinder's base onto the semiconductor layer 112. When the protective structure 121 is shaped like a truncated cone, the orthographic projection of the truncated cone onto the semiconductor layer 112 is the orthographic projection of the truncated cone's lower base onto the semiconductor layer 112. The upper base of the truncated cone is parallel to the lower base, and the area of ​​the upper base is smaller than the area of ​​the lower base. When the protective structure 121 is shaped like a cone, the orthographic projection of the cone onto the semiconductor layer 112 is the orthographic projection of the cone's base onto the semiconductor layer 112.

[0153] It is understood that the shape of the orthographic projection of the protection structure 121 on the semiconductor layer 112 may be the same as or different from the shape of the orthographic projection of the end surface of the conductive structure 113 on the side away from the electronic component 114 on the semiconductor layer 112. In some examples, the shape of the orthographic projection of the protection structure 121 on the semiconductor layer 112 and the shape of the orthographic projection of the end surface of the conductive structure 113 on the side away from the electronic component 114 on the semiconductor layer 112 are both circular.

[0154] In some examples, the number of protection structures 121 is the same as the number of conductive structures 113, and the orthographic projection of one protection structure 121 on the semiconductor layer 112 covers the orthographic projection of the exposed end surface of one conductive structure 113 on the semiconductor layer 112. In other examples, the number of protection structures 121 may be less than the number of conductive structures 113, and the orthographic projection of one protection structure 121 on the semiconductor layer 112 covers the orthographic projection of the exposed end surfaces of at least two conductive structures 113 on the semiconductor layer 112.

[0155] In some examples, as shown in FIG17 , other film layers (eg, an isolation layer 131 ) may be provided between the protective structure 121 and the exposed end surface of the conductive structure 113 ; in other examples, the protective structure 121 and the exposed end surface of the conductive structure 113 may also be provided adjacent to each other.

[0156] Referring again to FIG. 16 , after step S203 , the method for preparing the semiconductor structure further includes:

[0157] In step S204 , a portion of the semiconductor layer is etched from one side of the second surface of the semiconductor layer along the first direction using the protection structure as a mask.

[0158] It can be understood that due to the orthographic projection of the protective structure 121 on the semiconductor layer 112, the orthographic projection of the end face of the covering conductive structure 113 away from the electronic component 114 on the semiconductor layer 112, the protective structure 121 can protect the exposed end face of the conductive structure 113.

[0159] For example, a dry etching process may be used to etch a portion of the semiconductor layer 112 ; a wet etching process may also be used to etch a portion of the semiconductor layer 112 .

[0160] By using the protective structure 121 as a mask, when etching the semiconductor layer 112, the end face of the conductive structure 113 away from the electronic component 114 will not be exposed, thereby preventing the conductive structure 113 from being bombarded by the etching ion beam and causing metal particles to fall on the second surface P2 of the semiconductor layer 112, reducing the metal contamination of the semiconductor layer 112 caused by the conductive structure 113, and improving the electrical reliability of the semiconductor structure 100.

[0161] Step S205: removing the protective structure.

[0162] As shown in FIG18 , after a portion of the semiconductor layer 112 is etched from one side of the second surface P2 of the semiconductor layer 112 along the first direction X using the protective structure 121 as a mask, the end of the conductive structure 113 away from the electronic component 114 can protrude from the semiconductor layer 112. At this point, the protective structure 121 can be removed, as shown in FIG19 , to prevent the protective structure 121 from affecting subsequent processing.

[0163] For example, the protective structure 121 may be removed by cleaning.

[0164] In an embodiment of the present application, a protective structure 121 is formed on a side of the conductive structure 113 away from the first dielectric layer 111. The orthographic projection of the protective structure 121 on the semiconductor layer 112 covers the orthographic projection of the exposed end face of the conductive structure 113 (that is, the end face of the conductive structure 113 away from the electronic component 114) on the semiconductor layer 112, so that the protective structure 121 can shield and cover the end face of the conductive structure 113 away from the electronic component 114.

[0165] In this way, the protective structure 121 can be used as a mask. When etching a portion of the semiconductor layer 112 from the side of the second surface P2 of the semiconductor layer 112 along the first direction X, the etching ion beam will not bombard the end face of the conductive structure 113 away from the electronic component 114, thereby reducing the risk of the conductive structure 113 splashing under the action of the etching ion beam when etching a portion of the semiconductor layer 112, causing metal particles to fall on the second surface P2 of the semiconductor layer 112. This can reduce the residual conductive metal particles, reduce the metal contamination of the semiconductor layer 112 caused by the conductive structure 113, and improve the electrical reliability of the semiconductor structure 100.

[0166] Furthermore, after etching a portion of the semiconductor layer 112 , the protection structure 121 is removed, thereby preventing the protection structure 121 from affecting subsequent processing techniques.

[0167] In some examples, while etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction using the protection structure as a mask (i.e., simultaneously with step S204), the method further includes:

[0168] The first portion of the second dielectric layer is etched. The first portion of the second dielectric layer covers the outer periphery of the conductive structure away from the end of one side of the electronic component and is away from the conductive structure along a second direction. The second direction is parallel to the surface of the semiconductor layer.

[0169] It can be understood that the first direction X intersects the surface of the semiconductor layer 112 and the second direction Y is parallel to the surface of the semiconductor layer 112 , so that the first direction X intersects the second direction Y. In some examples, the first direction X is perpendicular to the second direction Y.

[0170] For example, as shown in Figures 19 and 20, while etching the semiconductor layer 112, the first portion of the second dielectric layer 115 can be etched, that is, the portion of the second dielectric layer 115 on the outer peripheral side of the end portion of the conductive structure 113 away from the electronic component 114, which is away from the conductive structure 113 along the second direction Y, is etched.

[0171] As can be understood, as shown in FIG20 , before etching the semiconductor layer 112, the second surface P2 of the semiconductor layer 112 is located at a first position a. After etching the semiconductor layer 112, the second surface P2 of the semiconductor layer 112 is located at a second position b. The distance between the first position a and the second position b is a third distance L3. That is, the semiconductor layer 112 is etched to a thickness of the third distance L3 along the first direction X. The length of the portion of the second dielectric layer 115 etched along the first direction X is a fourth distance L4. As shown in FIG20 , the third distance L3 is equal to the fourth distance L4.

[0172] Etching the first portion of the second dielectric layer 115 while etching the semiconductor layer 112 can reduce the risk of the semiconductor layer 112 adhering to the second dielectric layer 115 and causing the semiconductor layer 112 to remain on the surface of the second dielectric layer 115 away from the conductive structure 113, thereby improving the reliability of the semiconductor structure manufacturing method.

[0173] Furthermore, a portion of the second dielectric layer 115 covering the outer periphery of the end portion of the conductive structure 113 away from the electronic component 114 and close to the conductive structure 113 along the second direction Y is not etched away. For example, this portion of the second dielectric layer 115 can be referred to as the second portion of the second dielectric layer 115 .

[0174] The second portion of the second dielectric layer 115 can protect the outer periphery of the end portion of the conductive structure 113 away from the electronic component 114. In other words, the protective structure 121 can protect the end face of the conductive structure 113 away from the electronic component 114. The second portion of the second dielectric layer 115 can protect the outer periphery of the end portion of the conductive structure 113 away from the electronic component 114, thereby preventing the etching ion beam from bombarding the end portion (including the end face and the outer periphery) of the conductive structure 113 away from the electronic component 114 when etching the semiconductor layer 112. This reduces metal contamination of the semiconductor layer 112 by the conductive structure 113, thereby improving the electrical reliability of the semiconductor structure 100.

[0175] In some examples, as shown in FIG20 , the thickness D of the second portion of the second dielectric layer 115 can be half the thickness of the unetched portion of the second dielectric layer 115. In other examples, the thickness D of the second portion of the second dielectric layer 115 can also be greater than or less than half the thickness of the unetched portion of the second dielectric layer 115. It is understood that the embodiments of the present application do not further limit the value of the thickness D of the second portion of the second dielectric layer 115.

[0176] In some examples, the thickness D of the second portion of the second dielectric layer 115 adjacent to different locations of the conductive structure 113 may be different.

[0177] FIG21 is a diagram showing the positional relationship between the edge of the orthographic projection of the protection structure on the semiconductor layer and the orthographic projection of the second dielectric layer on the semiconductor layer provided in some embodiments of the present application.

[0178] In some examples, an edge Q1 of the orthographic projection of the protection structure 121 on the semiconductor layer 112 is located between an orthographic projection Q2 of the surface of the second dielectric layer 115 on the side away from the conductive structure 113 on the semiconductor layer 112 and an orthographic projection Q3 of the surface of the second dielectric layer 115 on the side close to the conductive structure 113 on the semiconductor layer 112.

[0179] Taking the example where the orthographic projection of the protective structure 121 on the semiconductor layer 112 is a circle, the orthographic projection of the end face of the conductive structure 113 away from the electronic component 114 on the semiconductor layer 112 is a circle, and the orthographic projection of the second dielectric layer 115 on the semiconductor layer 112 is a ring, as shown in FIG21 , the second dielectric layer 115 covers the conductive structure 113 so that the orthographic projection of the conductive structure 113 on the semiconductor layer 112 can be located within the orthographic projection of the second dielectric layer 115 on the semiconductor layer 112.

[0180] An edge Q1 of the orthographic projection of the protection structure 121 on the semiconductor layer 112 is located between an orthographic projection Q2 of the surface of the second dielectric layer 115 on the side away from the conductive structure 113 on the semiconductor layer 112 and an orthographic projection Q3 of the surface of the second dielectric layer 115 on the side close to the conductive structure 113 on the semiconductor layer 112, so that the protection structure 121 can cover the end face of the conductive structure 113 on the side away from the electronic component 114, as well as a second portion of the second dielectric layer 115 (see region M3 in FIG. 21 ).

[0181] It can be understood that the protection structure 121 can protect the end surface of the conductive structure 113 covered by it away from the electronic component 114, as well as the second portion along the second dielectric layer 115, while the first portion of the second dielectric layer 115 not covered by the protection structure 121 can be etched away (see the M4 area in Figure 21).

[0182] That is, by adopting the above-mentioned arrangement, the protection structure 121 can protect the end surface of the conductive structure 113 away from the electronic component 114 and the second portion of the second dielectric layer 115, and can also enable the first portion of the second dielectric layer 115 to be etched away, thereby reducing the risk of the semiconductor layer 112 adhering to the second dielectric layer 115 and causing the semiconductor layer 112 to remain on the surface of the second dielectric layer 115 away from the conductive structure 113, thereby improving the reliability of the semiconductor structure manufacturing method.

[0183] Figure 22 is a flowchart of the steps of a method for preparing a semiconductor structure provided by some other embodiments of the present application. Figure 23 is a schematic diagram of the structure of a semiconductor layer group provided by some other embodiments of the present application. Figure 24 is a schematic diagram of the structure of a semiconductor layer group provided by some other embodiments of the present application.

[0184] In some examples, as shown in FIG22 , forming a protection structure on a side of the conductive structure away from the first dielectric layer (ie, step S203 ) includes:

[0185] Step S2031 , forming a photoresist layer on a side of the semiconductor layer away from the first dielectric layer.

[0186] As shown in FIG23 , a photoresist layer (full name: Photoresist, English abbreviation: PR) 120 can be formed on a side of the semiconductor layer 112 away from the first dielectric layer 111. In some examples, as shown in FIG23 , other film structures can be disposed between the photoresist layer 120 and the second surface P2 of the semiconductor layer 112; in other examples, the photoresist layer 120 can also be disposed adjacent to the second surface P2 of the semiconductor layer 112.

[0187] In some examples, a printing process may be used to form the photoresist layer 120 on a side of the isolation layer 131 away from the semiconductor layer 112 .

[0188] In step S2032 , the photoresist layer is patterned by exposure and development to form a protection structure.

[0189] For example, a mask can be placed between a light source and the photoresist layer 120 , and light passes through a pattern on the mask to illuminate the photoresist layer 120 , so that the photoresist layer 120 can be patterned to form a protective structure 121 (see FIG. 17 ).

[0190] In some examples, a positive developing photoresist layer may be used; in other examples, a negative developing photoresist layer may also be used.

[0191] It can be understood that the photoresist layer 120 is patterned by exposure and development to form a protective structure 121 without the need for complex preparation methods. On the basis of improving the electrical performance of the semiconductor structure 100, the preparation process of the semiconductor structure 100 is simplified and the preparation cost of the semiconductor structure 100 is reduced.

[0192] Before forming a photoresist layer on a side of the semiconductor layer facing away from the first dielectric layer, the method includes:

[0193] An isolation layer is formed on one side of the second surface of the semiconductor layer, and the isolation layer covers the semiconductor layer and the exposed end surface of the conductive structure.

[0194] As shown in FIG24 , before forming the photoresist layer 120, an isolation layer 131 is formed on one side of the second surface P2 of the semiconductor layer 112. For example, the isolation layer 131 can be disposed adjacent to the second surface P2 of the semiconductor layer 112 so that the isolation layer 131 can cover the exposed end face of the semiconductor layer 112 and the conductive structure 113 (i.e., the end face of the conductive structure 113 away from the electronic component 114). The photoresist layer 120 can be located on the side of the isolation layer 131 away from the semiconductor layer 112.

[0195] It can be understood that the isolation layer 131 can play an isolation role. For example, the material of the isolation layer 131 can be an oxide (English name: oxide), such as silicon dioxide (chemical formula: SiO2); or, the material of the isolation layer 131 can also be a nitride (English name: nitrides), such as silicon nitride (chemical formula: SiN); or, the material of the isolation layer 131 can also be a combination of one or more other high dielectric constant insulating materials. The materials of the first dielectric layer 111, the second dielectric layer 115, the third dielectric layer 116, and the isolation layer 131 can be the same or different. The embodiments of the present application do not further limit the material of the isolation layer 131.

[0196] Taking the conductive structure 113 as a cylinder, the bottom diameter of the cylinder is 5 μm, and the height of the cylinder is 50 μm as an example, the thickness of the isolation layer 131 can be (Unit: Angstrom). In some examples, the larger the size of the conductive structure 113, the thicker the isolation layer 131. The smaller the size of the conductive structure 113, the thinner the isolation layer 131. The embodiments of the present application do not further limit the thickness of the isolation layer 131.

[0197] It can be understood that the isolation layer 131 is formed before forming the photoresist layer 120, so that the isolation layer 131 can isolate the photoresist layer 120 from the end face of the conductive structure 113 away from the electronic component 114, thereby avoiding contact between the photoresist layer 120 and the end face of the conductive structure 113 away from the electronic component 114, thereby avoiding the photoresist layer 120 from contaminating the end face of the conductive structure 113 away from the electronic component 114, and improving the electrical reliability of the semiconductor structure 100.

[0198] In some examples, before etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction using the protection structure as a mask (that is, before step S204), the method further includes:

[0199] Using the protection structure as a mask, the portion of the isolation layer covering the semiconductor layer is etched.

[0200] Referring to Figure 17 again, since the isolation layer 131 covers the second surface P2 of the semiconductor layer 112 and the exposed end face of the conductive structure 113, before etching the semiconductor layer 112, it is necessary to use the protective structure 121 as a mask to etch the part of the isolation layer 131 covering the semiconductor layer 112 so that the semiconductor layer 112 can be exposed, thereby avoiding the isolation layer 131 affecting subsequent processes.

[0201] In one example, etching the portion of the isolation layer 131 covering the semiconductor layer 112 and etching the semiconductor layer 112 can be achieved in the same step.

[0202] 18 , after etching the portion of isolation layer 131 covering semiconductor layer 112, the remaining portion of isolation layer 131 covers the end surface of conductive structure 113 away from electronic component 114. In some examples, the orthographic projection of protection structure 121 on semiconductor layer 112 coincides with the orthographic projection of the remaining portion of isolation layer 131 on semiconductor layer 112.

[0203] In some examples, as shown in FIG. 19 and FIG. 20 , after etching the portion of the isolation layer 131 covering the semiconductor layer 112 and a portion of the semiconductor layer 112 , the protection structure 121 may be removed.

[0204] Figure 25 is a schematic diagram of the structure of a semiconductor layer group provided in some embodiments of the present application. Figure 26 is a schematic diagram of the structure of a semiconductor structure provided in some embodiments of the present application.

[0205] In some examples, after removing the protective structure (that is, after step S205), the following steps are further included:

[0206] A third dielectric layer is formed, and the third dielectric layer covers the second surface of the semiconductor layer and encapsulates the end of the conductive structure protruding from the semiconductor layer.

[0207] It can be understood that the above embodiments of the present application have already provided examples of the material of the third dielectric layer 116 , which will not be described in detail here.

[0208] As shown in FIG25 , third dielectric layer 116 is located on a side of semiconductor layer 112 away from first dielectric layer 111, such that third dielectric layer 116 sufficiently covers semiconductor layer 112 and encapsulates the end of conductive structure 113 protruding from semiconductor layer 112. In some examples, third dielectric layer 116 may be disposed adjacent to second surface P2 of semiconductor layer 112.

[0209] A portion of the third dielectric layer and the isolation layer are removed along the first direction to expose the end surface of the conductive structure.

[0210] It is understood that after forming the third dielectric layer 116, a portion of the third dielectric layer 116 and the isolation layer 131 covering the end surface of the conductive structure 113 away from the electronic component 114 can be removed along the first direction X, as shown in FIG26 , so that the end surface of the conductive structure 113 away from the electronic component 114 can be exposed. For example, the end surface of the conductive structure 113 away from the electronic component 114 is flush with the surface of the third dielectric layer 116 away from the semiconductor layer 112.

[0211] In some examples, a CMP process may be used to remove a portion of the third dielectric layer 116 and the isolation layer 131 covering the end surface of the conductive structure 113 away from the electronic component 114. For example, when removing a portion of the third dielectric layer 116 and the isolation layer 131 covering the end surface of the conductive structure 113 away from the electronic component 114, a portion of the conductive structure 113 along the first direction X may be removed, thereby achieving polishing and planarization of the surface of the third dielectric layer 116 away from the semiconductor layer 112 and the end surface of the conductive structure 113 away from the electronic component 114, thereby improving the structural regularity of the semiconductor structure 100.

[0212] It can be understood that by removing the third dielectric layer 116 along the first direction X, the end surface of the conductive structure 113 away from the electronic component 114 can be exposed, thereby allowing other components (such as external components or other semiconductor structures 100) to be electrically connected to the semiconductor structure 100 through the conductive structure 113. In addition, the third dielectric layer 116 can play an electrical isolation role, thereby improving the reliability of the semiconductor structure 100 when electrically connected to other components.

[0213] On the other hand, an embodiment of the present application provides a semiconductor structure 100. As shown in FIG26 , the semiconductor structure 100 may include a semiconductor layer group 110 and a third dielectric layer 116.

[0214] For example, as shown in FIG26 , semiconductor layer assembly 110 may include a first dielectric layer 111, a semiconductor layer 112, a second dielectric layer 115, a conductive structure 113, and an electronic component 114. Semiconductor layer 112 includes a first surface P1 and a second surface P2 opposite to each other. First dielectric layer 111 is disposed adjacent to first surface P1 of semiconductor layer 112. Electronic component 114 is located within first dielectric layer 111. One end of conductive structure 113 is located within first dielectric layer 111 and is electrically connected to electronic component 114. Second dielectric layer 115 covers conductive structure 113.

[0215] The third dielectric layer 116 is disposed adjacent to the second surface P2 of the semiconductor layer 112. The end of the conductive structure 113 away from the electronic component 114 passes through the semiconductor layer 112 and the third dielectric layer 116.

[0216] It can be understood that the above embodiments of the present application have provided examples of the materials and positional relationship of the semiconductor layer group 110 and the third dielectric layer 116 , which will not be repeated here.

[0217] 26 , the second dielectric layer 115 includes a first sub-portion 115a and a second sub-portion 115b. The first sub-portion 115a is located between the third dielectric layer 116 and the conductive structure 113, and the second sub-portion 115b is located between the semiconductor layer 112 and the conductive structure 113. The thickness of the first sub-portion 115a is less than that of the second sub-portion 115b.

[0218] It can be understood that since the first portion along the second dielectric layer 115 is etched while etching the semiconductor layer 112, the thickness of the remaining portion of the second dielectric layer 115 (the second portion of the second dielectric layer 115, that is, the first sub-portion 115a) after etching can be less than the thickness of the unetched second dielectric layer 115.

[0219] Such a configuration can reduce the risk of the semiconductor layer 112 adhering to the surface of the first sub-portion 115 a away from the conductive structure 113 , thereby improving the electrical reliability of the semiconductor structure 100 .

[0220] In summary, the embodiments of the present application have at least the following beneficial effects:

[0221] In an embodiment of the present application, a protective structure 121 is formed on a side of the conductive structure 113 away from the first dielectric layer 111. The orthographic projection of the protective structure 121 on the semiconductor layer 112 covers the orthographic projection of the exposed end face of the conductive structure 113 (that is, the end face of the conductive structure 113 away from the electronic component 114) on the semiconductor layer 112, so that the protective structure 121 can shield and cover the end face of the conductive structure 113 away from the electronic component 114.

[0222] In this way, the protective structure 121 can be used as a mask. When etching a portion of the semiconductor layer 112 from the side of the second surface P2 of the semiconductor layer 112 along the first direction X, the etching ion beam will not bombard the end face of the conductive structure 113 away from the electronic component 114, thereby reducing the risk of metal particles falling on the second surface P2 of the semiconductor layer 112 due to splashing of the conductive structure 113 under the action of the etching ion beam when etching a portion of the semiconductor layer 112. This can reduce the residual conductive metal particles, reduce the metal contamination of the semiconductor layer 112 caused by the conductive structure 113, and improve the electrical reliability of the semiconductor structure 100.

[0223] Furthermore, after etching a portion of the semiconductor layer 112 , the protection structure 121 is removed, thereby preventing the protection structure 121 from affecting subsequent processing techniques.

[0224] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a semiconductor layer group, the semiconductor layer group comprising a first dielectric layer, a semiconductor layer, a conductive structure and an electronic element; The semiconductor layer comprises a first surface and a second surface which are arranged opposite to each other, the first dielectric layer is arranged adjacent to the first surface of the semiconductor layer, and the electronic component is located in the first dielectric layer; One end of the conductive structure is located in the first dielectric layer and is electrically connected to the electronic component, and the other end of the conductive structure passes through the first surface of the semiconductor layer and extends into the semiconductor layer; Along the first direction, a portion of the semiconductor layer is removed from one side of the second surface of the semiconductor layer to expose an end surface of the conductive structure away from the electronic component; The first direction intersects with the surface of the semiconductor layer; forming a protection structure on a side of the conductive structure away from the first dielectric layer, wherein the orthographic projection of the protection structure on the semiconductor layer covers the orthographic projection of the exposed end surface of the conductive structure on the semiconductor layer; Using the protection structure as a mask, etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along a first direction; The protective structure is removed.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The semiconductor layer group further includes a second dielectric layer, and the second dielectric layer covers the conductive structure; Using the protection structure as a mask, etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction, further comprising: The first portion of the second dielectric layer is etched; the first portion of the second dielectric layer covers the outer peripheral side of the conductive structure away from the end of one side of the electronic component and is away from the conductive structure along a second direction; the second direction is parallel to the surface of the semiconductor layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The edge of the orthographic projection of the protection structure on the semiconductor layer is located between the orthographic projection of the surface of the second dielectric layer away from the conductive structure on the semiconductor layer and the orthographic projection of the surface of the second dielectric layer close to the conductive structure on the semiconductor layer.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The protection structure is formed on a side of the conductive structure away from the first dielectric layer, comprising: forming a photoresist layer on a side of the semiconductor layer away from the first dielectric layer; The photoresist layer is patterned by exposure and development to form the protection structure.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: Before forming the photoresist layer on a side of the semiconductor layer away from the first dielectric layer, the method comprises: forming an isolation layer on one side of the second surface of the semiconductor layer, wherein the isolation layer covers the semiconductor layer and the exposed end surface of the conductive structure; Before etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction using the protection structure as a mask, the method further includes: Using the protection structure as a mask, etching the portion of the isolation layer covering the semiconductor layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: After removing the protective structure, the method further comprises: forming a third dielectric layer, wherein the third dielectric layer covers the second surface of the semiconductor layer and wraps the end of the conductive structure protruding from the semiconductor layer; A portion of the third dielectric layer and the isolation layer are removed along the first direction to expose an end surface of the conductive structure away from the electronic component.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: There are multiple conductive structures, and the multiple conductive structures include a first conductive structure and a second conductive structure; before a portion of the semiconductor layer is removed from one side of the second surface of the semiconductor layer along the first direction to expose an end surface of the conductive structure away from the electronic component, a distance between the end surface of the first conductive structure away from the electronic component and the second surface of the semiconductor layer is not equal to a distance between the end surface of the second conductive structure away from the electronic component and the second surface of the semiconductor layer; Removing a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction to expose an end surface of the conductive structure away from the electronic component comprises: Along the first direction, a portion of the semiconductor layer and a portion of the conductive structure are removed from one side of the second surface of the semiconductor layer to expose the end faces of the first conductive structure and the second conductive structure away from the electronic component; wherein the exposed end face of the first conductive structure is flush with the exposed end face of the second conductive structure.

8. A semiconductor structure, characterized in that: include: A semiconductor layer group, the semiconductor layer group comprising a first dielectric layer, a semiconductor layer, a second dielectric layer, a conductive structure and an electronic element; Said The semiconductor layer comprises a first surface and a second surface which are arranged opposite to each other, the first dielectric layer is arranged adjacent to the first surface of the semiconductor layer, and the electronic component is located in the first dielectric layer; One end of the conductive structure is located in the first dielectric layer and is electrically connected to the electronic component; The second dielectric layer covers the conductive structure; a third dielectric layer, the third dielectric layer being disposed adjacent to the second surface of the semiconductor layer; an end of the conductive structure away from the electronic component passes through the semiconductor layer and the third dielectric layer, and an end surface of the conductive structure away from the electronic component is exposed to the third dielectric layer; The second dielectric layer includes a first sub-portion and a second sub-portion, the first sub-portion is located between the third dielectric layer and the conductive structure, and the second sub-portion is located between the semiconductor layer and the conductive structure; the thickness of the first sub-portion is smaller than the thickness of the second sub-portion.

9. A functional chip, characterized in that: comprising at least one semiconductor structure; the semiconductor structure being the semiconductor structure as claimed in claim 8; or, The semiconductor structure is manufactured according to the method for manufacturing a semiconductor structure according to any one of claims 1 to 7.

10. The functional chip according to claim 9, characterized in that: When the functional chip includes at least two semiconductor structures, the at least two semiconductor structures include a first semiconductor structure and a second semiconductor structure; The exposed end surface of the conductive structure in the first semiconductor structure is bonded to the exposed end surface of the conductive structure in the second semiconductor structure.

11. An electronic device, characterized in that: include: bus; The function chip as claimed in claim 9 or 10, wherein the function chip is electrically connected to the bus.

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