Signal processing circuit

Abstract

In this signal processing circuit (1), an input circuit (2) generates an input signal (SIN) by binarizing an external input wave (EW). A digital filter circuit (4) samples the input signal (SIN) on the basis of a clock signal (CLK), and removes noise included in the input signal (SIN) on the basis of a plurality of sampling values. A counter circuit (5) counts the number of pulses included in the input signal (SIN) from which the noise has been removed by the digital filter circuit (4). A clock supply circuit (3) which generates the clock signal (CLK) selectively outputs one of a phase synchronization circuit output and a timer circuit output as the clock signal (CLK).

Description

signal processing circuit

[0001] The present disclosure relates to signal processing circuits.

[0002] Japanese Patent Laid-Open Publication No. 3-195112 (Patent Document 1) discloses a counter unit provided with a filter circuit on the input side to remove noise from the input signal.

[0003] In particular, in this document, the time constant of the filter circuit is determined not by a CR configuration but by a programmable configuration. Specifically, the clock signal used in the filter circuit is generated by dividing the input clock by a set division ratio.

[0004] Japanese Patent Application Publication No. 3-195112

[0005] The setting range of the clock frequency is limited by simply dividing the input clock using a frequency divider circuit as described in the above-mentioned Patent Document 1. The present disclosure has been made in consideration of the above-mentioned background art, and one of its purposes is to expand the setting range of the time constant of a filter circuit more than ever before.

[0006] In one embodiment, the signal processing circuit includes an input circuit, a digital filter circuit, a counter circuit, and a clock supply circuit that generates a clock signal. The input circuit generates the input signal by binarizing an external input wave. The digital filter circuit samples the input signal based on the clock signal and removes noise contained in the input signal based on a plurality of sampled values ​​that are successive in time series. The counter circuit counts the number of pulses contained in the input signal from which noise has been removed by the digital filter circuit. The clock supply circuit includes a phase-locked loop circuit that multiplies and divides an original frequency, and a timer circuit that outputs a square wave that is inverted when the count number of a reference signal matches a set value. The clock supply circuit selects and outputs one of the output of the phase-locked loop circuit and the output of the timer circuit as a clock signal.

[0007] According to the above embodiment, by selecting one of the output of the phase locked loop and the output of the timer circuit as a clock signal and outputting it to the digital filter circuit, the setting range of the time constant of the filter circuit can be expanded more than ever before.

[0008] 1. A block diagram showing an example of the configuration of a signal processing circuit according to a first embodiment. 2. A circuit diagram showing an example of the configuration of the digital filter circuit of FIG. 1. 3. A circuit diagram showing a modified example of the digital filter circuit of FIG. 2. 4. A block diagram showing an example of the configuration of the clock supply circuit of FIG. 1. 5. A block diagram showing an example of the configuration of the phase locked loop circuit of FIG. 4. 6. A block diagram showing an example of the configuration of the timer circuit of FIG. 4. 7. A block diagram showing a first modified example of the clock supply circuit of FIG. 4. 8. A block diagram showing a second modified example of the clock supply circuit of FIG. 4. 9. A block diagram showing an example of the configuration of a signal processing circuit according to a second embodiment. 10. A block diagram showing an example of the configuration of the digital filter circuit of FIG. 9. 11. A block diagram showing a modified example of the signal processing circuit of FIG. 11. 12. A block diagram showing an example of the configuration of a signal processing circuit according to a third embodiment. 13. A block diagram showing examples of the digital filter circuit and clock buffer circuit of FIG. 13.

[0009] Hereinafter, each embodiment will be described in detail with reference to the drawings. Note that the same or similar reference characters are used to refer to the same or corresponding parts, and the description thereof will not be repeated.

[0010] Embodiment 1 [Overall Configuration of Signal Processing Circuit] Fig. 1 is a block diagram showing an example configuration of a signal processing circuit 1 according to embodiment 1. Referring to Fig. 1, signal processing circuit 1 includes an input circuit 2, a clock supply circuit 3, a digital filter circuit 4, and a counter circuit 5. The signal processing circuit is mounted on, for example, a microcomputer or the like.

[0011] The input circuit 2 generates a digital input signal SIN having high and low logical values ​​by binarizing the external input wave EW. The input signal SIN contains noise that partially inverts the logical value due to noise contained in the external input wave EW. The input signal SIN may also contain chattering. The input signal SIN is input to a digital filter circuit 4.

[0012] The clock supply circuit 3 generates a clock signal CLK having a set frequency based on a reference clock. The clock signal CLK is input to a digital filter circuit 4.

[0013] The digital filter circuit 4 samples the input signal SIN at each cycle of the clock signal CLK. The digital filter circuit 4 determines the logical value of the input signal SIN at the current sampling time based on the logical values ​​of the input signal SIN at multiple consecutive sampling times in a time series including the current sampling time.

[0014] For example, the digital filter circuit 4 sets the input signal SIN at the current sampling time to a high level when all of the input signals SIN at the multiple sampling times are at a high level, and sets the input signal SIN at the current sampling time to a low level when all of the input signals SIN at the multiple sampling times are at a low level. If the input signal SIN at the multiple sampling times includes both a high level and a low level, the logical value at the sampling time immediately preceding the current sampling time is maintained. The digital filter circuit 4 may perform signal processing based on majority vote instead of this signal processing based on unanimity.

[0015] The digital filter circuit 4 performs the above-described signal processing on the input signal S IN to generate an output signal S OUT from which noise and chattering contained in the input signal S IN has been removed. The output signal S OUT is input to the counter circuit 5.

[0016] The counter circuit 5 counts the number of pulses contained in the output signal SOUT output from the digital filter circuit 4 .

[0017] [Configuration Example of Digital Filter Circuit] Fig. 2 is a circuit diagram showing a configuration example of digital filter circuit 4 of Fig. 1. Referring to Fig. 2, digital filter circuit 4 is formed of logic circuits, and includes a shift register 10 and a logical operation circuit 11.

[0018] The shift register 10 includes n stages of D flip-flops DF1 to DFn connected in series. FIG. 2 shows the case where n=4. An input signal SIN is input to the D terminal of the first-stage D flip-flop DF1. The output of the Q terminal of the (i-1)th stage D flip-flop DFi-1 is input to the D terminal of the ith stage (2≦i≦n) D flip-flop DFi. The outputs Q1 to Qn from the Q terminals of the D flip-flops DF1 to DFn of each stage are input to a logical operation circuit 11.

[0019] A clock signal CLK is input to the clock terminal of each of the D flip-flops DF1 to DFn. The sampling period of the input signal SIN can be changed by changing the period of the clock signal CLK. Each of the D flip-flops DF1 to DFn may be provided with a reset terminal (not shown).

[0020] The logical operation circuit 11 includes an AND circuit 12, a NOR circuit 13, and an RS (Reset-Set) flip-flop 14. The AND circuit 12 calculates the logical product of the outputs Q1 to Qn from the Q terminals of the D flip-flops DF1 to DFn in each stage. The NOR circuit 13 calculates the negation of the logical sum of the outputs Q1 to Qn from the Q terminals of the D flip-flops DF1 to DFn in each stage. The result of the operation by the AND circuit 12 is input to the S terminal of the RS flip-flop 14. The result of the operation by the NOR circuit 13 is input to the R terminal of the RS flip-flop 14. The output signal SOUT of the digital filter circuit 4 is output from the Q terminal of the RS flip-flop 14.

[0021] According to the configuration of the logic operation circuit 11, when the outputs Q1 to Qn of the Q terminals of the D flip-flops DF1 to DFn in each stage are all high level ("1"), "1" is input to the S terminal of the RS flip-flop 14 and "0" is input to the R terminal. As a result, the RS flip-flop 14 is set, and a high level output signal SOUT is output.

[0022] When the outputs Q1 to Qn of the Q terminals of the D flip-flops DF1 to DFn in each stage are all low level ("0"), "1" is input to the R terminal of the RS flip-flop 14 and "0" is input to the S terminal thereof. As a result, the RS flip-flop 14 is reset and outputs a low level output signal SOUT.

[0023] When the outputs Q1 to Qn of the Q terminals of the D flip-flops DF1 to DFn in each stage contain a mixture of "1" and "0," "0" is input to both the S terminal and the R terminal of the RS flip-flop 14. As a result, the output of the RS flip-flop 14 maintains its current state.

[0024] Fig. 3 is a circuit diagram showing a modification of the digital filter circuit 4 shown in Fig. 2. In the digital filter circuit 4A shown in Fig. 3, the logical operation circuit 11 shown in Fig. 2 is replaced with a logical operation circuit 11A. For simplicity, the following description will be given assuming that the number of stages n of the shift register 10 is 4.

[0025] 2 in that it further includes a NOT circuit 21 and an RS flip-flop 22. Furthermore, in the logic operation circuit 11A of FIG. 3, the configurations of the AND circuit 12 and the NOR circuit 13 of FIG. 2 are shown in more detail.

[0026] Specifically, the AND circuit 12 includes AND circuits 15, 16, and 17. The AND circuit 15 calculates the logical product of the outputs Q1 and Q2 of the first- and second-stage D flip-flops DF1 and DF2. The AND circuit 16 calculates the logical product of the outputs Q3 and Q4 of the third- and fourth-stage D flip-flops DF3 and DF4. The AND circuit 17 calculates the logical product of the operation result of the AND circuit 15 and the operation result of the AND circuit 16. The operation result of the AND circuit 17 is input to the S terminal of the RS flip-flop 14 as the operation result of the AND circuit 12.

[0027] The NOR circuit 13 includes OR circuits 18 and 19 and a NOR circuit 20. The OR circuit 18 calculates the logical sum of the outputs Q1 and Q2 of the first- and second-stage D flip-flops DF1 and DF2. The OR circuit 19 calculates the logical sum of the outputs Q3 and Q4 of the third- and fourth-stage D flip-flops DF3 and DF4. The NOR circuit 20 calculates the negation of the logical sum of the calculation result of the OR circuit 18 and the calculation result of the OR circuit 19. The calculation result of the NOR circuit 20 is input to the R terminal of the RS flip-flop 14 as the calculation result of the NOR circuit 13.

[0028] The S terminal of the RS flip-flop 22 receives the operation result of the AND circuit 15, which is an intermediate stage of the logical AND operation of the AND circuit 12. The R terminal of the RS flip-flop 22 receives the negation of the operation result of the OR circuit 18, which is an intermediate stage of the logical OR operation of the NOR circuit 13.

[0029] According to the above configuration, the logic operation circuit 11A of FIG. 3 outputs both an output signal SOUT based on the logical values ​​of the input signal SIN at four consecutive sampling times including the current sampling time, and an output signal SOUT' based on the logical values ​​of the input signal SIN at two consecutive sampling times including the current sampling time. Therefore, these output signals SOUT and SOUT' are signals obtained by performing logical operations on sampled values ​​at different sampling points. The counter circuit 5 of FIG. 1 can selectively use these output signals SOUT and SOUT'.

[0030] [Configuration Example of Clock Supply Circuit] Fig. 4 is a block diagram showing a configuration example of the clock supply circuit 3 of Fig. 1. Referring to Fig. 4, the clock supply circuit 3 includes a phase locked loop (PLL) 30 and a timer circuit 31. The clock supply circuit 3 outputs an output signal selected from either the phase locked loop 30 or the timer circuit 31 as the clock signal CLK.

[0031] The phase-locked loop 30 generates a signal with a frequency obtained by multiplying and dividing the original frequency generated by the reference oscillator. The timer circuit 31 counts the pulse signal generated by the reference oscillator and generates a square wave that inverts when the count value equals a set value. By using the phase-locked loop 30 and the timer circuit 31 together, the frequency of the clock signal CLK can be set over an extremely wide range.

[0032] When the clock signal CLK is output from the phase locked loop 30, the output terminal of the timer circuit 31 is set to high impedance, thereby preventing any influence on the phase locked loop 30. Conversely, when the clock signal CLK is output from the timer circuit 31, the output terminal of the phase locked loop 30 is set to high impedance.

[0033] Fig. 5 is a block diagram showing an example of the configuration of the phase locked loop 30 of Fig. 4. Referring to Fig. 5, the phase locked loop 30 includes a reference oscillator 40, a frequency divider 41, a phase comparator 42, a low-pass filter 43, a voltage controlled oscillator 44, and a frequency divider 45.

[0034] The reference oscillator 40 generates a reference signal having an excitation frequency. The frequency divider 41 divides the excitation frequency by 1 / M. The phase comparator 42 detects the phase difference between the reference signal divided by the frequency divider 41 and the clock signal CLK1 divided by the frequency divider 45. The low-pass filter 43 removes ripples from the ripple-containing DC signal output from the phase comparator 42. The voltage-controlled oscillator 44 generates the clock signal CLK1 having a frequency corresponding to the magnitude of the DC signal that has passed through the low-pass filter 43. The frequency divider 45 divides the clock signal CLK1 by 1 / N.

[0035] By the above feedback control, the phase locked loop 30 can stably generate the clock signal CLK1 having a frequency N / M times the excitation frequency.

[0036] Fig. 6 is a block diagram showing an example of the configuration of the timer circuit 31 of Fig. 4. The timer circuit 31 includes a counter 50, a data register 51, a comparator 52, and an output circuit 53.

[0037] Counter 50 counts the reference signal output from reference oscillator 54 for each period. Data register 51 stores a count value set by CPU (Central Processing Unit) 55. Comparator 52 compares the current count value of counter 50 with the count value stored in data register 51 and activates its output when the two match. When the output of comparator 52 is activated, the count value of counter 50 is reset. Output circuit 53 outputs a signal to the outside in response to the activation of the output of comparator 52. For example, output circuit 53 outputs, as clock signal CLK2, a square wave that is inverted when the output of comparator 52 is activated.

[0038] According to the above-described configuration of the timer circuit 31, by changing the count value set in the data register 51, it is possible to generate clock signals CLK having various frequencies.

[0039] The phase locked loop 30 and the timer circuit 31 are selectively used when the frequency generated by the reference oscillator 40 of the phase locked loop 30 and its division can be selected as the clock signal CLK. On the other hand, when a frequency that cannot be realized by the phase locked loop 30, i.e., a frequency that does not correspond to the reference oscillator 40 or its division, is desired, the output (rising edge, etc.) of the timer circuit 31 is selected as the frequency of the clock signal CLK. This allows the window length of the digital filter circuit 4 (the period containing multiple consecutive sampling values ​​in a time series) to be changed over a wide range and with fine adjustment.

[0040] [Modification of Clock Supply Circuit] Fig. 7 is a block diagram showing a first modification of the clock supply circuit 3 of Fig. 4. In the configuration of the clock supply circuit 3 of Fig. 4, only one port is provided for outputting a selected one of the output signal of the phase locked loop 30 and the output signal of the timer circuit 31 as the clock signal CLK.

[0041] 7 is provided with a port 60 for outputting the output signal of the phase locked loop 30 and a port 61 for outputting the output signal of the timer circuit 31. When the output signal of the phase locked loop 30 is used as the clock signal CLK, the output signal of the phase locked loop 30 is output from the port 60. When the output signal of the timer circuit 31 is used as the clock signal CLK, the output signal of the timer circuit 31 is output from the port 61.

[0042] Fig. 8 is a block diagram showing a second modified example of the clock supply circuit 3 of Fig. 4. The configuration of Fig. 8 includes a first clock supply circuit 3A including a phase locked loop 30 and a second clock supply circuit 3B including a timer circuit 31. When the output signal of the phase locked loop 30 is used as the clock signal CLK, the output signal of the phase locked loop 30 is output from the first clock supply circuit 3A. When the output signal of the timer circuit 31 is used as the clock signal CLK, the output signal of the timer circuit 31 is output from the second clock supply circuit 3B.

[0043] Which of the clock supply circuits 3A and 3B outputs the clock signal CLK may be controlled by mutual communication or by a higher-level control system.

[0044] Furthermore, since the division into the first clock supply circuit 3A and the second clock supply circuit 3B is for convenience's sake, the clock supply circuits 3A and 3B may be considered collectively as one clock supply circuit 3. In this case, the modified example of Fig. 8 can be considered to be substantially the same as the clock supply circuits 3 of Figs. 4 and 7.

[0045] Summary of First Embodiment As described above, the digital filter circuit 4 samples the input signal SIN based on the clock signal CLK, and removes noise contained in the input signal SIN based on a plurality of sampled values ​​that are consecutive in time series.

[0046] For the sake of explanation, the period during which the time series includes a plurality of consecutive sampled values ​​is referred to as the window length (or time constant) of the digital filter circuit 4. The window length is expressed as the product of the number of sampling points and the sampling period. The window length must be set to be sufficiently shorter than the pulse width of the external input wave EW or the input signal SIN.

[0047] To change the window length, (i) the sampling period is changed by changing the frequency of the clock signal CLK, or (ii) the number of sampling points is changed by changing the number of data used for processing from the output of each stage of the shift register 10.

[0048] As described with reference to FIGS. 4 to 6 , in order to increase the frequency of the clock signal CLK and shorten the sampling period, the division ratio M of the frequency divider 41 in the phase locked loop 30 is decreased and the division ratio N of the frequency divider 45 is increased. Alternatively, the count value set in the data register 51 in the timer circuit 31 is changed to a smaller value. In order to decrease the frequency of the clock signal CLK and lengthen the sampling period, the division ratio M of the frequency divider 41 in the phase locked loop 30 is increased and the division ratio N of the frequency divider 45 is decreased. Alternatively, the count value set in the data register 51 in the timer circuit 31 is changed to a larger value.

[0049] 3, the number of sampling points used for signal processing in the logic operation circuit 11A can be changed, thereby making it possible to change the window length.

[0050] According to the signal processing circuit 1 of this embodiment, by changing the frequency of the clock signal CLK used for signal processing by using the phase locked loop 30 and the timer circuit 31 in combination as described above, the window length (i.e., the time constant) of the digital filter circuit 4 can be changed over a wider range than conventionally possible.

[0051] Embodiment 2 In embodiment 2, in the digital filter circuit 4, the output signal of the D flip-flop DF at an intermediate stage of the shift register 10 can be output as is to the counter circuit 5 without undergoing filtering processing with a window length configured by the logic operation circuit 11. If the window length of the digital filter circuit 4 cannot be made sufficiently shorter than the period of the input signal SIN even when the excitation frequency is multiplied using the phase locked loop 30, the digital filter circuit 4 outputs the output signal of the D flip-flop DF at an intermediate stage of the shift register 10 as is without undergoing filtering processing with a window length configured by the logic operation circuit 11. The following will be described with reference to the drawings.

[0052] Fig. 9 is a block diagram showing an example of the configuration of a signal processing circuit 1A according to embodiment 2. In the signal processing circuit 1A of Fig. 9, a digital filter circuit 4B is provided instead of the digital filter circuit 4 of Fig. 1. The digital filter circuit 4B outputs an output Qi of any one of the D flip-flops DFi constituting the shift register 10 together with a filtered output signal SOUT.

[0053] Counter circuit 5 performs counting processing on a selected signal from output signals SOUT and Qi output from digital filter circuit 4 B. Since the other configuration in Fig. 9 is the same as that in Fig. 1, the same or corresponding parts are given the same reference characters and description thereof will not be repeated.

[0054] Fig. 10 is a block diagram showing an example of the configuration of digital filter circuit 4B of Fig. 9. Digital filter circuit 4A of Fig. 10 differs from digital filter circuit 4 of Fig. 2 in that it further includes a terminal for outputting output signal Q1 of first-stage D flip-flop DF1 that constitutes shift register 10. Since other points in Fig. 10 are the same as those in Fig. 2, the same or corresponding parts are designated with the same reference numerals and description thereof will not be repeated.

[0055] Fig. 11 is a block diagram showing a modification of the signal processing circuit 1A of Fig. 9. In the signal processing circuit 1B of Fig. 11, a digital filter circuit 4C is provided instead of the digital filter circuit 4 of Fig. 1. The digital filter circuit 4C outputs the output signals Q1 to Qn of all the D flip-flops DF1 to DFn that make up the shift register 10, together with the filtered output signal SOUT.

[0056] Counter circuit 5 performs counting processing on a selected signal from output signals SOUT and Q1 to Qn output from digital filter circuit 4 C. Since the other configurations in Fig. 11 are the same as those in Fig. 1, the same or corresponding parts are given the same reference numerals and description thereof will not be repeated.

[0057] Fig. 12 is a block diagram showing an example of the configuration of the digital filter circuit 4C of Fig. 11. Fig. 11 shows the case where the number of stages of the shift register 10 is n=4.

[0058] Digital filter circuit 4C in Fig. 12 differs from digital filter circuit 4 in Fig. 2 in that it further includes four terminals for outputting output signals Q1 to Q4 of D flip-flops DF1 to DF4 that constitute shift register 10. Since other points in Fig. 12 are the same as those in Fig. 2, the same or corresponding parts are designated with the same reference characters and description thereof will not be repeated.

[0059] Third Embodiment In the third embodiment, the input signal SIN can be output as is without filtering in the digital filter circuit 4. Even if the excitation frequency is multiplied using the phase locked loop 30, if the window length of the digital filter circuit 4 cannot be made sufficiently short compared to the period of the input signal SIN, the digital filter circuit 4 outputs the input signal SIN as is without filtering. This makes it possible to input a signal with even less delay and a shorter window length into the counter circuit 5. The following will be described with reference to the drawings.

[0060] 13 is a block diagram showing an example configuration of a signal processing circuit 1C according to a third embodiment. The signal processing circuit 1C of FIG. 13 differs from the signal processing circuit 1 of FIG. 1 in that it further includes a clock buffer circuit 6. An input signal SIN from an input circuit 2 is input to both a digital filter circuit 4 and a clock buffer circuit 6. As described in the first embodiment, the digital filter circuit 4 filters the input signal SIN and outputs an output signal SOUT to the counter circuit 5. The clock buffer circuit 6 outputs a signal shaped in accordance with the input signal SIN as an output signal SOUT_Buff to the counter circuit 5.

[0061] Counter circuit 5 performs count processing on a selected signal from output signal SOUT from digital filter circuit 4 and output signal SOUT_Buff from clock buffer circuit 6. Since other points in Figure 13 are the same as those in Figure 1, the same or corresponding parts are given the same reference characters and description thereof will not be repeated.

[0062] Figure 14 is a block diagram showing an example of the configuration of digital filter circuit 4 and clock buffer circuit 6 of Figure 13. Digital filter circuit 4 of Figure 14 is similar to digital filter circuit 4 of Figure 2, so the same or corresponding parts are given the same reference numerals and description thereof will not be repeated. Clock buffer circuit 6 of Figure 14 is connected in parallel with digital filter circuit 4 between input circuit 2 and counter circuit 5 of Figure 13. Clock buffer circuit 6 has a Schmitt trigger function.

[0063] Instead of the digital filter circuit 4 of Fig. 14, any of the digital filter circuit 4A of Fig. 3, the digital filter circuit 4B of Fig. 10, and the digital filter circuit 4C of Fig. 12 may be used. When the digital filter circuit 4B of Fig. 10 is used, the counter circuit 5 performs count processing on a signal selected from the output signal Qi of the D flip-flop DFi, the output signal SOUT of the logic operation circuit 11, and the output signal SOUT_Buff of the clock buffer circuit 6. When the digital filter circuit 4C of Fig. 12 is used, the counter circuit 5 performs count processing on a signal selected from the output signals Q1 to Q4 of the D flip-flops DF1 to DF4 that constitute the shift register 10, the output signal SOUT of the logic operation circuit 11, and the output signal SOUT_Buff of the clock buffer circuit 6.

[0064] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0065] 1, 1A, 1B, 1C signal processing circuit, 2 input circuit, 3, 3A, 3B clock supply circuit, 4, 4A, 4B, 4C digital filter circuit, 5 counter circuit, 6 clock buffer circuit, 10 shift register, 11, 11A logic operation circuit, 12, 15, 16, 17 AND circuit, 13, 20 NOR circuit, 14, 22 RS flip-flop, 18, 19 OR circuit, 21 NOT circuit, 30 phase synchronization circuit, 31 timer circuit, 40, 54 reference oscillator, 41, 45 frequency divider, 42 phase comparator, 43 low-pass filter, 44 voltage-controlled oscillator, 50 counter, 51 data register, 52 comparator, 53 output circuit, CLK, CLK1, CLK2 clock signal, DF1 to DF4 D flip-flop, EW External input wave, Q1 to Q4 D flip-flop outputs, SOUT output signal, SOUT_Buff output signal, SIN input signal.

Claims

1. A signal processing circuit comprising: an input circuit that generates an input signal by binarizing an external input wave; a digital filter circuit that samples the input signal based on a clock signal and removes noise contained in the input signal based on a plurality of sampled values ​​that are successive in a time series; a counter circuit that counts the number of pulses contained in the input signal from which noise has been removed by the digital filter circuit; and a clock supply circuit that generates the clock signal, wherein the clock supply circuit comprises: a phase synchronization circuit that multiplies and divides an original frequency; and a timer circuit that outputs a square wave that is inverted when the count number of a reference signal matches a set value, and the clock supply circuit selects and outputs one of the output of the phase synchronization circuit and the output of the timer circuit as the clock signal.

2. The signal processing circuit according to claim 1, wherein the digital filter circuit comprises a shift register and a logical operation circuit, the shift register including n stages (n is an integer equal to or greater than 2) of D flip-flops connected in series and operating in synchronization with the clock signal, the input signal being input to a first stage of D flip-flop, and the logical operation circuit determines an output signal of the digital filter circuit for each cycle of the clock signal based on the logical values ​​of the output signals of the n stages of D flip-flops.

3. The signal processing circuit of claim 2, wherein the logic operation circuit includes an RS (Reset-Set) flip-flop, and inputs an output signal of the RS flip-flop to the counter circuit as an output signal of the digital filter circuit, and the logic operation circuit is configured to: input a "1" to the set terminal and a "0" to the reset terminal of the RS flip-flop when the outputs of the n-stage D flip-flops are all "1", input a "1" to the reset terminal and a "0" to the set terminal of the RS flip-flop when the outputs of the n-stage D flip-flops are all "0", input a "1" to the reset terminal and a "0" to the set terminal of the RS flip-flop when the outputs of the n-stage D flip-flops are a mixture of "1" and "0", and input a "0" to each of the set terminal and reset terminal of the RS flip-flop.

4. The signal processing circuit according to claim 2 or 3, wherein the digital filter circuit outputs an output signal of at least one of the n-stage D flip-flops together with an output signal of the logical operation circuit to the counter circuit, and the counter circuit is configured to count the number of pulses of a signal selected from the output signal of the at least one D flip-flop and the output signal of the logical operation circuit.

5. The signal processing circuit according to any one of claims 1 to 3, further comprising a clock buffer circuit connected in parallel with the digital filter circuit between the input circuit and the counter circuit, the clock buffer circuit outputs a signal shaped in accordance with the input signal to the counter circuit, and the counter circuit is configured to count the number of pulses of a signal selected from the output signal of the digital filter circuit and the output signal of the clock buffer circuit.

6. The signal processing circuit according to claim 4, further comprising a clock buffer circuit connected in parallel with the digital filter circuit between the input circuit and the counter circuit, the clock buffer circuit outputs a signal shaped in accordance with the input signal to the counter circuit, and the counter circuit is configured to count the number of pulses of a signal selected from the output signal of the at least one D flip-flop, the output signal of the logical operation circuit, and the output signal of the clock buffer circuit.

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