Storage unit, and memory and preparation method therefor

Abstract

The present disclosure relates to the technical field of storage, and relates to a storage unit, and a memory and a preparation method therefor. In the storage unit, a semiconductor layer is in a closed ring shape; and an inner area of the ring of the semiconductor layer comprises a first area and a second area, which are insulated and isolated from each other in a first direction. The semiconductor layer comprises: a first semiconductor portion, which surrounds part of the boundary of the first area, and a second semiconductor portion, which surrounds part of the boundary of the second area. A first gate electrode is located in the first area. Two second gate electrodes are respectively located on two sides of the first semiconductor portion that are away from the first gate electrode and opposite each other in a second direction, the second direction intersecting with the first direction. A contact electrode conformally covers an inner side wall of the second semiconductor portion. A first electrode is located in the second area and is insulated from the contact electrode. A second electrode is located on the outer side of the second semiconductor portion that is away from the first electrode in the first direction and the second direction, and the second electrode is insulated from the second semiconductor portion.

Description

Storage unit, memory and preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on July 6, 2023, with application number 202310828778.0 and invention name “Memory unit, memory and preparation method thereof”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of storage technology, and in particular to a storage unit, a memory and a preparation method thereof. Background Art

[0004] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of a number of memory cells arranged in an array. The memory cell may adopt a 1T1C architecture, for example, comprising a transistor and a capacitor.

[0005] Currently, with the increasing demand for memory capacity, memory cells are being arranged in three dimensions. However, the scalability issues and complex manufacturing processes of 1T1C architecture memory cells can easily degrade the electrical performance of memory cells when the size is further reduced, making it difficult to further reduce the size of memory cells while maintaining their electrical performance.

[0006] Summary of the Invention

[0007] According to some embodiments, the present disclosure provides a storage unit, a memory, and a method for manufacturing the same.

[0008] According to some embodiments, a memory cell includes: a semiconductor layer, a first gate, two second gates, a contact electrode, a first dielectric layer, a first electrode, a second dielectric layer, and a second electrode. The semiconductor layer is in a closed ring shape; the region within the ring includes a first region and a second region that are insulated and isolated in a first direction. The semiconductor layer includes: a first semiconductor portion surrounding a portion of the first region, and a second semiconductor portion surrounding a portion of the second region. The first gate is located within the first region. The two second gates are located on opposite sides of the first semiconductor portion, facing away from the first gate and in a second direction; the second direction intersects the first direction. The contact electrode conformally covers the inner sidewalls of the second semiconductor portion. The first electrode is located within the second region. The first dielectric layer wraps around each sidewall of the first electrode and conformally covers the inner sidewalls of the contact electrode. The second electrode is located on the outer side of the second semiconductor portion, facing away from the first electrode in the first and second directions. The second dielectric layer is located between the second semiconductor portion and the second electrode and conformally covers a portion of the outer sidewalls of the second semiconductor portion. The second electrode conformally covers the outer sidewalls of the second dielectric layer.

[0009] According to some embodiments, the second gate includes a first sub-gate and a second sub-gate stacked in the second direction away from the first semiconductor portion and made of different materials.

[0010] According to some embodiments, the first sub-gate is a polysilicon gate, and the second sub-gate and the first gate are metal gates.

[0011] According to some embodiments, the second electrode includes: a first sub-electrode and two second sub-electrodes. The first sub-electrode conformally covers an outer sidewall of the second dielectric layer. The two second sub-electrodes respectively cover outer sidewalls of the first sub-electrode that face away from the second dielectric layer and are opposite in the second direction.

[0012] According to some embodiments, the first sub-electrode is a polysilicon electrode, the second sub-electrode is a metal electrode, and the first electrode and the second sub-electrode are electrically connected.

[0013] According to some embodiments, the memory cell further includes: a first isolation structure and two second isolation structures. The first isolation structure is located between the first region and the second region. The two second isolation structures are respectively located between the corresponding second gate and the second electrode. The first isolation structure and the second isolation structure are staggered in the first direction.

[0014] According to some embodiments, a memory includes: at least one memory cell as described in any of the above embodiments, at least one bit line, and at least one word line. The bit line extends along a second direction and is electrically connected to an outer sidewall of a first semiconductor portion of the memory cell that faces away from the first gate and extends along the second direction. The word line is electrically connected to the first gate and two second gates of the memory cell.

[0015] According to some embodiments, there are a plurality of memory cells, and the memory cells are arranged in a row along a third direction, the third direction intersecting the first direction and the second direction in pairs, wherein the memory cells in a row share the same word line.

[0016] According to some embodiments, a method for preparing a memory includes the following steps.

[0017] A stacked structure is formed, wherein the stacked structure includes a plurality of first sacrificial layers and a plurality of second sacrificial layers that are alternately stacked.

[0018] The stack structure is etched along a stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole.

[0019] A semiconductor layer is formed on the inner sidewall of the second sacrificial layer within the first receiving hole. The semiconductor layer is in a closed ring shape, and the region within the ring includes a first region and a second region insulated and isolated from each other in a first direction. The semiconductor layer includes a first semiconductor portion surrounding a portion of the first region, and a second semiconductor portion surrounding a portion of the second region.

[0020] A first gate is formed in the first region.

[0021] Second gates are formed on two sides of the first semiconductor portion that are away from the first gate and opposite to each other in a second direction. The second direction intersects the first direction.

[0022] A contact electrode is formed in the second region to conformally cover the inner sidewall of the second semiconductor portion.

[0023] A first dielectric layer in a closed ring shape is formed in the second region to conformally cover the inner sidewall of the contact electrode.

[0024] A first electrode is formed in the inner ring area of ​​the first dielectric layer.

[0025] A second dielectric layer is formed on an outer sidewall of the second semiconductor portion away from the first electrode along the first direction and the second direction.

[0026] A second electrode is formed on an outer sidewall of the second dielectric layer away from the second semiconductor portion.

[0027] According to some embodiments, the second gate and the second electrode are formed simultaneously.

[0028] According to some embodiments, the second gate includes: a first sub-gate and a second sub-gate stacked in a second direction away from the first semiconductor portion and made of different materials. The second electrode includes: a first sub-electrode conformally covering an outer sidewall of the second semiconductor portion, and a second sub-electrode respectively covering outer sidewalls of the first sub-electrode facing away from the second semiconductor portion and opposite in the second direction.

[0029] The etching of the stacked structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form the first accommodating hole includes: etching the stacked structure to form two first accommodating areas extending along the first direction and spaced apart in the second direction; forming a third sacrificial layer in the first accommodating area; etching the stacked structure between the two first accommodating areas to form the first accommodating hole.

[0030] The method for preparing the memory further includes: etching the stack structure to form a first isolation trench, so as to separate the stack structure into a first section located on a side of the first semiconductor portion away from the first gate and a second section located on a side of the second semiconductor portion away from the first electrode through the first isolation trench.

[0031] Correspondingly, the second gates are formed on both sides of the first semiconductor portion that are away from the first gate and opposite to each other in the second direction, including: removing at least a portion of the third sacrificial layer near the first semiconductor portion in the first sub-portion to form a second accommodating hole, while making the second sacrificial layer retained in the first sub-portion between the first semiconductor portion and the second accommodating hole constitute a first sub-gate; forming a second sub-gate and a word line connected to the second sub-gate in the second accommodating hole.

[0032] The second electrode is formed on the outer wall of the second dielectric layer away from the second semiconductor part, including: removing at least a portion of the third sacrificial layer in the second section close to the second semiconductor part along the second direction to form a third accommodating hole, and at the same time making the second sacrificial layer in the second section conformally covering the outer wall of the second semiconductor part constitute a first sub-electrode; forming a second sub-electrode in the third accommodating hole.

[0033] According to some embodiments, the method for preparing the memory further includes the following steps.

[0034] While etching the stack structure to form the first isolation trench, a second isolation trench is formed to separate a third section located on the side of the first section away from the second section in the stack structure through the second isolation trench; the second sacrificial layer in the third section is connected to the outer side wall of the first semiconductor section away from the first gate and extending along the second direction.

[0035] The second sacrificial layer in the third section is removed to form a bit line accommodating groove.

[0036] A bit line is formed in the bit line receiving groove.

[0037] According to some embodiments, forming a semiconductor layer on an inner sidewall of a second sacrificial layer in a first receiving hole includes the following steps.

[0038] A dielectric material layer is formed to conformally cover the wall of the first receiving hole.

[0039] A fourth sacrificial layer is formed to cover the inner sidewall of the dielectric material layer and fill the first receiving hole.

[0040] A portion of the fourth sacrificial layer and a portion of the dielectric material layer close to the first end of the first accommodating hole in the first direction are removed to expose a portion of the hole wall of the first accommodating hole.

[0041] The remaining fourth sacrificial layer is removed.

[0042] A semiconductor material layer is formed to conformally cover the inner sidewall of the remaining dielectric material layer and the exposed hole wall of the first receiving hole.

[0043] The outer sidewall of the first sacrificial layer extending along the second direction is etched until the semiconductor material layer is exposed.

[0044] The semiconductor material layer is etched based on the removal area of ​​the first sacrificial layer extending along the second direction to remove the semiconductor material layer extending along the second direction between adjacent second sacrificial layers to form an initial semiconductor layer.

[0045] The outer sidewall of the first sacrificial layer extending along the first direction is etched until the initial semiconductor layer is exposed.

[0046] The initial semiconductor layer is etched based on the removal area of ​​the first sacrificial layer extending along the first direction to remove the initial semiconductor layer extending along the first direction between adjacent second sacrificial layers, forming semiconductor layers respectively located on the inner sidewalls of each second sacrificial layer.

[0047] According to some embodiments, before etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed, the method for manufacturing the memory further includes the following steps.

[0048] A fifth sacrificial layer is formed to cover the inner sidewall of the semiconductor material layer and fill the first receiving hole.

[0049] A first portion of the fifth sacrificial layer close to the first end of the first receiving hole is removed to expose the first region, so as to form a first gate in the first region.

[0050] After forming the first gate, a second portion of the fifth sacrificial layer near the second end of the first receiving hole in the first direction is removed to expose the second region. The first end and the second end are two opposite ends of the fifth sacrificial layer in the first direction.

[0051] A contact electrode material layer is formed in the second region to conformally cover the inner sidewall of the semiconductor material layer and the remaining sidewall of the fifth sacrificial layer, and a sixth sacrificial layer is formed to cover the inner sidewall of the contact electrode material layer and fill the second region.

[0052] The remaining fifth sacrificial layer is removed.

[0053] The contact electrode material layer is etched based on the removed area of ​​the fifth sacrificial layer, so that the contact electrode material layer conformally covering the inner sidewall of the second semiconductor portion forms a contact electrode.

[0054] A first isolation structure is formed in the removed area of ​​the fifth sacrificial layer and the contact electrode material layer.

[0055] According to some embodiments, forming a first dielectric layer in a closed ring shape in the second region that conformally covers the inner sidewall of the contact electrode and forming a first electrode in the region inside the ring of the first dielectric layer includes the following steps.

[0056] The sixth sacrificial layer is removed.

[0057] A first dielectric layer is formed conformally covering the inner sidewall of the contact electrode and the first isolation structure close to the sidewall of the contact electrode.

[0058] A first electrode is formed to cover the inner sidewall of the first dielectric layer and fill the sixth sacrificial layer removed area.

[0059] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0061] FIG1 is a schematic diagram of a three-dimensional structure of a storage unit provided in some embodiments;

[0062] FIG2 is a schematic top view of a storage unit provided in some embodiments;

[0063] FIG3 is a schematic diagram of the structure of a memory provided in some embodiments;

[0064] FIG4 is a schematic flow chart of a method for preparing a memory provided in some embodiments;

[0065] FIG5 is a schematic structural diagram of a structure obtained after forming a stacked structure provided in some embodiments;

[0066] FIG6 is a schematic structural diagram of a structure obtained after forming a first accommodating area, provided in some embodiments;

[0067] FIG7 is a schematic structural diagram of a structure obtained after forming a third sacrificial layer, provided in some embodiments;

[0068] FIG8 is a schematic structural diagram of a structure obtained after forming a first receiving hole provided in some embodiments;

[0069] FIG9 is a schematic structural diagram of a structure obtained after forming a first dielectric material layer, provided in some embodiments;

[0070] FIG10 is a schematic structural diagram of a structure obtained after forming a fourth sacrificial layer, provided in some embodiments;

[0071] FIG11 is a schematic structural diagram of a structure obtained after a portion of the fourth sacrificial layer is removed, provided in some embodiments;

[0072] FIG12 is a schematic structural diagram of a structure obtained after forming a semiconductor material layer, provided in some embodiments;

[0073] FIG13 is a schematic structural diagram of a structure obtained after forming a fifth sacrificial layer, provided in some embodiments;

[0074] FIG14 is a schematic structural diagram of a structure obtained after forming a first region, provided in some embodiments;

[0075] FIG15 is a schematic structural diagram of a structure obtained after forming a first gate dielectric layer, provided in some embodiments;

[0076] FIG16 is a schematic structural diagram of a structure obtained after forming a first gate provided in some embodiments;

[0077] FIG17 is a schematic structural diagram of a structure obtained after forming a second region provided in some embodiments;

[0078] FIG18 is a schematic structural diagram of a structure obtained after forming a contact electrode material layer provided in some embodiments;

[0079] FIG19 is a schematic structural diagram of a structure obtained after forming a sixth sacrificial layer, provided in some embodiments;

[0080] FIG20 is a schematic structural diagram of a structure obtained after removing the remaining fifth sacrificial layer provided in some embodiments;

[0081] FIG21 is a schematic structural diagram of a structure obtained after forming a first isolation structure, provided in some embodiments;

[0082] FIG22 is a schematic structural diagram of a structure obtained after etching the outer sidewall of the first sacrificial layer extending along the second direction, provided in some embodiments;

[0083] FIG23 is a schematic structural diagram of a structure obtained after forming an initial semiconductor layer, provided in some embodiments;

[0084] FIG24 is a schematic structural diagram of a structure obtained after backfilling the etched regions of the first sacrificial layer and the semiconductor material layer with insulating material, provided in some embodiments;

[0085] FIG25 is a schematic structural diagram of a structure obtained after removing the third sacrificial layer, provided in some embodiments;

[0086] FIG26 is a schematic structural diagram of a structure obtained after etching the outer sidewall of the first sacrificial layer extending along the first direction, provided in some embodiments;

[0087] FIG27 is a schematic diagram of a structure obtained after forming a semiconductor layer and a contact electrode, provided in some embodiments;

[0088] FIG28 is a schematic structural diagram of a structure obtained after re-forming a third sacrificial layer, provided in some embodiments;

[0089] FIG29 is a schematic structural diagram of a structure obtained after forming a first isolation trench and a second isolation trench, provided in some embodiments;

[0090] FIG30 is a schematic structural diagram of a structure obtained after forming a second isolation structure and a third isolation structure, provided in some embodiments;

[0091] FIG31 is a schematic structural diagram of a structure obtained after forming a second accommodating hole and a third accommodating hole provided in some embodiments;

[0092] FIG32 is a schematic structural diagram of a structure obtained after forming a second sub-gate, a second word line, and a second sub-electrode, provided in some embodiments;

[0093] FIG33 is a schematic structural diagram of a structure obtained after removing the sixth sacrificial layer, provided in some embodiments;

[0094] FIG34 is a schematic structural diagram of a structure obtained after forming a first dielectric layer and a first electrode, provided in some embodiments;

[0095] FIG35 is a schematic structural diagram of a structure obtained after forming a bit line accommodating groove provided in some embodiments;

[0096] FIG36 is a schematic structural diagram of a structure obtained after forming a bit line provided in some embodiments. DETAILED DESCRIPTION

[0097] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0098] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0099] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "electrically connected to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0100] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0101] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0102] In the current DRAM manufacturing process, the memory cell 6F is mostly used. 2A manufacturing method for arranged and buried word lines. Because further reducing the size of memory cells becomes very difficult with this method, as the demand for memory storage capacity continues to increase, memory cells have begun to be arranged in three dimensions. However, due to the scalability issues of memory cells in DRAM and the complexity of their process, further reducing the size of memory cells can easily degrade their electrical performance, making it difficult to further reduce the size of memory cells while ensuring their electrical performance.

[0103] Based on this, the embodiments of the present disclosure provide a storage unit and a memory, which are beneficial to reducing the planar occupied area of ​​the storage unit to improve the storage density and storage capacity of the memory, and are also beneficial to ensuring that the storage unit has better electrical performance and reliability to improve the electrical performance and reliability of the memory.

[0104] 1 and 2 , an embodiment of the present disclosure provides a memory cell that can be used in a memory, particularly a DRAM. The memory cell adopts a 1T1C architecture, that is, includes a transistor 1 and a capacitor 2 .

[0105] By way of example, the memory cell includes: a semiconductor layer 11, a first gate 12, two second gates 13, a contact electrode 21, a first dielectric layer 22, a first electrode 23, a second dielectric layer 24, and a second electrode 25. Specifically, the transistor 1 includes: a semiconductor layer 11, a first gate 12, and two second gates 13. The capacitor 2 includes: a contact electrode 21, a first dielectric layer 22, a first electrode 23, a second dielectric layer 24, and a second electrode 25.

[0106] For example, as shown in Figures 1 and 2, the semiconductor layer 11 is in the form of a closed ring, including but not limited to a rectangular ring structure or a square ring structure. The region within the ring of the semiconductor layer 11 includes a first region R1 and a second region R2 that are insulated and isolated in a first direction (e.g., the X direction). The semiconductor layer 11 includes a first semiconductor portion 111 surrounding a portion of the boundary of the first region R1, and a second semiconductor portion 112 surrounding a portion of the boundary of the second region R2.

[0107] In some examples, the semiconductor layer 11 is a rectangular ring structure, with a first direction (e.g., the X direction) being the length direction of the rectangular ring structure, and a second direction (e.g., the Y direction) being the width direction of the rectangular ring structure. The first region R1 and the second region R2 may be arranged side by side in the first direction (e.g., the X direction). The memory cell further includes a first isolation structure 31 located between the first region R1 and the second region R2 to insulate the first region R1 from the second region R2. Thus, the dividing line between the first semiconductor portion 111 and the second semiconductor portion 112 in the semiconductor layer 11 may be located within the region corresponding to the sidewall of the first isolation structure 31.

[0108] It is understood that the semiconductor layer 11 is in a closed ring shape, with the first semiconductor portion 111 and the second semiconductor portion 112 being an integral structure. In the disclosed embodiment, the portions of the semiconductor layer 11 located in different regions are divided into the first semiconductor portion 111 and the second semiconductor portion 112 merely to clearly describe the relative positional relationship between the semiconductor layer 11 and other structures; that is, there is no physical structural boundary between the first semiconductor portion 111 and the second semiconductor portion 112.

[0109] For example, as shown in Figures 1 and 2, the first gate 12 is located in the first region R1. The two second gates 13 are located on opposite sides of the first semiconductor portion 111, facing away from the first gate 12 and in a second direction (e.g., direction Y). The second direction intersects the first direction, e.g., is orthogonal.

[0110] In some examples, the second gate 13 includes a first sub-gate 131 and a second sub-gate 132 that are stacked in a second direction (eg, the Y direction) away from the first semiconductor portion 111 and made of different materials.

[0111] For example, the first sub-gate 131 is a polysilicon gate, and the second sub-gate 132 and the first gate 12 are metal gates.

[0112] For example, the metal gate includes, but is not limited to, a single structure of tungsten or copper having excellent conductivity, and may also include a stacked structure of metal and metal, or metal and metal compound. For example, the metal gate includes a stacked structure of titanium nitride and tungsten.

[0113] In some examples, the memory cell further includes a first gate dielectric layer 14 and a second gate dielectric layer 15. The first gate dielectric layer 14 is located between the first gate 12 and the first semiconductor portion 111 of the semiconductor layer 11. The first gate dielectric layer 14 may surround and cover the entire sidewall of the first gate 12, and cover the inner sidewall of the first semiconductor portion 111 exposed to the first region R1 and the sidewall of the first isolation structure 31 exposed to the first region R1. The second gate dielectric layer 15 is located between the second gate 13 and the sidewall of the first semiconductor portion 111 facing away from the first gate 12 in the second direction (e.g., the Y direction).

[0114] For example, the second gate dielectric layer 15 is disposed parallel to the second gate 13, and the second gate dielectric layer 15 and the second gate 13 may have the same length in a first direction (e.g., the X direction). For further example, the orthographic projection of the second gate dielectric layer 15 along the second direction (e.g., the Y direction) substantially coincides with the orthographic projection of the first sub-gate 131 in the second gate 13 in the second direction (e.g., the Y direction).

[0115] For example, the materials of the first gate dielectric layer 14 and the second gate dielectric layer 15 may be the same or different.

[0116] In some examples, the material of the first gate dielectric layer 14 and / or the second gate dielectric layer 15 includes, but is not limited to, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-K dielectric material, ferroelectric material, antiferroelectric material, or a combination thereof. K represents a dielectric constant, and the dielectric constant of the high-K dielectric material is, for example, greater than or equal to 3.9, and may be, for example, 20.

[0117] In some examples, the high-K dielectric material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0118] For example, the material of the first gate dielectric layer 14 and / or the second gate dielectric layer 15 may be silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), zinc oxide (ZnO), zirconium oxide (ZrO 2 ) or hafnium oxide (HfO 2 ).

[0119] For example, referring again to Figures 1 and 2 , the contact electrode 21 conformally covers the inner sidewalls of the second semiconductor portion 112. The first electrode 23 is located within the second region R2. The first dielectric layer 22 covers the sidewalls of the first electrode 23 and conformally covers the inner sidewalls of the contact electrode 21. The second electrode 25 is located on the outer side of the second semiconductor portion 112, away from the first electrode 23 along a first direction (e.g., the X direction) and a second direction (e.g., the Y direction). The second dielectric layer 24 is located between the second semiconductor portion 112 and the second electrode 25, and conformally covers a portion of the outer sidewalls of the second semiconductor portion 112. The second electrode 25 conformally covers the outer sidewalls of the second dielectric layer 24.

[0120] Here, the contact electrode 21 conformally covers the inner sidewalls of the second semiconductor portion 112 and can be directly electrically connected to the semiconductor layer 11 of the transistor 1. Furthermore, the contact electrode 21 is a conformal thin film and can have the same shape as the inner sidewalls of the second semiconductor portion 112. In the example where the first isolation structure 31 is provided between the first region R1 and the second region R2, the end surface of the contact electrode 21 facing the first isolation structure 31 contacts the sidewalls of the first isolation structure 31. The first electrode 23 and the second electrode 25 are located on the inner and outer sides of the contact electrode 21, respectively, so as to oppose the contact electrode 21 and constitute the electrodes of the capacitor 2.

[0121] In the embodiment of the present disclosure, the semiconductor layer 11 of the transistor 1 is configured as a closed ring, and the area within the ring of the semiconductor layer 11 is divided into a first region R1 and a second region R2 that are insulated and isolated in a first direction (e.g., the X direction). In this way, a first gate 12 can be provided in the first region R1, and a second gate 13 can be provided on both sides of the first gate 12 along a second direction (e.g., the Y direction) outside the semiconductor layer 11, so as to increase the turn-on current of the transistor 1 and reduce the leakage current. Furthermore, the contact electrode 21 and the first electrode 23 of the capacitor 2 can be provided in the second region R2, and a second electrode 25 can be provided on the side of the contact electrode 21 facing away from the first electrode 23 outside the semiconductor layer 11, so as to increase the storage capacity of the capacitor 2. Therefore, the memory cell in the embodiment of the present disclosure adopts the above-mentioned structure, which not only helps to improve the space utilization of the memory cell to effectively reduce the planar area of ​​a single memory cell, but also increases the thickness of the semiconductor layer 11, so as to increase the turn-on current of the transistor 1 and reduce the leakage current, and helps to increase the storage capacity of the capacitor 2. This helps to improve the storage density and storage capacity of the memory, and ensures that the storage unit has better electrical performance and reliability, thereby improving the electrical performance and reliability of the memory.

[0122] In some embodiments, the semiconductor layer 11 includes, but is not limited to, an indium gallium zinc oxide film layer (i.e., an IGZO film layer). Based on the excellent leakage resistance, low cost, and simple manufacturing process of the IGZO film layer, the leakage resistance of the transistor 1 can be improved accordingly, thereby reducing the production cost of the memory cell and simplifying the manufacturing process of the memory cell to improve production efficiency.

[0123] It can be understood that the contact electrode 21 is in contact with the second semiconductor portion 112 in the semiconductor layer 11. In the example where the semiconductor layer 11 is an IGZO film layer, the second semiconductor portion 112 and the contact electrode 21 can also be equivalent to one electrode of the capacitor 2.

[0124] In some embodiments, the first electrode 23 and the second electrode 25 are electrically connected.

[0125] In some embodiments, the second electrode 25 includes a first sub-electrode 251 and two second sub-electrodes 252. The first sub-electrode 251 conformally covers the outer sidewalls of the second dielectric layer 24. The two second sub-electrodes 252 respectively cover the outer sidewalls of the first sub-electrode 251 facing away from the second dielectric layer 24 and opposite to each other in the second direction (e.g., the Y direction).

[0126] In some embodiments, the first sub-electrode 251 is a polysilicon electrode, the second sub-electrode 252 is a metal electrode, and the first electrode 23 and the second sub-electrode 252 are electrically connected.

[0127] For example, the first electrode 23 and the second sub-electrode 252 are both formed of metal materials, which include but are not limited to single structures with excellent conductivity such as tungsten or copper, and can also include a stacked structure of metal and metal, or metal and metal compound.

[0128] For example, the first electrode 23 and the second sub-electrode 252 are a stacked structure of titanium nitride and tungsten.

[0129] Illustratively, the contact electrode 21 and the first electrode 23 are made of the same material, including but not limited to titanium nitride.

[0130] For example, the first dielectric layer 22 and the second dielectric layer 24 are made of the same or different materials, for example, silicon oxide, silicon nitride, high-K dielectric materials or a combination thereof.

[0131] In some embodiments, the memory cell further includes two second isolation structures 32 . The two second isolation structures 32 are respectively located between the corresponding second gate 13 and the second electrode 25 .

[0132] For example, the first isolation structure 31 and the second isolation structure 32 may be staggered in a first direction (eg, X direction).

[0133] For example, the first gate 12 and the second gate 13 are staggered in a first direction (e.g., the X direction). In the disclosed embodiment, the two second gates 13 are located on either side of the first gate 12 and are staggered relative to the first gate 12 in the first direction (e.g., the X direction), which helps to further increase the turn-on current of the transistor 1 and reduce the leakage current of the transistor 1, thereby further improving the electrical performance and reliability of the memory cell.

[0134] For example, the size of the second gate 13 in the first direction (e.g., X direction) is larger than the size of the first gate 12 in the first direction (e.g., X direction). In addition, the sidewall of the second gate 13 facing away from the second electrode 25 in the first direction (e.g., X direction) may be flush with the sidewall of the first gate 12 facing away from the first isolation structure 31 in the first direction (e.g., X direction).

[0135] In some embodiments, referring to FIG. 1 and FIG. 2 , an outer sidewall of the first semiconductor portion 111 , which is away from the first gate 12 and extends along the second direction (eg, the Y direction), is connected to the bit line BL.

[0136] For example, the dimension of the outer side wall of the first semiconductor portion 111 connected to the bit line BL in the second direction (for example, the Y direction) is a first dimension D1; the distance between the outer side walls of the first semiconductor portion 111 on opposite sides in the second direction (for example, the Y direction) is a second dimension D2; wherein, the first dimension D1 is greater than the second dimension D2.

[0137] In the embodiment of the present disclosure, the outer side wall of the first semiconductor portion 111 connected to the bit line BL has a larger dimension in the second direction (for example, the Y direction), which is beneficial to ensure that the first semiconductor portion 111 can have a larger contact area with the bit line BL along the extension direction of the bit line BL, so as to further reduce the contact resistance between the transistor 1 (for example, the first semiconductor portion 111) and the bit line BL.

[0138] In some embodiments, the bit line BL is formed of a conductive material, including but not limited to silicon-based materials, metal-based materials, or combinations thereof. For example, the bit line BL may be made of polysilicon, metal, metal nitride, metal silicide, or combinations thereof. For example, the bit line BL may be a single-layer structure of tungsten, titanium nitride, or polysilicon, or a stacked-layer structure of titanium nitride, tungsten, or the like.

[0139] For example, the first semiconductor portion 111 includes: a first portion 111A connected to the bit line BL, and a second portion 111B integrally connected to the first portion 111A and located between the first gate 12 and the second gate 13; wherein the size of the first portion 111A in a first direction (for example, the X direction) is larger than the size of the second portion 111B in a second direction (for example, the Y direction).

[0140] For example, the size of the second semiconductor portion 112 in the first direction (eg, X direction) and the size of the second semiconductor portion 112 in the second direction (eg, Y direction) are both the same as the size of the second portion 111B in the second direction (eg, Y direction).

[0141] In some embodiments, referring again to Figures 1 and 2 , the memory cell further includes a third isolation structure 33 and a fourth isolation structure 34. The third isolation structure 33 is located between the second gate 13 and the bit line BL. The fourth isolation structure 34 is located between the third isolation structure 33 and the second isolation structure 32 and covers the sidewall of the second gate 13 facing away from the first gate 12.

[0142] In the embodiment of the present disclosure, the first isolation structure 31 , the second isolation structure 32 , the third isolation structure 33 and the fourth isolation structure 34 adopt the aforementioned configuration, which is also beneficial for eliminating the GIDL effect of the transistor 1 , thereby improving the electrical performance and reliability of the transistor 1 .

[0143] It should be noted that the first isolation structure 31, the second isolation structure 32, the third isolation structure 33, and the fourth isolation structure 34 are formed of insulating materials and may be single-layer structures or stacked-layer structures. Furthermore, the insulating materials used for the first isolation structure 31, the second isolation structure 32, the third isolation structure 33, and the fourth isolation structure 34 may be the same or different. For example, the insulating materials may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0144] In some examples, the materials of the first isolation structure 31 , the second isolation structure 32 , and the third isolation structure 33 are all silicon nitride, and the material of the fourth isolation structure 34 is silicon oxide.

[0145] It should be supplemented that, in some embodiments, the first gate 12 and the two second gates 13 are connected to the same word line WL.

[0146] In some other embodiments, the first gate 12 and the two second gates 13 are respectively connected to different word lines WL to achieve independent control of the first gate 12 and the second gate 13 .

[0147] The present disclosure also provides a memory. Referring to FIG. 3 , the memory includes: at least one memory cell as described in any of the above embodiments, at least one bit line BL, and at least one word line WL. The bit line BL extends along a second direction (e.g., the Y direction) and is electrically connected to the outer sidewalls of the first semiconductor portion 111 of the memory cell that face away from the first gate 12 and extend along the second direction (e.g., the Y direction). The word line WL is electrically connected to the first gate 12 and two second gates 13 of the memory cell.

[0148] Here, the word line WL is electrically connected to the first gate 12 and the two second gates 13 in a corresponding manner. This can be expressed as: one word line WL is electrically connected to the first gate 12 and the two second gates 13 of the same memory cell at the same time; or, the word line WL is electrically connected to the first gate 12 and the two second gates 13 in a one-to-one correspondence. That is, the embodiments of the present disclosure do not limit the corresponding relationship between the electrical connections between the word line WL and the first gate 12 and the second gate 13.

[0149] In some embodiments, there are multiple memory cells, and the memory cells are arranged in a row along a third direction (e.g., the Z direction). The third direction (e.g., the Z direction) intersects with the first direction (e.g., the X direction) and the second direction (e.g., the Y direction) in pairs, for example, they are orthogonal to each other. The memory cells in a row share the same word line WL.

[0150] In some embodiments, a plurality of memory cells are distributed in different layers in a third direction (e.g., Z direction). The third direction (e.g., Z direction) is perpendicular to the intersection plane of the first direction (e.g., X direction) and the second direction (e.g., Y direction). In which, a plurality of memory cells having the same orthographic projection position in the third direction (e.g., Z direction) and located in different layers are connected to a plurality of bit lines BL in different layers, and the orthographic projection positions of the plurality of bit lines BL in the third direction (e.g., Z direction) are the same. The memory further includes: a plurality of conductive pillars 41 arranged at intervals along the second direction (e.g., Y direction). Each conductive pillar 41 extends respectively along the third direction (e.g., Z direction) and is connected to the bit line BL of the target layer, and is insulated from the bit lines BL outside the target layer.

[0151] For example, the conductive pillar 41 penetrates each bit line BL above the target layer along a third direction (e.g., the Z direction), and the bottom surface of the conductive pillar 41 is in contact with the bit line BL of the target layer. The side wall of the conductive pillar 41 is covered with an insulating layer 42 to insulate the conductive pillar 41 from each bit line BL above the target layer.

[0152] In some embodiments, referring again to FIG. 3 , multiple memory cells are arranged in a row along a third direction (e.g., the Z direction). The second sub-electrodes 252 of a row of memory cells can be integral. Furthermore, the first electrode 23 of a single memory cell can be electrically connected to the second sub-electrode 252 in the same memory cell via a conductive line 43 .

[0153] Some embodiments of the present disclosure also provide a memory manufacturing method for manufacturing the memory described in some of the aforementioned embodiments. This manufacturing method also possesses the technical advantages of the aforementioned memories. Furthermore, the memory manufacturing method provided by the embodiments of the present disclosure reduces the difficulty of the process, is easy to implement, and also helps improve the production efficiency and yield of the memory.

[0154] Referring to FIG. 4 , the method for preparing the memory includes the following steps.

[0155] S10 , forming a stacked structure, where the stacked structure includes a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately stacked.

[0156] S20 , etching the stacked structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole.

[0157] S30: Form a semiconductor layer on the inner sidewall of the second sacrificial layer within the first receiving hole. The semiconductor layer is in a closed ring shape, and the region within the ring includes a first region and a second region insulated and isolated from each other in a first direction. The semiconductor layer includes a first semiconductor portion surrounding a portion of the first region, and a second semiconductor portion surrounding a portion of the second region.

[0158] S40 , forming a first gate in the first region.

[0159] S50 , forming second gates on two sides of the first semiconductor portion that are away from the first gate and opposite to each other in a second direction, where the second direction intersects the first direction.

[0160] S60 , forming a contact electrode in the second region to conformally cover the inner sidewall of the second semiconductor portion.

[0161] S70 , forming a first dielectric layer in the second region that conformally covers the inner sidewall of the contact electrode and is in a closed ring shape.

[0162] S80 , forming a first electrode in the inner ring region of the first dielectric layer.

[0163] S90 , forming a second dielectric layer on an outer sidewall of the second semiconductor portion away from the first electrode along the first direction and the second direction.

[0164] S100 , forming a second electrode on an outer sidewall of the second dielectric layer away from the second semiconductor portion.

[0165] It should be understood that, although the various steps in the flowchart of FIG4 are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in FIG4 may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0166] The following embodiments illustrate possible implementations of at least some of the steps shown in FIG. 4 , as well as other supplementary steps of the memory manufacturing method, but are not intended to be limiting. Furthermore, the step numbers preceding each step below do not limit the order in which the steps may be executed; that is, the steps may be executed in a different order to meet specific requirements.

[0167] In some embodiments, the second gate and the second electrode are formed simultaneously to simplify the manufacturing process.

[0168] In some embodiments, the second gate includes: a first sub-gate and a second sub-gate stacked in a second direction away from the first semiconductor portion and made of different materials. The second electrode includes: a first sub-electrode conformally covering an outer sidewall of the second semiconductor portion, and a second sub-electrode covering opposite outer sidewalls of the first sub-electrode facing away from the second semiconductor portion in the second direction.

[0169] Step S20 of etching the stacked structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole may include steps S201 to S203 .

[0170] S201 , etching the stack structure to form two first accommodating areas extending along a first direction and spaced apart in a second direction.

[0171] S202 , forming a third sacrificial layer in the first accommodating area.

[0172] S203 , etching the stacked structure between the two first accommodating areas to form a first accommodating hole.

[0173] Correspondingly, the method for preparing the memory further includes: step S310.

[0174] S310 , etching the stack structure to form a first isolation trench, so as to separate the stack structure into a first subsection located on a side of the first semiconductor portion away from the first gate and a second subsection located on a side of the second semiconductor portion away from the first electrode through the first isolation trench.

[0175] Accordingly, step S50 of forming the second gates on two sides of the first semiconductor portion that are away from the first gate and opposite to each other in the second direction may include steps S501 and S502 .

[0176] S501 , removing at least a portion of the third sacrificial layer in the first sub-section to form a second receiving hole, while making the second sacrificial layer remaining between the first semiconductor portion and the second receiving hole in the first sub-section constitute a first sub-gate.

[0177] S502 , forming a second sub-gate and a word line connected to the second sub-gate in the second receiving hole.

[0178] Correspondingly, step S100 forms a second electrode on the outer wall of the second dielectric layer away from the second semiconductor part, including: removing at least part of the third sacrificial layer in the second section close to the second semiconductor part along the second direction to form a third accommodating hole, and at the same time making the second sacrificial layer in the second section conformally covering the outer wall of the second semiconductor part to form a first sub-electrode; forming a second sub-electrode in the third accommodating hole.

[0179] In some embodiments, the method for preparing the memory further includes the following steps.

[0180] S110, while etching the stack structure to form the first isolation trench, a second isolation trench is formed to separate a third section located on the side of the first section away from the second section in the stack structure through the second isolation trench; the second sacrificial layer in the third section is connected to the outer side wall of the first semiconductor section away from the first gate and extending along the second direction.

[0181] S120 , removing the second sacrificial layer in the third section to form a bit line accommodating groove.

[0182] S130 , forming a bit line in the bit line receiving groove.

[0183] In some embodiments, step S30 of forming a semiconductor layer on the inner sidewall of the second sacrificial layer in the first receiving hole may include steps S301 to S309 .

[0184] S301 , forming a dielectric material layer conformally covering the wall of the first receiving hole.

[0185] S302 , forming a fourth sacrificial layer covering the inner sidewall of the dielectric material layer and filling the first receiving hole.

[0186] S303 , removing a portion of the fourth sacrificial layer and a portion of the dielectric material layer near the first end of the first receiving hole in the first direction, exposing a portion of the hole wall of the first receiving hole.

[0187] S304 , removing the remaining fourth sacrificial layer.

[0188] S305 , forming a semiconductor material layer that conformally covers the inner sidewalls of the remaining dielectric material layer and the exposed hole walls of the first receiving hole.

[0189] S306 , etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed.

[0190] S307 , etching the semiconductor material layer based on the removal area of ​​the first sacrificial layer extending along the second direction to remove the semiconductor material layer extending along the second direction between adjacent second sacrificial layers to form an initial semiconductor layer.

[0191] S308 , etching the outer sidewall of the first sacrificial layer extending along the first direction until the initial semiconductor layer is exposed.

[0192] S309 , etching the initial semiconductor layer based on the removal area of ​​the first sacrificial layer extending along the first direction to remove the initial semiconductor layer extending along the first direction between adjacent second sacrificial layers, forming semiconductor layers respectively located on inner sidewalls of each second sacrificial layer.

[0193] In some embodiments, before performing step S306 to etch the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed, the memory manufacturing method further includes the following steps S401 to S402 and steps S601 to S605.

[0194] S401 , forming a fifth sacrificial layer covering the inner sidewall of the semiconductor material layer and filling the first receiving hole.

[0195] S402 , removing a first portion of the fifth sacrificial layer close to the first end of the first receiving hole to expose the first region, so as to form a first gate in the first region.

[0196] S601, after forming the first gate, remove a second portion of the fifth sacrificial layer near the second end of the first receiving hole in the first direction (e.g., the X direction) to expose a second region. The first end and the second end are opposite ends of the fifth sacrificial layer in the first direction.

[0197] S602 , forming a contact electrode material layer in the second region conformally covering the inner sidewalls of the semiconductor material layer and the remaining sidewalls of the fifth sacrificial layer, and a sixth sacrificial layer covering the inner sidewalls of the contact electrode material layer and filling the second region.

[0198] S603 , removing the remaining fifth sacrificial layer.

[0199] S604 , etching the contact electrode material layer based on the removed area of ​​the fifth sacrificial layer, so that the contact electrode material layer conformally covers the inner sidewall of the second semiconductor portion to form a contact electrode.

[0200] S605 , forming a first isolation structure in the removed area of ​​the fifth sacrificial layer and the contact electrode material layer.

[0201] In some embodiments, step S70 of forming a first dielectric layer in a closed ring shape in the second region conformally covering the inner sidewall of the contact electrode includes steps S701 and S702 , and step S80 of forming a first electrode in the region inside the ring of the first dielectric layer includes step S801 .

[0202] S701, removing the sixth sacrificial layer.

[0203] S702 , forming a first dielectric layer conformally covering the inner sidewalls of the contact electrode and the sidewalls of the first isolation structure close to the contact electrode.

[0204] S801 , forming a first electrode covering the inner sidewall of the first dielectric layer and filling the sixth sacrificial layer removed area.

[0205] In order to more clearly illustrate the method for preparing the memory in some of the above embodiments, please refer to Figures 5 to 36 below to understand some embodiments of the present disclosure.

[0206] In step S10 , referring to FIG. 5 , a stacked structure N is formed. The stacked structure N includes a plurality of first sacrificial layers L1 and a plurality of second sacrificial layers L2 that are alternately stacked.

[0207] Here, the number of stacked layers of the first sacrificial layer L1 and the second sacrificial layer L2 in the stacked structure N can be set to match the storage requirement of the memory unit in the third direction (eg, Z direction).

[0208] For example, the alternating stacking of the first sacrificial layer L1 and the second sacrificial layer L2 in the stack structure N may start with the first sacrificial layer L1 and end with the second sacrificial layer L2. However, this is not limited to the above. For example, the alternating stacking of the first sacrificial layer L1 and the second sacrificial layer L2 may start with the second sacrificial layer L2 and end with the first sacrificial layer L1; or the alternating stacking of the first sacrificial layer L1 and the second sacrificial layer L2 may start with the second sacrificial layer L1 and end with the first sacrificial layer L1, etc., all of which are permitted.

[0209] In some examples, the first sacrificial layer L1 includes, but is not limited to, a silicon oxide layer.

[0210] In some examples, the second sacrificial layer L2 includes, but is not limited to, a polysilicon layer.

[0211] As a further example, the second sacrificial layer L2 is a heavily doped polysilicon layer. The doping concentration of the doping element in the second sacrificial layer L2 can be 1E21 / cm 3 ~1E22 / cm 3 .

[0212] Here, the second sacrificial layer L2 is a heavily doped polysilicon layer, which is beneficial for increasing the threshold voltage of the transistor 1 after the first sub-gate 131 of the second gate 13 is subsequently formed based on the second sacrificial layer L2.

[0213] In some examples, taking the first sacrificial layer L1 as the starting layer and the second sacrificial layer L2 as the ending layer in the stacked structure N as an example, the stacked structure N may further include a protective layer Y1 covering the top second sacrificial layer L2. The protective layer Y1 may be, for example, a hard mask layer, including but not limited to a silicon nitride layer.

[0214] In step S20 , referring to FIG. 6 to FIG. 8 , the stack structure N is etched along the stacking direction (ie, the third direction, such as the Z direction) of the first sacrificial layer L1 and the second sacrificial layer L2 to form a first receiving hole H1 .

[0215] In some embodiments, step S20 may include steps S201 to S203.

[0216] In step S201 , referring to FIG. 6 , the stacked structure N is etched to form two first accommodation areas A1 extending along a first direction (eg, X direction) and spaced apart in a second direction (eg, Y direction).

[0217] Here, it is understood that only two first accommodating areas A1 are used as an example in Figure 6. When forming the first accommodating areas A1, multiple first accommodating areas A1 can be formed in the stacking structure N, spaced apart in the second direction (e.g., the Y direction), so that corresponding memory cells can be prepared based on two adjacent first accommodating areas A1 in the second direction (e.g., the Y direction) and the stacking structure N therebetween.

[0218] In step S202 , referring to FIG. 7 , a third sacrificial layer L3 is formed in the first accommodating area A1 .

[0219] Here, the third sacrificial layer L3 can be formed by a deposition process and a grinding process. The top surface of the third sacrificial layer L3 is flush with the top surface of the stacked structure N.

[0220] Illustratively, the third sacrificial layer L3 and the first sacrificial layer L1 are made of the same material.

[0221] Illustratively, the third sacrificial layer L3 includes but is not limited to a silicon oxide layer.

[0222] In step S203 , referring to FIG. 8 , the stack structure N between the two first accommodating areas A1 is etched to form a first accommodating hole H1 .

[0223] Here, the first receiving hole H1 penetrates the stacked structure N and can expose the surface of the substrate 01. The first receiving hole H1 is used to define the formation position of the semiconductor layer 11 in the aforementioned transistor 1. The shape and size of the first receiving hole H1 can be set according to requirements.

[0224] For example, the cross-sectional shape of the first accommodating hole H1 includes but is not limited to a rectangle. The cross-sectional shape of the first accommodating hole H1 refers to a cross-sectional shape of the first accommodating hole H1 parallel to the XY plane.

[0225] In step S30, referring to Figures 9 to 27 , a semiconductor layer 11 is formed on the inner sidewall of the second sacrificial layer L2 within the first receiving hole H1. The semiconductor layer 11 is in the form of a closed ring. The region within the ring includes a first region R1 and a second region R2 that are insulated and isolated from each other in a first direction (e.g., the X direction). The semiconductor layer 11 includes a first semiconductor portion 111 surrounding a portion of the first region R1 and a second semiconductor portion 112 surrounding a portion of the second region R2.

[0226] In some embodiments, step S30 may include steps S301 to S309. Furthermore, step S40, forming the first gate 12 in the first region R1, and step S60, forming the contact electrode 21 conformally covering the inner sidewall of the second semiconductor portion 112 in the second region R2, may be performed between steps S305 and S306. Step S40 may include steps S401 to S402. Step S60 may include steps S601 to S605.

[0227] In step S301 , referring to FIG. 9 , a dielectric material layer 220 is formed to conformally cover the wall of the first receiving hole H1 .

[0228] Illustratively, the dielectric material layer 220 includes, but is not limited to, a high-K dielectric material layer.

[0229] In some examples, the dielectric material layer 220 may be formed of materials such as aluminum oxide (Al 2 O 3 ), zinc oxide (ZnO), zirconium oxide (ZrO 2 ), or hafnium oxide (HfO 2 ).

[0230] For example, the dielectric material layer 220 may be formed by a deposition process, including but not limited to an atomic layer deposition process.

[0231] For example, the top surface of the dielectric material layer 220 is flush with the top surface of the stacked structure N, and the top surface of the dielectric material layer 220 may be polished by a grinding process.

[0232] In step S302 , referring to FIG. 10 , a fourth sacrificial layer L4 is formed to cover the inner sidewall of the dielectric material layer 220 and fill the first receiving hole H1 .

[0233] Illustratively, the material of the fourth sacrificial layer L4 is the same as that of the first sacrificial layer L1 .

[0234] Illustratively, the material of the fourth sacrificial layer L4 includes but is not limited to silicon oxide.

[0235] In step S303 , referring to FIG. 11 , a portion of the fourth sacrificial layer L4 and a portion of the dielectric material layer 220 near the first end (eg, left end) of the first receiving hole H1 in the first direction (eg, X direction) are removed to expose a portion of the hole wall of the first receiving hole H1 .

[0236] In step S304 , referring to FIG. 12 , the remaining fourth sacrificial layer L4 is removed.

[0237] In step S305 , please continue to refer to FIG. 12 , a semiconductor material layer 110 is formed to conformally cover the inner sidewalls of the remaining dielectric material layer 220 and the exposed hole wall of the first receiving hole H1 .

[0238] By way of example, the semiconductor material layer 110 includes, but is not limited to, an IGZO layer.

[0239] For example, the top surface of the semiconductor material layer 110 is flush with the top surface of the stacked structure N, and the top surface of the semiconductor material layer 110 may be polished by a grinding process.

[0240] In step S401 , referring to FIG. 13 , a fifth sacrificial layer L5 is formed to cover the inner sidewall of the semiconductor material layer 110 and fill the first receiving hole H1 .

[0241] Illustratively, the material of the fifth sacrificial layer L5 is the same as that of the first sacrificial layer L1 .

[0242] Illustratively, the material of the fifth sacrificial layer L5 includes but is not limited to silicon oxide.

[0243] For example, the top surface of the fifth sacrificial layer L5 is flush with the top surface of the stacked structure N, and the top surface of the fifth sacrificial layer L5 can be polished by a grinding process.

[0244] In step S402 , referring to FIG. 14 to FIG. 16 , a first portion of the fifth sacrificial layer L5 near the first end (eg, the left end) of the first receiving hole H1 is removed to expose the first region R1 , thereby forming a first gate 12 in the first region R1 .

[0245] It is understood that, as shown in FIG15 , after the first region R1 is exposed, a first gate dielectric layer 14 can be conformally formed on the inner sidewalls of the first region R1 before forming the first gate 12. Then, as shown in FIG16 , the first gate 12 is formed to cover the inner sidewalls of the first gate dielectric layer 14 and fill the first region.

[0246] For example, the first gate dielectric layer 14 is formed by a deposition process, which includes but is not limited to an atomic layer deposition process.

[0247] For example, the material of the first gate dielectric layer 14 includes, but is not limited to, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-K dielectric material, ferroelectric material, antiferroelectric material, or a combination thereof.

[0248] For example, the top surfaces of the first gate dielectric layer 14 and the first gate electrode 12 are flush with the top surface of the stacked structure N, and the top surfaces of the first gate dielectric layer 14 and the first gate electrode 12 can be polished by a grinding process.

[0249] In step S601, referring to FIG. 17 , after forming the first gate 12, a second portion of the fifth sacrificial layer L5 near a second end (e.g., the right end) of the first receiving hole H1 in the first direction (e.g., the X direction) is removed to expose the second region R2. The first end and the second end are opposite ends of the fifth sacrificial layer L5 in the first direction (e.g., the X direction).

[0250] In step S602, referring to FIG18 , a contact electrode material layer 210 is formed in the second region R2, conformally covering the inner sidewalls of the semiconductor material layer 110 and the sidewalls of the remaining fifth sacrificial layer L5. Referring to FIG19 , a sixth sacrificial layer L6 is formed, covering the inner sidewalls of the contact electrode material layer 210 and filling the second region R2.

[0251] Illustratively, the material of the sixth sacrificial layer L6 is the same as that of the first sacrificial layer L1 .

[0252] Illustratively, the material of the sixth sacrificial layer L6 includes, but is not limited to, silicon oxide.

[0253] For example, the top surfaces of the contact electrode material layer 210 and the sixth sacrificial layer L6 are flush with the top surface of the stacked structure N, and the top surfaces of the contact electrode material layer 210 and the sixth sacrificial layer L6 can be polished by a grinding process.

[0254] In step S603 , referring to FIG. 20 , the remaining fifth sacrificial layer L5 is removed.

[0255] In step S604 , referring to FIG. 20 , the contact electrode material layer 210 is etched based on the removed area of ​​the fifth sacrificial layer L5 , so that the contact electrode material layer 210 conformally covers the inner sidewall of the second semiconductor portion 112 to form the contact electrode 21 .

[0256] Here, it can be understood that in step S604, the semiconductor material layer 110 has not yet been etched and separated to form the semiconductor layer 11. Accordingly, in FIG20 , after etching the sidewalls of the contact electrode material layer 210 to expose the sixth sacrificial layer L6 based on the removal area of ​​the fifth sacrificial layer L5, the remaining contact electrode material layer forms the initial contact electrode 21A. The initial contact electrode 21A can be subsequently etched and separated to form the contact electrode 21.

[0257] Illustratively, the contact electrode material layer 210 includes, but is not limited to, a titanium nitride layer.

[0258] In step S605 , referring to FIG. 21 , a first isolation structure 31 is formed in the removed regions of the fifth sacrificial layer L5 and the contact electrode material layer 210 .

[0259] Illustratively, the material of the first isolation structure 31 is different from the material of the sixth sacrificial layer L6 .

[0260] By way of example, the material of the first isolation structure 31 includes, but is not limited to, silicon nitride.

[0261] In step S306 , referring to FIG. 22 , the outer sidewall of the first sacrificial layer L1 extending along the second direction (eg, the Y direction) is etched until the semiconductor material layer 110 is exposed.

[0262] In step S307, referring to FIG. 23 , the semiconductor material layer 110 is etched based on the removal area extending along the second direction (e.g., the Y direction) of the first sacrificial layer L1 to remove the semiconductor material layer 110 extending along the second direction (e.g., the Y direction) between adjacent second sacrificial layers L2 to form an initial semiconductor layer 11A.

[0263] Here, the first gate dielectric layer 14 extending along the second direction (e.g., the Y direction) between adjacent second sacrificial layers L2 can serve as an etch stop layer for the semiconductor material layer 110. Furthermore, it is understood that the initial contact electrode 21 extending along the second direction (e.g., the Y direction) between adjacent second sacrificial layers L2 can also be etched and removed.

[0264] It should be supplemented, referring to FIG. 24 , after the initial semiconductor layer 11A is formed, the removed regions of the first sacrificial layer L1 and the semiconductor material layer 110 (including the initial contact electrode 21A) may be filled with an insulating material 5 .

[0265] Illustratively, the insulating material 5 is different from the material of the first sacrificial layer L1 .

[0266] By way of example, the material of the insulating material 5 includes, but is not limited to, silicon nitride.

[0267] In step S308 , referring to FIG. 25 and FIG. 26 , the outer sidewall of the first sacrificial layer L1 extending along the first direction (eg, the X direction) is etched until the initial semiconductor layer 11A is exposed.

[0268] For example, as shown in FIG25 , the third sacrificial layer L3 is removed to expose the outer sidewalls of the first sacrificial layer L1 extending along the first direction (e.g., the X direction). As shown in FIG26 , the outer sidewalls of the first sacrificial layer L1 extending along the first direction (e.g., the X direction) are etched until the initial semiconductor layer 11A and the dielectric material layer 220 are exposed.

[0269] Here, after step S308 is performed, each first sacrificial layer L1 in the stacked structure N has been effectively removed without any residue.

[0270] In step S309, referring to FIG. 27 , the initial semiconductor layer 11A is etched based on the removal area extending along the first direction (e.g., the X direction) of the first sacrificial layer L1 to remove the initial semiconductor layer 11A extending along the first direction (e.g., the X direction) between adjacent second sacrificial layers L2, thereby forming semiconductor layers 11 respectively located on the inner side walls of each second sacrificial layer L2.

[0271] Here, the first gate dielectric layer 14 extending along the first direction (e.g., the X direction) between adjacent second sacrificial layers L2 can serve as an etch stop for the initial semiconductor layer 11A. Furthermore, the initial contact electrodes 21A extending along the first direction (e.g., the X direction) between adjacent second sacrificial layers L2 can be removed by etching to form contact electrodes 21 located on the inner sidewalls of the semiconductor layer 11 corresponding to each second sacrificial layer L2.

[0272] At this point, the semiconductor layer 11 of the memory cell in the embodiment of the present disclosure has been prepared. The relevant structure of the semiconductor layer 11 can be found in the relevant descriptions in some of the aforementioned embodiments and will not be described in detail here.

[0273] It should be added that, referring to FIG. 28 , after forming the semiconductor layer 11 and the contact electrode 21 , the sacrificial material can be backfilled in the removed areas of the original third sacrificial layer L3 , the first sacrificial layer L1 and the semiconductor material layer 110 (including the initial contact electrode 21A) to re-form the third sacrificial layer L3 ′.

[0274] In step S310, please refer to Figures 2 and 29 to understand that after the stack structure N is etched to form the third sacrificial layer L3', a first isolation groove G1 is formed to separate the stack structure N into a first section N1 located on the side of the first semiconductor portion 111 away from the first gate 12, and a second section N2 located on the side of the second semiconductor portion 112 away from the first electrode 23 through the first isolation groove G1.

[0275] In step S110, please continue to refer to Figure 29. While etching the stack structure N to form the first isolation groove G1, a second isolation groove G2 is formed to separate the third section N3 located on the side of the first section N1 away from the second section N2 in the stack structure N through the second isolation groove G2; the second sacrificial layer L2 in the third section N3 is connected to the outer side wall of the first semiconductor section 111 away from the first gate 12 and extending along the second direction (for example, the Y direction).

[0276] Accordingly, referring to FIG. 30 , a second isolation structure 32 is formed in the first isolation trench G1 , and a third isolation structure 33 is formed in the second isolation trench G2 .

[0277] For example, the material of the second isolation structure 32 and the third isolation structure 33 is the same as the material of the first isolation structure 31 , and is different from the material of the third sacrificial layer L3 ′.

[0278] By way of example, the materials of the second isolation structure 32 and the third isolation structure 33 include, but are not limited to, silicon nitride.

[0279] It should be noted that in the above-described embodiment of forming the second isolation structure 32 and the third isolation structure 33, the dielectric material layer 220 retained within the first sub-portion N1 can constitute the second gate dielectric layer 15, and the dielectric material layer 220 retained within the second sub-portion N2 can constitute the second dielectric layer 24. That is, step S90 can be simultaneously implemented to form the second dielectric layer 24 on the outer sidewalls of the second semiconductor portion 112 along the first direction (e.g., the X direction) and the second direction (e.g., the Y direction) away from the first electrode 23. Furthermore, the second sacrificial layer L2 retained within the first sub-portion N1 can substantially constitute the first sub-gate 131 of the second gate 13, and the second sacrificial layer L2 retained within the second sub-portion N2 can substantially constitute the first sub-electrode 251 of the second electrode 25.

[0280] Based on this, in step S50 , please refer to FIG. 2 and FIG. 31 and FIG. 32 to understand that the second gate 13 is formed on both sides of the first semiconductor portion 111 away from the first gate 12 and opposite to each other in the second direction (eg, the Y direction).

[0281] For example, step S50 may include steps S501 and S502.

[0282] In step S501, referring to FIG. 31 , at least a portion of the third sacrificial layer L3′ in the first sub-portion N1 near the first semiconductor portion 111 is removed to form a second receiving hole H2. Meanwhile, the second sacrificial layer L2 remaining in the first sub-portion N1 between the first semiconductor portion 111 and the second receiving hole H2 constitutes the first sub-gate 131.

[0283] Here, the second receiving hole H2 exposes the sidewall of the second gate dielectric layer 15 facing away from the first semiconductor portion 111 .

[0284] In step S502 , referring to FIG. 32 , a second sub-gate 132 and a word line WL connected to the second sub-gate 132 are formed in the second receiving hole H2 .

[0285] For example, the second sub-gate 132 and the word line WL are formed of a metal material, such as tungsten or copper, and are an integrated structure.

[0286] For example, the second sub-gate 132 and the word line WL may also be a stacked structure of metal and metal, or metal and metal compound. For example, the second sub-gate 132 and the word line WL adopt a stacked structure of titanium nitride and tungsten.

[0287] In step S100 , please continue to understand in conjunction with FIG. 2 , FIG. 31 , and FIG. 32 , a second electrode 25 is formed on the outer sidewall of the second dielectric layer 24 away from the second semiconductor portion 112 .

[0288] For example, as shown in FIG31 , at least a portion of the third sacrificial layer L3′ in the second subsection N2 along the second direction (e.g., the Y direction) near the second semiconductor portion 112 is removed to form a third receiving hole H3. Simultaneously, the second sacrificial layer L2 in the second subsection N2 that conformally covers the outer wall of the second semiconductor portion 112 forms the first sub-electrode 251. As shown in FIG32 , a second sub-electrode 252 is formed in the third receiving hole H3.

[0289] In some examples, the second sub-gate 132 and the second sub-electrode 252 may be simultaneously formed with the same material and the same process.

[0290] In addition, it can be understood that after forming the second accommodating hole H2 and the third accommodating hole H3 , the third sacrificial layer L3 ′ remaining outside the second sub-gate 132 and the second sub-electrode 252 can constitute the fourth isolation structure 34 .

[0291] In step S70 , please refer to FIG. 2 and FIG. 33 and FIG. 34 to understand that a first dielectric layer 22 conformally covering the inner sidewall of the contact electrode 21 and having a closed ring shape is formed in the second region R2 .

[0292] For example, step S70 may include steps S701 to S702.

[0293] In step S701 , referring to FIG. 33 , the sixth sacrificial layer L6 is removed to expose the inner sidewalls of the contact electrode 21 and the sidewalls of the first isolation structure 31 close to the contact electrode 21 .

[0294] In step S702 , referring to FIG. 34 , a first dielectric layer 22 is formed conformally covering the inner sidewalls of the contact electrode 21 and the sidewalls of the first isolation structure 31 close to the contact electrode 21 .

[0295] In step S80 (ie, S801), referring to Figure 34, a first electrode 23 is formed in the inner region of the first dielectric layer 22. The first electrode 23 covers the inner sidewall of the first dielectric layer 22 and fills the removed region of the sixth sacrificial layer L6.

[0296] In step S120 , referring to FIG. 35 , the second sacrificial layer L2 in the third sub-portion N3 is removed to form a bit line receiving groove G3 .

[0297] Here, after removing the second sacrificial layer L2 in the third sub-portion N3 , the bit line receiving groove G3 may expose the outer sidewall of the first semiconductor portion 111 in the semiconductor layer 11 extending along the second direction (eg, the Y direction).

[0298] In step S130 , referring to FIG36 , a bit line BL is formed in the bit line receiving groove G3 . The bit line BL may be in contact with an outer sidewall of the first semiconductor portion 111 in the semiconductor layer 11 extending along the second direction (eg, the Y direction).

[0299] For example, the materials forming the bit lines BL include, but are not limited to, silicon-based materials, metal-based materials, or combinations thereof. For example, the material of the bit lines BL includes polysilicon, metal, metal nitride, metal silicide, or combinations thereof. For example, the bit lines BL may have a single-layer structure of tungsten, titanium nitride, or polysilicon, or a stacked-layer structure of titanium nitride, tungsten, or the like.

[0300] For example, the bit line BL is formed by filling the bit line receiving groove G4 with a metal material, such as tungsten or copper.

[0301] It is worth noting that, in some embodiments, referring to FIG. 3 , multiple memory cells are arranged in a row along a third direction (e.g., the Z direction). Furthermore, the multiple memory cells are distributed in different layers in the third direction (e.g., the Z direction). Furthermore, the multiple memory cells located in different layers and having the same orthographic projection position in the third direction (e.g., the Z direction) are connected to multiple bit lines BL in different layers, and the orthographic projection positions of the multiple bit lines BL in the third direction (e.g., the Z direction) are the same.

[0302] Based on this, the method for preparing the memory may further include the following steps.

[0303] S140, forming a through hole that passes through each layer of bit lines BL above the target layer bit line BL, and conformally forming an insulating layer 42 covering the through hole wall in the through hole, and a conductive column 41 covering the insulating layer 42 and filling the through hole, so that the bottom surface of the conductive column 41 is in contact with the target layer bit line BL, and the side wall of the conductive column 41 is insulated from the each layer of bit lines BL above the target layer.

[0304] In some embodiments, referring again to FIG. 3 , multiple memory cells are arranged in a row along a third direction (e.g., the Z direction). The second sub-electrodes 252 of a row of memory cells can be integral. Furthermore, the first electrode 23 of a single memory cell can be electrically connected to the second sub-electrode 252 in the same memory cell via a conductive line 43 .

[0305] Based on this, the method for preparing the memory may further include the following steps.

[0306] S150 , forming a conductive line 43 to electrically connect the first electrode 23 and the second sub-electrode 252 in the same memory cell through the conductive line 43 .

[0307] For example, the conductive pillars 41 and the conductive wires 43 can be formed of metal materials, such as tungsten or copper.

[0308] In the description of this specification, the terms "removing" and "etching" can be implemented by using at least one etching process of wet etching and / or dry etching as needed.

[0309] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0310] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0311] The above embodiments merely illustrate several implementations of the present disclosure, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art would be able to make numerous variations and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A storage unit, comprising: A semiconductor layer (11) in a closed ring shape; the inner region of the semiconductor layer (11) comprises a first region (R1) and a second region (R2) which are insulated and isolated in a first direction; the semiconductor layer (11) comprises: a first semiconductor portion (111) surrounding a portion of the boundary of the first region (R1), and a second semiconductor portion (112) surrounding a portion of the boundary of the second region (R2); A first gate (12), located in the first region (R1); Two second gate electrodes (13), respectively located on two sides of the first semiconductor portion (111) away from the first gate electrode (12) and opposite to each other in a second direction; the second direction intersects with the first direction; A contact electrode (21) conformally covers the inner side wall of the second semiconductor portion (112); A first electrode (23), located in the second region (R2); A first dielectric layer (22) covers each side wall of the first electrode (23) and conformally covers the inner side wall of the contact electrode (21); a second electrode (25) located on an outer side of the second semiconductor portion (112) away from the first electrode (23) along the first direction and the second direction; The second dielectric layer (24) is located between the second semiconductor portion (112) and the second electrode (25), and conformally covers a portion of the outer wall of the second semiconductor portion (112); the second electrode (25) conformally covers the outer wall of the second dielectric layer (24).

2. The storage unit according to claim 1, wherein: The second gate (13) comprises a first sub-gate (131) and a second sub-gate (132) which are stacked in the second direction away from the first semiconductor portion (111) and are made of different materials.

3. The storage unit according to claim 2, wherein: The first sub-gate (131) is a polysilicon gate; The second sub-gate (132) and the first gate (12) are metal gates respectively.

4. The storage unit according to claim 1, wherein: The second electrode (25) comprises: A first sub-electrode (251) conformally covers an outer side wall of the second dielectric layer (24); The two second sub-electrodes (252) respectively cover outer side walls of the first sub-electrode (251) that are away from the second dielectric layer (24) and opposite to each other in the second direction.

5. The storage unit according to claim 4, wherein: The first sub-electrode (251) is a polysilicon electrode; The second sub-electrode (252) is a metal electrode; the first electrode (23) and the second sub-electrode (252) are electrically connected.

6. The storage unit according to any one of claims 1 to 5, wherein: Also includes: A first isolation structure (31), located between the first region (R1) and the second region (R2); Two second isolation structures (32), respectively located between the corresponding second gate (13) and the second electrode (25); Wherein, the first isolation structure (31) and the second isolation structure (32) are staggered in the first direction.

7. A memory comprising: At least one storage unit according to any one of claims 1 to 6; at least one bit line (BL); The bit line (BL) extends along the second direction and is electrically connected to an outer side wall of the first semiconductor portion (111) in the memory cell that is away from the first gate (12) and extends along the second direction; At least one word line (WL); the word line (WL) is electrically connected to the first gate (12) and two second gates (13) in the storage unit respectively.

8. The memory according to claim 7, wherein: There are multiple storage units, and the multiple storage units are arranged along a third direction; the third direction intersects with the first direction and the second direction in pairs; Wherein, a column of the memory cells shares the same word line (WL).

9. A method for preparing a memory, comprising: forming a stacked structure (N), wherein the stacked structure (N) comprises a plurality of first sacrificial layers (L1) and a plurality of second sacrificial layers (L2) alternately stacked; Etching the stack structure (N) along the stacking direction of the first sacrificial layer (L1) and the second sacrificial layer (L2) to form a first receiving hole (H1); A semiconductor layer (11) is formed on the inner side wall of the second sacrificial layer (L2) in the first receiving hole (H1); the semiconductor layer (11) is in a closed ring shape, and the inner region of the semiconductor layer (11) includes a first region (R1) and a second region (R2) insulated and isolated in a first direction; the semiconductor layer (11) includes: a first semiconductor portion (111) surrounding a portion of the boundary of the first region (R1), and a second semiconductor portion (112) surrounding a portion of the boundary of the second region (R2); forming a first gate (12) in the first region (R1); Second gates (13) are respectively formed on two sides of the first semiconductor portion (111) that are away from the first gate (12) and opposite to each other in a second direction; the second direction intersects with the first direction; forming a contact electrode (21) in the second region (R2) that conformally covers the inner side wall of the second semiconductor portion (112); forming a first dielectric layer (22) in the second region (R2) that conformally covers the inner side wall of the contact electrode (21) and is in the form of a closed ring; forming a first electrode (23) in the inner ring region of the first dielectric layer (22); forming a second dielectric layer (24) on an outer side wall of the second semiconductor portion (112) away from the first electrode (23) along the first direction and the second direction; A second electrode (25) is formed on an outer side wall of the second dielectric layer (24) away from the second semiconductor portion (112).

10. The method for preparing a memory according to claim 9, wherein: The second gate (13) and the second electrode (25) are formed simultaneously.

11. The method for preparing a memory according to claim 9, wherein: The second gate (13) comprises: a first sub-gate (131) and a second sub-gate (132) which are stacked in the second direction and away from the first semiconductor portion (111) and are made of different materials; the second electrode (25) comprises: a first sub-electrode (251) which conformally covers the outer side wall of the second semiconductor portion (112), and a second sub-electrode (252) which respectively covers the outer side walls of the first sub-electrode (251) which are away from the second semiconductor portion (112) and opposite to each other in the second direction; The step of etching the stack structure (N) along the stacking direction of the first sacrificial layer (L1) and the second sacrificial layer (L2) to form a first accommodating hole (H1) comprises: etching the stack structure (N) to form two first accommodating areas (A1) extending along the first direction and spaced apart in the second direction; forming a third sacrificial layer (L3) in the first accommodating area (A1); etching the stack structure (N) between the two first accommodating areas (A1) to form the first accommodating hole (H1); The method for preparing the memory further comprises: etching the stacked structure (N) to form a first isolation groove (G1), so as to separate the stacked structure (N) into a first sub-portion (N1) located on a side of the first semiconductor portion (111) away from the first gate (12), and a second sub-portion (N2) located on a side of the second semiconductor portion (112) away from the first electrode (23) through the first isolation groove (G1); The second gate (13) is formed on two sides of the first semiconductor portion (111) that are away from the first gate (12) and opposite to each other in the second direction, comprising: removing at least a portion of the third sacrificial layer (L3 or L3') near the first semiconductor portion (111) in the first sub-portion (N1) to form a second receiving hole (H2), and at the same time making the second sacrificial layer (L2) retained in the first sub-portion (N1) between the first semiconductor portion (111) and the second receiving hole (H2) constitute the first sub-gate (131); forming the second sub-gate (132) and a word line (WL) connected to the second sub-gate (132) in the second receiving hole (H2); The second electrode (25) is formed on the outer wall of the second dielectric layer (24) away from the second semiconductor part (112), comprising: removing at least a portion of the third sacrificial layer (L3 or L3') in the second sub-portion (N2) close to the second semiconductor part (112) along the second direction to form a third receiving hole (H3), and at the same time making the second sacrificial layer (L2) in the second sub-portion (N2) conformally covering the outer wall of the second semiconductor part (112) to form the first sub-electrode (251); and forming the second sub-electrode (252) in the third receiving hole (H3).

12. The method for preparing a memory according to claim 11, wherein: Also includes: While etching the stacked structure (N) to form the first isolation groove (G1), a second isolation groove (G2) is formed, so as to separate a third subsection (N3) located on a side of the first subsection (N1) away from the second subsection (N2) in the stacked structure (N) through the second isolation groove (G2); the second sacrificial layer (L2) in the third subsection (N3) is connected to an outer side wall of the first semiconductor portion (111) away from the first gate (12) and extending along the second direction; removing the second sacrificial layer (L2) in the third subsection (N3) to form a bit line accommodating groove (G3); A bit line (BL) is formed in the bit line receiving groove (G3).

13. The method for preparing a memory according to any one of claims 9 to 12, wherein: The step of forming a semiconductor layer (11) on the inner side wall of the second sacrificial layer (L2) in the first receiving hole (H1) comprises: forming a dielectric material layer (220) conformally covering the hole wall of the first receiving hole (H1); forming a fourth sacrificial layer (L4) covering the inner side wall of the dielectric material layer (220) and filling the first receiving hole (H1); removing a portion of the fourth sacrificial layer (L4) and a portion of the dielectric material layer (220) close to the first end of the first receiving hole (H1) in the first direction, exposing a portion of the hole wall of the first receiving hole (H1); removing the remaining fourth sacrificial layer (L4); forming a semiconductor material layer (110) that conformally covers the inner sidewall of the remaining dielectric material layer (220) and the exposed hole wall of the first receiving hole (H1); Etching the outer side wall of the first sacrificial layer (L1) extending along the second direction until the semiconductor material layer (110) is exposed; etching the semiconductor material layer (110) based on the removal area of ​​the first sacrificial layer (L1) extending along the second direction, so as to remove the semiconductor material layer (110) extending along the second direction between adjacent second sacrificial layers (L2), thereby forming an initial semiconductor layer (11A); Etching the outer side wall of the first sacrificial layer (L1) extending along the first direction until the initial semiconductor layer (11A) is exposed; The initial semiconductor layer (11A) is etched based on the removal area of ​​the first sacrificial layer (L1) extending along the first direction to remove the initial semiconductor layer (11A) extending along the first direction between adjacent second sacrificial layers (L2), thereby forming the semiconductor layers (11) respectively located on the inner side walls of each second sacrificial layer (L2).

14. The method for preparing a memory according to claim 13, wherein: Before the outer sidewall of the first sacrificial layer (L1) extending along the second direction is etched until the semiconductor material layer (110) is exposed, the method further comprises: forming a fifth sacrificial layer (L5) covering the inner side wall of the semiconductor material layer (110) and filling the first receiving hole (H1); removing a first portion of the fifth sacrificial layer (L5) close to the first end of the first receiving hole (H1) to expose the first region (R1) so as to form the first gate (12) in the first region (R1); After forming the first gate (12), removing a second portion of the fifth sacrificial layer (L5) near the second end of the first receiving hole (H1) in the first direction to expose the second region (R2); the first end and the second end are respectively two opposite ends of the fifth sacrificial layer (L5) in the first direction; forming a contact electrode material layer (210) in the second region (R2) that conformally covers the inner sidewall of the semiconductor material layer (110) and the remaining sidewall of the fifth sacrificial layer (L5), and a sixth sacrificial layer (L6) that covers the inner sidewall of the contact electrode material layer (210) and fills the second region (R2); removing the remaining fifth sacrificial layer (L5); Etching the contact electrode material layer (210) based on the removed area of ​​the fifth sacrificial layer (L5), so that the contact electrode material layer (210) conformally covering the inner side wall of the second semiconductor portion (112) constitutes the contact electrode (21); A first isolation structure (31) is formed in the removed regions of the fifth sacrificial layer (L5) and the contact electrode material layer (210).

15. The method for preparing a memory according to claim 14, wherein: The method comprises forming a first dielectric layer (22) in the second region (R2) conformally covering the inner side wall of the contact electrode (21) and in a closed ring shape, and forming a first electrode (23) in the inner region of the first dielectric layer (22), comprising: removing the sixth sacrificial layer (L6); forming the first dielectric layer (22) conformally covering the inner side wall of the contact electrode (21) and the side wall of the first isolation structure (31) close to the contact electrode (21); The first electrode (23) is formed to cover the inner sidewall of the first dielectric layer (22) and fill the removed area of ​​the sixth sacrificial layer (L6).

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