Sensor element and ranging system

Abstract

The present disclosure relates to a sensor element and a ranging system with which it is possible to achieve higher functionality while maintaining a pixel size. A sensor element according to the present disclosure comprises: a sensor substrate in which a SPAD is provided for each pixel; a CMOS substrate that is superposed on the sensor substrate and is provided with a transistor for reading a signal; a logic substrate which is superposed on the CMOS substrate and on which a logic circuit is provided; and a through electrode that penetrates the CMOS substrate and electrically connects an anode region of the sensor substrate and the CMOS substrate. The present disclosure can be applied to a CMOS image sensor, for example.

Description

Sensor element and ranging system

[0001] The present disclosure relates to a sensor element and a ranging system, and more particularly to a sensor element and a ranging system that enable further enhancement of functionality while maintaining pixel size.

[0002] Range image sensors that measure distances using the ToF (Time-of-Flight) method are known. These range image sensors employ pixel arrays in which pixels using SPADs (Single Photon Avalanche Diodes) are arranged in a matrix. When a voltage greater than the breakdown voltage is applied to a SPAD, avalanche amplification occurs when a single photon enters a high-electric field PN junction region. By detecting the instantaneous current flow, distances can be measured with high accuracy.

[0003] Conventionally, distance measurement systems using SPADs have adopted a back-illuminated sensor element in which light is irradiated from the back side of the semiconductor substrate, with a laminated structure in which a sensor substrate on which a SPAD is provided and a logic substrate on which a logic circuit is provided are bonded together.

[0004] Patent Document 1 proposes that in order to achieve miniaturization and high functionality in a sensor element with a stacked structure, some of the multiple transistors for outputting a signal according to the cathode voltage or anode voltage of the SPAD are provided in a well formed in the semiconductor substrate of the sensor substrate.

[0005] Japanese Patent Application Laid-Open No. 2022-148028

[0006] In recent years, there has been a demand for even more sophisticated logic circuits in stacked sensor elements. However, in a two-layer sensor element such as that disclosed in Patent Document 1, it has not been easy to add a static random access memory (SRAM) or other memory for calculations in the logic circuit while maintaining the pixel size.

[0007] The present disclosure has been made in view of such circumstances, and aims to enable further enhancement of functionality while maintaining pixel size.

[0008] The sensor element of the present disclosure is a sensor element including: a sensor substrate on which a SPAD (Single Photon Avalanche Diode) is provided for each pixel; a CMOS (Complementary Metal Oxide Semiconductor) substrate stacked on the sensor substrate and provided with a transistor for signal readout; a logic substrate stacked on the CMOS substrate and provided with a logic circuit; and a through electrode that penetrates the CMOS substrate and electrically connects an anode region of the sensor substrate to the CMOS substrate.

[0009] The distance measurement system disclosed herein includes an illumination device that emits illumination light and a sensor element that detects reflected light from the illumination light, and the sensor element includes a sensor substrate on which a SPAD (Single Photon Avalanche Diode) is provided for each pixel, a CMOS (Complementary Metal Oxide Semiconductor) substrate stacked on the sensor substrate and provided with a transistor for signal readout, a logic substrate stacked on the CMOS substrate and provided with a logic circuit, and a through electrode that penetrates the CMOS substrate and electrically connects the anode region of the sensor substrate to the CMOS substrate.

[0010] In the present disclosure, a sensor substrate on which a SPAD is provided for each pixel, a CMOS substrate stacked on the sensor substrate and provided with a transistor for reading out signals, a logic substrate stacked on the CMOS substrate and provided with a logic circuit, and a through electrode that penetrates the CMOS substrate and electrically connects the anode region of the sensor substrate to the CMOS substrate are provided.

[0011] FIG. 1 is a cross-sectional view showing a configuration example of a sensor element to which the technology according to the present disclosure is applied. FIG. 2 is a cross-sectional view showing a configuration example of a CMOS substrate. FIG. 3 is a plan view showing a configuration example of a CMOS substrate. FIG. 4 is a plan view showing a configuration example of a CMOS substrate according to a first embodiment. FIG. 5 is a plan view showing another configuration example of a CMOS substrate according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration example of a CMOS substrate according to a second embodiment. FIG. 7 is a plan view showing another configuration example of a CMOS substrate according to the second embodiment. FIG. 8 is a cross-sectional view showing a configuration example of a CMOS substrate according to a third embodiment. FIG. 9 is a plan view showing an example of a CMOS substrate according to the third embodiment. FIG. 10 is a block diagram showing a configuration example of a ranging system.

[0012] Modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described below in the following order.

[0013] 1. Prior art and problems thereof 2. Configuration example of a sensor element to which the technology according to the present disclosure is applied 3. First embodiment (Configuration in which source region / drain region is used as shield region) 4. Second embodiment (Configuration in which well region of substrate contact is used as shield region) 5. Third embodiment (Configuration in which air gap is used as shield region) 6. Configuration example of a distance measurement system

[0014] <1. Prior art and its problems> Conventionally, distance measurement systems using SPADs (Single Photon Avalanche Diodes) have adopted back-illuminated sensor elements in which a sensor substrate on which a SPAD is provided and a logic substrate on which a logic circuit is provided are bonded together, and light is irradiated from the back side of the semiconductor substrate.

[0015] Patent Document 1 (JP 2022-148028 A) proposes that in order to achieve miniaturization and high functionality in a sensor element with a stacked structure, some of the multiple transistors for outputting signals according to the cathode voltage or anode voltage of the SPAD are provided in a well formed in the semiconductor substrate of the sensor substrate.

[0016] In recent years, there has been a demand for even more sophisticated logic circuits in stacked sensor elements. However, in a two-layer sensor element such as that disclosed in Patent Document 1, it has not been easy to add a static random access memory (SRAM) or other memory for calculations in the logic circuit while maintaining the pixel size.

[0017] Therefore, in the technology disclosed herein, a CMOS (Complementary Metal Oxide Semiconductor) substrate on which transistors for reading signals are provided is stacked between a sensor substrate on which a SPAD is provided for each pixel and a logic substrate on which a logic circuit is provided, thereby ensuring the area for the logic circuit.

[0018] On the other hand, in such a three-layer sensor element, a high voltage of -20 to -25 V is applied to the anode electrode that penetrates the CMOS substrate, which raises concerns about the impact on the ON-OFF characteristics of the transistor provided on the CMOS substrate.

[0019] In contrast, International Publication No. 2020 / 262558 (referred to as Publicly Known Example 2) discloses an imaging device in which a shield electrode is provided between a through electrode that electrically connects a floating diffusion on a first substrate and a pixel circuit on a second substrate and each transistor that constitutes the pixel circuit. The shield electrode is intended to reduce the influence of a bias applied to the through wiring on each transistor that constitutes the pixel circuit.

[0020] However, in the prior art example 2, no consideration is given to reducing the pixel size, and there is a problem in terms of area efficiency.

[0021] Therefore, in the technology disclosed herein, in a CMOS substrate, existing components of the CMOS substrate are arranged as a shielding region between the transistor and the through electrode when viewed in a plane from the stacking direction, thereby achieving maintenance of the pixel size without providing a new component such as a shielding electrode.

[0022] 2. Configuration Example of Sensor Element to which Technology According to the Present Disclosure is Applied> The configuration of a sensor element to which technology according to the present disclosure is applied will be described with reference to FIGS. 1 to 3 .

[0023] FIG. 1 shows an example of a cross-sectional configuration of a pixel 10 included in a sensor element 1 to which the technology according to the present disclosure is applied.

[0024] The sensor element 1 is configured as, for example, a CMOS image sensor. As shown in Fig. 1 , the sensor element 1 has a three-layer structure including a sensor substrate 11 on which a SPAD 31 is provided for each pixel 10, a CMOS substrate 12 laminated on the sensor substrate 11 and provided with transistors for signal readout, and a logic substrate 13 laminated on the CMOS substrate 12 and provided with a logic circuit. The sensor substrate 11 is configured by laminating an on-chip lens layer 22 on the upper surface (rear surface) of a semiconductor substrate 21. The logic substrate 13 is configured by laminating a wiring layer 24 on the upper surface of a semiconductor substrate 23. A microlens 25 is provided for each pixel 10 in the on-chip lens layer 22.

[0025] Each pixel 10 is configured such that the well layer 32 of the semiconductor substrate 21 is electrically isolated from the well layers 32 of adjacent pixels 10 by a pixel isolation portion 33. Although not shown, a P-type semiconductor region for accumulating holes is provided in the pixel 10 so as to surround the side and top surfaces of the well layer 32. An anode region 34 having a higher P-type impurity concentration than the P-type semiconductor region is formed on the lower surface side of the semiconductor substrate 21 corresponding to the region where the P-type semiconductor region is formed.

[0026] In the pixel 10, a SPAD 31 is formed on the underside of the semiconductor substrate 21 by a PN junction region between an N-type multiplication region and a P-type multiplication region. The SPAD 31 is a photodiode in which a cathode potential drops due to a current that flows when electrons generated in response to light incident on the pixel 10 are avalanche-amplified. In the SPAD 31, a cathode region 35 with a high N-type impurity concentration, which has a higher impurity concentration than the N-type multiplication region, is formed in the N-type multiplication region that forms the PN junction.

[0027] The CMOS substrate 12 is provided with a transistor 50 and a transistor 60 for reading out a signal according to the cathode voltage of the SPAD 31. The transistors 50 and 60 are configured with transistors of different conduction types. One of the transistors 50 and 60 may be configured with a PMOS transistor, and the other of the transistors 50 and 60 may be configured with an NMOS transistor.

[0028] For example, when transistor 50 is a PMOS transistor, gate electrode 53 is provided between source region 51 and drain region 52, which are P-type regions provided for an N-well, with an insulating film such as an oxide film sandwiched between them. Similarly, when transistor 60 is an NMOS transistor, gate electrode 63 is provided between source region 61 and drain region 62, which are N-type regions provided for a P-well, with an insulating film such as an oxide film sandwiched between them.

[0029] The transistors 50 and 60 are assumed to be configured as transistors with a planar structure, but are not limited to this and may be configured as transistors with a trench structure.

[0030] The CMOS substrate 12 is provided with through electrodes 71 and 72 that penetrate the CMOS substrate 12 and electrically connect the sensor substrate 11 and the CMOS substrate 12 .

[0031] The through electrode 71 is formed as an anode electrode that connects the anode region 34 formed in the sensor substrate 11 and each transistor provided in the CMOS substrate 12 via a SPAD circuit (not shown) formed on the logic substrate 13. The through electrode 72 is formed as a cathode electrode that connects the cathode region 35 formed in the N-type multiplication region of the SPAD 31 and each transistor provided in the CMOS substrate 12 via a SPAD circuit (not shown) formed on the logic substrate 13.

[0032] As described above, by stacking the CMOS substrate 12, on which the transistors 50 and 60 for reading signals are provided, between the sensor substrate 11, on which the SPAD 31 is provided for each pixel 10, and the logic substrate 13, on which the logic circuit is provided, it is possible to ensure the area for the logic circuit. In other words, it is possible to add an SRAM or the like for calculations in the logic circuit while maintaining the pixel size, and it is possible to achieve further high functionality of the sensor element 1.

[0033] The detailed configuration of the CMOS substrate 12 will be described with reference to FIG.

[0034] 2 shows a cross section of a partial region where a transistor 50 is provided on the CMOS substrate 12. The cross-sectional structure shown in FIG. 2 is obtained by turning the cross-sectional structure shown in FIG. 1 upside down.

[0035] In the CMOS substrate 12, an element isolation region 81 is formed between the transistor 50 and the through electrode 71. The element isolation region 81 is formed, for example, as an STI (Shallow Trench Isolation) region with a depth of about 250 nm formed of an insulating film such as a silicon oxide film, or as a DTI (Deep Trench Isolation) region formed of a silicon oxide film or the like that penetrates from the silicon surface to the bottom surface of the CMOS substrate 12, but may also be formed by ion implantation.

[0036] Furthermore, an element isolation region 82 is formed between the transistor 50 and the transistor 60 (not shown) of different conductivity types. The element isolation region 82 is formed, for example, as a DTI region formed of a Si oxide film or the like that penetrates from the Si surface to the bottom surface of the CMOS substrate 12, but may also be formed by ion implantation.

[0037] A voltage with an absolute value of 20 V or more is applied to the through electrode 71 connected to the anode region 34. Specifically, a high voltage of −20 to −25 V is applied to the through electrode 71. Therefore, there is concern about the effect on the ON-OFF characteristics of each transistor provided on the CMOS substrate 12.

[0038] Therefore, as shown in FIG. 3, in the CMOS substrate 12, existing components of the CMOS substrate 12 are arranged as a shielding region 100 between the transistor 50 and the through electrode 71 in a plan view from the stacking direction.

[0039] The shield region 100 is arranged so as to intersect, in plan view from the stacking direction, all line segments connecting the vertices of the overlap region OL, where the active region in which the source region 51 / drain region 52 of the transistor 50 is formed and the gate electrode 53 overlap, with the center (center of gravity on the two-dimensional figure) of the through electrode 71. The two-dimensional shape of the overlap region OL, formed by the overlap of the active region of the transistor 50 and the gate electrode 53, is shown as a rectangle in the example of Figure 3, but in reality it has a shape other than a rectangle, such as a polygon.

[0040] As described above, by arranging the existing components of the CMOS substrate 12 as the shield region 100, it is possible to maintain high reliability of the transistor 50 provided on the CMOS substrate 12, that is, to reduce the effect on the transistor 50 of application of a high voltage to the through electrode 71. Furthermore, it is possible to maintain the pixel size without providing a new member such as the shield electrode of the known example 2.

[0041] A specific example of an existing component of the CMOS substrate 12 arranged as the shield region 100 will be described below.

[0042] 3. First Embodiment FIG. 4 is a plan view showing an example of the configuration of a CMOS substrate 12 according to a first embodiment to which the technology of the present disclosure is applied.

[0043] The cross-sectional structure of the CMOS substrate 12 of this embodiment is the same as that shown in FIG. 2, and therefore a description thereof will be omitted.

[0044] In the example of FIG. 4, in the CMOS substrate 12, the drain region 52 of the active region of the transistor 50 is arranged as a shield region 100 between the transistor 50 and the through electrode 71 in a plan view in the stacking direction.

[0045] The drain region 52 is arranged, in plan view from the stacking direction, so as to intersect with all line segments connecting the vertices of the overlap region where the active region of the transistor 50 and the gate electrode 53 overlap with the center of the through electrode 71. This allows the influence of the electric field propagating from the through electrode 71 to be absorbed by the drain region 52.

[0046] As described above, by arranging the active region of the transistor 50 between the transistor 50 and the through electrode 71, it is possible to maintain the pixel size while reducing the effect on the transistor 50 caused by the application of a high voltage to the through electrode 71.

[0047] In the example of Figure 4, the drain region 52 of the active region of the transistor 50 is arranged between the transistor 50 and the through electrode 71, but the source region 51 of the active region of the transistor 50 may also be arranged therebetween.

[0048] 4. That is, for example, the drain region 52 may be disposed so as to intersect with all line segments connecting the centers of the through electrodes 71 and the vertices of the overlapping region where the active region of the transistor 50 and the gate electrode 53 overlap in the planar view from the stacking direction, and any shape may be adopted depending on the positional relationship between the transistor 50 and the through electrodes 71.

[0049] For example, as shown in Figure 5A, if the through electrode 71 is not provided on the longitudinal extension of the active region of the transistor 50, the drain region 52 (or the source region 51) may be formed in an L-shape.

[0050] Also, as shown in Figure B, when two through electrodes 71a and 71b are provided, the drain region 52 (or the source region 51) may be formed in a U-shape depending on their arrangement.

[0051] In the example of Figure 5, the active region of the transistor 50 is also arranged between the transistor 50 and the through electrode 71, so it is possible to maintain the pixel size while reducing the impact on the transistor 50 caused by applying a high voltage to the through electrode 71.

[0052] 4. Second Embodiment FIG. 6 is a cross-sectional view showing an example of the configuration of a CMOS substrate 12 according to a second embodiment to which the technology of the present disclosure is applied, and FIG. 7 is a plan view thereof.

[0053] 6, in addition to the cross-sectional structure shown in Fig. 2, a substrate contact 121 and its well region 122 are formed. The well region 122 is an N-type or P-type diffusion layer for the substrate contact, and is fixed to a constant potential by the substrate contact 121.

[0054] In the example of FIG. 7, in the CMOS substrate 12, a well region 122 of a substrate contact 121 is disposed as a shield region 100 between the transistor 50 and the through electrode 71 in a plan view from the stacking direction.

[0055] The well region 122 of the substrate contact 121 is arranged, in plan view from the stacking direction, so as to intersect with all line segments connecting the vertices of the overlap region where the active region of the transistor 50 and the gate electrode 53 overlap with the center of the through electrode 71. This allows the well region 122 of the substrate contact 121 to absorb the effect of the electric field propagating from the through electrode 71.

[0056] As described above, by arranging the well region 122 of the substrate contact 121 between the transistor 50 and the through electrode 71, it is possible to maintain the pixel size while reducing the impact on the transistor 50 caused by the application of a high voltage to the through electrode 71.

[0057] 7. In other words, the well region 122 of the substrate contact 121 may have any shape in plan view as long as it is disposed so as to intersect with all the line segments connecting the center of the through electrode 71 and each of the vertices of the overlap region where the active region of the transistor 50 and the gate electrode 53 overlap in plan view from the stacking direction, depending on the positional relationship between the transistor 50 and the through electrode 71.

[0058] For example, as shown in FIG. 8, the well region 122 of the substrate contact 121 may be formed in an L-shape according to the arrangement of the through electrodes 71.

[0059] In the example of Figure 8, the well region 122 of the substrate contact 121 is arranged between the transistor 50 and the through electrode 71, so it is possible to maintain the pixel size while reducing the impact on the transistor 50 caused by the application of a high voltage to the through electrode 71.

[0060] 5. Third Embodiment FIG. 9 is a cross-sectional view showing an example of the configuration of a CMOS substrate 12 according to a third embodiment to which the technology of the present disclosure is applied, and FIG. 10 is a plan view thereof.

[0061] In the cross-sectional configuration shown in Fig. 9, an air gap 131 is formed in addition to the cross-sectional configuration shown in Fig. 2. The air gap 131 is formed, for example, by a vacuum cavity.

[0062] In the example of FIG. 10, in the CMOS substrate 12, air gaps 131 are arranged as shielding regions 100 between the transistor 50 and each of the two through electrodes 71a and 71b in a plan view in the stacking direction.

[0063] The air gap 131 is arranged so as to intersect all line segments connecting the centers of the through electrodes 71 a and 71 b with the vertices of the overlap region where the active region of the transistor 50 and the gate electrode 53 overlap, in a plan view from the stacking direction. This allows the electric field from each of the through electrodes 71 a and 71 b to propagate while avoiding the air gap 131, which has a low dielectric constant.

[0064] According to the above configuration, by placing an air gap 131 between the transistor 50 and each of the through electrodes 71a and 71b, it is possible to maintain the pixel size while reducing the effect on the transistor 50 caused by the application of a high voltage to the through electrode 71.

[0065] 10. In other words, the air gap 131 may have any shape as long as it is disposed so as to intersect with all the line segments connecting the vertices of the overlap region where the active region of the transistor 50 and the gate electrode 53 overlap with the centers of the through electrodes 71 (71a, 71b) in the planar view from the stacking direction, depending on the positional relationship between the transistor 50 and the through electrodes 71.

[0066] 6. Configuration example of a ranging system The sensor element 1 of each of the above-described embodiments can be applied to a ranging system that uses the ToF method to detect the depth distance to a subject for each pixel and captures a distance image, which is an image made up of distance pixel signals based on the detected distances.

[0067] FIG. 11 is a block diagram showing an example configuration of an embodiment of a distance measuring system 211 to which the technology according to the present disclosure is applied.

[0068] As shown in FIG. 11, the distance measurement system 211 includes an illumination device 221 and an imaging device 222 .

[0069] The lighting device 221 includes a lighting control unit 231 and a light source 232 .

[0070] The illumination control unit 231 controls the pattern in which the light source 232 emits light under the control of the control unit 242 of the imaging device 222. Specifically, the illumination control unit 231 controls the pattern in which the light source 232 emits light in accordance with an illumination code included in an illumination signal supplied from the control unit 242. For example, the illumination code is composed of two values, 1 (High) and 0 (Low), and the illumination control unit 231 turns on the light source 232 when the illumination code value is 1, and turns off the light source 232 when the illumination code value is 0.

[0071] The light source 232 emits light in a predetermined wavelength range under the control of the illumination control unit 231. The light source 232 is, for example, an infrared laser diode. The type of the light source 232 and the wavelength range of the emitted light can be set arbitrarily depending on the application of the distance measurement system 211, etc.

[0072] The imaging device 222 is a device that receives reflected light that is generated when light (irradiated light) emitted from the lighting device 221 is reflected by the subject 212, the subject 213, etc. The imaging device 222 includes an imaging unit 241, a control unit 242, a display unit 243, and a storage unit 244.

[0073] The imaging unit 241 includes a lens 251 , a light receiving element 252 , and a signal processing circuit 253 .

[0074] The lens 251 forms an image of incident light on the light receiving surface of the light receiving element 252. The lens 251 may have any configuration, and for example, the lens 251 may be configured by a group of multiple lenses.

[0075] The sensor element 1 to which the technology disclosed herein is applied is applied to the light receiving element 252. Under the control of the control unit 242, the light receiving element 252 receives reflected light from the subject 212, the subject 213, etc., and supplies the resulting pixel signal to the signal processing circuit 253. This pixel signal represents a digital count value that counts the time from when the illumination device 221 emits light to when the light receiving element 252 receives the light. A light emission timing signal that indicates the timing at which the light source 232 emits light is also supplied from the control unit 242 to the light receiving element 252.

[0076] The signal processing circuit 253 processes pixel signals supplied from the light receiving element 252 under the control of the control unit 242. For example, the signal processing circuit 253 detects the distance to the subject for each pixel based on the pixel signals supplied from the light receiving element 252 and generates a distance image indicating the distance to the subject for each pixel. Specifically, the signal processing circuit 253 acquires the time (count value) from when the light source 232 emits light to when each pixel of the light receiving element 252 receives the light multiple times (e.g., thousands to tens of thousands of times) for each pixel. The signal processing circuit 253 creates a histogram corresponding to the acquired time. Then, by detecting peaks in the histogram, the signal processing circuit 253 determines the time it takes for the light emitted from the light source 232 to be reflected by the subject 212 or 213 and return. Furthermore, the signal processing circuit 253 performs a calculation to determine the distance to the object based on the determined time and the speed of light. The signal processing circuit 253 supplies the generated distance image to the control unit 242.

[0077] The control unit 242 is configured with a control circuit and a processor, such as a field programmable gate array (FPGA) or a digital signal processor (DSP). The control unit 242 controls the illumination control unit 231 and the light receiving element 252. Specifically, the control unit 242 supplies an irradiation signal to the illumination control unit 231 and a light emission timing signal to the light receiving element 252. The light source 232 emits irradiation light in response to the irradiation signal. The light emission timing signal may be the irradiation signal supplied to the illumination control unit 231. The control unit 242 also displays the distance image acquired from the imaging unit 241 on the display unit 243. The control unit 242 also stores the distance image acquired from the imaging unit 241 in the memory unit 244. The control unit 242 also outputs the distance image acquired from the imaging unit 241 to the outside.

[0078] The display unit 243 is, for example, a panel display device such as a liquid crystal display device or an organic EL (Electro Luminescence) display device.

[0079] The storage unit 244 can be configured with any storage device or storage medium, and stores distance images and the like.

[0080] In the distance measuring system 211 configured in this manner, by applying the sensor element 1 to which the technology according to the present disclosure is applied, it is possible to achieve, for example, further miniaturization and higher functionality.

[0081] In this specification, a system refers to a collection of multiple components (devices, modules (components), etc.), regardless of whether all of the components are housed in the same housing. Therefore, multiple devices housed in separate housings and connected via a network, and a single device housed in a single housing with multiple modules, are both systems.

[0082] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0083] Furthermore, the embodiments to which the technology according to the present disclosure is applied are not limited to the above-described embodiments, and various modifications are possible within the scope that does not deviate from the gist of the technology according to the present disclosure.

[0084] Furthermore, the present disclosure may have the following configurations: (1) A sensor element comprising: a sensor substrate on which a single photon avalanche diode (SPAD) is provided for each pixel; a complementary metal oxide semiconductor (CMOS) substrate stacked on the sensor substrate and provided with a transistor for signal readout; a logic substrate stacked on the CMOS substrate and provided with a logic circuit; and a through electrode that penetrates the CMOS substrate and electrically connects the sensor substrate to the CMOS substrate. (2) The sensor element described in (1), in which existing components of the CMOS substrate are arranged as a shield region between the transistor and the through electrode in a planar view from the stacking direction. (3) The sensor element described in (2), in which the shield region is arranged so as to intersect all line segments connecting the center of the through electrode to each vertex of an overlap region where the active region and gate electrode of the transistor overlap in a planar view from the stacking direction. (4) The sensor element described in (3), in which the shield region is a source region or a drain region of the active region of the transistor. (5) The sensor element according to (3), wherein the shield region is a well region of a substrate contact. (6) The sensor element according to (3), wherein the shield region is an air gap. (7) The sensor element according to any one of (3) to (6), wherein a voltage having an absolute value of 20 V or more is applied to the through electrode. (8) The sensor element according to any one of (3) to (7), wherein a first conduction type transistor and a second conduction type transistor are provided on the CMOS substrate, and an element isolation region is formed between the first conduction type transistor and the second conduction type transistor. (9) The sensor element according to (8), wherein the element isolation region is formed by a DTI (Deep Trench Isolation) region penetrating from the surface to the bottom surface of the CMOS substrate.(10) The sensor element according to (9), wherein an STI (Shallow Trench Isolation) region or the DTI region having a depth of about 250 nm is further formed between the transistor and the through electrode in the CMOS substrate. (11) A ranging system comprising: an illumination device that irradiates irradiation light; and a sensor element that detects reflected light of the irradiation light, the sensor element having: a sensor substrate in which a single photon avalanche diode (SPAD) is provided for each pixel; a CMOS (Complementary Metal Oxide Semiconductor) substrate stacked on the sensor substrate and provided with a transistor for reading out signals; a logic substrate stacked on the CMOS substrate and provided with a logic circuit; and a through electrode that penetrates the CMOS substrate and electrically connects the sensor substrate and the CMOS substrate.

[0085] 1 sensor element, 10 pixel, 11 sensor substrate, 12 CMOS substrate, 13 logic substrate, 31 SPAD, 34 anode region, 35 cathode region, 50 transistor, 51 source region, 52 drain region, 53 gate electrode, 60 transistor, 61 source region, 62 drain region, 63 gate electrode, 71, 72 through electrode, 81, 82 element isolation region, 100 shield region, 121 substrate contact, 122 well region, 131 air gap

Claims

1. A sensor element comprising: a sensor substrate on which a single photon avalanche diode (SPAD) is provided for each pixel; a complementary metal oxide semiconductor (CMOS) substrate laminated on the sensor substrate and provided with transistors for signal readout; a logic substrate laminated on the CMOS substrate and provided with a logic circuit; and a through electrode that penetrates the CMOS substrate and electrically connects an anode region of the sensor substrate to the CMOS substrate.

2. The sensor element according to claim 1, wherein an existing component of the CMOS substrate is disposed as a shielding region between the transistor and the through electrode in a plan view from the stacking direction in the CMOS substrate.

3. The sensor element according to claim 2, wherein the shielding region is arranged so as to intersect with all line segments connecting the center of the through electrode and each vertex of an overlapping region where the active region and gate electrode of the transistor overlap when viewed in a plane from the stacking direction.

4. The sensor element according to claim 3, wherein the shield region is a source region or a drain region of the active region of the transistor.

5. The sensor element according to claim 3, wherein the shield region is a well region of a substrate contact.

6. The sensor element according to claim 3, wherein the shield region is an air gap.

7. The sensor element according to claim 3, wherein a voltage having an absolute value of 20 V or more is applied to the through electrode.

8. The sensor element according to claim 3, wherein a first conductive type transistor and a second conductive type transistor are provided on the CMOS substrate, and an element isolation region is formed between the first conductive type transistor and the second conductive type transistor.

9. The sensor element according to claim 8, wherein the element isolation region is formed by a DTI (Deep Trench Isolation) region that penetrates from the surface to the bottom surface of the CMOS substrate.

10. The sensor element according to claim 9, wherein in the CMOS substrate, an STI (Shallow Trench Isolation) region or the DTI region having a depth of about 250 nm is further formed between the transistor and the through electrode.

11. A distance measurement system comprising: an illumination device which emits illumination light; and a sensor element which detects reflected light of the illumination light, the sensor element having: a sensor substrate on which a single photon avalanche diode (SPAD) is provided for each pixel; a complementary metal oxide semiconductor (CMOS) substrate which is laminated on the sensor substrate and on which a transistor for reading out signals is provided; a logic substrate which is laminated on the CMOS substrate and on which a logic circuit is provided; and a through electrode which penetrates the CMOS substrate and electrically connects an anode region of the sensor substrate to the CMOS substrate.

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