Semiconductor device, preparation method therefor and use thereof

Abstract

The present disclosure relates to a semiconductor device, a preparation method therefor and a use thereof. The semiconductor device comprises: a composite support, wherein the composite support comprises a substrate and a template layer, and the composite support comprises an area having tensile stress and an area having compressive stress; an active layer used for recombination of injected carriers; a first semiconductor layer used for injecting N-type carriers into the active layer; a second semiconductor layer used for injecting P-type carriers into the active layer; a first electrode used for energy transmission of the first semiconductor layer, the projection of the first electrode on the upper surface of the composite support falling within the area of the compressive stress or coinciding with the area; and a second electrode used for energy transmission of the second semiconductor layer, the projection of the second electrode on the upper surface of the composite support falling within the area of the tensile stress or coinciding with the area.

Description

A semiconductor device and its preparation method and application Technical Field

[0001] The present disclosure relates to the field of electronics, and in particular, to a semiconductor device and a preparation method and application thereof. Background Art

[0002] Ultraviolet radiation refers to radiation with a wavelength below 400nm. Based on wavelength, ultraviolet radiation can be further divided into UVA (400-320nm), UVB (320-280nm), and UVC (280-200nm). Nitride semiconductors can be used to generate ultraviolet radiation. Semiconductor devices made from nitride semiconductors hold great promise in industrial curing, medical devices, biochemical testing, lighting sterilization, the Internet of Things, and consumer electronics.

[0003] Taking the ultraviolet light-emitting device in the prior art as an example, it usually adopts a stacked structure, including a sapphire substrate, an epitaxial template on the sapphire substrate, and a light-emitting stack composed of a ternary or quaternary nitride alloy, a P-type electrode layer and an N-type electrode layer on the epitaxial template.

[0004] However, existing ultraviolet light-emitting devices still suffer from technical issues such as low carrier activation efficiency in the light-emitting stack, low current spreading capability, low luminous intensity, low light maintenance rate, poor wavelength uniformity, poor overdrive capability, increased leakage current during aging, unstable product performance, high processing difficulty, and low yield. Therefore, the industry is eager to provide a high-performance, high-reliability, and high-yield ultraviolet light-emitting device.

[0005] Summary of the Invention

[0006] The present disclosure designs a novel semiconductor device and its preparation method and application, which can overcome the above-mentioned technical problems and have the obvious advantages of high performance, high reliability and high yield.

[0007] A brief overview of the present disclosure will be provided below to provide a basic understanding of certain aspects of the present disclosure. It should be understood that this overview is not an exhaustive overview of the present disclosure. It is not intended to identify key or important aspects of the present disclosure, nor is it intended to limit the scope of the present disclosure. Its purpose is simply to present certain concepts in a simplified form as a prelude to the more detailed description that will be discussed later.

[0008] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a composite carrier, the composite carrier comprising a substrate and a template layer, the composite carrier comprising a region with tensile stress and a region with compressive stress; an active layer for recombination of injected carriers; a first semiconductor layer for injecting N-type carriers into the active layer; a second semiconductor layer for injecting P-type carriers into the active layer; a first electrode for energy transmission of the first semiconductor layer, the projection of the first electrode on the upper surface of the composite carrier falling within the region of compressive stress, or coinciding with it; a second electrode for energy transmission of the second semiconductor layer, the projection of the second electrode on the upper surface of the composite carrier falling within the region of tensile stress, or coinciding with it.

[0009] According to another aspect of the present disclosure, a method for preparing a semiconductor device is provided, comprising: providing a composite carrier, the composite carrier comprising a substrate and a template layer, forming a region with tensile stress and a region with compressive stress in the composite carrier; forming a first semiconductor layer on the composite carrier, the first semiconductor layer comprising N-type carriers; forming an active layer on the first semiconductor layer; forming a second semiconductor layer on the active layer, the second semiconductor layer comprising P-type carriers; forming a first electrode on the first semiconductor layer, the projection of the first electrode on the upper surface of the composite carrier falling within the region of compressive stress, or coinciding with it; forming a second electrode on the second semiconductor layer, the projection of the second electrode on the upper surface of the composite carrier falling within the region of tensile stress, or coinciding with it.

[0010] According to yet another aspect of the present disclosure, an electronic device is provided, comprising the aforementioned semiconductor device.

[0011] The solution disclosed in the present invention can help achieve at least one of the following effects: improving the carrier activation efficiency in the light-emitting stack in the semiconductor device, improving the current expansion capability, improving the luminous intensity, and improving the light maintenance rate, improving the wavelength uniformity, improving the ability of super-drive use, reducing the leakage current during aging and improving the stability of product performance, as well as reducing the processing difficulty and improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The following description of the present disclosure will provide a more comprehensive understanding of the above and other objectives, features, and advantages of the present disclosure with reference to the accompanying drawings. The accompanying drawings are provided solely to illustrate the principles of the present disclosure. The sizes and relative positions of elements in the accompanying drawings are not necessarily drawn to scale.

[0013] FIG1 shows a schematic structural diagram of an ultraviolet light emitting diode according to a first embodiment of the present disclosure;

[0014] FIG2 a shows a top view of the surface state of the first region in FIG1 ;

[0015] FIG2b shows a cross-sectional view taken along line AA in FIG2a;

[0016] FIG3 shows a modified embodiment of the ultraviolet light emitting diode structure;

[0017] FIG4 a shows a top view of the surface state of the second region in FIG3 ;

[0018] FIG4 b shows a cross-sectional view taken along line BB in FIG4 a ;

[0019] FIG5 is a schematic diagram showing a pattern of a first test chip;

[0020] FIG6 is a schematic diagram showing a pattern of a second test chip;

[0021] FIG7 shows an IV curve between an n-electrode on a first test chip and an n-electrode on a second test substrate;

[0022] FIG8 shows an IV curve between the p-electrode on the first test chip and the p-electrode on the second chip substrate;

[0023] FIG9 shows a comparison of current and optical power curves of the first test chip and the second test chip;

[0024] FIG10 shows a comparison diagram of current and voltage curves of the first test chip and the second test chip;

[0025] FIG11 shows a schematic diagram of a preparation process of an ultraviolet light-emitting diode in the first embodiment of the present disclosure;

[0026] FIG12 shows a photolithography mask pattern of a substrate in the first embodiment of the present disclosure;

[0027] FIG13 shows a photolithography mask pattern of a substrate in the first embodiment of the present disclosure;

[0028] FIG14 shows a schematic structural diagram of an ultraviolet light emitting diode according to a second embodiment of the present disclosure;

[0029] Figures 15 to 24 show a method for preparing a template layer in the second embodiment of the present disclosure;

[0030] FIG25 is a schematic structural diagram of an ultraviolet light emitting diode according to a third embodiment of the present disclosure;

[0031] 26-32 illustrate a method for preparing a portion of the structure in the third embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The exemplary disclosures of the present disclosure will be described below in conjunction with the accompanying drawings. For the sake of clarity and conciseness, not all features of the present disclosure are described in the specification. However, it should be understood that many decisions specific to the present disclosure can be made in the process of developing any such implementation of the present disclosure in order to achieve the specific goals of the developers, and these decisions may change from one disclosure to another. It should also be noted that in order to avoid obscuring the present disclosure with unnecessary details, only the device structures that are closely related to the technical solutions according to the present disclosure are shown in the accompanying drawings, and other details that are not closely related to the present disclosure are omitted.

[0033] It should be understood that the present disclosure is not limited to the described embodiments as a result of the following description with reference to the accompanying drawings. Herein, features between different embodiments may be interchanged or borrowed, and one or more features may be omitted from one embodiment, where feasible. It should be understood that the manufacturing steps described in the embodiments are illustrative and the order of the steps may be adjusted.

[0034] In this disclosure, a UV light-emitting diode is used as an example to explain the technical solution of the present disclosure in detail with the aid of the accompanying drawings, wherein like reference numerals represent like components. It will be understood by those skilled in the art that the technical solution of the present disclosure is not limited to UV light-emitting diodes, but may also include UV photodetectors or UV lasers, etc.

[0035] Implementation Method 1

[0036] Please refer to Figure 1, which is a schematic diagram of the structure of a UV LED. As shown in Figure 1, the UV LED comprises at least a substrate 1, a template layer 2, a first semiconductor layer 3, an active layer 4, a second semiconductor layer 6, a first electrode 8, and a second electrode 9.

[0037] Substrate 1 is used as a carrier for the ultraviolet light-emitting diode. Specifically, substrate 1 can be selected from sapphire, AlN, SiC, etc. Preferably, C-plane sapphire is used as substrate 1 for the ultraviolet light-emitting diode in the present disclosure. Substrate 1 in the present disclosure has a first region 11 and a second region 12. The first region 11 has a first surface state, and the second region 12 has a second surface state. The roughness of the first surface state is greater than the roughness of the second surface state.

[0038] Please refer to Figures 2a-2b. Figure 2a shows a top view of the surface state of the first region in Figure 1; Figure 2b shows a cross-sectional view taken along line AA in Figure 2a. In one specific embodiment, in conjunction with Figures 1 and 2a-2b, the first surface state of the first region 11 is a surface state having nanopatterns of a first size; the second surface state of the second region 12 is a surface state having a flat surface without nanopatterns. The top view of the nanopatterns of the first size can, for example, be a regular hexagon as shown in Figure 2a. It is understood that the top view of the nanopatterns of the first size can also be a circle, square, or other shape. Taking the regular hexagon shown in Figure 2a as an example, the spacing D1 between its symmetrical endpoints can be set to 700nm-1200nm, that is, the radius from the center of the regular hexagon to the endpoints can be set to 350nm-600nm. The distribution density of the nanopatterns of the first size in the first region 11 can be 70-200 per 100um. 2 The cross-sectional view thereof can be exemplarily a triangle as shown in FIG2 b. It is understood that the cross-sectional view of the nanopattern of the first size can also be a trapezoid, a rectangle, a square, etc., and the depth H1 thereof can be set to 300 nm-700 nm.

[0039] Please refer to Figure 3, which shows a modified embodiment of the ultraviolet light-emitting diode structure in the first embodiment. The difference between it and the ultraviolet light-emitting diode structure in Figure 1 mainly lies in the second surface state of the second region 12 in the substrate 1. Please refer to Figures 4a-4b, Figure 4a shows a top view of the surface state of the second region in Figure 3; Figure 4b shows a cross-sectional view along the BB direction in Figure 4a. Specifically, the first surface state of the first region 11 of the substrate 1 of the ultraviolet light-emitting diode shown in Figure 3 can be, as described above, the surface state of a nanograph of the first size as shown in Figures 2a-2b. In this modified embodiment, the second surface state of the second region 12 of the substrate 1 is the surface state of a nanograph of the second size. Specifically, the top view of the nanograph of the second size can be, for example, a regular hexagon as shown in Figure 4a. It is understood that the top view of the second-sized nanopattern can also be a circle, square, or other shape. Taking the regular hexagon shown in Figure 4a as an example, the spacing D2 between its symmetrical endpoints can be set to 200nm-500nm, that is, the radius from the center of the regular hexagon to the endpoint can be set to 100nm-250nm. The distribution density of the second-sized nanopattern in the second region 12 can be 400-2500 / 100um. 2 The cross-sectional view thereof can be exemplarily a triangle as shown in FIG4 b. It is understood that the cross-sectional view of the nanopattern of the second size can also be a trapezoid, a rectangle, a square, etc., and the depth H2 thereof can be set to 50 nm-500 nm.

[0040] A template layer 2 is formed on a substrate 1. The thickness of the template layer 2 can range from 1700 nm to 2950 nm. The template layer 2 can be composed of aluminum nitride (AlN) in a single layer or multiple layers. For example, the template layer 2 can be composed of an AlN composite layer. More specifically, the AlN composite layer includes a first buffer layer composed of AlN, a first template sublayer composed of AlN grown at a medium temperature (not shown), and a second template sublayer composed of AlN grown at a high temperature (not shown). In this disclosure, the substrate 1 and template layer 2 are defined as a composite carrier. Taking the ultraviolet light-emitting diode in Figure 3 as an example, since the size of the first-size nanopattern in the first region 11 of the substrate 1 is relatively large, the lattice constant of the template layer 2 grown on the first region 11 is smaller than the lattice constant of the template layer 2 in the stress-free state. By characterizing the stress-sensitive E2 (high) phonon mode in the Raman spectrum to explore the strain state of the template layer 2 corresponding to the first region 11, it can be found that the E2 (high) phonon mode peak shift of the template layer 2 in this region is ≥657.4 cm-1, that is, this region is in a compressive stress state. Because the second-sized nanopatterns in the second region 12 of the substrate 1 are relatively small, the AlN constituting the template layer 2 rapidly merges during growth, introducing tensile stress. Therefore, the lattice constant of the template layer 2 grown on the second region 12 is greater than the lattice constant of the template layer 2 in a stress-free state. By characterizing the stress-sensitive E2 (high) phonon mode in the Raman spectrum to explore the strain state of the template layer 2 corresponding to the second region 12, it was found that the E2 (high) phonon mode peak shift of the template layer 2 is less than 657.4 cm-1, indicating that the region exhibits a tensile stress state. In the present disclosure, by setting different surface states at different regions (11, 12) on the surface of the substrate 1, the stress state of different regions on the template layer 2 is regulated, thereby affecting the lattice constant of the template layer 2 in the corresponding regions.

[0041] The first semiconductor layer 3, i.e., the N-type layer, is formed on the template layer 2. The first semiconductor layer 3 is used for electron supply and can be formed in the form of a single layer or multiple layers. The material of the N-type layer is selected from metal nitrides with cations selected from the periodic table IIIA. The thickness of the first semiconductor layer 3 is set according to the parameter requirements of the specific device. For example, the material of the first semiconductor layer 3 can be AlN, GaN, InN, Al x Ga y N、In x Ga y N、In x Al y N (where 0≤x≤1, 0≤y≤1, x+y=1) or Al x In y Ga zN (wherein 0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z=1). Preferably, the first semiconductor layer 3 in the present disclosure is an N-type Al x Ga y N, wherein the value of x is 0.55-0.7. The thickness of the first semiconductor layer 3 can be selected to be 800-1600 nm. More preferably, the N-type Al x Ga y N is doped with Si donor impurities, with a Si doping concentration of 1E18 cm -3 ~1E20cm -3 Since different regions on the template layer 2 have different stress states, different regions on the first semiconductor layer 3 also have different stress states.

[0042] The active layer 4 is formed on the first semiconductor layer 3 and is used for the recombination of the injected carriers. The active layer 4 can be a multi-quantum well active layer MQW composed of two thin layers of different semiconductor materials. For example, the multi-quantum well active layer MQW can be made of AL a Ga 1-a N barrier and Al b Ga 1-b The potential barrier is composed of N potential wells, wherein a in the potential barrier can be 0.6-0.75, and the thickness can be set to 8nm-15nm; b in the potential well can be 0.49-0.54, and the thickness can be set to 1.3nm-3nm.

[0043] The electron blocking layer (EBL layer) 5 is formed on the active layer 4 to block electrons, which can be a stacked pAl x Ga 1-X N / A y Ga 1-y N or monolayer pAl x Ga 1-x N. The stacked EBL layer 5 can be a multi-quantum well structure with a period of 1 to 5 pairs. x Ga 1-X The Al composition of N is 0.7≤x≤0.8, the thickness is 8~15nm, and the well layer Al y Ga 1-y The Al component of N is 0.53≤y≤0.6, and the thickness is 1.5~3.5nm; the single layer pAl x Ga 1-x In the N layer, 0.7≤x≤0.9, the thickness is 15nm~60nm, and the doping concentration of Cp2Mg is 1E17cm -3 ~1E18cm -3 .

[0044] The second semiconductor layer 6, i.e., the P-type layer, is formed on the EBL layer 5. The second semiconductor layer 6 is used for hole injection. It will be understood by those skilled in the art that the positions of the second semiconductor layer 6 and the first semiconductor layer 3 are interchangeable. The second semiconductor layer 6 can be formed in the form of a single layer or multiple layers. The thickness of the second semiconductor layer 6 is set according to the parameter requirements of the specific device. The material of the second semiconductor layer 6 is selected from metal nitrides with cations selected from the periodic table IIIA. Preferably, the second semiconductor layer 6 in the present disclosure can be Al c Ga 1-c N, wherein the value of c is 0.3-0.6, and the thickness of the second semiconductor layer 6 can be set to 10nm-30nm; more preferably, the P-type Al c Ga 1-c N is doped with Mg acceptor impurities, with a Mg doping concentration of 1E18 cm -3 ~1E20cm -3 .

[0045] Since different regions on the template layer 2 have different stress states, the stress is transferred, causing the second semiconductor layer 6 to be in a tensile stress state.

[0046] Due to Al c Ga 1-c There is a piezoelectric polarization effect in N materials. The relationship between piezoelectric polarization and lattice constant is: Among them, P pe is the piezoelectric polarization strength, a is Al x Ga 1-c Lattice constant of N, e 31 and e 33 is the piezoelectric constant; C 13 and C 33 is the elastic constant, a0 is Al x Ga 1-c The lattice constant of N in a completely relaxed state. When subjected to tensile stress, Al x Ga 1-c The lattice constant a of N is greater than that of Al x Ga 1-c The lattice constant a0 of N in the fully relaxed state, at this time P pe The sign is positive, that is, the direction of piezoelectric polarization is the same as the direction of spontaneous polarization, and Al c Ga 1-c The total polarization intensity inside N is P = P sp +P pe , where P sp Therefore, the polarization electric field strength inside p-type AlGaN can be controlled by controlling the stress state of p-type AlGaN, thereby improving the activation efficiency of holes.

[0047] In the present disclosure, the projection of the area corresponding to the second semiconductor layer 6 on the surface of the substrate 1 falls within the second area 12 of the substrate 1 or overlaps with the second area 12. Therefore, the stress state of the second semiconductor layer 6 can be controlled by the stress state of different areas on the template layer 2, thereby controlling the polarization electric field strength inside the second semiconductor layer 6, and then affecting the activation efficiency of the holes in the second semiconductor layer 6.

[0048] Furthermore, the third semiconductor layer 7, i.e., the P-type ohmic contact layer, can be provided on the second semiconductor layer 6 as shown in FIG1 or 3. The thickness of the third semiconductor layer 7 can be 1 nm to 50 nm. Preferably, in the present disclosure, the third semiconductor layer 7 can be a P-type GaN layer, AlGaN or AlN layer, wherein the Mg doping concentration in the P-type GaN, AlGaN or AlN layer can be 1E19 cm -3 ~1E21cm -3 .

[0049] Since different regions on the template layer 2 have different stress states, the third semiconductor layer 7 is in a tensile stress state through stress transfer.

[0050] In addition, in the present disclosure, by c Ga 1-c N and P-type GaN layers are doped with Mg impurities, and P-type Al c Ga 1-c The N lattice constant is greater than the lattice constant in the fully relaxed state, and the P-type Al in the tensile stress state c Ga 1-c The direction of the piezoelectric polarization electric field of N is the same as that of the spontaneous polarization electric field, which enhances the total internal polarization electric field and helps to improve the P-type Al c Ga 1-c The activation probability of holes in the N material increases, thereby increasing the surface hole concentration, reducing contact resistance and p-layer body resistance, improving current spreading, reducing heat generation, and improving light maintenance rate.

[0051] The stress state of the first semiconductor layer on the template layer is described as a comparative example with the template layer in a completely relaxed state and other device structures being the same. x Ga 1-x For example, the first semiconductor layer composed of N (0≤x≤1) ternary compound, Al x Ga 1-x The lattice constant of the first semiconductor layer composed of N (0≤x≤1) in a completely relaxed state is defined as a1, the lattice constant of AlN is defined as a2, and the lattice constant of GaN is defined as a3. According to Vegard's law, a1=x×a2+(1-x)×a3. Since the lattice constant a3 of GaN is about 2.5% larger than the lattice constant a2 of AlN, for a certain composition of Alx Ga 1-x As for N, the lower the Al component, that is, the smaller x is, the larger the lattice constant a1 is. It can be seen that a certain component of Al grows on the surface of the template layer AlN in a stress state close to relaxation. x Ga 1-x N, Al x Ga 1-x There will be a large compressive stress inside N. Therefore, through stress transfer, there will also be compressive stress at the second semiconductor layer (P-type layer) and the third semiconductor layer (P-type ohmic contact layer), thereby reducing the activation efficiency of holes. The reduction in the carrier concentration in the second semiconductor layer (P-type layer) will significantly reduce the number of holes transmitted to the active area, reduce the recombination of electrons and holes in the active area, reduce the internal quantum efficiency, and the reduction in carrier concentration will increase the operating voltage of the device, increase heat generation, and reduce service life. It can be seen that compared with the comparative example, the present disclosure effectively overcomes the above-mentioned defects and improves device performance.

[0052] The first electrode 8, also known as the N electrode, serves as the energy transfer layer of the first semiconductor layer 3 and can be a multi-layer or single-layer structure. The first electrode 8 is formed on the surface of the first semiconductor layer 3, and the projection of the first electrode 8 on the upper surface of the substrate 1 falls within the first region 11 of the substrate 1, or overlaps therewith. For example, in the present disclosure, the first electrode 8 is a Cr / Al / Ti / Au or Cr / Ti / Al / Ni / Au / Ti metal stack. The second electrode 9, also known as the P electrode, serves as the energy transfer layer of the second semiconductor layer 6 and can be a multi-layer or single-layer metal structure. The second electrode 9 is formed on the surface of the third semiconductor layer 7, and the projection of the second electrode 9 on the upper surface of the substrate 1 falls within the second region 12 of the substrate 1, or overlaps therewith. For example, in the present disclosure, the second electrode 9 is a Ni / Au / Ni / Au or Ni / Au / Ni / Rh / Ti metal stack.

[0053] Continuing to refer to Figure 1 or Figure 3, it can be understood that in addition to the basic structural layers such as substrate 1, template layer 2, first semiconductor layer 3, active layer 4, first semiconductor layer 6, first electrode 8 and second electrode 9, the ultraviolet light emitting diode in the present disclosure may also include other layer structures. For example, the ultraviolet light emitting diode in this embodiment may also have a superlattice layer (not shown in the figure) between the substrate 1 and the template layer 2, and may also have a hole injection and electron blocking layer (EBL) 5 between the active layer 4 and the second semiconductor layer 6, etc. In addition to the above-mentioned basic structural layers, the additional functional layers in other ultraviolet light emitting diodes are applicable to the present disclosure, and the present disclosure does not make specific limitations on this, which is included in the protection scope of the present disclosure.

[0054] Please refer to Figures 5-6. Figure 5 shows a schematic diagram of a pattern for a first test chip; Figure 6 shows a schematic diagram of a pattern for a second test chip. As shown in Figure 5, the pattern for the first test chip can be a nanopattern having a certain size in the area corresponding to the first electrode on the substrate surface. This size corresponds to the first size in Figures 1 or 3, while the area corresponding to the second electrode remains unchanged, forming a planar substrate. Furthermore, as shown in Figure 6, the pattern for the second test chip can be a nanopattern having a certain size in the area corresponding to the first electrode on the substrate surface remaining unchanged, forming a planar substrate, while the area corresponding to the second electrode is fabricated. Corresponding N-electrode and P-electrode metals are then evaporated on the surfaces of the first and second test chips, respectively. Probes are used to measure the resistance values ​​at the N-electrode and P-electrode on the first and second test substrates, respectively.

[0055] Please refer to Figure 7, which shows the IV curve between the first electrode (N electrode) on the first test chip and the first electrode (N electrode) on the second test substrate. The dashed line represents the measurement value on the first test chip, and the solid line represents the measurement value on the second test chip. As can be seen from Figure 7, the resistance of the N electrode grown on the first test chip is lower than the resistance of the N electrode grown on the second test chip (i.e., the IV curve slope is lower in the nanopatterned substrate region). Please refer to Figure 8, which shows the IV curve between the second electrode (P electrode) on the first test chip and the second electrode (P electrode) on the second test chip. The dashed line represents the measurement value on the second test chip, and the solid line represents the measurement value on the first test chip. As can be seen from Figure 8, the resistance of the P electrode grown on the first test chip is lower than the resistance of the P electrode grown on the second test chip (i.e., the IV curve slope is lower in the planar substrate region). Through the IV curve testing experiments of the P and N electrodes, it can be confirmed that the present disclosure achieves different stress states by using substrate patterns with different surface states for the P and N electrodes, thereby reducing the resistance of the P-type and N-type layers.

[0056] Saturation power tests were performed on the first and second test chips, respectively. Please refer to Figures 9 and 10. Figure 9 shows a comparison of the current and optical power curves of the first and second test chips, and Figure 10 shows a comparison of the current and voltage curves of the first and second test chips. As shown in Figures 9 and 10, the saturation current of the first test chip is 399.9 mA, while the saturation current of the second test chip is 300 mA; the saturation power of the first test chip is 51.35 mW, while the saturation power of the second test chip is 29.32 mW; the voltage of the first test chip at normal operating current is 5.7 V, while the voltage of the second test chip at normal operating current is 5.76 V; the voltage of the first test chip at overdrive current is 5.79 V, while the voltage of the second test chip at overdrive current is 5.96 V. This shows that by using different substrate states at the bottom of the P-electrode layer and the bottom of the N-electrode layer, and respectively manipulating the P-electrode layer and the N-electrode layer to achieve tensile and compressive stress states, the saturation current and saturation power can be significantly increased, while the operating voltage at normal operating current and the operating voltage at overdrive current can be reduced.

[0057] Please refer to Figure 11, which shows a schematic diagram of a preparation process of the ultraviolet light emitting diode in the first embodiment of the present disclosure. The preparation process of the ultraviolet light emitting diode in this embodiment will be further described below in conjunction with Figures 1, 3 and 11.

[0058] Step S100: forming a patterned substrate

[0059] A substrate 1 is provided. The material of the substrate 1 is as described above and will not be described again. A photoresist is coated on the substrate 1. For example, the thickness of the photoresist may be 600 nm to 1500 nm.

[0060] Using the photoresist mask pattern shown in Figure 12 or Figure 13, the substrate coated with photoresist is exposed, developed, baked, etched, de-gum-treated and cleaned to form a first pattern in the first area 11 of each chip area on the substrate 1 and a second pattern in the second area 12. The first pattern and the second pattern are as described above and will not be described in detail here. An exemplary embodiment of the etching process in this embodiment is to etch the substrate with the mask pattern formed thereon. For example, Cl2 and BCl3 are selected as etching gases, with flow rates of 25 sccm to 80 sccm and etching time of 150s to 350s. It should be understood by those skilled in the art that any method of forming the first pattern and the second pattern on the substrate can be used. The parameters provided in this disclosure are only examples and are not intended to be a specific limitation on the scope of this disclosure.

[0061] Step S200: Forming a template layer: A template layer 2 is then formed on substrate 1. In one embodiment of the present disclosure, the process for forming template layer 2 is as follows: a first buffer layer (not shown) composed of AlN with a thickness of 2 nm to 13 nm is sputtered on the surface of substrate 1 using a magnetron sputtering device. The process parameters used in the sputtering process are: sputtering power of 3300 to 4000 W, N2 flow rate of 70 sccm to 95 sccm, Ar gas flow rate of 1 sccm to 4 sccm, and temperature of 700 to 750°C. A first template sublayer (not shown) is then grown on the first buffer layer (not shown). The thickness of the first template sublayer can be a medium-temperature grown AlN layer of 200 nm to 450 nm. For example, the first template sublayer can be grown by MOCVD. The process parameters in the MOCVD deposition process can be: NH3 flow rate of 1SLM to 5SLM, TMAl flow rate of 200umol / min to 300umol / min, pressure of 45torr to 60torr, temperature of 900°C to 1100°C, and H2 flow rate of 30SLM to 60SLM. A second template sublayer (not shown) is grown on the first template sublayer. The second template sublayer can be a high-temperature AlN layer with a thickness of 1500nm to 2500nm. For example, the second template sublayer can be deposited by MOCVD. The process parameters in the MOCVD deposition process can be: NH3 flow rate of 20-1000sccm, TMAl flow rate of 150umol / min to 220umol / min, pressure of 25torr to 50torr, temperature of 1150°C to 1300°C, and H2 flow rate of 45SLM to 100SLM.

[0062] Step S300: forming a structure stack: then forming a first semiconductor layer 3 on the template layer, illustratively, growing 800nm ​​to 1600nm of n-type Al x Ga y N layer (x value is 0.55-0.7, x+y=1), where n-type impurities can be Si atoms, and the Si atom doping concentration is 1E19cm -3 ~1E20cm -3Exemplary growth process parameters may be: 1000°C to 1100°C, pressure 40 torr to 80 torr, TMAl (trimethylaluminum) flow rate of 260 to 300 umol / min, TMGa (trimethylgallium) flow rate of 200 to 160 umol / min, NH3 flow rate of 4000 to 8000 sccm, SiH4 flow rate of 2.6E-8 to 2.6E-9 mol / min, pure H2 carrier gas (push gas), H2 flow rate of 30 to 80 slm, and growth time of 50 to 100 minutes. It is understood that other n-type impurities may also be used, and this is not a specific limitation of the present disclosure.

[0063] A multi-quantum well active layer 4 is grown on the first semiconductor layer 3. The number of periods of the multi-quantum wells can be 1 to 10 pairs. a Ga 1-a The Al composition of the N barrier layer can be 0.6-0.75, with a thickness of 8nm-15nm. b Ga 1-b The Al composition of the N potential well layer can be 0.49 to 0.54, and the thickness can be 1.3 nm to 3 nm. Optionally, an electron blocking layer (EBL layer) 5 can be further formed on the multi-quantum well active layer 4, which can be a stacked pAl x Ga 1-X N / A y Ga 1-y N or monolayer pAl x Ga 1-x N. The stacked EBL layer 5 can be a multi-quantum well structure with a period of 1 to 5 pairs. The barrier layer Al composition is 0.7≤x≤0.8, the thickness is 8 to 15nm, the well layer Al composition is 0.53≤y≤0.6, the thickness is 1.5 to 3.5nm; the single layer pAl x Ga 1-x N layer, 0.7≤x≤0.9, thickness 15nm~60nm, Cp2Mg doping concentration 1E17cm -3 ~1E18cm -3 .

[0064] A second semiconductor layer 6 is grown on the EBL layer 5. The thickness of the second semiconductor layer 6 is 10 nm to 30 nm. For example, the second semiconductor layer 6 is a P-type AlGaN layer. The process parameters include a growth time of 100 s to 300 s, an Al composition of 0.3 to 0.6, and a Mg doping concentration of 1E18 cm -3 ~1E20cm -3The specific growth process at this stage may be: 900℃~1000℃, pressure 60torr~100torr, TMAl flow rate of 180umol / min~210umol / min, TMGa flow rate of 50umol / min~80umol / min, NH3 flow rate of 2000sccm~8000sccm, Cp2Mg flow rate of 200scm~600sccm, pure H2 carrier gas, and the carrier gas flow rate is 30SLM~80SLM. A third semiconductor layer 7 is grown on the second semiconductor layer 6. The thickness of the third semiconductor layer 7 is 1nm~50nm. Exemplarily, the third semiconductor layer 7 is P-type GaN. The growth time is 100s~500s, and the Mg doping concentration is 1E19cm -3 ~1E21cm -3 The specific growth process at this stage is: 800℃~950℃, pressure 100torr~300torr, TMGa flow rate of 30umol / min~60umol / min, NH3 (ammonia) flow rate of 6000sccm~20000sccm, Cp2Mg (dipentyl magnesium) flow rate of 400sccm~800sccm, pure H2 carrier gas, H2 flow rate of 10SLM~30SLM.

[0065] A first electrode 8 and a second electrode 9 are formed. The second electrode 9 is formed on the third semiconductor layer 7. Exemplarily, the second electrode 9 can be formed by a lift-off process. By forming a patterned photoresist, the third semiconductor layer 7 is exposed, and then a Ni / Au / Ni / Au or Ni / Au / Ni / Rh / Ti metal stack is deposited, and then the photoresist is removed to form the second electrode 9 on the third semiconductor layer 7. It will be understood that the second electrode 9 can also be formed by other processes, which are only examples and not specific limitations of the present disclosure. Similarly, the first electrode 8 can also be formed by a lift-off process. A Cr / Al / Ti / Au or Cr / Ti / Al / Ni / Au / Ti electrode layer can be formed on the first semiconductor layer 3, which will not be described in detail in the present disclosure.

[0066] S400: Other preparation processes: After the structure stack is formed, other preparation processes such as packaging, cutting, etc. can be carried out.

[0067] Implementation Method 2

[0068] Please refer to FIG14 , which shows a schematic structural diagram of a second embodiment of the ultraviolet light emitting diode disclosed herein, wherein the same reference numerals represent the same components.

[0069] The main difference between Embodiment 2 and Embodiment 1 is that in this embodiment, the surface of substrate 1 has the same surface state, and a third region 21 and a fourth region 22 are formed in template layer 2. The third region is in a compressive stress state and corresponds to the area where first electrode 8 will be subsequently formed. That is, the projection of first electrode 8 on the surface of substrate 1 falls within or overlaps with the projection of third region 21 on the surface of substrate 1. The third region 21 includes an air gap having a first height Th1, which can be set to 450-1000 nm. The fourth region 22 is in a tensile stress state and corresponds to the area where second electrode 9 will be subsequently formed. That is, the projection of second electrode 9 on the surface of substrate 1 falls within or overlaps with the projection of fourth region 22 on the surface of substrate 1. The fourth region 22 includes an air gap having a second height Th2, which can be set to 200-430 nm. The rest of the device structure is the same as that of Embodiment 1 and will not be further described here. The E2 (high) phonon mode peak shift in the third region of the template layer 2 is ≥657.4 cm-1, and the E2 (high) phonon mode peak shift in the fourth region of the template layer 2 is <657.4 cm-1.

[0070] Exemplarily, the third region 21 includes a fourth template sublayer 222 and a sixth template sublayer 224; the fourth region 22 includes a third template sublayer 221, a fifth template sublayer 223, and a sixth template sublayer 224. The thickness of the fourth template sublayer 222 is equal to the total thickness of the third and fifth template sublayers 221 and 223. The third template sublayer 221 is an AlN layer with a thickness of 100 to 300 nm and grown at 900°C to 1100°C. The fourth template sublayer 222 is an AlN layer with a thickness of 400 to 800 nm and grown at 900°C to 1100°C. The fifth template sublayer 223 is an AlN layer with a thickness of 300 to 500 nm and grown at 1150°C to 1300°C. The sixth template sublayer 224 covers both the third and fourth regions 21 and 22 and is an AlN layer grown at 1150°C to 1300°C.

[0071] The steps of the preparation method corresponding to this embodiment are mainly different from those of the preparation method of embodiment 1 in that step S100 is replaced by step S101, and step S200 is replaced by step S201. The other steps are the same. Please refer to Figures 15-24 for further explanation of the preparation method of the template layer in embodiment 2.

[0072] Specifically, step S101: providing a substrate 1. The material of the substrate 1 is as described above and will not be repeated here.

[0073] Step S201: Forming a Template Layer: As shown in FIG15 , a first mask 100 is formed on substrate 1. The thickness of the first mask 100 can be set to 100 nm to 200 nm. The first mask 100 can be composed of silicon dioxide (SiO2). The first mask 100 covers the third region 21. Then, a second buffer layer (not shown) with a thickness of 2 nm to 13 nm is deposited. The second buffer layer can be composed of AlN. As shown in FIG16 , a third template sublayer 221 is formed on the surface of the second buffer layer, outside the third region 21. The third template sublayer 221 is an AlN layer grown at a medium temperature, with a thickness of 100 nm to 300 nm. The growth process parameters for the third template sublayer 221 are: NH3 flow rate of 1 SLM to 5 SLM, TMAl flow rate of 200 μmol / min to 300 μmol / min, pressure of 45 Torr to 60 Torr, temperature of 900°C to 1100°C, and H2 flow rate of 30 SLM to 60 SLM. As shown in Figure 17, the first mask 100 is removed, and then a second mask 200, such as silicon dioxide (SiO2), is formed on the third template sublayer 221. The thickness of the second mask 200 can be set to 300-500nm. Next, a third buffer layer (not shown) with a thickness of 2nm to 13nm is deposited. The third buffer layer can be composed of AlN. Then, as shown in Figure 18, a fourth template sublayer 222 with a thickness of 400-800nm ​​is grown on the surface of the third buffer layer. The fourth template sublayer 222 is an AlN layer grown at a medium temperature. The growth process of the fourth template sublayer 222 is as follows: NH3 flow rate of 1SLM to 5SLM, TMAl flow rate of 200umol / min to 300umol / min, pressure of 45torr to 60torr, temperature of 900°C to 1100°C, and H2 flow rate of 30SLM to 60SLM. As shown in Figure 19, the second mask 200 is removed. The second mask 200 can be removed using an ICP process. Then, as shown in FIG20 , a third mask 300, such as silicon dioxide (SiO 2 ), is formed on the fourth template sublayer 222 . The thickness of the third mask can be set to 100-200 nm. Next, as shown in FIG21 , a fifth template sublayer 223 is formed on the third template sublayer 221 . The fifth template sublayer 223 can be an AlN layer grown at a high temperature. The thickness of the fifth template sublayer 223 can be set to 300-500 nm, and the total thickness of the fifth template sublayer 223 and the third template sublayer 221 should be such that the upper surface of the fifth template sublayer 223 is flush with the upper surface of the fourth template sublayer 222 . The growth process of the fifth template sublayer 223 is as follows: NH 3 flow rate of 20-1000 sccm, TMAl flow rate of 150 umol / min to 220 umol / min, pressure of 25 torr to 50 torr, temperature of 1150° C. to 1300° C., and H 2 flow rate of 45 SLM to 100 SLM. As shown in FIG. 22 , the third mask 300 is removed.Then, as shown in Figure 23, a sixth template sublayer 224 is deposited. The sixth template sublayer 224 can be a high-temperature AlN layer. The sixth template sublayer 224 covers both the fifth template sublayer and the fourth template sublayer. The growth process for the sixth template sublayer 224 is as follows: NH3 flow rate of 20-1000 sccm, TMAl flow rate of 150umol / min to 220umol / min, pressure of 25torr to 50torr, temperature of 1150°C to 1300°C, and H2 flow rate of 45SLM to 100SLM. It is understood that after forming the fourth template sublayer 222, a fifth template sublayer 223 composed of high-temperature grown AlN can be formed by selective epitaxy, and then a planarization process can be performed to form the structure shown in Figure 24.

[0074] In this embodiment, a two-step growth process is used to control the thickness, growth rate, temperature, and location of the template sublayers to form air gaps of varying heights in different regions (21, 22) within the template layer 2, thereby controlling the stress state in the corresponding regions. Specifically, in this embodiment, a third template sublayer 221 of a certain thickness is first grown in the fourth region 22, and then a fifth template sublayer 223 of a certain thickness is grown on the third template sublayer 221. The height difference between the third template sublayer 221 and the fourth template sublayer 222 grown in the third region 21 is leveled, resulting in a smooth, regular step flow morphology. The thickness of the third template sublayer 221, the size of the fourth region 22, and the lateral migration ability of the Al atoms in the fifth template sublayer 223 determine the speed at which the height difference is leveled, which in turn affects the stress state in the fourth region 22. The faster the leveling speed, the more tensile stress tends to be in the fourth region 22, while the slower the leveling speed, the more compressive stress tends to be in the corresponding region. The effect of the leveling speed on the stress state of the template layer 2 can be reflected in the height of the air gaps in the template layer 2. The faster the filling speed, the lower the height of the air gap, and the slower the filling speed, the higher the height of the air gap. By testing the cross section of the template layer 2 by SEM or TEM, the height of the "air gap" can be easily measured, and the stress state of the epitaxial layer can be determined.

[0075] In this embodiment, the selective area epitaxy method is adopted. By designing the combination of different sublayers in the template layer 2, especially the thickness of the template sublayer grown at medium temperature, different stress states are obtained in different areas of the AlN template, and then N-type layers and P-type layers with different stress states are obtained. The P-type layer has tensile stress, which can increase the polarization electric field strength, reduce resistance, and improve the current expansion capability of the P-type layer. The N-type layer has compressive stress, has higher mobility and lower resistance, and can improve the current expansion capability of the N-type layer. The two improvement measures work together to increase the saturation current and saturation power of the chip, and reduce the saturation voltage, thereby improving the chip's ability to be used in overdrive.

[0076] It can be further understood that the template layer 2 in this embodiment can be further coordinated with the patterned substrate 1 in the first embodiment to better obtain a composite carrier with different stress states, and then obtain an N-type layer, a P-type layer and a P-type contact layer with different stress states, so as to better obtain the technical effects as described above.

[0077] Implementation Method 3

[0078] Please refer to FIG. 25 , which shows a schematic structural diagram of an ultraviolet light emitting diode according to a third embodiment of the present disclosure, wherein the same reference numerals represent the same components.

[0079] The main difference between Embodiment 3 and Embodiment 1 is that in this embodiment, the surface of substrate 1 has the same surface state, and a third region 21 and a fourth region 22 are formed in template layer 2. Third region 21 has a compressive stress state and corresponds to the region where first electrode 8 will be subsequently formed. That is, the projection of first electrode 8 on the surface of substrate 1 falls within or overlaps with the projection of third region 21 on the surface of substrate 1. Fourth region 22 has a tensile stress state and corresponds to the region where second electrode 9 will be subsequently formed. That is, the projection of second electrode 9 on the substrate surface falls within or overlaps with the projection of fourth region 22 on the surface of substrate 1.

[0080] The main difference between Embodiment 3 and Embodiment 2 lies in the different configurations of the third region 21 and the fourth region 22. In Embodiment 3, the third region 21 has a first thickness Th3, which can be set to 3600-5100 nm. The fourth region 22 has a second thickness Th4, which can be set to 2000-3500 nm. The rest of the structure of the UV LED is the same as in Embodiments 1 and 2 and will not be further described here.

[0081] In this embodiment, the E2 (high) phonon mode peak shift of the third region of the template layer 2 is ≥657.4 cm-1, and the E2 (high) phonon mode peak shift of the fourth region of the template layer 2 is <657.4 cm-1. Exemplarily, the third region 21 includes the first template sublayer, the seventh template sublayer and the eighth template sublayer 226; the fourth region 22 includes the first template sublayer and the seventh template sublayer. The growth temperature of the seventh template sublayer and the eighth template sublayer 226 is higher than the growth temperature of the first template sublayer. The first template sublayer and the seventh template sublayer cover both the third region 21 and the fourth region 22, and the eighth template sublayer 226 is only located in the third region 21. The first template sublayer is an AlN layer with a thickness of 200nm to 450nm and grown at 900℃ to 1100℃. The seventh template sublayer is an AlN layer with a thickness of 1798 nm to 3037 nm and grown at 1150° C. to 1300° C., and the eighth template sublayer 226 is an AlN layer with a thickness of 200 nm to 1600 nm and grown at 1150° C. to 1300° C.

[0082] The main difference between the steps of the preparation method of this embodiment and the preparation method of embodiment 1 is that step S101 replaces step S100, and step S202 replaces step S200. Please refer to Figures 26-32, which illustrate the preparation method of the template layer in this embodiment.

[0083] Specifically, step S101: providing a substrate 1. The material of the substrate 1 is as described above and will not be repeated here.

[0084] Step S202: Forming a Template Layer: Referring to FIG. 26 , a first buffer layer (not shown) with a thickness of 2 nm to 13 nm is deposited on substrate 1. The first buffer layer may be composed of AlN. Exemplarily, the first buffer layer may be formed by magnetron sputtering. The magnetron sputtering process parameters are: sputtering power of 3300 to 4000 W, N2 flow rate of 70 sccm to 95 sccm, Ar flow rate of 1 sccm to 4 sccm, and temperature of 700 to 750°C. A first template sublayer (not shown) is deposited on the first buffer layer. The first template sublayer may be an AlN layer grown at a medium temperature with a thickness of 200 nm to 450 nm. The growth process for the first template sublayer is: NH3 flow rate of 1 SLM to 5 SLM, TMAl flow rate of 200 to 300 umol / min, pressure of 45 torr torr, temperature of 900 to 1100°C, and H2 flow rate of 30 to 60 SLM. A seventh template sublayer (not shown) is deposited on the first template sublayer. The thickness of the seventh template sublayer may be 1798 nm to 3037 nm. For example, the seventh template sublayer may be deposited by MOCVD. The process parameters in the MOCVD deposition process may be: NH3 flow rate of 20-1000 sccm, TMAl flow rate of 150 umol / min to 220 umol / min, pressure of 25 torr to 50 torr, temperature of 1150°C to 1300°C, and H2 flow rate of 45 SLM to 100 SLM. The first template sublayer and the seventh template sublayer constitute the template base layer 225 as described in FIG26. As shown in FIG27, a fourth mask 400 is formed on the fourth region 22. The thickness of the fourth mask 400 may be set to 200 nm to 1600 nm. The fourth mask 400 may be composed of silicon dioxide (SiO2). Then, as shown in FIG28 , an eighth template sublayer 226 is deposited with a thickness of 200 to 1600 nm. The eighth template sublayer 226 can be composed of high-temperature grown AlN. The process parameters for the eighth template sublayer 226 can be the same as those for the seventh template sublayer. The thickness of the eighth template sublayer 226 can be grown to be flush with the upper surface of the fourth mask 400. Then, as shown in FIG29 , the fourth mask layer 400 is removed, exemplarily using an ICP process, to form the template layer 2.

[0085] Step S301: Forming a structural stack: In the step of forming the structural stack, this embodiment differs from the first embodiment mainly in the formation of the first semiconductor layer 3, and the other steps are the same.

[0086] Specifically, referring to FIG29 , a fifth mask layer 500 is formed at the third region 21 , and the thickness of the fifth mask layer 500 is set to 100-200 nm. As shown in FIG30 , a first sublayer 31 of the first semiconductor layer 3 is grown, and the first sublayer 31 can be an N-type Al x Ga 1-x The N layer has an x ​​value of 0.55 to 0.7 and a thickness of 200 nm to 1600 nm. The doping concentration of the n-type impurity Si is 1E19 cm -3 ~1E20cm -3 The growth process parameters are: temperature 1000℃~1100℃, pressure 40torr~80torr, TMAl flow rate 260umol / min~300umol / min, TMGa flow rate 200umol / min~160umol / min, NH3 flow rate 4000sccm~8000sccm, SiH4 flow rate 2.6E-8mol / min~2.6E-9mol / min, pure H2 carrier gas, H2 flow rate 30SLM~80SLM, growth time 12.5min~100min. As shown in FIG32 , the second sublayer 32 of the first semiconductor layer 3 is deposited on the template layer 2. The second sublayer 32 is 400nm~800nm ​​of N-type Al. x Ga 1-x N layer (x value is 0.55-0.7), where N-type impurities can be Si atoms, and the Si atom doping concentration is 1E19cm -3 ~1E20cm -3 Exemplary growth process parameters include: 1000°C to 1100°C, pressure of 40 torr to 80 torr, TMAl (trimethylaluminum) flow rate of 260 to 300 umol / min, TMGa (trimethylgallium) flow rate of 200 to 160 umol / min, NH3 flow rate of 4000 to 8000 sccm, SiH4 flow rate of 2.6E-8 to 2.6E-9 mol / min, pure H2 carrier gas, H2 flow rate of 30 to 80 slm, and growth time of 50 to 100 minutes. Subsequent structural stacking and other fabrication steps are then performed on the second sublayer 32.

[0087] In this embodiment, the thickness, growth temperature and position of the template sublayer are controlled separately by selective epitaxy, and template sublayers of different thicknesses are formed in different areas within the template layer, thereby controlling the stress state in the corresponding areas of the template layer. Specifically, in the template area corresponding to the P electrode, the thickness is thinner and exhibits tensile stress, while in the template area corresponding to the N electrode, the thickness is thicker and exhibits compressive stress. Thus, high-performance ultraviolet light-emitting diodes can be ultimately prepared. It can be further understood that the template layer 2 in this embodiment can be further coordinated with the patterned substrate 1 in the first embodiment to better obtain a composite carrier with different stress states, thereby obtaining an N-type layer, a P-type layer and a P-type contact layer with different stress states, and better obtaining the technical effects described above.

[0088] In summary, from the above detailed description, it can be seen that the light-emitting diode provided by the present disclosure has the following excellent characteristics:

[0089] 1) By providing different surface states on the substrate regions corresponding to the N-electrode and P-electrode, and in particular introducing tensile stress in the substrate region corresponding to the P-electrode, the buffer layer on the substrate surface has a low dislocation density and improves light extraction efficiency, while also increasing the polarization electric field within the P-type layer, thereby improving the activation efficiency of holes and the hole concentration. This not only reduces the voltage on the P-side and improves the current expansion capability of the P-type layer, but also increases the luminous intensity. 2) By transferring the tensile stress on the composite substrate to the P-type layer, there is no need to increase the doping level of acceptor impurities in the P-type layer, which prevents the introduction of excessive impurities and avoids degrading the crystal quality of the material. This improves the light maintenance rate during long-term aging, protects the chip from being significantly affected by temperature changes, and improves product stability. 3) There is no need to increase the thickness of the N-type layer to reduce the resistance of the N-type layer, thus avoiding substrate warping, improving the wavelength uniformity of the device, reducing the difficulty of chip processing, and improving product yield. 4) By setting different stress devices in different areas, the resistance of the P-type layer or the N-type layer is avoided from increasing, the saturation current and saturation power are increased, the operating voltage is reduced, and the ability to be used in overdrive is improved. When used under overdrive conditions, the leakage current is not likely to increase during the aging process.

[0090] The semiconductor device disclosed herein can be used in electronic devices in the fields of industrial curing, medical equipment, biochemical testing, lighting sterilization, Internet of Things, consumer electronics, and the like.

[0091] The present disclosure has been described above in conjunction with specific embodiments. However, it should be clear to those skilled in the art that these descriptions are exemplary only and are not intended to limit the scope of protection of the present disclosure. Those skilled in the art may make various variations and modifications to the present disclosure based on the spirit and principles of the present disclosure, and such variations and modifications are also within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A composite carrier, the composite carrier comprising a substrate and a template layer, the composite carrier comprising a region with tensile stress and a region with compressive stress; Active layer, for recombination of injected carriers; A first semiconductor layer, used for injecting N-type carriers into the active layer; A second semiconductor layer, used for injecting P-type carriers into the active layer, wherein the second semiconductor layer is a metal nitride with cations selected from element period IIIA; A first electrode, used for energy transmission of the first semiconductor layer, wherein a projection of the first electrode on the upper surface of the composite carrier falls within the region of the compressive stress or coincides with the region; The second electrode is used for energy transmission of the second semiconductor layer, and the projection of the second electrode on the upper surface of the composite carrier falls within the region of the tensile stress or coincides with it.

2. The semiconductor device according to claim 1, characterized in that : The phonon mode peak shift in the tensile stress region is less than 657.4 cm -1 , the phonon mode peak shift in the compressive stress region is ≥657.4cm -1 .

3. The semiconductor device according to claim 1 or 2, characterized in that: The substrate includes a first region with a first surface state and a second region with a second surface state, the first region corresponds to the compressive stress region of the composite carrier, and the second region corresponds to the tensile stress region of the composite carrier.

4. The semiconductor device according to claim 3, wherein: The roughness of the first surface state is greater than the roughness of the second surface state.

5. The semiconductor device according to claim 4, wherein: The first surface state is a surface state having nanopatterns of a first size, and the second surface state is a flat surface state without nanopatterns; Alternatively, the first surface state is a surface state having nanopatterns of a first size, and the second surface state is a surface state having nanopatterns of a second size.

6. The semiconductor device according to claim 5, wherein: The distribution density of the first size nano-pattern is 70-200 / 100um 2 , its radius is set to 350nm~600nm, and its depth is set to 300nm~700nm.

7. The semiconductor device according to claim 5 or 6, characterized in that: The distribution density of the second size nano-pattern is 400 to 2500 per 100 um. 2 , its radius is set to 100nm~250nm, and its depth is set to 50nm~500nm.

8. The semiconductor device according to claim 5, wherein: The template layer includes a first template sublayer and a second template sublayer. The growth temperature of the first template sublayer is lower than the growth temperature of the second template sublayer. The thickness of the template layer is 1700nm-2950nm.

9. The semiconductor device according to claim 1, 2 or 4, characterized in that: The template layer includes a third region and a fourth region, the third region corresponds to the compressive stress region of the composite carrier, and the fourth region corresponds to the tensile stress region of the composite carrier.

10. The semiconductor device according to claim 9, wherein: The third region has an air gap with a first height, and the fourth region has an air gap with a second height, wherein the first height is greater than the second height.

11. The semiconductor device according to claim 10, wherein: The first height is 450-1000 nm, and the second height is 200-430 nm.

12. The semiconductor device according to claim 10 or 11, characterized in that: The third region includes a fourth template sublayer and a sixth template sublayer; the fourth region includes a third template sublayer, a fifth template sublayer and a sixth template sublayer.

13. The semiconductor device according to claim 12, wherein: The thickness of the fourth template sub-layer is equal to the total thickness of the third template sub-layer and the fifth template sub-layer.

14. The semiconductor device according to claim 13, wherein: The growth temperature of the sixth template sublayer is higher than that of the fourth template sublayer and the third template sublayer, and the temperature of the fifth template sublayer is higher than that of the fourth template sublayer and the third template sublayer.

15. The semiconductor device according to claim 14, wherein: The third template sublayer is an AlN layer with a thickness of 100 to 300 nm and grown at 900° C. to 1100° C.

16. The semiconductor device according to claim 15, wherein: The fourth template sublayer is an AlN layer with a thickness of 400-800 nm and grown at 900° C.-1100° C., and the fifth template sublayer is an AlN layer with a thickness of 300-500 nm and grown at 1150° C.-1300° C.

17. The semiconductor device according to claim 15 or 16, characterized in that: The sixth template sublayer covers both the third region and the fourth region and is an AlN layer grown at 1150° C. to 1300° C.

18. The semiconductor device according to claim 9, wherein: The third region has a first thickness, and the fourth region has a second thickness, wherein the first thickness is greater than the second thickness.

19. The semiconductor device according to claim 18, wherein: The first thickness is 3600-5100 nm, and the second thickness is 2000-3500 nm.

20. The semiconductor device according to claim 18 or 19, characterized in that: The third region includes the first template sublayer, the seventh template sublayer and the eighth template sublayer; the fourth region includes the first template sublayer and the seventh template sublayer.

21. The semiconductor device according to claim 20, wherein: The growth temperature of the seventh template sublayer and the eighth template sublayer is higher than the growth temperature of the first template sublayer.

22. The semiconductor device according to claim 21, wherein: The first template sublayer and the seventh template sublayer cover the third area and the fourth area at the same time, and the eighth template sublayer is only located in the third area.

23. The semiconductor device according to claim 21, wherein: The first template sublayer is an AlN layer with a thickness of 200nm to 450nm and grown at 900°C to 1100°C.

24. The semiconductor device according to claim 23, wherein: The seventh template sublayer is an AlN layer with a thickness of 1798nm to 3037nm and grown at 1150°C to 1300°C, and the eighth template sublayer is an AlN layer with a thickness of 200nm to 1600nm and grown at 1150°C to 1300°C.

25. The semiconductor device according to any one of claims 1-2, 4-6, 8, 10-11, 13-16, 18-19, 21-24, characterized in that: The thickness of the first semiconductor layer is 800-1600 nm.

26. The semiconductor device according to claim 25, wherein: The thickness of the second semiconductor layer is 10-30 nm, and the doping concentration of the acceptor impurity in the second semiconductor layer is 1E18 cm -3 ~1E20cm -3 .

27. The semiconductor device according to claim 26, wherein: The invention further comprises a third semiconductor layer, the third semiconductor layer serving as an ohmic contact layer of the second semiconductor layer, the thickness of the third semiconductor layer being 1 to 50 nm, and the doping concentration of the acceptor impurity in the third semiconductor layer being 1E19 cm -3 ~1E21cm -3 .

28. A method for preparing a semiconductor device, characterized in that: include: A composite carrier is provided, the composite carrier comprising a substrate and a template layer, a stress and areas with compressive stress; forming a first semiconductor layer on the composite carrier, wherein the first semiconductor layer includes N-type carriers; forming an active layer on the first semiconductor layer; forming a second semiconductor layer on the active layer, wherein the second semiconductor layer includes P-type carriers, wherein the second semiconductor layer is a metal nitride with cations selected from element period IIIA; forming a first electrode on the first semiconductor layer, wherein a projection of the first electrode on the upper surface of the composite carrier falls within the region of the compressive stress or coincides with the region; A second electrode is formed on the second semiconductor layer, and a projection of the second electrode on the upper surface of the composite carrier falls within the region of the tensile stress or coincides with the region of the tensile stress.

29. The preparation method according to claim 28, characterized in that: A first region with a first surface state and a second region with a second surface state are formed in the substrate, the first region corresponding to a region of compressive stress of the composite carrier and the second region corresponding to a region of tensile stress of the composite carrier.

30. The preparation method according to claim 29, characterized in that: The roughness of the first surface state is greater than the roughness of the second surface state.

31. The preparation method according to claim 30, characterized in that: Etching the first region to form a surface state having a nano-pattern of a first size, and etching the second region to form a flat surface state without a nano-pattern; Alternatively, the first region is etched to form a surface state having a nano-pattern of a first size, and the second region is etched to form a surface state having a nano-pattern of a second size.

32. The preparation method according to any one of claims 28 to 31, characterized in that: A third region and a fourth region are formed in the template layer, the third region corresponds to a region of compressive stress of the composite carrier, and the fourth region corresponds to a region of tensile stress of the composite carrier.

33. The preparation method according to claim 32, characterized in that: The step of forming the third region and the fourth region in the template layer comprises: forming a first mask, wherein the first mask covers the third area; Depositing a second buffer layer, and growing a third template sublayer on a surface of the second buffer layer; removing the first mask and forming a second mask on the third template sublayer; Depositing a third buffer layer, and growing a fourth template sublayer on the surface of the third buffer layer; removing the second mask and forming a third mask on the fourth template sublayer; forming a fifth template sublayer on the third template sublayer so that an upper surface of the fifth template sublayer is flush with an upper surface of the fourth template sublayer; The third mask is removed, and a sixth template sublayer is deposited on the upper surfaces of the fifth template sublayer and the fourth template sublayer.

34. The preparation method according to claim 33, characterized in that: The third template sublayer is an AlN layer with a thickness of 100-300nm, and its growth process parameters include: the flow rate of reaction gas NH3 is 1SLM~5SLM, the flow rate of reaction gas TMAl is 200umol / min~300umol / min, the reaction pressure is 45torr~60torr, the temperature is 900℃~1100℃, and the flow rate of H2 is 30SLM~60SLM.

35. The preparation method according to claim 34, characterized in that: The fourth template sublayer is an AlN layer with a thickness of 400-800nm, and its growth process parameters include: the flow rate of reaction gas NH3 is 1SLM~5SLM, the flow rate of reaction gas TMAl is 200umol / min~300umol / min, the reaction pressure is 45torr~60torr, the temperature is 900℃~1100℃, and the flow rate of H2 is 30SLM~60SLM.

36. The preparation method according to claim 35, characterized in that: The fifth template sublayer is an AlN layer with a thickness of 300-500nm, and its growth process parameters include: the flow rate of reaction gas NH3 is 20-1000sccm, the flow rate of reaction gas TMAl is 150umol / min~220umol / min, the reaction pressure is 25torr~50torr, the temperature is 1150℃~1300℃, and the flow rate of H2 is 45SLM~100SLM.

37. The preparation method according to claim 36, characterized in that: The sixth template sublayer is an AlN layer, and its growth process parameters include: NH3 flow rate 20-1000 sccm, TMAl flow rate 150umol / min~220umol / min, reaction pressure 25torr~50torr, temperature 1150℃~1300℃, and H2 flow rate 45SLM~100SLM.

38. The preparation method according to claim 32, characterized in that: The step of forming the third region and the fourth region in the template layer comprises: forming a first buffer layer on the substrate; forming a first template sublayer on a surface of the first buffer layer; forming a seventh template sub-layer on the surface of the first template sub-layer; forming a fourth mask, wherein the fourth mask covers the fourth region; An eighth template sub-layer is deposited, wherein the upper surface of the eighth template sub-layer is flush with the upper surface of the fourth mask.

39. The preparation method according to claim 38, characterized in that: The first template sublayer is an AlN layer with a thickness of 200 to 450 nm, and its growth process parameters include: the flow rate of reaction gas NH3 is 1SLM to 5SLM, the flow rate of reaction gas TMAl is 200umol / min to 300umol / min, the reaction pressure is 45torr to 60torr, the temperature is 900℃ to 1100℃, and the flow rate of H2 is 30SLM to 60SLM.

40. The preparation method according to claim 39, characterized in that: The seventh template sublayer is an AlN layer with a thickness of 1798nm to 3037nm, and its growth process parameters include: the flow rate of the reaction gas NH3 is 20-1000sccm, the flow rate of the reaction gas TMAl is 150umol / min to 220umol / min, the reaction pressure is 25torr to 50torr, the temperature is 1150℃ to 1300℃, and the flow rate of H2 is 45SLM to 100SLM.

41. The preparation method according to claim 40, characterized in that: The eighth template sublayer is an AlN layer with a thickness of 200 to 1600 nm, and its growth process parameters include: the flow rate of the reaction gas NH3 is 20-1000 sccm, the flow rate of the reaction gas TMAl is 150umol / min to 220umol / min, the reaction pressure is 25torr to 50torr, the temperature is 1150℃ to 1300℃, and the flow rate of H2 is 45SLM to 100SLM.

42. The preparation method according to claim 40, characterized in that: The sum of the thickness of the first template sublayer and the seventh template sublayer is 2000-3500 nm.

43. The preparation method according to claim 42, characterized in that: removing the fourth mask, forming a fifth mask, wherein the fifth mask covers the third region; forming a first sublayer of a first semiconductor layer, wherein an upper surface of the first sublayer of the first semiconductor layer is flush with an upper surface of the eighth template sublayer; A second sublayer of the first semiconductor layer is formed, wherein the second sublayer of the first semiconductor layer covers the third region and the fourth region at the same time.

44. The preparation method according to claim 43, characterized in that: The thickness of the second sublayer of the first semiconductor layer is 400 nm to 800 nm.

45. The preparation method according to claim 44, characterized in that: The thickness of the second semiconductor layer is 10-30 nm, and the doping concentration of the acceptor impurity in the second semiconductor layer is 1E18 cm -3 ~1E20cm -3 .

46. ​​The preparation method according to claim 45, characterized in that: The method further includes forming a third semiconductor layer on the second semiconductor, wherein the thickness of the third semiconductor layer is 1 to 50 nm, and the doping concentration of the acceptor impurity in the third semiconductor layer is 1E19 cm -3 ~1E21cm -3 .

47. An electronic device, characterized in that: The electronic device comprises the semiconductor device according to any one of claims 1 to 27.

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