Semiconductor device, semiconductor module, and wireless communication apparatus

Abstract

A first semiconductor device according to an embodiment of the present disclosure comprises: a substrate; a channel layer provided on one surface side of the substrate and including a first nitride semiconductor; a barrier layer provided on the opposite side of the channel layer from the substrate, and having a first surface facing the channel layer and a second surface opposite to the first surface, the barrier layer including a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; an intermediate layer provided in the barrier layer and including a semiconductor material having an etching rate lower than that of the barrier layer; a gate electrode provided on the second surface side of the barrier layer; a drain electrode and a source electrode provided on the second surface side of the barrier layer with the gate electrode therebetween; and a recess provided between the gate electrode and the drain electrode and reaching the intermediate layer from the second surface side of the barrier layer.

Description

Semiconductor device, semiconductor module, and wireless communication device

[0001] The present disclosure relates to a semiconductor device, a semiconductor module, and a wireless communication device.

[0002] For example, Patent Document 1 discloses a semiconductor device in which a recess is formed in a channel layer from below a gate electrode to the drain electrode side.

[0003] Japanese Patent Application Laid-Open No. 2003-59947

[0004] Incidentally, there is a demand for improved device characteristics in HEMTs.

[0005] It is desirable to provide a semiconductor device, a semiconductor module, and a wireless communication device that can improve device characteristics.

[0006] A first semiconductor device according to an embodiment of the present disclosure includes a substrate, a channel layer including a first nitride semiconductor provided on one surface of the substrate, a barrier layer provided on the side of the channel layer opposite the substrate, the barrier layer having a first surface facing the channel layer and a second surface opposite the first surface, the barrier layer including a second nitride semiconductor having a larger band gap than the first nitride semiconductor, an intermediate layer provided in the barrier layer and including a semiconductor material having a lower etching rate than the barrier layer, a gate electrode provided on the second surface of the barrier layer, a drain electrode and a source electrode provided on the second surface of the barrier layer with the gate electrode in between, and a recess provided between the gate electrode and the drain electrode and reaching from the second surface of the barrier layer to the intermediate layer.

[0007] A semiconductor module according to an embodiment of the present disclosure includes the first semiconductor device according to the embodiment of the present disclosure.

[0008] A wireless communication device according to an embodiment of the present disclosure includes the first semiconductor device according to the embodiment of the present disclosure.

[0009] A second semiconductor device according to an embodiment of the present disclosure includes a substrate, a channel layer including a first nitride semiconductor provided on one side of the substrate, a barrier layer provided on the side of the channel layer opposite the substrate, the barrier layer having a first surface facing the channel layer and a second surface opposite the first surface, the barrier layer including a second nitride semiconductor having a larger band gap than the first nitride semiconductor, an intermediate layer provided in the barrier layer and including a semiconductor material having a lower etching rate than the barrier layer, a gate electrode provided on the second surface side of the barrier layer, a drain electrode and a source electrode provided on the second surface side of the barrier layer with the gate electrode between them, and a two-dimensional electron gas layer formed in the vicinity of the interface between the channel layer and the barrier layer, the two-dimensional electron gas layer having a low electron gas region between the gate electrode and the drain electrode and having a lower electron gas concentration than between the gate electrode and the source electrode.

[0010] In a first and second semiconductor device according to an embodiment of the present disclosure, a semiconductor module according to an embodiment, and a wireless communication device according to an embodiment, an intermediate layer including a semiconductor material having a lower etching rate than the barrier layer is provided in a barrier layer including a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor and stacked on a channel layer including a first nitride semiconductor. A recess is provided between the gate electrode and the drain electrode, extending from the surface (second surface) of the barrier layer opposite the surface facing the channel layer to the intermediate layer. A two-dimensional electron gas layer is formed near the interface between the channel layer and the barrier layer. This configuration results in a lower electron gas concentration between the gate electrode and the drain electrode than between the gate electrode and the source electrode. This reduces parasitic capacitance between the gate electrode and the drain electrode without damaging the barrier layer.

[0011] FIG. 1 is a cross-sectional view schematically illustrating an example of a configuration of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a characteristic diagram illustrating an electron gas concentration between a source electrode and a drain electrode. FIG. 3 is a characteristic diagram illustrating a relationship between a film thickness ratio of a barrier layer between a gate electrode and a source electrode and between a gate electrode and a drain electrode, and a parasitic capacitance between the gate electrode and the drain electrode. FIG. 4 is a characteristic diagram illustrating a relationship between an electron gas concentration and a threshold voltage. FIG. 5A is a cross-sectional view schematically illustrating an example of a process of a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 5B is a cross-sectional view schematically illustrating a process subsequent to FIG. 5A. FIG. 5C is a cross-sectional view schematically illustrating a process subsequent to FIG. 5B. FIG. 5D is a cross-sectional view schematically illustrating a process subsequent to FIG. 5C. FIG. 5E is a cross-sectional view schematically illustrating a process subsequent to FIG. 5D. FIG. 6 is a cross-sectional view schematically illustrating a detailed shape of a damage prevention layer in a recess. FIG. 7 is a cross-sectional view schematically illustrating an example of a configuration of a semiconductor device as a comparative example. FIG. 8 is a cross-sectional view schematically illustrating an example of a configuration of a semiconductor device according to a first modification of the present disclosure. FIG. 9 is a cross-sectional view schematically illustrating an example of a configuration of a semiconductor device according to a second modification of the present disclosure. Fig. 10 is a schematic perspective view showing the configuration of a semiconductor module, and Fig. 11 is a block diagram showing the configuration of a wireless communication device.

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The following description is one specific example of the present disclosure, and the present disclosure is not limited to the following embodiment. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of each component shown in each drawing.

[0013] The description will be given in the following order: 1. Embodiment (Example of semiconductor device having a damage prevention layer in a barrier layer) 1-1. Configuration of semiconductor device 1-2. Method for manufacturing semiconductor device 1-3. Actions and effects 2. Modifications 2-1. Modification 1 (Another example of semiconductor device configuration) 2-2. Modification 2 (Another example of semiconductor device configuration) 3. Application examples 3-1. Application example to semiconductor module 3-2. Application example to wireless communication device

[0014] 1. Embodiments 1-1. Configuration of Semiconductor Device FIG. 1 is a schematic diagram illustrating an example of a cross-sectional configuration of a semiconductor device (semiconductor device 1) according to an embodiment of the present disclosure.

[0015] The semiconductor device 1 has a layered structure in which a substrate 11, a buffer layer 12, a channel layer 13, a spacer layer 14, and a barrier layer 15 are layered in this order. The semiconductor device 1 further has a gate electrode G provided on the barrier layer 15, a pair of contact layers 16 arranged opposite each other in the in-plane direction (XY plane direction) of the substrate 11 with the gate electrode G therebetween, a source electrode S and a drain electrode D provided on the contact layer 16, and an insulating film Z provided on the barrier layer 15 between the gate electrode G and the source electrode S and the drain electrode D. The semiconductor device 1 has, for example, a Schottky gate structure.

[0016] The semiconductor device 1 is a high electron mobility transistor (HEMT) that uses a two-dimensional electron gas layer (2DEG) as a channel. The two-dimensional electron gas layer (2DEG) is generated due to a difference in the magnitude of polarization between the channel layer (13) and the barrier layer (15). The two-dimensional electron gas layer (2DEG) is generated in the channel layer (13), for example, near the interface with the spacer layer (14).

[0017] In this embodiment, the barrier layer 15 includes a damage prevention layer 15B having an etching rate lower than that of the barrier layer 15. Specifically, the barrier layer 15 has a stacked structure in which a first layer 15A, a damage prevention layer 15B, and a second layer 15C are stacked in this order, and the damage prevention layer 15B has an etching rate lower than that of the first layer 15A and the second layer 15C. The barrier layer 15 further includes a recess H between the gate electrode G and the drain electrode D, the recess H penetrating the second layer 15C from the surface 15S2 side of the barrier layer 15 and reaching the damage prevention layer 15B. As a result, the electron gas concentration constituting the two-dimensional electron gas layer 2DEG formed in the channel layer 13 below the recess H near the interface with the spacer layer 14 is lower than the electron gas concentration in other regions (e.g., a region Lgs between the gate electrode G and the source electrode S and a region Lgd between the gate electrode G and the drain electrode D outside the recess H).

[0018] Each component of the semiconductor device 1 will be described in detail below.

[0019] The substrate 11 is a support for the semiconductor device 1. The substrate 11 is, for example, a compound semiconductor substrate. Specifically, the substrate 11 is, for example, a semi-insulating single-crystal GaN substrate containing a III-V group compound semiconductor material. Alternatively, the substrate 11 may be, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, or an aluminum nitride (AlN) substrate. A suitable Si substrate is, for example, a single-crystal Si(111) substrate having a (111) plane as its main surface. The semiconductor device 1 includes a buffer layer 12 as described above. The buffer layer 12 can reduce the mismatch between the lattice constant of the substrate 11 and the lattice constant of the channel layer 13. Therefore, the substrate 11 may be made of a material with a lattice constant different from that of the channel layer 13.

[0020] The substrate 11 made of the above materials can provide the effects of the semiconductor device of the present disclosure described below. The semiconductor device 1 using a substrate made of SiC or GaN, which has better single crystallinity than Si(111) and a lower threading dislocation density, can be expected to further reduce off-leak current and increase breakdown voltage. Therefore, the substrate 11 can be constructed by selecting a suitable material depending on the application, etc.

[0021] The buffer layer 12 is made of an epitaxially grown compound semiconductor. When the lattice constants of the substrate 11 and the channel layer 13 are different, the lattice mismatch between the substrate 11 and the channel layer 13 can be alleviated by controlling the lattice constant of the surface of the buffer layer 12 on which the channel layer 13 is provided. Therefore, the buffer layer 12 can improve the crystalline state of the channel layer 13 and suppress warping of the substrate 11. The buffer layer 12 is made of, for example, a nitride semiconductor. Specifically, when the substrate 11 is a single-crystal Si substrate and the channel layer is made of GaN, the buffer layer 12 is made of, for example, AlN, AlGaN (aluminum gallium nitride), GaN, or the like.

[0022] Depending on the configuration of the substrate 11 and the channel layer 13, the buffer layer 12 may be omitted.

[0023] The channel layer 13 constitutes a part of the current path between the source electrode S and the drain electrode D. The channel layer 13 is made of a nitride semiconductor having a band gap smaller than the band gap of the spacer layer 14 and the band gap of the barrier layer 15. The channel layer 13 is provided on the buffer layer 12. The channel layer 13 can accumulate carriers at the interface on the barrier layer 15 side due to the difference in the magnitude of polarization between the channel layer 13 and the barrier layer 15.

[0024] The channel layer 13 is made of an epitaxially grown nitride semiconductor, such as gallium nitride (GaN). The channel layer 13 may be made of undoped u-GaN, which is not doped with impurities. This allows the channel layer 13 to suppress impurity scattering of carriers and further increase carrier mobility.

[0025] The spacer layer 14 is made of a nitride semiconductor having a band gap larger than that of the channel layer 13. The spacer layer 14 is provided on the channel layer 13. The spacer layer 14 reduces alloy scattering between the barrier layer 15 and the channel layer 13, and suppresses a decrease in carrier mobility in the two-dimensional electron gas layer 2DEG due to the alloy scattering.

[0026] The spacer layer 14 is an epitaxially grown Al ｘ１ In ｙ１ Ga （１－ｘ１－ｙ１） N (0<x1≦1, 0≦y1<1, 0≦x1+y1≦1). The spacer layer 141 may be made of, for example, a binary nitride semiconductor such as AlN, a ternary nitride semiconductor such as AlGaN, or a quaternary nitride semiconductor such as AlInGaN.

[0027] The thickness of the spacer layer 14 is preferably, for example, 0.26 nm or more and 3.0 nm or less, and particularly preferably 0.5 nm or more and 1.5 nm or less. When the thickness of the spacer layer 14 is 0.26 nm or more, the spacer layer 14 is expected to be more effective in suppressing alloy scattering. On the other hand, when the thickness of the spacer layer 14 is 3.0 nm or less, the spacer layer 14 can more appropriately control the band gap profile of the semiconductor device 1. This allows for a further increase in the carrier density of the two-dimensional electron gas layer 2DEG generated in the channel layer 13.

[0028] The barrier layer 15 is made of a nitride semiconductor having a band gap larger than that of the channel layer 13. The barrier layer 15 is provided on the spacer layer 14. The barrier layer 15 can accumulate carriers in a region of the channel layer 13 near the barrier layer 15 due to spontaneous polarization or piezoelectric polarization. This allows the semiconductor device 1 to form a two-dimensional electron gas layer 2DEG with high mobility and high carrier concentration in a region of the channel layer 13 near the interface with the barrier layer 15 (here, near the interface with the spacer layer 14).

[0029] The barrier layer 15 is an epitaxially grown nitride semiconductor, Al ｘ２ In １―ｘ２ The barrier layer 15 is made of, for example, undoped u-Al (0<x2<1). ｘ３ In （１－ｘ３） The barrier layer 15 may be made of AlN, which is an epitaxially grown nitride semiconductor. （１－ｘ２－ｙ２） In ｘ２ Ga ｙ２ The barrier layer 15 may be made of, for example, undoped u-Al, which is not doped with impurities. （１－ｘ２－ｙ２） In ｘ２ Ga ｙ２ The barrier layer 15 may be made of N. In this case, the barrier layer 15 can suppress impurity scattering of carriers in the channel layer 13, and can further increase the mobility of carriers.

[0030] The carrier density of the two-dimensional electron gas layer 2DEG can be controlled, for example, by the band gap profile of each layer from the barrier layer 15 to the channel layer 13. One factor that determines the carrier density of the two-dimensional electron gas layer 2DEG is the height of the conduction band minimum of the barrier layer 15.

[0031] For example, the higher the Al composition of each layer, the greater the polarization of each layer. Therefore, the slope of the conduction band minimum becomes steeper. Furthermore, the thicker each layer becomes, the higher the height of the conduction band minimum becomes. Therefore, by appropriately controlling the thickness and composition of each layer from the barrier layer 15 to the channel layer 13 and controlling the height of the conduction band minimum of the barrier layer 15, the carrier density of the two-dimensional electron gas layer 2DEG can be increased.

[0032] For example, the barrier layer 15 is made of Al, which constitutes the spacer layer 14. ｘ１ In ｙ１ Ga （１－ｘ１－ｙ１） Al with a higher Al composition ratio than N ｘ２ In （１－ｘ２） N. That is, by forming the barrier layer 15 from a nitride semiconductor such that x1 < x2 with respect to the spacer layer 14, a larger polarization can be obtained. This allows for a higher carrier concentration in the two-dimensional electron gas layer 2DEG. The barrier layer 15 is formed from, for example, a ternary nitride semiconductor such as AlInN. Alternatively, the barrier layer 15 may be formed from, for example, a binary nitride semiconductor such as AlN, a ternary nitride semiconductor such as AlGaN, or a quaternary nitride semiconductor such as AlInGaN. When the barrier layer 15 is formed from AlInGaN, a certain design margin can be obtained for the band gap and strain amount. Furthermore, the inclusion of Ga in the barrier layer 15 improves the single crystallinity of the barrier layer 15.

[0033] In this embodiment, as described above, the barrier layer 15 has a three-layer structure in which the first layer 15A, the damage prevention layer 15B, and the second layer 15C are stacked in this order. The first layer 15A, the damage prevention layer 15B, and the second layer 15C can be formed by continuous crystal growth.

[0034] The damage prevention layer 15B corresponds to a specific example of an "intermediate layer" in the embodiment of the present disclosure. The damage prevention layer 15B functions as an etching stopper layer when forming a recess H between the gate electrode G and the drain electrode D by dry etching, for example, and is made of a compound semiconductor having a lower etching rate than the first layer 15A and the second layer 15C. For example, the damage prevention layer 15B contains Al, and the Al composition is lower than that of the other layers (the first layer 15A and the second layer 15C) constituting the barrier layer 15. Furthermore, the damage prevention layer 15B contains In, and the In composition is higher than that of the other layers (the first layer 15A and the second layer 15C) constituting the barrier layer 15.

[0035] Specifically, the other layers (first layer 15A and second layer 15C) constituting the barrier layer 15 are Al. ｘ２ In （１－ｘ２） When the damage prevention layer 15B is made of N (0<x2<1), the damage prevention layer 15B is made of Al ｚ２ In （１－ｚ２） N (0<z2<1). Here, the composition of Al satisfies x2>Z2. In addition, other layers (first layer 15A and second layer 15C) constituting the barrier layer 15 are Al. ｘ２ In （１－ｘ２） When the damage prevention layer 15B is made of In (0<x2<1), ｗ２ Ga （１－ｗ２） N (0<w2<1). Here, the composition of Al satisfies 1-x2>w2. Alternatively, other layers (first layer 15A and second layer 15C) constituting the barrier layer 15 may be Al. （１－ｘ２－ｙ２） In ｘ２ Ga ｙ２ When the damage prevention layer 15B is made of AlN (0≦x2<1, 0≦y2<1, x2+y2≦1), （１－ｚ２－ｗ２） In ｚ２ Ga ｗ２ N (0≦z2<1, 0≦w2<1, z2+w2≦1), where the Al composition satisfies 1−x2−y2>1−z2−w2, and the In composition satisfies x2<z2.

[0036] 1 , the barrier layer 15 has a recess H between the gate electrode G and the drain electrode D, which extends from the surface 15S2 side of the barrier layer 15 through the second layer 15C and reaches the damage prevention layer 15B. As will be described in detail later, the damage prevention layer 15B is exposed at the bottom of the recess H, and the thickness of the damage prevention layer 15B exposed at the bottom of the recess H is thinner than the thickness of the damage prevention layer 15B covered by the second layer 15C. In this way, the electron gas concentration of the two-dimensional electron gas layer 2DEG in the region X where a portion of the barrier layer 15 is removed and the thickness of the barrier layer 15 is reduced is lower than that in other regions.

[0037] In this embodiment, the recess H is formed between the gate electrode G and the drain electrode D. The position of the recess H between the gate electrode G and the drain electrode D is preferably closer to the gate electrode G, for example. This can suppress deterioration of device characteristics due to increased contact resistance between the contact layer 16 on which the drain electrode D is stacked and the two-dimensional electron gas layer 2DEG. Specifically, the end of the recess H on the gate electrode G side is preferably flush with the side surface of the gate electrode G, or is preferably located closer to the drain electrode D than the side surface of the gate electrode G, as shown in FIG. 1 . The end of the recess H on the drain electrode D side is preferably located closer to the gate electrode G than the side surface of the drain electrode D, and the barrier layer 15 preferably has a sufficient thickness near the drain electrode D (for example, a first layer 15A, a damage prevention layer 15B, and a second layer 15C are stacked). In other words, the distance l2 from the drain electrode D to the end of the recess H is preferably greater than the distance l1 from the gate electrode G to the end of the recess H.

[0038] 2 shows the change in the electron gas concentration between the source electrode S and the drain electrode D. When the barrier layer 15 has a constant thickness T1 between the source electrode S and the drain electrode D, the electron gas concentration Ns1 of the two-dimensional electron gas layer 2DEG between the source electrode S and the drain electrode D is approximately constant. On the other hand, when a recess H is formed between the gate electrode G and the drain electrode D and the thickness of the barrier layer 15 is reduced to T2, for example, the electron gas concentration Ns1 of the two-dimensional electron gas layer 2DEG is maintained from the region Lgs between the gate electrode G and the source electrode S to just below the gate electrode G (just below Lgs-G), as in the case where the barrier layer 15 has a constant thickness T1, whereas the electron gas concentration Ns2 of the two-dimensional electron gas layer 2DEG in the region Lgd between the gate electrode G and the drain electrode D decreases (Ns1>Ns2). Furthermore, as will be described in detail later, when a recess H is formed by dry etching without forming a damage prevention layer 15B and the film thickness of the barrier layer is reduced to T2' (T2 > T2'), the electron gas concentration Ns2' of the two-dimensional electron gas layer 2DEG in the region Lgd between the gate electrode G and the drain electrode D further decreases (Ns2 > Ns2').

[0039] 3 shows the relationship between the ratio (T2 / T1) of the thickness (T1) of the barrier layer 15 between the gate electrode G and the source electrode S to the thickness (T2) of the barrier layer 15 between the gate electrode G and the drain electrode D, and the parasitic capacitance between the gate electrode G and the drain electrode D. By reducing the thickness of the barrier layer 15 between the gate electrode G and the drain electrode D, Lgd (more precisely, the region X corresponding to the recess H), the parasitic capacitance Cgd between the gate electrode G and the drain electrode D is reduced.

[0040] FIG. 4 is a characteristic diagram showing the relationship between electron gas concentration and threshold voltage. To drive a circuit incorporating the semiconductor device 1, for example, a forward voltage in the range of about +1 V to +3 V is applied. Meanwhile, there is also an upper limit to the forward voltage. The upper limit of the forward voltage is determined as follows. For example, in a Schottky transistor such as the semiconductor device 1 of this embodiment, it is determined by an increase in leakage current. Furthermore, in a MIS (Metal Insulated Semiconductor) transistor (e.g., semiconductor device 2, see FIG. 8 ), which will be described later, it is determined by the limit of the forward breakdown voltage. Therefore, when the threshold voltage (Vth), which is the starting point of driving, exceeds a certain value (e.g., about −1.25 V) and becomes shallower (approaching the positive side), the range in which the circuit can be driven narrows, and the characteristics cannot be exhibited. From the above, it is determined that the lower limit of the electron gas concentration of the Schottky semiconductor device 1 is 5.0E+12 [cm －２ Therefore, the electron gas concentration Ns2 of the two-dimensional electron gas layer 2DEG in the region X of the semiconductor device 1 is 5.0E+12 [cm －２ The lower limit of the electron gas concentration of the MIS type semiconductor device 2 is preferably 7.0E+12 [cm －２ Therefore, the electron gas concentration Ns1 of the two-dimensional electron gas layer 2DEG in the region X of the semiconductor device 2 is 7.0E+12 [cm －２ ] or more is desirable.

[0041] The thickness of the barrier layer 15 between the gate electrode G and the source electrode S (Lgs) and between the gate electrode G and the drain electrode D (Lgd) outside the recess H is preferably, for example, 3 nm or more and 10 nm or less. In such a case, the barrier layer 15 can more appropriately control the bandgap profile of the semiconductor device 1. This can further increase the carrier density of the two-dimensional electron gas layer 2DEG generated in the channel layer 13. The thickness of the barrier layer 15 within the recess H is preferably 1 nm or more and 5 nm or less. The thickness of the damage prevention layer 15B is sufficient as long as it is at least one atomic layer. When the thickness of the first layer 15A is t1 and the thickness of the second layer 15C is t2, the ratio (t1 / t2) of the thickness of the first layer 15A to the thickness of the second layer 15C is preferably 0.025 < t1 / t2 < 1.0. For this reason, the thickness of the first layer 15A is preferably, for example, 0.25 nm or more and less than 5 nm. The thickness of the second layer 15C is preferably, for example, not less than 0.5 nm and less than 10 nm.

[0042] The contact layer 16 constitutes a part of the current path between the source electrode S and the drain electrode D arranged with the gate electrode G therebetween. As shown in FIG. 1, the contact layer 16 is provided below each of the source electrode S and the drain electrode D arranged with the gate electrode G therebetween, and is electrically connected to the two-dimensional electron gas layer 2DEG.

[0043] The contact layer 16 is made of an epitaxially grown nitride semiconductor, such as GaN, in the same manner as the channel layer 13. １８ cm －３ 10 above ２１ cm －３ The contact layer 16 has a carrier concentration in the following range and contains, for example, silicon (Si) or germanium (Ge) as a dopant: The contact layer 16 is formed by, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), or sputtering.

[0044] The gate electrode G, source electrode S, and drain electrode D are all made of conductive materials. The gate electrode G, source electrode S, and drain electrode D are all provided on the semiconductor layer. The gate electrode G is disposed between the source electrode S and the drain electrode D. The gate electrode G is a Schottky gate that forms a Schottky junction by contacting the nitride semiconductor that constitutes the barrier layer 15 without an insulating film. The gate electrode G has a two-layer structure, for example, in which a Ni (nickel) layer and an Au (gold) layer are stacked in sequence. As described above, the source electrode S and the drain electrode D are each provided on a pair of contact layers 16 that are arranged opposite each other in the in-plane direction (XY plane direction) of the substrate 11, with the gate electrode G sandwiched between them. The source electrode S and the drain electrode D have a structure in which a Ti (titanium) layer, an Al (aluminum) layer, a Ni (nickel) layer, and an Au (gold) layer are stacked in sequence.

[0045] The insulating film Z is made of an insulating material. The insulating film Z is provided so as to cover a region on the barrier layer 15 that is not covered by any of the gate electrode G, the source electrode S, and the drain electrode D. The insulating film Z is made of, for example, Al ２ O ３ (aluminum oxide), SiO ２ (silicon dioxide), Si ３ N ４ (silicon nitride) or HfO ２ The insulating film Z may be a single layer film made of the above-mentioned constituent material, or may be a multilayer film in which multiple layers made of the above-mentioned constituent material are stacked.

[0046] 5A to 5E, an example of a method for manufacturing the semiconductor device 1 according to this embodiment will be described. 5A to 5E are cross-sectional schematic views showing the steps of the method for manufacturing the semiconductor device 1.

[0047] 5A , for example, a buffer layer 12, a channel layer 13, a spacer layer 14, a first layer 15A, a damage prevention layer 15B, and a second layer 15C are epitaxially grown in this order on a substrate 11. Although the substrate 11 may be a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate, a GaAs substrate, a ZnO substrate, or a ScAlMgO substrate, the following description will be given taking a Si substrate as an example.

[0048] For example, first, a Si substrate having a (111) plane as its main surface is placed in a MOCVD (metal organic chemical vapor deposition) apparatus and thermally cleaned for about 10 minutes at 1000° C. After that, AlN is epitaxially grown at about 700° C. to 1100° C. to a thickness of about 100 nm to 300 nm, thereby forming the buffer layer 12.

[0049] Next, a channel layer 13 is formed on the buffer layer 12 by epitaxially growing, for example, GaN at approximately 900° C. to 1100° C. to a thickness of 500 nm to 2000 nm.

[0050] Subsequently, a spacer layer 14 is formed on the channel layer 13 by epitaxially growing, for example, AlN at 900° C. to 1100° C. to a thickness of about 0.5 nm to 1.5 nm.

[0051] Next, the first layer 15A is formed on the spacer layer 14 by epitaxially growing, for example, AlInN to a thickness of about 1 nm to 10 nm at 700° C. to 900° C. Next, the damage prevention layer 15B is formed on the first layer 15A by epitaxially growing, for example, AlInN to a thickness of about one atomic layer at a growth temperature lower than that of the first layer 15A. Thereafter, the second layer 15C is formed on the damage prevention layer 15B by epitaxially growing, for example, AlInN to a thickness of about 1 nm to 10 nm at 700° C. to 900° C.

[0052] Next, as shown in FIG. 5B , resist is applied to the barrier layer 15, and a resist film 21 with openings at predetermined positions is formed using photolithography and etching techniques. Subsequently, the second layer 15C of the barrier layer 15 exposed in the openings is removed using dry etching, such as inductively coupled plasma etching (ICP-RIE), to form recesses H. Because the element shapes of the second layer 15C and the damage prevention layer 15B are different, the evaporation and desorption rates of reaction products during dry etching differ, resulting in different etching rates. By utilizing this, etching can be stopped repeatedly and accurately when the damage prevention layer 15B is exposed. This minimizes etching damage to the barrier layer 15 (first layer 15A) below the damage prevention layer 15B.

[0053] When etching is stopped so that the damage prevention layer 15B is exposed, the amount of etching is small, but the damage prevention layer 15B is also thinned by over-etching, as shown in FIG. 6 . This creates a difference in thickness between the damage prevention layer 15B exposed at the bottom of the recess H and the damage prevention layer 15B outside the recess H, forming a step. The dry etching conditions (e.g., pressure, stage temperature, or bias) are optimized depending on the compound semiconductors used for the second layer 15C and the damage prevention layer 15B.

[0054] Next, as shown in FIG. 5C, after the resist film 21 is removed, an insulating film Z is formed on the barrier layer 15 by using, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0055] 5D, a resist is applied onto the insulating film Z, and a resist film 22 having openings at predetermined positions is formed by photolithography and etching techniques. Next, the insulating film Z exposed in the openings is removed by dry etching such as reactive ion etching (RIE), to form openings GH.

[0056] 5E , after the resist film 22 is peeled off, for example, Ni / Au films are sequentially formed on the insulating film Z so as to cover the opening GH, and then the gate electrode G is formed by photolithography and milling. As a result, the gate electrode G is electrically connected to the barrier layer 15 through the opening GH.

[0057] Thereafter, in the same manner as in the gate electrode G, the insulating film Z is removed by photolithography and etching from the positions where the source electrode S and the drain electrode D are to be formed, and then, for example, Au / Ge alloy / Ni / Au films are sequentially formed on the entire surface as an ohmic electrode material, and then the source electrode S and the drain electrode D are formed by a lift-off method and a subsequent alloying process. Note that, in order to reduce the contact resistance of the source electrode S and the drain electrode D, a contact layer 16 may be formed below each of the source electrode S and the drain electrode D.

[0058] Through the above steps, the semiconductor device 1 shown in FIG. 1 can be formed.

[0059] [1-3. Actions and Effects] In recent years, research and development of HEMTs using nitride semiconductors has been actively conducted. Nitride semiconductors have a larger band gap than Si, GaAs, etc., and have polarization specific to hexagonal crystals. Therefore, HEMTs using nitride semiconductors have characteristics such as high breakdown voltage, high heat resistance, high saturation electron velocity, and high channel electron concentration, and are being developed as transistors applicable to small, high-performance power devices and high-frequency devices.

[0060] Next-generation mobile communication systems, such as the fifth-generation (5G) and sixth-generation (6G) mobile communication systems, are expected to use millimeter-wave signals to improve data rates. Because millimeter-wave signals, which have significant spatial attenuation, require high power output, there is a need to develop power amplifiers that combine high frequency and high efficiency. At the same time, the trend toward lower power consumption in mobile phones requires improved performance (high gain and high power-added efficiency) for power amplifier modules, which consume a lot of power. In particular, the recent advances in mobile communication systems have led to a demand for devices with high gain characteristics. This has led to a demand for high gain characteristics in the amplifier transistors used within the modules.

[0061] To meet these demands, semiconductor devices made of GaN-based materials are expected to replace semiconductor devices made of GaAs-based materials as high-output, high-frequency semiconductor devices.

[0062] In order to improve the gain characteristics of a HEMT made of GaN-based materials (hereinafter referred to as a GaN-HEMT), it is generally said that it is effective to reduce the source parasitic resistance R, reduce the gate resistance Rg, or reduce the parasitic capacitance Cgd between the gate and drain. In particular, reducing the parasitic capacitance Ddg between the gate and drain is very effective.

[0063] In order to reduce the parasitic capacitance Cgd between the gate and drain, it is first considered to increase the distance between the gate electrode and the drain electrode, but this would increase the size of the device itself, leading to an increase in the IC chip area, which would be a major obstacle when considering miniaturization of the device.

[0064] Another possible approach is to reduce the electron gas concentration in the two-dimensional electron gas layer 2DEG only between the gate electrode and the drain electrode. For example, as in the semiconductor device 100 shown in FIG. 7, it is possible to thin the barrier layer 115 between the gate electrode G and the drain electrode D by etching. However, GaN-based materials are highly resistant to wet etching. For this reason, dry etching such as ICP-RIE is used to thin the barrier layer 115. However, dry etching damages the barrier layer 115, which increases leakage paths, reduces reliability, and even causes a significant decrease in the electron gas concentration in the two-dimensional electron gas layer 2DEG (for example, the electron gas concentration Ns2' shown in FIG. 2).

[0065] In contrast to this, in the semiconductor device 1 of this embodiment, a damage prevention layer 15B having an etching rate lower than that of the barrier layer 15 is provided within the barrier layer 15. This prevents damage to the barrier layer 15 when the barrier layer 15 between the gate electrode G and the drain electrode D is thinned by dry etching, and makes it possible to make the electron gas concentration of the two-dimensional electron gas layer 2DEG between the gate electrode G and the drain electrode D lower than the electron gas concentration between the gate electrode and the source electrode.

[0066] As described above, according to the semiconductor device 1 of this embodiment, the parasitic capacitance Cgd between the gate electrode G and the drain electrode D can be reduced without increasing the parasitic resistance Rs of the source electrode S, thereby making it possible to improve device characteristics such as gain characteristics.

[0067] Next, first and second modifications and application examples of the present disclosure will be described. Note that components corresponding to those in the semiconductor device of the above embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0068] 2. Modifications (2-1. Modification 1) FIG. 8 is a schematic diagram illustrating an example of a cross-sectional configuration of a semiconductor device (semiconductor device 2) according to Modification 1 of the present disclosure.

[0069] In the above embodiment, the present technology has been described using a Schottky junction semiconductor device 1 in which the gate electrode G is in contact with the barrier layer 15 without an insulating film therebetween, but the present technology is not limited to Schottky junction semiconductor devices. A semiconductor device 2 of this modification employs an insulated gate structure (MIS type) in which the gate electrode G is disposed on the barrier layer 15 via an insulating film Z.

[0070] The semiconductor device 2 has a layered structure in which a substrate 11, a buffer layer 12, a channel layer 13, a spacer layer 14, a barrier layer 15, and an insulating film Z are layered in this order. The semiconductor device 2 further has a gate electrode G provided on the barrier layer 15 with the insulating film Z interposed therebetween, a pair of contact layers 16 arranged opposite each other in the in-plane direction (XY plane direction) of the substrate 11 with the gate electrode G interposed therebetween, and a source electrode S and a drain electrode D provided on the contact layer 16.

[0071] Similar to the above embodiment, the barrier layer 15 includes a damage prevention layer 15B therein, which has an etching rate lower than that of the barrier layer 15. Specifically, the barrier layer 15 has a layered structure in which a first layer 15A, a damage prevention layer 15B, and a second layer 15C are stacked in this order, and the damage prevention layer 15B has an etching rate lower than that of the first layer 15A and the second layer 15C. The barrier layer 15 further includes a recess H between the gate electrode G and the drain electrode D, which extends from the surface 15S2 side of the barrier layer 15 through the second layer 15C and reaches the damage prevention layer 15B. As a result, the electron gas concentration constituting the two-dimensional electron gas layer 2DEG formed near the interface between the channel layer 13 and the spacer layer 14 below the recess H is lower than the electron gas concentration in other regions (e.g., between the gate electrode G and the source electrode S).

[0072] In this way, the same effects as those of the above-described embodiment can be obtained in the MIS type semiconductor device 2. Furthermore, in the MIS type semiconductor device 2, it is possible to achieve low loss and high output of the GaN-based HEMT.

[0073] (2-2. Modification 2) FIG. 9 is a schematic diagram illustrating an example of a cross-sectional configuration of a semiconductor device (semiconductor device 33) according to Modification 2 of the present disclosure.

[0074] In the above embodiment, an example was shown in which the spacer layer 14 consisting of a single layer was provided between the channel layer 13 and the barrier layer 15. In contrast, in the semiconductor device 3 of this modified example, a spacer layer 24 having a two-layer structure in which a first spacer layer 24A and a second spacer layer 24B are stacked in this order is provided between the channel layer 13 and the barrier layer 15.

[0075] The first spacer layer 24A is made of a nitride semiconductor having a band gap larger than the band gap of the channel layer 13. The first spacer layer 24A is provided on the channel layer 13. The first spacer layer 24A reduces alloy scattering between the barrier layer 15 and the channel layer 13, and suppresses a decrease in carrier mobility in the two-dimensional electron gas layer 2DEG due to the alloy scattering.

[0076] The first spacer layer 24A is an epitaxially grown Al ｘ４ In ｙ４ Ga （１－ｘ４－ｙ４） N (0<x4<1, 0≦y4<1, 0<x4+y4<1). For example, the first spacer layer 24A1 may be composed of a binary nitride semiconductor such as AlN, a ternary nitride semiconductor such as AlGaN, or a quaternary nitride semiconductor such as AlInGaN.

[0077] The second spacer layer 24B is made of a nitride semiconductor having a bandgap larger than that of the channel layer and smaller than that of the first spacer layer 24A. The second spacer layer 24B is provided on the first spacer layer 24A. The second spacer layer 24B forms a region for capturing carriers. This allows carriers (electrons in this case) that transition from the two-dimensional electron gas layer 2DEG generated by stress during operation to the gate electrode G side to be captured (trapped) in the energy potential region of the second spacer layer 24B. The stress includes voltage application stress and high-temperature application stress.

[0078] For example, when the channel layer 13 is made of GaN, the second spacer layer 24B can be made of a nitride semiconductor containing Al, Ga, and In. ｘ５ In ｙ５ Ga （１－ｘ５－ｙ５） N (0<x5<1, 0<y5<1, 0<x5+y5≦1). For example, the second spacer layer 24B is made of a quaternary nitride semiconductor such as AlInGaN. Here, the first spacer layer 24A and the second spacer layer 24B are configured to satisfy X4>x5 and x4+y4>x5+y5.

[0079] The thickness of the spacer layer 24 is preferably, for example, 0.26 nm or more and 3.0 nm or less, and particularly preferably 0.5 nm or more and 1.5 nm or less. When the thickness of the spacer layer 24 is 0.26 nm or more, the spacer layer 24 is expected to be more effective in suppressing alloy scattering. On the other hand, when the thickness of the spacer layer 24 is 3.0 nm or less, the spacer layer 24 can more appropriately control the band gap profile of the semiconductor device 1. This allows for a further increase in the carrier density of the two-dimensional electron gas layer 2DEG generated in the channel layer 13.

[0080] The thickness of the spacer layer 24 is preferably, for example, 0.5 nm or more and 5 nm or less, and particularly preferably 0.3 nm or more and 3 nm or less. The first spacer layer 24A is thicker than the second spacer layer 24B, and is preferably, for example, 0.5 nm or more. This allows the spacer layer 24 to be expected to have a greater effect of suppressing alloy scattering. The thickness of the second spacer layer 24B is preferably, for example, 0.8 nm or more. This makes it possible to capture carriers that transition from the two-dimensional electron gas layer 2DEG generated by stress during operation to the gate electrode G side.

[0081] With this configuration, the same effects as those of the above embodiment can be obtained.

[0082] In this modification, the spacer layer 24 has a two-layer structure in which a first spacer layer 24A and a second spacer layer 24B are stacked in this order, and a second spacer layer is provided on the first spacer layer 24A, which suppresses alloy scattering, to capture carriers that transition from the two-dimensional electron gas layer 2DEG, which is generated by stress during operation, to the gate electrode G. This allows carriers to be captured before they are captured in the barrier layer 15 or the insulating film Z. This makes it possible to reduce fluctuations in the threshold voltage of the semiconductor device 3.

[0083] 3. Application Examples (3-1. Semiconductor Module) Next, a semiconductor module, which is a first application example of the technology according to the present disclosure, will be described with reference to Fig. 10. Fig. 10 is a schematic perspective view showing the configuration of a semiconductor module 1000.

[0084] 10 , the semiconductor module 1000 is, for example, an antenna-integrated module in which an edge antenna 1020 and multiple front-end components are mounted as a module on a single chip 1050. For example, multiple edge antennas 1020 are formed in an array on the chip 1050. The front-end components include, for example, a switch 1010, a low-noise amplifier 1041, a band-pass filter 1042, and a power amplifier 1043. The semiconductor module 1000 can be used, for example, as a transceiver for wireless communication.

[0085] The semiconductor module 1000 includes a semiconductor device (e.g., semiconductor device 1) according to the above-described embodiments as a transistor constituting, for example, the switch 1010, the low-noise amplifier 1041, or the power amplifier 1043. For example, in fifth-generation mobile communications (5G), which use radio waves in a higher frequency band, radio wave propagation loss increases. Therefore, it is desirable for the semiconductor module 1000 compatible with 5G to transmit radio waves at higher power. The semiconductor module 1000 including the semiconductor device 1 can improve device characteristics, thereby enabling high-output, low-power, and highly reliable wireless communication. In other words, the semiconductor module 1000 can be more suitably used for fifth-generation mobile communications (5G).

[0086] (3-2. Wireless Communication Device) Next, a wireless communication device that is a second application example of the technology according to the present disclosure will be described with reference to Fig. 11. Fig. 11 is a block diagram showing the configuration of a wireless communication device 2000.

[0087] 11 , wireless communication device 2000 includes an antenna ANT, an antenna switch circuit 2003, a high-power amplifier HPA, a radio frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I / F (e.g., a wireless local area network (W-LAN) or Bluetooth (registered trademark)). Wireless communication device 2000 is, for example, a mobile phone system having multiple functions such as voice and data communication and LAN connection.

[0088] In the wireless communication device 2000, during transmission, a transmission signal is output from the baseband unit BB to the antenna ANT via the radio frequency integrated circuit RFIC, the high power amplifier HPA, and the antenna switch circuit 203. Furthermore, during reception in the wireless communication device 2000, a received signal is input from the antenna ANT to the baseband unit BB via the antenna switch circuit 2003 and the radio frequency integrated circuit RFIC. The received signal processed by the baseband unit BB is output to the outside of the wireless communication device 2000, for example, from the audio output unit MIC, the data output unit DT, or the interface unit I / F.

[0089] The wireless communication device 2000 includes a semiconductor device (e.g., semiconductor device 1) according to the above-described embodiment as a transistor constituting the antenna switch circuit 2003, the high-power amplifier HPA, the radio-frequency integrated circuit RFIC, the baseband unit BB, etc. This allows the wireless communication device 2000 to further improve device characteristics, thereby enabling wireless communication with high output, low power consumption, and high reliability.

[0090] The technology according to the present disclosure has been described above by giving an embodiment, modifications 1 and 2, and application examples. However, the technology according to the present disclosure is not limited to the above-described embodiment, etc., and various modifications are possible. For example, in the above-described embodiment, etc., the present technology has been described using as an example a heterojunction device in which nitride semiconductors are used for each layer constituting a semiconductor device (e.g., semiconductor device 1), but the present technology can also be applied to devices using other compound semiconductors.

[0091] Furthermore, not all of the configurations and operations described in the embodiments are necessarily essential to the configurations and operations of the present disclosure. For example, among the components in each embodiment, any component that is not recited in an independent claim that represents the highest concept of the present disclosure should be understood as an optional component.

[0092] Terms used throughout this specification and the appended claims should be interpreted as "open-ended" terms. For example, the terms "including" or "including" should be interpreted as "not limited to the manner described as including." The term "having" should be interpreted as "not limited to the manner described as having."

[0093] The terms used in this specification include terms that are used merely for the convenience of description and are not intended to limit the configuration or operation. For example, terms such as "right," "left," "upper," and "lower" merely indicate directions in the drawings to which reference is made. Furthermore, the terms "inner" and "outer" merely indicate directions toward and away from the center of a focused element, respectively. The same applies to terms similar to these and terms of a similar meaning.

[0094] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0095] The present technology can also be configured as follows. According to the present technology configured as follows, the electron gas concentration between the gate electrode and the drain electrode is lower than the electron gas concentration between the gate electrode and the source electrode. This reduces the parasitic capacitance between the gate electrode and the drain electrode without damaging the barrier layer. This makes it possible to improve device characteristics. (1) A semiconductor device comprising: a substrate; a channel layer including a first nitride semiconductor provided on one surface of the substrate; a barrier layer provided on the channel layer opposite the substrate, the barrier layer having a first surface facing the channel layer and a second surface opposite the first surface, the barrier layer including a second nitride semiconductor having a larger band gap than the first nitride semiconductor; an intermediate layer provided in the barrier layer and including a semiconductor material having a lower etching rate than the barrier layer; a gate electrode provided on the second surface of the barrier layer; a drain electrode and a source electrode provided on the second surface of the barrier layer with the gate electrode sandwiched therebetween; and a recess provided between the gate electrode and the drain electrode, the recess extending from the second surface of the barrier layer to the intermediate layer. (2) The semiconductor device according to (1), wherein the intermediate layer is exposed at the bottom of the recess, and the thickness of the intermediate layer exposed at the bottom of the recess is thinner than the thickness of the intermediate layer covered with the barrier layer. (3) The semiconductor device according to (1) or (2), wherein the intermediate layer has a thickness of one atomic layer or more. (4) The semiconductor device according to any one of (1) to (3), wherein, when the thickness of the barrier layer directly below the recess between the gate electrode and the drain electrode is a first thickness and the thickness of the barrier layer between the gate electrode and the source electrode is a second thickness, the ratio of the first thickness to the second thickness satisfies the relationship 0.025<first thickness / second thickness<1.0. (5) The semiconductor device according to any one of (1) to (4), wherein the recess is provided closer to the gate electrode.(6) The semiconductor device according to any one of (1) to (5), wherein a first end of the recess on the gate electrode side coincides with a side surface of the gate electrode or is located closer to the drain electrode than the side surface of the gate electrode, and a second end of the recess on the drain electrode side is located closer to the gate electrode than the side surface of the drain electrode. (7) The semiconductor device according to (6), wherein the distance between the drain electrode and the second end of the recess is greater than the distance between the gate electrode and the first end of the recess. (8) The semiconductor device according to any one of (1) to (7), wherein the barrier layer and the intermediate layer each contain aluminum, and wherein the aluminum composition of the intermediate layer is lower than the aluminum composition of the barrier layer. (9) The semiconductor device according to any one of (1) to (8), wherein the barrier layer and the intermediate layer each contain indium, and wherein the indium composition of the intermediate layer is higher than the indium composition of the barrier layer. (10) The semiconductor device according to any one of (1) to (9), further comprising a spacer layer between the channel layer and the barrier layer. (11) The semiconductor device according to (10), wherein the spacer layer includes a first spacer layer and a second spacer layer stacked in this order from the channel layer side, and wherein the thickness of the first spacer layer is greater than the thickness of the second spacer layer. (12) The semiconductor device according to any one of (1) to (11), wherein the channel layer includes GaN (gallium nitride). (13) The semiconductor device according to any one of (1) to (12), wherein the substrate includes at least one of Si (silicon), sapphire, SiC (silicon carbide), GaN (gallium nitride), and AlN (aluminum nitride).(14) A semiconductor device comprising: a substrate, a channel layer including a first nitride semiconductor provided on one surface side of the substrate, a barrier layer provided on the side of the channel layer opposite the substrate, the barrier layer having a first surface facing the channel layer and a second surface opposite the first surface, the barrier layer including a second nitride semiconductor having a larger band gap than the first nitride semiconductor, an intermediate layer provided in the barrier layer and including a semiconductor material having a lower etching rate than the barrier layer, a gate electrode provided on the second surface side of the barrier layer, a drain electrode and a source electrode provided on the second surface side of the barrier layer with the gate electrode between them, and a two-dimensional electron gas layer formed in the vicinity of the interface between the channel layer and the barrier layer, the two-dimensional electron gas layer having a low electron gas region between the gate electrode and the drain electrode having a lower electron gas concentration than between the gate electrode and the source electrode. (15) The semiconductor device according to (14), further comprising an insulating film between the barrier layer and the gate electrode. (16) The first electron gas concentration between the gate electrode and the drain electrode and the second electron gas concentration between the gate electrode and the source electrode are 7.0E+12 cm. －２ ]≦first electron gas concentration<second electron gas concentration. (17) The semiconductor device according to any one of (14) to (16), wherein the gate electrode is formed directly on the barrier layer. (18) The first electron gas concentration between the gate electrode and the drain electrode and the second electron gas concentration between the gate electrode and the source electrode are 5.0E+12 [cm －２]≦first electron gas concentration<second electron gas concentration. (19) A semiconductor device according to (17), wherein the semiconductor device has a relationship of: 1) first electron gas concentration<second electron gas concentration; 2) a semiconductor module including: a substrate; a channel layer including a first nitride semiconductor provided on one surface side of the substrate; a barrier layer provided on the channel layer opposite the substrate, the channel layer having a first surface facing the channel layer and a second surface opposite the first surface, the barrier layer including a second nitride semiconductor having a larger band gap than the first nitride semiconductor; an intermediate layer provided in the barrier layer and including a semiconductor material having a lower etching rate than the barrier layer; a gate electrode provided on the second surface side of the barrier layer; a drain electrode and a source electrode provided on the second surface side of the barrier layer with the gate electrode between them; and a recess provided between the gate electrode and the source electrode, the recess extending from the second surface side of the barrier layer to the intermediate layer. (20) A wireless communication device comprising a semiconductor device, the semiconductor device comprising: a substrate; a channel layer including a first nitride semiconductor provided on one surface side of the substrate; a barrier layer provided on the channel layer opposite the substrate, the barrier layer having a first surface facing the channel layer and a second surface opposite to the first surface, the barrier layer including a second nitride semiconductor having a larger band gap than the first nitride semiconductor; an intermediate layer provided in the barrier layer and including a semiconductor material having a lower etching rate than the barrier layer; a gate electrode provided on the second surface side of the barrier layer; a drain electrode and a source electrode provided on the second surface side of the barrier layer with the gate electrode between them; and a recess provided between the gate electrode and the source electrode, the recess reaching from the second surface side of the barrier layer to the intermediate layer.

[0096] This application claims priority based on Japanese Patent Application No. 2023-118667, filed on July 20, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0097] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a substrate; a channel layer including a first nitride semiconductor provided on one surface side of the substrate; a barrier layer provided on the channel layer opposite the substrate, the barrier layer having a first surface facing the channel layer and a second surface opposite the first surface, the barrier layer including a second nitride semiconductor having a larger band gap than the first nitride semiconductor; an intermediate layer provided in the barrier layer and including a semiconductor material having a lower etching rate than the barrier layer; a gate electrode provided on the second surface side of the barrier layer; a drain electrode and a source electrode provided on the second surface side of the barrier layer with the gate electrode between them; and a recess provided between the gate electrode and the drain electrode, the recess extending from the second surface side of the barrier layer to the intermediate layer.

2. The semiconductor device according to claim 1, wherein the intermediate layer is exposed at the bottom of the recess, and the thickness of the intermediate layer exposed at the bottom of the recess is thinner than the thickness of the intermediate layer covered by the barrier layer.

3. The semiconductor device according to claim 1, wherein the intermediate layer has a thickness of at least one atomic layer.

4. The semiconductor device according to claim 1, wherein when a thickness of the barrier layer directly below the recess between the gate electrode and the drain electrode is a first thickness, and a thickness of the barrier layer between the gate electrode and the source electrode is a second thickness, a ratio of the first thickness to the second thickness satisfies the relationship: 0.025<first thickness / second thickness<1.

0.

5. The semiconductor device according to claim 1, wherein the recess is provided near the gate electrode.

6. The semiconductor device according to claim 1, wherein a first end of the recess on the gate electrode side coincides with a side surface of the gate electrode or is located closer to the drain electrode than the side surface of the gate electrode, and a second end of the recess on the drain electrode side is located closer to the gate electrode than the side surface of the drain electrode.

7. The semiconductor device according to claim 6, wherein a distance between said drain electrode and said second end of said recess is greater than a distance between said gate electrode and a first end of said recess.

8. The semiconductor device of claim 1, wherein the barrier layer and the intermediate layer each contain aluminum, and the aluminum composition of the intermediate layer is lower than the aluminum composition of the barrier layer.

9. The semiconductor device of claim 1, wherein the barrier layer and the intermediate layer each contain indium, and the intermediate layer has a higher indium composition than the barrier layer.

10. The semiconductor device of claim 1, further comprising a spacer layer between said channel layer and said barrier layer.

11. The semiconductor device according to claim 10, wherein the spacer layer includes a first spacer layer and a second spacer layer stacked in this order from the channel layer side, and the thickness of the first spacer layer is greater than the thickness of the second spacer layer.

12. The semiconductor device of claim 1, wherein the channel layer comprises GaN (gallium nitride).

13. The semiconductor device of claim 1, wherein the substrate comprises at least one of Si (silicon), sapphire, SiC (silicon carbide), GaN (gallium nitride), and AlN (aluminum nitride).

14. A semiconductor device comprising: a substrate; a channel layer including a first nitride semiconductor provided on one surface side of the substrate; a barrier layer provided on the channel layer opposite the substrate, the barrier layer having a first surface facing the channel layer and a second surface opposite to the first surface, the barrier layer including a second nitride semiconductor having a larger band gap than the first nitride semiconductor; an intermediate layer provided in the barrier layer and including a semiconductor material having a lower etching rate than the barrier layer; a gate electrode provided on the second surface side of the barrier layer; a drain electrode and a source electrode provided on the second surface side of the barrier layer with the gate electrode between them; and a two-dimensional electron gas layer formed in the vicinity of an interface between the channel layer and the barrier layer, the two-dimensional electron gas layer having a low electron gas region between the gate electrode and the drain electrode having a lower electron gas concentration than between the gate electrode and the source electrode.

15. The semiconductor device of claim 14, further comprising an insulating film between said barrier layer and said gate electrode.

16. The first electron gas concentration between the gate electrode and the drain electrode and the second electron gas concentration between the gate electrode and the source electrode are 7.0E+12 [cm －２ ]≦first electron gas concentration<second electron gas concentration.

17. The semiconductor device of claim 14, wherein the gate electrode is formed directly on the barrier layer.

18. The first electron gas concentration between the gate electrode and the drain electrode and the second electron gas concentration between the gate electrode and the source electrode are 5.0E+12 [cm －２ 20. The semiconductor device of claim 17, wherein the first electron gas concentration is greater than the second electron gas concentration.

19. A semiconductor module comprising a semiconductor device comprising: a substrate; a channel layer including a first nitride semiconductor provided on one surface side of the substrate; a barrier layer provided on the channel layer opposite the substrate, having a first surface facing the channel layer and a second surface opposite to the first surface, the barrier layer including a second nitride semiconductor having a larger band gap than the first nitride semiconductor; an intermediate layer provided in the barrier layer and including a semiconductor material having a lower etching rate than the barrier layer; a gate electrode provided on the second surface side of the barrier layer; a drain electrode and a source electrode provided on the second surface side of the barrier layer with the gate electrode between them; and a recess provided between the gate electrode and the source electrode, the recess extending from the second surface side of the barrier layer to the intermediate layer.

20. A wireless communication device comprising a semiconductor device comprising: a substrate; a channel layer including a first nitride semiconductor provided on one surface side of the substrate; a barrier layer provided on the channel layer opposite the substrate, having a first surface facing the channel layer and a second surface opposite to the first surface, the barrier layer including a second nitride semiconductor having a larger band gap than the first nitride semiconductor; an intermediate layer provided in the barrier layer and including a semiconductor material having a lower etching rate than the barrier layer; a gate electrode provided on the second surface side of the barrier layer; a drain electrode and a source electrode provided on the second surface side of the barrier layer with the gate electrode between them; and a recess provided between the gate electrode and the source electrode, reaching from the second surface side of the barrier layer to the intermediate layer.

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