Semiconductor device and power conversion device

Abstract

According to the present invention, a semiconductor chip (200) has a selective crystal defect region (237) provided within a drift layer (234) that includes at least a main joining region (224), with said crystal defect region (237) being provided so as to surround an active region (210). Moreover, if the depth at which the crystal defect density of the main joining region (224) is higher than the crystal defect density of the active region (210), or the depth from an interface of a surface oxide film (233) of the semiconductor device at which the crystal defect density is maximized, is defined as d_max (238), the average crystal defect density up to said depth d_max (238) in the main joining region (224) is higher than the average crystal defect density of the active region (210), and the depth d_max (238) is formed more on a back surface side than 40% of the thickness D of the drift layer of the semiconductor device.

Description

Semiconductor device and power conversion device

[0001] The present invention relates to a semiconductor device and a power conversion device.

[0002] IGBTs (Insulated Gate Bipolar Transistors), which are capable of switching large currents at high speeds, are widely used as power conversion devices for driving electric motors and the like. IGBTs are required to have high withstand voltages capable of interrupting large currents flowing through them without damaging the device, along with increasing current densities. As current densities in IGBTs increase, a problem arises in that the withstand voltages of the IGBTs decrease when they are turned off. To address this problem, known technologies are known, such as those shown in Patent Documents 1 and 2, that improve turn-off withstand voltages by introducing crystal defects to control lifetime.

[0003] IGBTs have a problem in that the turn-off breakdown voltage (RBSOA) decreases as the current density increases. In particular, in high-voltage IGBTs used in electric railways, the area of ​​the guard ring region that maintains the breakdown voltage and is placed around the periphery of the device becomes larger, which causes an increase in carriers accumulated in the periphery, resulting in a phenomenon in which current concentrates near the main junction on the surface when the device is turned off.

[0004] Japanese Patent Application Laid-Open No. 2003-144992 describes a technique for suppressing temperature distribution within a semiconductor chip by introducing crystal defects into the surface of the semiconductor chip that constitutes a semiconductor device.

[0005] Patent Document 2 describes a technique for providing a semiconductor device with high resistance to avalanche breakdown by introducing crystal defects into a limited irradiation area from the back surface of a semiconductor chip.

[0006] JP 2005-197472 A JP 2015-153784 A

[0007] However, in the technologies described in Patent Documents 1 and 2, ion irradiation is performed including on the conductive region (active region) of the semiconductor chip to introduce crystal defects, which poses the risk of increased conduction loss (on-state voltage) and fluctuations in threshold voltage due to irradiation of the gate oxide film of the active region with light ions.

[0008] The present invention has been made in consideration of the above circumstances, and aims to provide a semiconductor device and a power conversion device that can achieve high breakdown resistance while suppressing the effects of increased conduction loss and fluctuations in threshold voltage.

[0009] In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device that conducts current vertically between a main surface and a back surface of a semiconductor substrate and includes an active region that is a current conduction region, and a peripheral region that is arranged to surround the active region, the peripheral region having a main junction region, an FLR region, and an edge region, the main junction region being provided between the active region and the FLR region, the active region and the peripheral region having a drift layer made of an integral substrate, and the drift layer having a selective crystal defect region caused by light ion irradiation, a crystal defect region is provided in a drift layer including at least the main junction region so as to surround the active region, and the density of crystal defects in the main junction region is higher than the density of crystal defects in the active region; or, when the depth at which the density of crystal defects becomes maximum from the interface of a surface oxide film of the semiconductor device is defined as d_max, the average density of crystal defects in the main junction region up to the depth d_max is higher than the average density of crystal defects in the active region, and the depth d_max is formed on the back surface side of 40% of the thickness D of the drift layer of the semiconductor device.

[0010] According to the present invention, it is possible to provide a semiconductor device and a power conversion device that can achieve high breakdown resistance while suppressing the effects of increased conduction loss and fluctuations in threshold voltage.

[0011] 1 is a diagram showing the overall configuration of an electric motor control system using a power conversion device to which the semiconductor device of the first embodiment of the present invention is applied. FIG. 2 is a plan view of a semiconductor chip constituting the semiconductor device of the first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along A-B of the semiconductor chip of the first embodiment of the present invention. FIG. 4 is a schematic diagram showing a transient current path at turn-off in a cross-section taken along A-B of the semiconductor chip of the first embodiment of the present invention. FIG. 5 is a schematic diagram showing the depth direction distribution of crystal defect density along a-b and c-d of the semiconductor chip of the first embodiment of the present invention. FIG. 6 is a diagram showing the effect of the present invention. FIG. 7 is a diagram showing a modification of the first embodiment of the present invention. FIG. 8 is a diagram showing the effect of the modification of the first embodiment of the present invention. FIG. 9 is an enlarged view of region C in the semiconductor chip shown in FIG. 2. FIG. 10 is a cross-sectional view taken along D-E of a semiconductor chip of the second embodiment of the present invention, and a schematic diagram showing a transient current path at turn-off. FIG. 11 is a diagram showing a modification of the second embodiment of the present invention. FIG. 11 is a plan view of a semiconductor chip according to a third embodiment of the present invention, and a diagram showing a connection form with a gate driver. FIG. 12 is a cross-sectional view taken along P-Q of the semiconductor chip according to the third embodiment of the present invention. FIG. 13 is a cross-sectional view taken along R-S of the semiconductor chip according to the third embodiment of the present invention. FIG. 14 is a diagram showing a drive sequence of a gate driver according to the third embodiment of the present invention. FIG. 10 is a diagram showing a structure of a unit cell in an active region of a semiconductor chip, which is a modified example of the third embodiment of the present invention.

[0012] Hereinafter, modes for carrying out the present invention (hereinafter referred to as "embodiments") will be described with reference to the drawings as appropriate. (First Embodiment) Fig. 1 is a diagram showing the overall configuration of an electric motor control system 100 using a power conversion device according to a first embodiment of the present invention. The power conversion device is a device that converts electric power using power semiconductor devices. In this embodiment, the electric motor control system 100 will be described as an example using an inverter circuit that uses IGBTs as the power semiconductor devices.

[0013] The motor control system 100 includes a DC power supply 10, an inverter circuit 20, and an electric motor 70. The inverter circuit 20 includes a smoothing capacitor 21, inverter units 30 for three phases, UVW (U-phase inverter unit 30U, V-phase inverter unit 30V, and W-phase inverter unit 30W), and a command logic unit 22. The inverter circuit 20 outputs AC power based on DC power supplied from the DC power supply to drive the electric motor 70. The smoothing capacitor 21 is provided between the DC power supply 10 (power supply voltage = Vcc) and the positive electrode connecting wire 23 and negative electrode connecting wire 24 of the inverter circuit 20.

[0014] The inverter unit 30 is composed of upper and lower arms, and has a series circuit of semiconductor devices 31. Each of the semiconductor devices 31 in the upper and lower arms is composed of an IGBT. A gate signal is transmitted to the IGBT from a gate driver 40. The high-potential terminal of the IGBT in the upper arm is connected to a first end (positive electrode connection line 23) of the smoothing capacitor 21. The low-potential terminal of the IGBT in the upper arm is connected to a high-potential terminal of the IGBT in the lower arm. The low-voltage terminal of the IGBT in the lower arm is connected to a second end (negative electrode connection line 24) of the smoothing capacitor 21.

[0015] In each phase, a connection point 33 between the low potential side terminal of the IGBT in the upper arm and the high potential side terminal of the IGBT in the lower arm is connected to one end of a winding of the electric motor 70. The other end of the winding of each phase is connected to a neutral point. The electric motor 70 is, for example, an induction motor.

[0016] Each IGBT is connected in anti-parallel to a freewheeling diode 32. Various types of diodes can be used as the freewheeling diode 32, such as a pn junction diode, a Schottky barrier diode, or a diode that uses both a pn junction and a Schottky junction.

[0017] The command logic unit 22 outputs an ON command instructing an ON state or an OFF command instructing an OFF state to the gate drive device 40 as a drive command signal P for the semiconductor device 31. As a result, the command logic unit 22 alternately turns on the semiconductor device 31 of the upper arm and the semiconductor device 31 of the lower arm in each phase to control the control variable of the electric motor 70 to the command value. The control variable is, for example, the torque of the electric motor.

[0018] The gate driving device 40 is provided corresponding to each semiconductor device 31, acquires a driving command signal P from the command logic unit 22, and turns the semiconductor device 31 on or off based on the acquired driving command signal P.

[0019] Fig. 2 is a plan view of a semiconductor chip 200 constituting the semiconductor device 31 according to the first embodiment. Fig. 2 shows a semiconductor chip constituting a semiconductor device relating to the lower arm of the U-phase in the inverter circuit 20 shown in Fig. 1. The other semiconductor devices in the upper arm of the U-phase and the upper and lower arms of the V-phase and W-phase have the same configuration. The semiconductor device 31 may be in the form of a power module (IGBT module) in which a plurality of semiconductor (IGBT) chips as shown in Fig. 2 are mounted in parallel.

[0020] In the following, the configuration and operation of the semiconductor device 31 of the lower arm of the U phase and its gate driver 40 will be described, but the configurations and operations of the other semiconductor devices and their gate drivers are similar.

[0021] The semiconductor chip 200 is composed of an active region 210 and a non-active region 220. The active region 210 is a region through which current flows, for example, a region where an emitter-side electrode is formed. The non-active region 220 is a region through which no current flows, for example, a peripheral region 221 having a guard ring for maintaining voltage resistance, a gate finger region 222 which is a wiring region for supplying power to the gate, and a gate pad 223 which is a pad region connected to the gate finger and supplies power to the gate.

[0022] FIG. 3 is a cross-sectional view of the semiconductor chip 200 of the first embodiment taken along the line A-B. As shown in FIG. 3, the active region 210 is the region inside the left end X of the electric field relaxation layer (main junction) 229 made of a p-type semiconductor, which corresponds to the region A-X in FIG. 3. The peripheral region 221 is the region outside the left end X of the main junction 229, which corresponds to the region X-B in FIG. 3. The peripheral region 221 is composed of a main junction region 224, an FLR region 225, and an edge region 226. The FLR region 225 is a region in which a guard ring 231 is located, extending from the right end Y of the main junction 229 to the left end Z of the electric field blocking layer (channel stopper) 232. The FLR region 225 is provided to maintain the breakdown voltage of the semiconductor chip 200 by mitigating the electric field provided by the electric field relaxation layer (guard ring) 231 made of a plurality of p-type semiconductors.

[0023] 3, where a main junction 229 is located, sandwiched between the active region 210 and the FLR region 225. The main junction region 224 is provided to suppress current concentration and electric field concentration when the semiconductor chip 200 is turned off. The edge region 226 is a region from the left end Z of the electric field blocking layer (channel stopper) 232 made of a high-concentration n-type semiconductor to the chip edge B, and corresponds to the region Z-B in FIG.

[0024] As shown in FIG. 3 , a collector electrode 212 is present over the entire back surface of the semiconductor chip 200. A high-concentration p-type semiconductor layer (p-emitter layer) 236, which is a hole injection layer, is present in contact with the collector electrode 212. A high-concentration n-type semiconductor layer (n-buffer layer) 235 is present on the upper surface of the p-emitter layer 236. An n-type semiconductor layer (n-drift layer) 218 ​​having a lower concentration than the n-buffer layer region 235 is present on the upper surface of the n-buffer layer 235 in the active region 210. A p-type semiconductor layer (p-base layer) 217 ​​is present on the upper surface of the n-drift layer 218 in the active region 210. A trench-type gate electrode 213 is provided so as to straddle the p-base layer 217 and n-drift layer 218 in the active region 210.

[0025] An emitter electrode 211 is present on the surface side of the active region 210. A gate insulating film 215 is present between the gate electrode 213 and the emitter electrode 211. The gate electrode 213 is covered with a gate oxide film 214 and a gate insulating film 215, and is electrically insulated from the emitter electrode 211. A high-concentration n-type semiconductor layer (n+ emitter layer) 216 is present in a portion of the p-base layer 217 of the active region 210 that contacts the gate insulating film 215, so as to contact the gate oxide film 214.

[0026] A surface oxide film 233 exists on the surface side of the peripheral region 221. In the peripheral region 221 as well, an n-drift layer 234 exists on an n-buffer layer 235. The n-drift layer 218 and the n-drift layer 234 are formed as an integral substrate. A gate wiring 227 and a field plate (main junction FP) 228 exist on the surface oxide film 233 of the main junction region 224.

[0027] A main junction 229 exists below the surface oxide film 233 of the main junction region 224. A plurality of field plates 230 exist on the surface oxide film 233 of the FLR region 225. A plurality of guard rings 231 exist below the surface oxide film 233 of the FLR region 225.

[0028] 3, there is a depth (d_max) 238 where the crystal defect density (density of crystal defects) is maximum, and the region from the surface oxide film 233 to d_max 238 (see FIG. 5 below) is a range region 237 (see FIG. 5 below). A channel stopper 232 exists below the surface oxide film 233 of the edge region 226 shown in FIG.

[0029] [Explanation of Operation] The following describes the operation of the semiconductor chip 200. When a positive voltage relative to the emitter electrode 211 is applied to the collector electrode 212 (FIG. 3) of the semiconductor chip 200, power is supplied from the gate driver 40 of FIG. 1 to the gate electrode 213 of the semiconductor chip 200 of FIG. 3 via the gate pad 223 and gate finger region 222 of FIG. 2, and a voltage exceeding the threshold voltage of the semiconductor chip 200 is applied between the gate electrode 213 and the emitter electrode 211, the semiconductor surface of the p-base layer 217 in contact with the gate oxide film 214 is strongly inverted, increasing the electron concentration and forming an n-type inversion layer.

[0030] 3 are connected via an n-type inversion layer, and electrons are injected from the n+ emitter layer 216 into the n- drift layer 218. The injected electrons reach the vicinity of the n buffer layer 235 and p emitter layer 236 on the back surface, forward biasing the pn junction between the p emitter layer 236 and the n buffer layer 235, and holes are injected from the p emitter layer 236. In this way, conductivity modulation occurs in the n- drift layer 218 of the active region 210, and the semiconductor chip 200 becomes conductive (ON state).

[0031] At this time, holes are also injected from the p-emitter layer 236 on the back surface of the peripheral region 221 shown in FIG. 3, and the injected holes are accumulated not only in the n-drift layer 218 in the active region 210 but also in the n-drift layer 234 in the peripheral region.

[0032] When the voltage applied from gate driver 40 (FIG. 1) to gate electrode 213 of semiconductor chip 200 (FIG. 3) falls below the threshold voltage, the n-type inversion layer of semiconductor chip 200 disappears, injection of electrons from n+ emitter layer 216 into n- drift layer 218 stops, and semiconductor chip 200 begins to shut down (turn off).

[0033] Since semiconductor chip 200 is a bipolar device, even if the injection of electrons from n+ emitter layer 216 stops, a tail current continues to flow until the holes accumulated in n- drift layer 218 in active region 210 and n- drift layer 234 in the peripheral region are discharged from emitter electrode 211 on the surface, and turn-off does not end.

[0034] Fig. 4 is a schematic diagram showing a transient current path during turn-off in a cross section taken along line A-B of semiconductor chip 200 shown in Fig. 2. Fig. 4 simulates a current path 700 through which holes accumulated in n-drift layer 234 in peripheral region 221 during turn-off pass through to emitter electrode 215, as well as equipotential lines 701 during turn-off. Most of the holes accumulated in peripheral region 221 are discharged to emitter electrode 211 through field relaxation layer 229 in main junction region 224 in accordance with the potential gradient, as shown in Fig. 4.

[0035] 3 and 4 is covered with a surface oxide film 233, and no current flows through the peripheral region 221. Furthermore, during turn-off, the depletion layer extends vertically in the active region 210 and horizontally in the peripheral region 221, resulting in equipotential lines in the main junction region 224 and the field limiting ring (FLR) region 225 being distributed as shown in FIG. 4. Therefore, as shown by a current path 700 in FIG. 4, most of the holes accumulated in the peripheral region 221 flow as a hole current in accordance with the potential gradient, as shown in FIG. 4, resulting in transient current concentration in the field relaxation layer 229 of the main junction region 224.

[0036] Furthermore, in the transient state in which holes are being discharged during turn-off, the concentration of holes accumulated in n-drift layer 234 in the peripheral region is higher than in the steady-off state, and therefore the electric field is not sufficiently relaxed by field relaxation layer 231 in FLR region 225 and field relaxation layer 229 in main junction region 224. As a result, a dynamic avalanche occurs at the junction (253 in FIG. 4) between field relaxation layer 229 in main junction region 224 and n-drift layer 234, where the electric field and current are particularly concentrated.

[0037] The avalanche current generated by this dynamic avalanche locally heats the semiconductor chip 200, causing a parasitic npn transistor in the active region to operate, resulting in a latch-up state in which on / off control by the gate is no longer possible, and the semiconductor chip 200 is destroyed. In other words, there is a problem of a decrease in turn-off resistance.

[0038] [Improvement Method] In this embodiment, a method is provided for improving the problem that, when holes accumulated in the n-drift layer 234 in the peripheral region are discharged during turn-off, they flow through the field relaxation layer 229 in the main junction region 224, causing current concentration, reducing the turn-off resistance, and adversely affecting high current densities. The cross-sectional structure of a semiconductor chip 200 for solving this problem is described with reference to FIG. 3 . Crystal defects are introduced by irradiating light ions from the surface so as to include the field relaxation layer 229 in the main junction region 224, where current concentration and electric field concentration occur. These crystal defects have a depth (d_max) 238 (see FIG. 5 below) at which the crystal defect density is maximized. Between the surface oxide film 233 and the depth (d_max) 238 at which the crystal defect density is maximized, there is a region (crystal defect region) called a light ion pass-through region, where crystal defects exist due to the passage of the light ions. This region is called a range region 237.

[0039] When introducing these crystal defects, the crystal defects are introduced by irradiating light ions from the surface so as to avoid the gate oxide film 214 in the active region 210, thereby reducing the concentration of holes accumulated in the n-drift layer 234 in the peripheral region without increasing the on-voltage (Vcesat). In addition, since the gate oxide film 214 in the active region 210 is not affected by the irradiation of light ions, fluctuations in the threshold voltage can be suppressed.

[0040] 5 shows the depth distribution of the crystal defect density along lines a-b in the main junction region 224 of the semiconductor chip 200 shown in FIG. 3, and the depth distribution of the crystal defect density along lines c-d in the active region 210. Because the active region 210 (c-d) shown in FIG. 3 is not irradiated with light ions, the crystal defect density remains substantially constant at a low value from the front surface to the back surface. Meanwhile, in the main junction region 224 (a-b), crystal defects are generated due to the irradiation of light ions from the front surface, and a region with a high crystal defect density due to the passage of light ions, i.e., a range region 237 (FIG. 5), exists on the front surface side of the depth (d_max) 238 where the crystal defect density is maximum.

[0041] In the regions where the crystal defects exist, i.e., the range region 237 (FIG. 5) and the depth (d_max) 238 (FIG. 3) where the crystal defect density is maximum, the carrier lifetime is shorter than in regions where no crystal defects exist. In other words, carrier recombination occurs more easily in these regions than in other regions of the n-drift layer, and the number of accumulated holes can be suppressed.

[0042] Furthermore, because the lifetime of regions where crystal defects exist is short and the carrier density is relatively low, the following magnitude relationship holds when comparing the resistivities of the substrate in regions where the n-drift layer exists in semiconductor chip 200. That is, the following magnitude relationship holds among resistivity ρ1 in n-drift layer 237 in range region 237, resistivity ρ2 at depth (d_max) 238 where the crystal defect density is maximum, and resistivity ρ3 in n-drift layer 218 in active region 210: ρ3<ρ1<ρ2.

[0043] Furthermore, by forming the depth (d_max) 238 where the crystal defect density is maximum on the back surface side of the semiconductor chip 200, a light ion passage region (crystal defect region) 237, which is a range region where the carrier lifetime is short, is formed up to a region close to the back surface. As a result, the recombination of holes and electrons injected from the p-emitter layer 236 in the peripheral region 221 can be promoted, and the hole transport efficiency from the p-emitter layer 236 to the emitter electrode 211 can be more effectively suppressed. Therefore, when holes accumulated in the n-drift layer 234 in the peripheral region are discharged at turn-off, current concentration caused by the holes flowing via the field relaxation layer 229 in the main junction region 224 can be more effectively suppressed, and the turn-off resistance can be improved.

[0044] As described above, when light ions are selectively irradiated from the surface of peripheral region 221 of semiconductor chip 200 so as to include at least main junction region 224, range region 237, in which carrier lifetime is short, is formed on the surface side of peripheral region 221 including at least electric field relaxation layer 229 of main junction region 224. As a result, the carrier concentration accumulated in n-drift layer 234 of the peripheral region decreases, and the width of the depletion layer formed from electric field relaxation layer 229 of main junction region 224 to n-drift layer 234 of the peripheral region at turn-off increases, which also increases the spacing between equipotential lines 701 near the junction portion (253 in FIG. 4 ) between electric field relaxation layer 229 and n-drift layer 234 in FIG. 4 , and the electric field intensity near electric field relaxation layer 229 of main junction region 224 is reduced. Furthermore, due to the effect of the range region 237 where the carrier lifetime is short as described above, holes accumulated in the n-drift layer 234 in the peripheral region are prevented from concentrating in the electric field relaxation layer 229 of the main junction region 224 at turn-off, and current concentration in the vicinity of the electric field relaxation layer 229 can also be suppressed.

[0045] Dynamic avalanche is caused by the concentration of an electric field and current, and these effects suppress dynamic avalanche that occurs in the electric field relaxation layer 229 of the main junction region 224. As a result, this prevents a latch-up state in which the avalanche current generated by dynamic avalanche locally heats the semiconductor chip 200, causing a parasitic npn transistor in the active region to operate and making on / off control by the gate impossible, thereby improving the turn-off resistance and making the semiconductor chip 200 less likely to be destroyed.

[0046] Furthermore, since no crystal defects are introduced into the active region 210 or the gate oxide film 214 within the active region 210, the breakdown resistance can be improved without causing an increase in the on-voltage (Vcesat) or a change in the threshold voltage.

[0047] In the following, a method of selectively forming a range region 237 from the backside of the semiconductor chip 200 will be referred to as a conventional technique (τCC) for comparison. FIG. 6 illustrates the effects of the semiconductor chip 200 of this embodiment. The vertical axis of FIG. 6 represents the maximum value of current (maximum blocking current) that can be blocked when the semiconductor chip 200 is turned off, normalized with the maximum blocking current when the conventional technique (τCC) is applied as 100%. The horizontal axis of FIG. 6 represents the amount of crystal defects (e.g., light ion irradiation dose) introduced into the semiconductor chip 200, normalized with the amount of crystal defects when the conventional technique (τCC) is applied as 100%. In this embodiment (τEC in FIG. 6), the range region 237 is selectively formed from the front side of the semiconductor chip 200, including at least the main junction region 224, so as to include the electric field relaxation layer 229 of the main junction region 224, which is the avalanche point where electric field and current transiently concentrate during turn-off. Therefore, the same maximum blocking current can be achieved with a smaller amount of crystal defects than in the conventional technology (τCC) in which the range region is formed from the back surface side and does not include the electric field relaxation layer 229. In other words, current concentration in the main junction region can be more effectively suppressed, and a high breakdown resistance of the semiconductor chip can be achieved.

[0048] 7 shows another effect of the present embodiment, particularly an example of an analysis result showing the trade-off between leakage current and the number of accumulated carriers in the peripheral region. The vertical axis of FIG. 7 shows the number of accumulated carriers in the peripheral region of the semiconductor chip 200, normalized to 100% when the conventional technology (τ CC) is applied. The horizontal axis of FIG. 7 shows the leakage current of the semiconductor chip 200, normalized to 1 when the conventional technology (τ CC) is applied.

[0049] The number of accumulated carriers in the peripheral region refers to the number of holes accumulated in the peripheral region 221 immediately before the semiconductor chip 200 is turned off. The smaller the number of accumulated carriers in the peripheral region, the more the current density that transiently concentrates near the electric field relaxation layer 229 of the main junction region 224 during turn-off can be reduced, resulting in a larger maximum cut-off current. In other words, the number of accumulated carriers in the peripheral region is an index of the maximum cut-off current. In addition, generally, as the number of crystal defects introduced into the semiconductor chip 200 increases, the number of carriers generated in the depletion region increases, resulting in an increase in leakage current and a larger amount of heat generated when the semiconductor chip is turned off. Therefore, there is a trade-off between the leakage current and the number of accumulated carriers in the peripheral region.

[0050] In Figure 7, the dotted-dash line represents the trade-off line determined between a semiconductor chip with no crystal defects (no τ control) and a semiconductor chip (τCC) in which crystal defects are introduced by irradiating light ions from the backside, a conventional technology. In contrast to this trade-off line, in this embodiment (τEC), in which crystal defects are introduced by irradiating light ions from the frontside, the trade-off is improved by setting the depth (d_max) at which the crystal defect density is maximum to 40% or more of the drift layer thickness D, i.e., 0.4D or more. Furthermore, in this embodiment (τEC), by setting d_max to 0.5D or more, it is possible to reduce only the leakage current without significantly increasing the number of accumulated carriers in the peripheral region. To this end, it is preferable to irradiate light ions so as to satisfy the relationship 0.5D≦d_max<D.

[0051] [Modification of Semiconductor Switching Element] Figure 8 is a diagram showing a modification of the semiconductor chip according to the first embodiment. Components that are the same as those in Figure 3 are given the same reference numerals. For example, when introducing crystal defects into the main junction region 224 as in this embodiment, as shown in Figure 8, the crystal defects may be introduced not only in the main junction region 224 but also so as to extend over part of the active region 210 adjacent to the main junction region 224. This can also alleviate current concentration in the active region 210, thereby improving the withstand voltage.

[0052] However, if the area of ​​crystal defects introduced into the active region 210 is too large, the carriers stored in the active region during conduction are more likely to disappear due to recombination, resulting in an increase in on-state voltage (Vcesat) and an increase in conduction loss (Econd).

[0053] FIG. 9 is a diagram showing the effect of the modification shown in FIG. 8 . FIG. 9 shows an example of the analysis results of the dependence of the on-voltage and the number of accumulated carriers in the peripheral region immediately before turn-off on the region of crystal defects (the width of the crystal defect region) (penetration amount ΔX shown in FIG. 8 ) introduced into the active region 210. The horizontal axis of FIG. 9 represents the ratio of the penetration amount ΔX of crystal defects into the active region to the thickness D of the drift layer. The left vertical axis of FIG. 9 represents the on-voltage (Vcesat), and the right vertical axis of FIG. 9 represents the number of accumulated carriers in the peripheral region immediately before turn-off, both normalized to the case where ΔX = 0. According to the inventors' studies, as the penetration amount ΔX into the active region 210 increases, Vcesat increases and the number of accumulated carriers in the peripheral region immediately before turn-off decreases. To keep the increase rate of Vcesat to 1% or less, it is preferable that the penetration amount ΔX of crystal defects into the active region 210 be 40% or less of the thickness D of the drift layer.

[0054] [Effects of the First Embodiment] As described above, the semiconductor chip 200 (FIGS. 2 to 7) according to the first embodiment conducts current vertically between the main surface and the back surface of the semiconductor substrate, and includes an active region (210) that is a current conduction region, and a peripheral region (221) that is arranged to surround the active region (210). The peripheral region (221) has a main junction region (224), an FLR region (225), and an edge region (226). The main junction region (224) is provided between the active region (210) and the FLR region (225). The active region (210) and the peripheral region (221) have drift layers (218, 234) made of an integral substrate, and the drift layers (218, 234) have selective crystal defect regions (237) formed by light ion irradiation. The semiconductor device is characterized in that the selective crystal defect region (237) is provided in a drift layer (234) including at least a main junction region (224) so ​​as to surround the active region (210), and the crystal defect density of the main junction region (224) is higher than the crystal defect density of the active region (210), or when the depth at which the crystal defect density becomes maximum from the interface of a surface oxide film (233) of the semiconductor device is defined as d_max (238), the average crystal defect density in the main junction region (224) up to the depth d_max (238) is higher than the average crystal defect density of the active region (210), and the depth d_max (238) is formed on the back surface side of 40% of the thickness D of the drift layer of the semiconductor device (d_max≧0.4×D).

[0055] As described in the problem to be solved, in a high-voltage IGBT, the area of ​​the guard ring region arranged around the periphery of the device for maintaining the breakdown voltage becomes large, and the carriers accumulated in the periphery increase, resulting in a phenomenon of current concentration near the main junction on the surface at turn-off. When the carriers accumulated in the periphery are discharged at turn-off, they flow through the main junction on the surface, causing current concentration, reducing the RBSOA and hindering higher current densities.

[0056] In this embodiment, protons are selectively irradiated from the surface of the IGBT element, avoiding the gate oxide film, including the gate wiring. In particular, protons are selectively irradiated to the main junction (including the gate finger portion) where current transiently concentrates during turn-off, without irradiating the active region, to form a low-lifetime region from the front side of the chip. That is, by introducing crystal defects from the surface into the inactive region while avoiding the gate oxide film, the lifetime of the region where current transiently concentrates during turn-off is shortened compared to the active region. This allows current concentration to be alleviated by selectively reducing the lifetime near the main junction where current transiently concentrates during turn-off, while avoiding adverse effects on the on-state voltage and threshold voltage. The RBSOA is improved by suppressing current and field concentration during turn-off while preventing an increase in on-state voltage.

[0057] As a result, it is possible to achieve high breakdown voltage resistance while suppressing the effects of increased conduction loss and fluctuations in threshold voltage. Because it is possible to achieve both low loss performance and high breakdown voltage performance, it is ideal for systems that require low loss and high reliability, such as electric vehicles and railways, where low loss and high reliability are required for power conversion devices.

[0058] The semiconductor chip 200 according to the first embodiment is characterized in that the inner edge of the selective crystal defect region (light ion passage region 237) is closer to the FLR region (225) than the center of the main junction region (224).

[0059] In the semiconductor chip 200 according to the first embodiment, the outer edge of the selective crystal defect region (light ion passage region 237) is characterized in that it exists in the region from the electric field relaxation layer (231) closest to the active region in the FLR region (225) to the edge region (226).

[0060] In the semiconductor chip 200 according to the first embodiment, the selective crystal defect region (light ion passage region 237) is characterized in that it is the entire peripheral region (221) including the main junction region (224), the FLR region (225), and the edge region (226).

[0061] In the semiconductor device according to the first embodiment, a portion of the selective crystal defect region (237) penetrates into the active region (210) adjacent to the main junction region (224), and the width (ΔX) of the crystal defect region penetrating into the active region (210) is 40% or less (0≦ΔX≦0.4×D) of the thickness D of the drift layer.

[0062] In the semiconductor device according to the first embodiment, when the resistivities of the substrates of the drift layers (218, 234) are compared, a magnitude relationship of ρ3<ρ1<ρ2 is established among the resistivity ρ2 of the selective crystal defect region (237), the resistivity ρ2 of the depth d_max (238) at which the crystal defect density is maximum, and the resistivity ρ3 of the active region (210).

[0063] The semiconductor device according to the first embodiment is characterized in that the depth d_max (238) is in the range of 0.5×D≦d_max<D, where D is the chip thickness of the semiconductor device.

[0064] Second Embodiment FIG. 10 is an enlarged view of region C in a semiconductor chip according to a second embodiment of the present invention. FIG. 10 is an enlarged plan view of region C in FIG. 2, i.e., the vicinity of gate finger region 222 (gate finger region). As shown in FIG. 10, gate finger region 222 is composed of gate wiring 227 and a surface oxide film 250 of the gate finger region provided thereunder. Gate finger region 222 is located between active region 210. FIG. 10 schematically illustrates the planar positional relationship between emitter electrode 211 of active region 210 and gate electrode 213 located thereunder, which are located on both sides of gate wiring 227 of gate finger region 222.

[0065] 11 is a cross-sectional view of a semiconductor chip according to the second embodiment taken along line D-E in FIGS. 2 and 10. FIG. 11 is a schematic diagram showing a transient current path during turn-off. As shown in FIG. 11, the gate finger region 222 is a part of the components of the semiconductor chip 200, and therefore the presence of the collector electrode 212, the high-concentration p-type semiconductor layer (p-emitter layer) 236, the high-concentration n-type semiconductor layer (n-buffer layer) 235, and the low-concentration n-type semiconductor layer (n-drift layer) 218 ​​is the same as in the first embodiment shown in FIG. 2. In addition, the active regions 210 present on both sides of the gate finger region 222 are also the same as in the first embodiment.

[0066] A gate electrode 227 exists on the surface of the gate finger region 222. A surface oxide film 250 of the gate finger region exists below the gate electrode 227, and the gate wiring 227 is electrically insulated from the emitter electrode 211 and the n-drift layer of the active region 210. A field relaxation layer 251 of the gate finger region exists below the surface oxide film 250 of the gate finger region, and is formed deeper than the p-base layer 217 of the active region 210. An n-drift layer 252 of the gate finger region exists between the field relaxation layer 251 of the gate finger region and the n-buffer layer 235. A depth (d_max) 238 at which crystal defects become maximum exists in the n-drift layer 252 of the gate finger region, and the region from the surface oxide film 233 to d_max 238 becomes a range region 237.

[0067] A current flow line 700 represents the path of a current around the gate finger region 222 at the time of turn-off. The difference from the first embodiment is that a crystal defect region (range region 237) is formed by irradiation of light ions from the chip surface not only in the peripheral region 221 of the semiconductor chip 200 but also in the gate finger region 222 located between the active regions 210 on both sides.

[0068] [Explanation of Operation] The operation at turn-off will be explained, focusing on the differences from the first embodiment. In Fig. 11, an emitter electrode 211 is present on the surface of the active region 210, but the emitter electrode 211 is not present in the gate finger region 222, and the n-drift layer 252 in the gate finger region and the emitter electrode 211 are separated by a surface oxide film 250 in the gate finger region. Therefore, there is no path for current to escape directly upward from the gate finger region 222.

[0069] On the other hand, the p-emitter layer 236, which is the hole injection source, is present over the entire back surface of the semiconductor chip 200, including the gate finger region 222, and therefore the holes injected into the gate finger region 222 from the back surface flow toward the emitter electrode 211 in the active region 210. At this time, current flow lines 700 concentrate near the electric field relaxation layer 251 in the gate finger region (253 in FIG. 11), causing localized heat generation and reducing the withstand voltage.

[0070] Furthermore, the junction (254 in FIG. 11 ) between the deepest part of the electric field relaxation layer 251 in the gate finger region, which is formed deeper than the p-base layer 217 in the active region 210, and the n-drift layer 252 is a region where an electric field concentrates. Since dynamic avalanche is caused by the concentration of an electric field and current, dynamic avalanche is likely to occur near the electric field relaxation layer 251 in the gate finger region 222 during turn-off, which becomes a factor in reducing the breakdown resistance of the semiconductor chip 200.

[0071] 11 , when light ions are selectively irradiated from the surface of the gate finger region 222, a range region 237 where carrier lifetime is short is formed on the surface side of the gate finger region 222. As a result, the carrier concentration accumulated in the n-drift layer 252 of the gate finger region decreases, and holes accumulated in the n-drift layer 252 of the gate finger region are prevented from concentrating in the electric field relaxation layer 251 of the gate finger region at turn-off, thereby suppressing current concentration. In addition, the carrier concentration accumulated in the n-drift layer 252 of the gate finger region decreases, and the width of the depletion layer formed from the electric field relaxation layer 251 of the gate finger region to the active region 210 increases, thereby reducing the electric field strength in the vicinity of the electric field relaxation layer 251 of the gate finger region 222.

[0072] Since dynamic avalanche is caused by the concentration of an electric field and current, these effects can suppress dynamic avalanche occurring in the electric field relaxation layer 251 in the gate finger region. As a result, localized heat generation can be prevented, and the breakdown resistance of the semiconductor chip 200 can be improved.

[0073] [Modification of Semiconductor Switching Element] Figure 12 is a diagram showing a modification of the second embodiment. Components that are the same as those in Figure 11 are assigned the same reference numerals. As shown in Figure 12, in the second embodiment, when crystal defects are introduced into the gate finger region 222, the crystal defects may be introduced not only in the gate finger region 222 but also so as to extend over part of the active region 210 adjacent to the gate finger region 222, where the current flow lines 700 are concentrated. This makes it possible to alleviate current concentration in the active region 210, thereby improving the withstand capability.

[0074] However, if the area of ​​crystal defects introduced into the active region 210 is too large, as described in the modified example of the first embodiment ( FIG. 8 ), the carriers stored in the active region during conduction are likely to disappear due to recombination. This increases the on-state voltage (Vcesat), resulting in an increase in conduction loss (Econd). Therefore, in order to keep the increase rate of Vcesat to 1% or less, even in this embodiment, it is preferable that the amount of penetration ΔX of crystal defects into the active region 210 be 40% or less of the thickness D of the drift layer.

[0075] [Effects of the Second Embodiment] The semiconductor chip 200 (FIGS. 2, 8 to 11) according to the second embodiment conducts current vertically between the main surface and the back surface of the semiconductor substrate, and includes an active region (210) which is a current conduction region, a peripheral region (221) arranged to surround the active region (210), and gate finger regions (222) sandwiched on both sides by the active region (210). The peripheral region (221) includes a main junction region (224), an FLR region (225), and The gate finger region (222) has a p-well region (251) provided in contact with the main surface, and the p-well region (251) is provided between the active regions (210). The active region (210) and the gate finger region (222) have a drift layer (218, 252) made of an integral substrate. The semiconductor device has a selective crystal defect region (237) formed in the drift layer (218, 252) by light ion irradiation, the selective crystal defect region (237) being provided in the drift layer (252) including at least a gate finger region (222) so as to be sandwiched between active regions (210), and the crystal defect density of the gate finger region (222) is higher than the crystal defect density of the active region (210), or when the depth from the interface of a surface oxide film (233) of the semiconductor device at which the crystal defect density becomes maximum is defined as d_max (238), the average crystal defect density in the gate finger region (222) up to said depth d_max (238) is higher than the average crystal defect density of the active region (210), and the depth d_max (238) is formed on the back surface side of 40% of the thickness D of the drift layer of the semiconductor device (d_max≧0.4×D).

[0076] By doing so, the semiconductor chip 200 according to the second embodiment can prevent holes accumulated in the n-drift layer 252 in the gate finger region from concentrating in the electric field relaxation layer 251 in the gate finger region at turn-off, thereby suppressing current concentration. Furthermore, the width of the depletion layer formed from the electric field relaxation layer 251 in the gate finger region to the active region 210 is widened, thereby reducing the electric field strength in the vicinity of the electric field relaxation layer 251 in the gate finger region 222. Dynamic avalanche occurring in the electric field relaxation layer 251 in the gate finger region can be suppressed. As a result, localized heat generation can be prevented, and the breakdown resistance of the semiconductor chip 200 can be improved.

[0077] Furthermore, by setting the amount ΔX of intrusion of crystal defects into the active region 210 to 40% or less of the thickness D of the drift layer, the rate of increase in the on-state voltage (Vcesat) can be suppressed to 1% or less.

[0078] In the semiconductor chip 200 according to the second embodiment, the gate finger region (222) is a region that does not include the n+ emitter (216) in the active region (210).

[0079] In the semiconductor device according to the second embodiment, the gate finger region (222) is a p-well region (251) sandwiched between active regions (210), and the junction depth of the p-well region (251) is deeper than the depth of the bottom of a gate electrode (213) formed by a trench gate within the active region (210).

[0080] Third Embodiment Fig. 13 is a plan view of a semiconductor chip 200 according to a third embodiment of the present invention. Fig. 13 schematically shows a connection configuration with a gate driver. The third embodiment differs from the first embodiment as follows. First, the semiconductor chip 200 according to the third embodiment has two gate pads (321a and 322a, 321b and 322b), and includes a first gate pad 321 and a second gate pad 322 that are electrically insulated from each other and can be controlled independently.

[0081] Next, the semiconductor chip 200 is characterized in that two semiconductor chips 200a and 200b, which have different crystal defect structures, are connected in parallel and driven. Figure 13 also shows the connection between the two semiconductor chips 200a and 200b and the gate drivers that drive them. The first gate pad 321a and second gate pad 322a of the semiconductor chip 200a, and the first gate pad 321b of the semiconductor chip 200b, are connected to the first gate driver 41. The second gate pad 322b of the semiconductor chip 200b is connected to the second gate driver 42.

[0082] Figure 14 is a cross-sectional view taken along PQ of the semiconductor chip 200a shown in Figure 13. The difference from the cross-sectional view of the first embodiment shown in Figure 3 is that the first gate electrode 239a is connected to the first gate pad 321a shown in Figure 13, and the second gate electrode 240a is connected to the second gate pad 322a shown in Figure 13. In this embodiment, the first gate pad 321a and the second gate pad 322a are connected to the first gate driver 41 and have the same potential, so the electrical connection configuration in the semiconductor chip 200a is substantially the same as in the first embodiment.

[0083] FIG. 15 is a cross-sectional view taken along RS of the semiconductor chip 200b shown in FIG. 13. The difference from the cross-sectional view of the first embodiment shown in FIG. 3 is that there are two types of gate electrodes that can be controlled independently. The differences from FIG. 14 are as follows. First, the second gate electrode 240b is connected to the second gate pad 322b that is connected to the second gate driver 42 shown in FIG. 13. The first gate electrode 239b is connected to the first gate pad 321b shown in FIG. 13. In other words, the first gate electrode 239b and the second gate electrode 240b are independently controlled by separate gate drivers 41 and 42, respectively.

[0084] Next, the semiconductor chip 200b differs in that second crystal defect regions (237b, 241b) are formed on the back surface of the semiconductor chip 200b across the entire active region 210b and the peripheral region 221b. The second crystal defect region has a depth (d_max2) 241b where the second defect density is maximum, and a second range region 237b (light ion passage region) where crystal defects caused by the passage of light ions exist between the collector electrode 212b and the depth (d_max2) 241b where the second crystal defect density is maximum.

[0085] In the regions where the crystal defects exist, i.e., second range region 237b and depth (d_max2) 241b where the second crystal defect density is maximum, the carrier lifetime is shorter than in regions where no crystal defects exist, i.e., carrier recombination is more likely to occur in these regions than in other regions of the n-drift layer.

[0086] In the first embodiment, the purpose of irradiating light ions from the surface of the semiconductor chip 200 was to reduce the number of accumulated holes in the semiconductor chip 200. However, in addition to that purpose, the purpose of irradiating light ions in this embodiment in FIG. 15 is to more effectively suppress current concentration in the main junction region 224b by suppressing the amount of holes injected from the p emitter layer 236b, and therefore light ions are irradiated over the entire region of the semiconductor chip 200b where the p emitter layer 236b is present.

[0087] 15, the closer the depth (d_max2) 241b at which the second crystal defect density is maximum is to the p-emitter layer 236b, which is the hole injection source, the more effectively the hole injection can be suppressed. Therefore, it is preferable that the depth (d_max2) 241b at which the second crystal defect density is maximum satisfies the relationship d_max≦d_max2<D.

[0088] As in the first embodiment, the active region 210a of the semiconductor chip 200a does not have any crystal defects, so the breakdown voltage can be improved without increasing the on-state voltage (Vcesat). In other words, the semiconductor chip 200a has low conduction loss (Econd). On the other hand, the semiconductor chip 200b used in this embodiment has a second crystal defect region throughout the entire backside of the chip, including the active region, which reduces the number of holes injected from the p-emitter layer 236b and inevitably increases the on-state voltage (Vcesat). In this embodiment, the number of holes injected and accumulated in the semiconductor chip 200b is reduced, which increases the discharge rate of accumulated carriers during switching and enables high-speed switching. In other words, the conduction loss (Econd) is larger than that of the semiconductor chip 200a, but the switching loss (turn-off loss: Eoff) is smaller than that of the semiconductor chip 200a.

[0089] 16 is a diagram showing the drive sequence of the first gate drive device 41 and the second gate drive device 42 in this embodiment. The first gate pad 321a and the second gate pad 322a of the semiconductor chip 200a and the first gate pad 321b of the semiconductor chip 200b are connected to the first gate drive device 41. The second gate drive device 42 is connected to the second gate pad 322b of the semiconductor chip 200b.

[0090] When the semiconductor chips 200a and 200b are conducting, and until just before they are turned off, the first gate drive device 41 and the second gate drive device 42 apply a voltage (Von) that is equal to or higher than the threshold voltage of the semiconductor chips 200a and 200b (see Gs and Gc in Figure 16).

[0091] During turn-off, the output voltage Gc of the first gate driver 41 turns off before the output voltage Gs of the second gate driver 42 and becomes equal to or lower than the threshold voltage Vth of the semiconductor chip 200a (Voff≦Vth). This causes the gate of the semiconductor chip 200a, which has a large amount of hole accumulation and low conduction loss, to turn off first, and the extraction of stored carriers begins. On the other hand, the output voltage Gs of the second gate driver 42 connected to the second gate pad 322b is equal to or higher than the threshold voltage Vth (Von>Vth). Therefore, current continues to flow through the semiconductor chip 200b, which has a small amount of hole accumulation and can be switched on quickly. After a delay time (Td_off) between Gc and Gs, the output voltage Gs of the second gate driver 42 becomes equal to or lower than the threshold voltage (Voff≦Vth). This completes the turn-off of the entire semiconductor device consisting of the semiconductor chips 200a and 200b connected in parallel.

[0092] [Effects of the Third Embodiment] The semiconductor chip 200 (Figures 12 to 16) according to the third embodiment has a second crystal defect region (237, 241) at a depth d_max (238) or on the back side of the depth d_max (238), the second crystal defect region (237, 241) including all of the active region (210), the peripheral region (221), and the gate finger region (222).

[0093] In the semiconductor chip 200 according to the third embodiment, the semiconductor device is composed of a plurality of semiconductor devices having different on-state voltages (Vcesat) or crystal defect densities, and the semiconductor device according to the first embodiment is applied to the semiconductor device of one or more of the components.

[0094] The semiconductor chip 200 according to the third embodiment is composed of a first semiconductor device (Hc chip 200a) to which the semiconductor device of the first embodiment is applied, and a second semiconductor device (Hs chip 200b), and the first semiconductor device (Hc chip 200a) and the second semiconductor device (Hs chip 200b) have their respective main surfaces and back surfaces connected to each other (parallel connection), the first semiconductor device (200a) having first gate electrodes (321a, 322a), the second semiconductor device (200b) having a first gate electrode (321b) and a second gate electrode (322b), and the first gate electrodes (321a, 322a, 321b) are driven and controlled independently by a first gate driver (41), and the second gate electrode (322b) is driven and controlled independently by a second gate driver (42).

[0095] As described above, in the third embodiment, a semiconductor chip 200 having a plurality of gate electrodes is combined with chips (semiconductor chip 200a and semiconductor chip 200b) each having different crystal defects introduced therein, and a plurality of gate drivers (gate driver 41 and gate driver 42) are driven with a time lag, thereby achieving low conduction loss (Econd) by causing current to flow mainly through semiconductor chip 200a, which has low conduction loss, during conduction, and reducing switching loss (turn-off loss: Eoff) by shutting off (turning off) the semiconductor device using semiconductor chip 200b, which has a small amount of hole accumulation and can switch quickly, during switching (turn-off). In other words, by driving two semiconductor chips having different crystal defect structures with two independent gate drivers with a time lag, it is possible to achieve both reduced conduction loss and reduced switching loss, and it is possible to achieve both high breakdown resistance and low loss more effectively than by using a single semiconductor device and gate driver.

[0096] In addition to introducing different crystal defects into the semiconductor chips connected in parallel, more flexible control of output characteristics is possible by appropriately changing the concentration of the p emitter layer 236a of the highly conductive semiconductor chip 200a and the concentration of the p emitter layer 236b of the high-speed semiconductor chip 200b, and it is not necessarily required that the impurity concentration of the p emitter layer 236a of the highly conductive semiconductor chip 200a and the impurity concentration of the p emitter layer 236b of the high-speed semiconductor chip 200b are the same.

[0097] [Variations of semiconductor switching element] For example, by making the impurity concentration of the p emitter layer 236a of the highly conductive semiconductor chip 200a higher than the impurity concentration of the p emitter layer 236b of the high-speed semiconductor chip 200b, the on-voltage of the entire semiconductor device consisting of the semiconductor chips 200a and 200b connected in parallel is further reduced, and it is therefore possible to control the output characteristics to an appropriate level depending on the application of the power conversion device to which it is applied.

[0098] FIG. 17 is a diagram showing the structure of a unit cell in the active region of a semiconductor chip, which is a modification of the third embodiment. The semiconductor device in FIG. 17 includes a semiconductor chip 200a and a semiconductor chip 200b connected in parallel. Specifically, the first semiconductor chip 200a (Hc chip 200a), which is a semiconductor chip with a high efficiency of hole injection from the collector side, and the second semiconductor chip 200b (Hs chip 200b), which is a semiconductor chip with a low efficiency of hole injection from the collector side, are connected in parallel and driven in the same manner. That is, the collector electrodes (212a, 212b) and the emitter electrodes (211a, 211b) shown in FIG. 17 are connected to each other.

[0099] The components of the Hc chip 200a and the Hs chip 200b are similar to the components of the active region 210b in FIG. 15 of the third embodiment, except for the impurity concentration of the p-emitter layers (236a, 236b).

[0100] In the third embodiment, the impurity concentrations of the p-emitter layers (236 a, 236 b) of the two semiconductor chips are the same. In contrast, in this modification, the impurity concentration of the p-emitter layer 236 a of the Hc chip 200 a, which is a high conductivity chip, is higher than the impurity concentration of the p-emitter layer 236 b of the Hs chip 200 b, which is a high-speed chip.

[0101] In this modification, the gate electrodes (239a, 239b, 240a, 240b) have a side gate shape that has a small gate parasitic capacitance and enables high-speed switching. However, the present invention is not limited to this, and the gate electrodes (239a, 239b, 240a, 240b) may have a trench gate shape, as in Example 3 shown in FIGS. 14 and 15 .

[0102] The first gate electrode 239a and second gate electrode 240b of the Hc chip 200a, which is the high conductivity chip, are connected to the first gate driver 41 (Gc). The first gate electrode 239b of the Hs chip 200b, which is the high-speed chip, is connected to the first gate driver 41 (Gc), and the second gate electrode 240b is connected to the second gate driver 42 (Gs). In other words, the Hc chip 200a, which is the high conductivity chip, is controlled only by the first gate driver 41 (Gc), and the Hs chip 200b, which is the high-speed chip, is independently controlled by both the first gate driver 41 (Gc) and the second gate driver 42 (Gs).

[0103] In this modification, the Hc chip 200a, which has high conductivity and low conduction loss, and the Hs chip 200b, which has high speed and low switching loss, are connected in parallel, and the efficiency of hole injection from the backside is spatially divided by controlling the impurity concentration of the p-emitter layers (236a, 236b). By combining this with the drive of the two gate drivers (41, 42) of this embodiment, which provides a delay (Td_off) between turning off the Gc gate electrodes (239a, 240a, 239b) and turning off the second gate electrode (240b), the amount of accumulated carriers in the entire drift region from the collector side (backside) to the emitter side (front side) can be dynamically (temporally) controlled. As a result, the effect of reducing both conduction loss and switching loss is enhanced, which has the advantage of further reducing losses generated in the semiconductor device.

[0104] The present invention is not limited to the above-described embodiments, and includes other modifications and applications without departing from the spirit of the present invention as defined in the claims. For example, the above-described embodiments have been described in detail to facilitate understanding of the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another example, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0105] REFERENCE SIGNS LIST 10 DC power supply 20 Inverter circuit 21 Smoothing capacitor 22 Command logic unit 23 Positive electrode connecting wire 24 Negative electrode connecting wire 30 Inverter unit 31 Semiconductor device 32 Freewheeling diode 33 Connection point 40 Gate drive device (gate drive circuit) 41 First gate drive device 42 Second gate drive device 70 Electric motor 100 Electric motor control system 200, 200a, 200b Semiconductor chip (semiconductor device) 210, 210a, 210b Active region 211, 211a, 211b Emitter electrode 212, 212a, 212b Collector electrode 213 Gate electrode 214, 214a, 214b Gate oxide film 215, 215a, 215b Gate insulating film of active region 216, 216a, 216b n+ emitter layer in active region 217, 217a, 217b p base layer in active region 218, 218a, 218b n- drift layer in active region 220 Inactive region 221, 221a, 221b Peripheral region 222, 222a, 222b Gate finger region 223 Gate pad 224, 224a, 224b Main junction region 225, 225a, 225b FLR region 226, 226a, 226b Edge region 227, 227a, 227b Gate wiring 228, 228a, 228b Field plate in main junction region (main junction FP) 229, 229a, 229b Electric field relaxation layer in main junction region (main junction FP) 230, 230a, 230b Field plate (FP) in the FLR region 231, 231a, 231b Electric field relaxation layer (guard ring) in the FLR region 232, 232a, 232b Electric field blocking layer (channel stopper) in the edge region 233, 233a, 233b Surface oxide film in the peripheral region 234, 234a, 234b N-drift layer in the peripheral region 235, 235a, 235b N buffer layer 236, 236a, 236b P emitter layer 237, 237a, 237b Light ion passage region (crystal defect region) 238, 238a, 238b Depth at which the crystal defect density is maximum (d_max) 239, 239a,239b First gate electrode 240, 240a, 240b Second gate electrode 241b Depth at which second crystal defect density is maximum (d_max2) 250 Surface oxide film in gate finger region 251 Electric field relaxation layer in gate finger region 252 N-drift layer in gate finger region 253 Point where current concentrates 254 Point where electric field concentrates 321, 321a, 321b First gate pad 322, 322a, 322b Second gate pad 700 Current flow line 701 Equipotential line,

Claims

1. A semiconductor device comprising: an active region which vertically conducts current between a main surface and a back surface of a semiconductor substrate and which is a current conduction region; and a peripheral region arranged to surround the active region, wherein the peripheral region has a main junction region, a field limiting ring (FLR) region, and an edge region, wherein the main junction region is provided between the active region and the FLR region, wherein the active region and the peripheral region have a drift layer made of an integral substrate, and wherein the drift layer has a selective crystal defect region formed by light ion irradiation, wherein the selective crystal defect region is provided in the drift layer including at least the main junction region so as to surround the active region, and wherein a density of crystal defects in the main junction region is higher than a density of crystal defects in the active region, or wherein, when a depth from an interface of a surface oxide film of the semiconductor device at which the density of crystal defects is maximum is defined as d_max, an average density of crystal defects in the main junction region up to the depth d_max is higher than an average density of crystal defects in the active region, the depth d_max is formed on a back surface side that is greater than 40% of a thickness D of the drift layer of the semiconductor device.

2. A semiconductor device comprising: an active region which conducts current vertically between a main surface and a back surface of a semiconductor substrate and which is a current conducting region; a peripheral region arranged so as to surround the active region; and a gate finger region sandwiched on both sides by the active region, wherein the peripheral region has a main junction region, an FLR (Field Limiting Ring) region, and an edge region, wherein the main junction region is provided between the active region and the FLR region, and the gate finger region has a p-well region provided in contact with the main surface, the p-well region being provided between the active regions, wherein the active region and the gate finger region have a drift layer made of an integral substrate, and wherein the drift layer has a selective crystal defect region caused by light ion irradiation, wherein the selective crystal defect region is provided in the drift layer including at least the gate finger region so as to be sandwiched between the active regions, and the density of crystal defects in the gate finger region is higher than the density of crystal defects in the active region, or a depth d_max from an interface of a surface oxide film of the semiconductor device at which density of crystal defects is maximum, an average density of crystal defects up to the depth d_max in the gate finger region is higher than an average density of crystal defects in the active region, and the depth d_max is formed on the back surface side more than 40% of a thickness D of a drift layer of the semiconductor device.

3. The semiconductor device according to claim 1, characterized in that an end portion on an inner periphery side of the selective crystal defect region is located closer to the FLR region than the center of the main junction region.

4. The semiconductor device according to claim 1, characterized in that the outer peripheral end of the selective crystal defect region is present in a region extending from the electric field relaxation layer closest to the active region in the FLR region to the edge region.

5. The semiconductor device according to claim 1, characterized in that the selective crystal defect region is the entire outer periphery region including the main junction region, the FLR region, and the edge region.

6. The semiconductor device according to claim 1, wherein a portion of the selective crystal defect region invades into the active region adjacent to the main junction region, and a width ΔX of the crystal defect region invading into the active region is 40% or less of a thickness D of the drift layer.

7. The semiconductor device according to claim 1, characterized in that, when comparing the resistivities of the substrate of the drift layer, the following magnitude relationship holds between the resistivity ρ2 of the selective crystal defect region, the resistivity ρ2 at the depth d_max where the density of crystal defects is maximum, and the resistivity ρ3 of the active region: ρ3<ρ1<ρ2.

8. The semiconductor device according to claim 1, wherein the depth d_max is in the range of the following formula, 0.5×D≦d_max<D, where D is a chip thickness of the semiconductor device.

9. The semiconductor device according to claim 1, characterized in that a second crystal defect region including all of the active region, the peripheral region, and the gate finger region is provided on the depth d_max or on the back side of the depth d_max.

10. A power conversion device comprising a semiconductor device according to any one of claims 1 to 9.

Images