Load current detection device

Abstract

The present invention relates to a load current detection device. The load current detection device includes: a first transistor connected between an upper power voltage application end and a load to supply a driving voltage to the load according to a switching control signal; a second transistor forming a current mirror and mirroring a load current flowing in the load through the first transistor to generate a mirror current; a current-voltage conversion unit configured to generate a sensing voltage by voltage-converting the mirror current such that a drain-source voltage of the second transistor follows a drain-source voltage of the first transistor; and a voltage-current conversion unit configured to generate a detection current by current-converting the sensing voltage.

Description

Load current detection device

[0001] The present invention relates to a load current detection device, and more specifically, to a load current detection device capable of precisely detecting a load current flowing to a load through a semiconductor switch connected to a high-side terminal of a power source.

[0002] Typically, a power control system connects a high-side switch between the high-side terminal of a power supply and a load, and supplies or cuts off power to the load through the high-side switch. Here, the high-side switch can be implemented using a semiconductor device such as a metal oxide semiconductor field effect transistor.

[0003] A power control system configured in this manner can detect load current flowing through a high-side switch to detect load abnormalities, or, if the load is a battery-powered device, monitor battery usage. Therefore, many devices require the ability to detect current supplied to a load through a high-side switch as a critical function.

[0004] However, high-side switches are designed to have very small on-resistance values ​​to perform switching operations and minimize power consumption. Therefore, it is impossible to directly connect a resistor in series with the high-side switch to detect the current flowing to the load through the high-side switch. Therefore, a method has been proposed to detect the current flowing to the load through the high-side switch using a current mirror method.

[0005] Figures 1 and 2 are circuit diagrams illustrating a typical load current detection device.

[0006] Referring to Fig. 1, a load current detection device (10) may include a first transistor (T1), a load (12), a gate driver (14), a second transistor (T2), and a current detection unit (16). The first transistor (T1) is a high-side switch connected to a high-side power voltage (VHH) application terminal, and is controlled by the gate driver (14) to supply a driving voltage to the load (12).

[0007] The second transistor (T2) forms a current mirror with the first transistor (T1), and mirrors the load current (I1) flowing to the load (12) through the first transistor (T1) to generate a mirror current (I2). The current detection unit (16) detects the size of the mirror current (I2).

[0008] Here, the ratio between the load current (I1) and the mirror current (I2) is controlled according to the ratio between the width (W) and the length (L) of each of the first and second transistors (T1, T2), i.e., W / L. For example, if the W / L of the second transistor (T2) is formed to be 1 / 100,000 times that of the first transistor (T1), the mirror current (I2) flows at a size corresponding to 1 / 100,000 of the load current (I1).

[0009] However, since the first transistor (T1) has a very small on-resistance, the drain-source voltage of the first transistor (T1) is very small when the first transistor (T1) is on. Generally, in the case of a high-current switch, the drain-source voltage of the first transistor (T1) is designed to have a value of approximately 0.2 V or less.

[0010] In contrast, the W / L of the second transistor (T2) is designed to be smaller than the W / L of the first transistor (T1), and since the smaller the W / L, the larger the on-resistance, the drain-source voltage of the second transistor (T2) has a larger value than the drain-source voltage of the first transistor (T1).

[0011] As the difference between the drain-source voltages between the first and second transistors (T1, T2) increases, an error may occur between the load current (I1) and the mirror current (I2). To reduce this error, as shown in Fig. 2, a method has been proposed in which a bias transistor (T3) is added between the second transistor (T2) and the current detection unit (16), and the drain-source voltage of the second transistor (T2) is prevented from having a large difference from the drain-source voltage of the first transistor (T1) through the bias transistor (T3).

[0012] However, since the bias voltage (VB) is a fixed voltage value, it cannot accurately track the drain-source voltage of the first transistor (T1). Therefore, this method may also result in errors in current detection.

[0013] The embodiment is intended to overcome the above-described problem and relates to a load current detection device capable of precisely detecting a load current flowing to a load through a semiconductor switch connected to an upper terminal of a power source.

[0014] The technical tasks to be achieved by the embodiments are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary knowledge in the relevant field from the description of the embodiments.

[0015] A load current detection device according to an embodiment includes a first transistor connected between an upper power voltage supply terminal and a load to supply a driving voltage to the load according to a switching control signal, a second transistor forming a current mirror and mirroring a load current flowing to the load through the first transistor to generate a mirror current; a current-to-voltage conversion unit converting the mirror current to voltage so that a drain-source voltage of the second transistor follows a drain-source voltage of the first transistor to generate a detection voltage; and a voltage-to-current conversion unit converting the detection voltage to current to generate a detection current.

[0016] Here, the current-to-voltage conversion unit includes an operational amplifier including a non-inverting input terminal for receiving the drain-source voltage of the first transistor, an inverting input terminal for receiving the drain-source voltage of the second transistor, and an output terminal for outputting the detection voltage; and a resistor connected between the second transistor and the output terminal.

[0017] Here, the voltage-current converter generates a voltage that follows the detection voltage, converts the voltage that follows the detection voltage into a current, and outputs the detection current.

[0018] Here, the voltage-current conversion unit includes a third transistor connected between the upper power voltage application terminal and a resistor and having a gate terminal connected to the gate terminal of the first transistor; a resistor connected between the third transistor and the first node; an operational amplifier that adjusts the voltage of the first node to follow the detection voltage; and a fourth transistor that adjusts and outputs the size of the detection current according to the output of the operational amplifier.

[0019] Here, the voltage-to-current converter includes a first voltage-to-current converter that follows the detection voltage to generate a first detection current having a first amplification factor compared to the mirror current; and a second voltage-to-current converter that follows the detection voltage to generate a second detection current having a second amplification factor compared to the mirror current.

[0020] Here, a current detection unit is further included that converts the detection current into voltage and outputs a detection voltage.

[0021] Here, the current detection unit amplifies a voltage proportional to the detection current and outputs it as the detection voltage.

[0022] Here, the current detection unit includes a detection resistor through which the detection current flows at both ends; and an operational amplifier including a non-inverting input terminal connected to one end of the detection resistor, an inverting input terminal connected to the other end of the detection resistor, and an output terminal for outputting the detection voltage.

[0023] A load current detection device according to an embodiment can precisely detect a load current flowing to a load through a semiconductor switch connected to an upper terminal of a power source.

[0024] Fig. 1 is a circuit diagram illustrating a typical load current detection device.

[0025] Fig. 2 is a circuit diagram illustrating a typical load current detection device.

[0026] FIG. 3 is a diagram illustrating a power control system according to one embodiment of the present invention.

[0027] Figure 4 is a detailed circuit diagram of the power control system illustrated in Figure 3.

[0028] FIG. 5 is an equivalent circuit diagram illustrating a load current detection method performed in the power control system illustrated in FIG. 4.

[0029] Fig. 6 is a circuit diagram illustrating another embodiment of the current detection unit illustrated in Fig. 4.

[0030] FIG. 7 is a detailed circuit diagram illustrating a power control system according to another embodiment of the present invention.

[0031] FIG. 3 is a diagram illustrating a power control system according to one embodiment of the present invention.

[0032] Figure 4 is a detailed circuit diagram of the power control system illustrated in Figure 3.

[0033] FIG. 5 is an equivalent circuit diagram illustrating a load current detection method performed in the power control system illustrated in FIG. 4.

[0034] Fig. 6 is a circuit diagram illustrating another embodiment of the current detection unit illustrated in Fig. 4.

[0035] FIG. 7 is a detailed circuit diagram illustrating a power control system according to another embodiment of the present invention.

[0036] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the attached drawings. The same or similar components will be given the same or similar drawing reference numerals, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" used for components in the following description are given or used interchangeably only for the convenience of writing the specification, and do not in themselves have distinct meanings or roles. In addition, when describing the embodiments disclosed in this specification, if it is determined that a specific description of a related known technology may obscure the gist of the embodiments disclosed in this specification, a detailed description thereof will be omitted. In addition, the attached drawings are only intended to facilitate easy understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and technical scope of the embodiments.

[0037] Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

[0038] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0039] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0040] In this application, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but should be understood not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0041] FIG. 3 is a diagram illustrating a power control system according to one embodiment of the present invention.

[0042] Referring to FIG. 3, a power control system (100) according to one embodiment of the present invention may include a switching unit (110), a load (120), a gate driving unit (130), and a load current detection unit (140). Here, the switching unit (110) is connected between an upper power voltage (VHH) application terminal and a first node (N11), and outputs a driving voltage (VOUT) according to a switching control signal (CONT). The first node (N11) is connected to an output terminal (TO).

[0043] The load (120) is connected between the output terminal (TO) and the lower power supply voltage (VSS) application terminal, and receives a driving voltage (VOUT) through the switching unit (110). The gate driving unit (130) generates a switching control signal (CONT) and applies it to the switching unit (110).

[0044] The load current detection unit (140) detects the load current (I11) flowing to the load (120) through the switching unit (110) and outputs the detection result as a detection voltage (VA). The load current detection unit (140) may include a current mirroring unit (142), a current-to-voltage conversion unit (144), a voltage-to-current conversion unit (146), and a current detection unit (148).

[0045] When the driving voltage (VOUT) is supplied to the load (120) through the switching unit (110), the current mirroring unit (142) mirrors the load current (I11) flowing from the upper power voltage (VHH) application terminal to the load (120) to generate a mirror current (I12). The current mirroring unit (142) outputs the mirror current (I12) to the second node (N12). Here, the current mirroring unit (142) can generate the mirror current (I12) by mirroring 1 / 100000 times the load current (I11), but one embodiment of the present invention is not limited thereto.

[0046] The current-to-voltage conversion unit (144) is connected to the first and second nodes (N11, N12) and converts the mirror current (I12) to voltage so that the voltage of the second node (N12) follows the voltage of the first node (N11) to generate a detection voltage (V1). The current-to-voltage conversion unit (144) outputs the detection voltage (V1) to the voltage-to-current conversion unit (146).

[0047] The voltage-to-current conversion unit (146) receives the detection voltage (V1) from the current-to-voltage conversion unit (144), converts it into current to generate a detection current (I13), and outputs it to the current detection unit (148). That is, the voltage-to-current conversion unit (146) according to one embodiment of the present invention converts the detection voltage (V1) into the form of current and transmits it to the current detection unit (148) connected to the lower power voltage (VSS) application terminal, thereby preventing the detection result from being affected by the difference between the upper power voltage (VHH) and the lower power voltage (VSS).

[0048] The current detection unit (148) is connected to the lower power supply voltage (VSS) input terminal, receives the detection current (I13) from the voltage-current conversion unit (146), converts it into voltage, and outputs the detection voltage (VA). The current detection unit (148) is configured as a current-voltage converter to generate a voltage proportional to the detection current (I13), amplify it, and output the detection voltage (VA). One embodiment of the present invention is not limited thereto, and the current detection unit (148) may be omitted, and the detection current (I13) may be used as the final output of the load current detection unit (140). In this case, a separate resistor (not shown) may be configured externally to convert the detection current (I13) into voltage.

[0049] Figure 4 is a detailed circuit diagram of the power control system illustrated in Figure 3.

[0050] Referring to FIG. 4, a switching unit (110) according to one embodiment of the present invention may include a first transistor (T11). Here, the first transistor (T11) is a high-side switch connected to the upper power voltage (VHH) supply terminal, and serves as a control switch that supplies a driving voltage (VOUT) to a load (120).

[0051] The first transistor (T11) is connected between the upper power voltage (VHH) application terminal and the first node (N11) and outputs a driving voltage (VOUT) according to a switching control signal (CONT). Here, the first transistor (T11) may be formed as an NMOS transistor. The first transistor (T11) includes a drain terminal connected to the upper power voltage (VHH) application terminal, a source terminal connected to the first node (N11), and a gate terminal to which a switching control signal (CONT) is applied.

[0052] The current mirroring unit (142) may include a second transistor (T12). Here, the second transistor (T12) forms a current mirror with the first transistor (T11). The second transistor (T12) mirrors the load current (I11) to generate a mirror current (I12) and outputs it to the second node (N12).

[0053] The second transistor (T12) can be formed as an NMOS transistor and includes a drain terminal connected to the upper power supply voltage (VHH) application terminal, a gate terminal connected to the gate terminal of the first transistor (T11), and a source terminal connected to the second node (N12).

[0054] The current-to-voltage converter (144) may include a first operational amplifier (OPA1) and a resistor (R1). The first operational amplifier (OPA1) includes a non-inverting input terminal (+) connected to a first node (N11), an inverting input terminal (-) connected to a second node (N12), and an output terminal.

[0055] The resistor (R1) has one end connected to the second node (N12) and the other end connected to the output terminal of the first operational amplifier (OPA1).

[0056] The voltage-current converter (146) includes a third transistor (T13), a second resistor (R2), a second operational amplifier (OPA2), and a fourth transistor (T14). The third transistor (T13) may be formed as an NMOS transistor. The third transistor (T13) includes a drain terminal connected to the drain terminal of the first transistor (T11), a gate terminal connected to the gate terminal of the first transistor (T11), and a source terminal connected to one end of the second resistor (R2).

[0057] The second resistor (R2) has one end connected to the source terminal of the third transistor (T13) and the other end connected to the third node (N13). The second resistor (R2) may have the same characteristics as the first resistor (R1).

[0058] The second operational amplifier (OPA2) includes a non-inverting input terminal (+) connected to the output terminal of the first operational amplifier (OPA1), an inverting input terminal (-) connected to the third node (N13), and an output terminal.

[0059] The fourth transistor (T14) can be formed as a PMOS transistor and includes a source terminal connected to the third node (N13), a gate terminal connected to the output terminal of the second operational amplifier (OPA2), and a drain terminal connected to one end of the detection resistor (RA).

[0060] The current detection unit (148) may include a detection resistor (RA) and a third operational amplifier (OPA3). The detection resistor (RA) includes one end connected to the drain terminal of the fourth transistor (T14) and the other end connected to the lower power supply voltage (VSS) application terminal. The detection resistor (RA) may have the same characteristics as the first and second resistors (R1, R2).

[0061] FIG. 5 is an equivalent circuit diagram illustrating a load current detection method performed in the power control system illustrated in FIG. 4.

[0062] Referring to Fig. 5, first, when the first transistor (T11) is turned on by the switching control signal (CONT), the driving voltage (VOUT) is supplied to the load (120). At this time, the driving voltage (VOUT) is output as a voltage that is lowered by the drain-source voltage (VDS1) of the first transistor (T11) from the upper power supply voltage (VHH). That is, the drain-source voltage (VDS1) of the first transistor (T11) corresponds to the difference between the upper power supply voltage (VHH) and the driving voltage (VOUT), and has a voltage value corresponding to the product of the load current (I11) flowing through the first transistor (T11) and the on-resistance (RDSON1) of the switching transistor (T11).

[0063] In this state, the second transistor (T12) mirrors the load current (I11) and outputs the mirror current (I12). At this time, the mirror current (I12) is output as a value proportional to the load current (I11) by the W / L ratio between the first transistor (T11) and the second transistor (T12). That is, the mirror current (I12) has a value obtained by multiplying the load current (I11) by the value obtained by dividing the W / L value of the second transistor (T12) by the W / L value of the first transistor (T11). One embodiment of the present invention is described assuming that the W / L ratio between the first transistor (T11) and the second transistor (T12) is 1 / 100000 times, and in this case, the mirror current (I12) can be generated in a size as large as 1 / 100000 of the load current (I11).

[0064] At this time, the drain-source voltage (VDS2) (voltage of the second node (N12)) of the second transistor (T12) tracks the drain-source voltage (VDS1) (voltage of the first node (N11)) of the first transistor (T11) by the first operational amplifier (OPA1). Since the first transistor (T11) is designed to have a very small on-resistance (RDSON1) value, the drain-source voltage (VDS1) of the first transistor (T11) has a very small value of several mV to 200 mV. Therefore, if the first resistor (R1) is not present, it is difficult for the first operational amplifier (OPA1) to track the drain-source voltage (VDS1) of the first transistor (T11), but one embodiment of the present invention designs the first operational amplifier (OPA1) to track the drain-source voltage (VDS1) of the first transistor (T11) by connecting the first resistor (R1). At this time, the detection voltage (V1) output from the first operational amplifier (OPA1) is as shown in [Mathematical Formula 1] below.

[0065] [Mathematical Formula 1]

[0066] V1=VHH-(VDS2+I12*R1)

[0067] Here, the drain-source voltage (VDS2) of the second transistor (T12) has a voltage value corresponding to the product of the mirror current (I12) and the on-resistance (RDSON2) of the second transistor (T12). When this is substituted into [Mathematical Formula 1], the detection voltage (V1) is as shown in [Mathematical Formula 2] below.

[0068] [Equation 2]

[0069] V1=VHH-{I12*(RDSON2+R1)}

[0070] =VHH-{I12*RDSON2*(1+R1 / RDSON2)}

[0071] Here, the value of 1+R1 / RDSON corresponds to the amplification (A0) of the first operational amplifier (OPA1). At this time, the value of I12*RDSON2 is the drain-source voltage (VDS2) of the second transistor (T12), and the drain-source voltage (VDS2) of the second transistor (T12) follows the drain-source voltage (VDS1) of the first transistor (T11), so that the detection voltage (V1) is ultimately as shown in [Mathematical Formula 3] below.

[0072] [Equation 3]

[0073] V1=VHH-VDS1*A0

[0074] That is, since the first operational amplifier (OPA1) outputs a detection voltage (V1) having an amplification factor of A0 with respect to the drain-source voltage (VDS1) of the first transistor (T11), even if the drain-source voltage (VDS1) of the first transistor (T11) is a voltage of very small magnitude, it can output a detection voltage (V1) proportional to the drain-source voltage (VDS1) of the first transistor (T11).

[0075] Next, the second operational amplifier (OPA2) outputs a gate voltage (VG) that is adjusted so that the voltage (V1') of the third node (N13) follows the sensing voltage (V1). At this time, the voltage (V1') of the third node (N13) is equal to the sum of the drain-source voltage (VDS3) of the third transistor (T13) and the voltage (I13*R2) applied across the two terminals of the second resistor (R2), as in [Mathematical Formula 4] below.

[0076] [Equation 4]

[0077] V1'=VHH-(VDS3+I13*R2)

[0078] Next, the fourth transistor (T14) outputs the sensing current (I13) according to the gate voltage (VG). That is, the magnitude of the sensing current (I13) is adjusted by the fourth transistor (T14) so ​​that the voltage (V1') of the third node (N13) becomes equal to the sensing voltage (V1). Here, if V1'=V1 is substituted into the above-mentioned [Mathematical Formula 4], a relationship such as the following [Mathematical Formula 5] is derived.

[0079] [Equation 5]

[0080] VDS3+I13*R3=VDS2+I12*R1

[0081] That is, the third transistor (T13) can prevent a current error from occurring due to the difference between the drain-source voltage (VDS1) of the first transistor (T11) and the drain-source voltages (VDS2, VDS3) of the second and third transistors (T12, T13) by canceling out the drain-source voltage (VDS2) of the second transistor (T12).

[0082] And, the sensing current (I13) flowing through the fourth transistor (T14) is determined by the potential difference between the voltage (V1') of the third node (N13) and the drain-source voltage (VDS3) of the third transistor (TR13), as in [Mathematical Formula 6] below.

[0083] [Equation 6]

[0084] I13=(V1'-VDS3) / R2

[0085] At this time, when the W / L values ​​of the second transistor (TR12) and the third transistor (TR13) are the same and the resistance values ​​of the first resistor (R1) and the second resistor (R2) are the same, the detection current (I13) is the same as the mirror current (I12).

[0086] In contrast, when the W / L value of the third transistor (TR13) is formed to be twice the W / L value of the second transistor (TR12), that is, the on-resistance (RDSON3) value of the third transistor (TR13) is formed to be half the on-resistance (RDSON2) of the second transistor (TR12), and the resistance value of the second resistor (R2) is formed to be half the first resistor (R1), the sensing current (I13) is output as twice the mirror current (I12).

[0087] That is, the amplification (A1) of the sense current (I13) with respect to the mirror current (I12) can be determined according to the W / L value of the second transistor (TR12), the W / L value of the third transistor (TR13), and the resistance values ​​of the first resistor (R1) and the second resistor (R2). That is, the amplification (A1) is defined as I13 / I12, and the conversion ratio of the sense current (I13) with respect to the mirror current (I12) can be determined according to the amplification (A1).

[0088] When the detection current (I13) flows from one end to the other end of the detection resistor (RA), the third operational amplifier (OPA3) amplifies the voltage across both ends of the detection resistor (RA) and outputs the detection voltage (VA). The detection voltage (VA) is as shown in [Mathematical Formula 7] below.

[0089] [Equation 7]

[0090] VA=A2*I13*RA

[0091] Here, A2 is the amplification factor of the third operational amplifier (OPA3).

[0092] That is, one embodiment of the present invention causes the drain-source voltage (VDS2) of the second transistor (T12) to follow the drain-source voltage (VDS1) of the first transistor (T11) so that the mirror current (I12) has a value that is precisely proportional to the load current (I11), and generates a detection voltage (V1) that is proportional to the mirror current (I12). Then, the detection voltage (V1) is converted into a current to generate a detection current (I13) that is proportional to the mirror current (I12), and then the magnitude of the detection current (I13) is detected and output as a detection voltage (VA), thereby enabling the load current (I11) to be accurately detected.

[0093] Fig. 6 is a circuit diagram illustrating another embodiment of the current detection unit illustrated in Fig. 4.

[0094] Referring to FIG. 6, a current detection unit (148') according to another embodiment of the present invention may include a detection resistor (RA'), first to fourth operational amplifiers (OPA11 to OPA14), first to seventh resistors (R11 to R17), and a variable resistor (RV). One end of the detection resistor (RA') includes one end connected to the drain terminal of the fourth transistor (T14 of FIG. 2) and the other end connected to the lower power supply voltage (VSS) application terminal.

[0095] The first operational amplifier (OPA11) includes a non-inverting input terminal (+) connected to one end of the detection resistor (RA'), an inverting input terminal (-) connected to the other end of the first resistor (R11), and an output terminal. The second operational amplifier (OPA12) includes a non-inverting input terminal (+) connected to the other end of the detection resistor (RA'), an inverting input terminal (-) connected to one end of the third resistor (R13), and an output terminal.

[0096] The third operational amplifier (OPA13) includes a non-inverting input terminal (+) connected to the other end of the sixth resistor (R16), an inverting input terminal (-) connected to one end of the fifth resistor (R15), and an output terminal. The fourth operational amplifier (OPA14) includes a non-inverting input terminal (+) connected to the output terminal of the third operational amplifier (OPA13), an inverting input terminal (-) connected to a variable resistor (RA), and an output terminal for outputting a detection voltage (VA).

[0097] The first resistor (R11) includes one end connected to the output terminal of the first operational amplifier (OPA11) and the other end connected to the inverting input terminal (-) of the first operational amplifier (OPA11). The second resistor (R12) includes one end connected to the other end of the first resistor (R11) and the other end connected to the inverting input terminal (-) of the second operational amplifier (OPA12).

[0098] The third resistor (R13) includes one end connected to the other end of the second resistor (R12) and the other end connected to the output terminal of the second operational amplifier (OPA12). The fourth resistor (R14) includes one end connected to the other end of the third resistor (R13) and the other end connected to one end of the fifth resistor (R15).

[0099] The other end of the fifth resistor (R15) is connected to the lower power supply voltage (VSS), the sixth resistor (R8) has one end connected to the output terminal of the first operational amplifier (OPA11) and the other end connected to one end of the seventh resistor (R17). The other end of the seventh resistor (R17) is connected to the output terminal of the third operational amplifier (OPA13). The variable resistor (RV) has one end connected to the output terminal of the fourth operational amplifier (OPA14) and the other end connected to the lower power supply voltage (VSS) application terminal.

[0100] The current detection unit (148') having the above configuration amplifies the voltage at both ends of the detection resistor (RA') through the first to third operational amplifiers (OPA11 to OPA13) and inputs it to the non-inverting terminal (+) of the fourth operational amplifier (OPA14), and controls the amplification of the fourth operational amplifier (OPA14) by adjusting the voltage fed back to the inverting terminal (-) of the fourth operational amplifier (OPA14) through the variable resistor (RV).

[0101] At this time, the resistance value of the variable resistor (RV) can be controlled through an external resistance controller (not shown), and can be controlled according to the output scale of the detection voltage (VA) for the preset detection current (I13). In this way, the precision of the load current detection unit (140) can be increased by adjusting the amplification of the fourth operational amplifier (OPA14) to change the size of the detection voltage (VA).

[0102] FIG. 7 is a detailed circuit diagram illustrating a power control system according to another embodiment of the present invention.

[0103] Referring to FIG. 7, a power control system (100') according to another embodiment of the present invention may include a switching unit (110), a load (120), a gate driving unit (130), and a load current detection unit (140'). Here, the switching unit (110), the load (120), and the gate driving unit (130) have the same configuration as those of FIG. 2 and are thus illustrated with the same drawing numbers, and a detailed description thereof is omitted for convenience of explanation.

[0104] The load current detection unit (140') detects the load current (I11) flowing in the load (120) through the first transistor (T11) and outputs first and second detection voltages (VA, VB). The load current detection unit (140') may include a current mirroring unit (142), a current-to-voltage conversion unit (144), a voltage-to-current conversion unit (146, 146'), and a current detection unit (148, 148'). Here, the current mirroring unit (142) and the current-to-voltage conversion unit (144) have the same configuration as those of Fig. 2 and are illustrated with the same reference numerals, and a detailed description thereof is omitted for convenience of explanation.

[0105] That is, the load current detection unit (140') according to another embodiment of the present invention is configured with two voltage-current conversion units, and correspondingly, two current detection units are configured. For convenience of explanation, the current-voltage conversion unit (146) is referred to as a first current-voltage conversion unit, and the current-voltage conversion unit (146') is referred to as a second current-voltage conversion unit. Similarly, the current detection unit (148) is referred to as a first current detection unit, and the current detection unit (148') is referred to as a second current detection unit. Here, the first current-voltage conversion unit (146) and the first current detection unit (148) have the same configuration as those of FIG. 2, and thus are illustrated with the same reference numerals, and a detailed description thereof is omitted.

[0106] The second voltage-current converter (146') includes a fifth transistor (T15), a third resistor (R3), a third operational amplifier (OPA3), and a sixth transistor (T16). The fifth transistor (T15) forms a current mirror with the first transistor (T11), and mirrors the load current (I11) flowing to the load (120) through the first transistor (T11) to output a second detection current (I14).

[0107] The third resistor (R3) has one end connected to the source terminal of the fifth transistor (T15) and the other end connected to the fourth node (N14). The third operational amplifier (OPA3) has a non-inverting input terminal (+) that receives the sense voltage (V1), an inverting input terminal (-) that receives the voltage (V1") of the fourth node (N14), and an output terminal.

[0108] The sixth transistor (T16) controls and outputs the size of the second detection current (I14) according to the output of the fourth operational amplifier (OPA4). Here, the sixth transistor (T16) may be formed as a PMOS transistor and includes a source terminal connected to the fourth node (N14), a gate terminal connected to the output terminal of the fourth operational amplifier (OPA4), and a drain terminal connected to one end of the second detection resistor (RB).

[0109] The current detection unit (148') may include a second detection resistor (RB) and a fifth operational amplifier (OPA5). The second detection resistor (RB) includes one end connected to the drain terminal of the sixth transistor (T16) and the other end connected to the lower power supply voltage (VSS) application terminal.

[0110] The fifth operational amplifier (OPA5) includes a non-inverting input terminal (+) connected to one end of the second detection resistor (RB), an inverting input terminal (-) connected to the other end of the second detection resistor (RB), and an output terminal for outputting a second detection voltage (VB).

[0111] A power control system (100') according to another embodiment of the present invention having the above-described configuration may be configured with a plurality of voltage-current conversion units (146, 146') and corresponding current detection units (148, 148') to set amplification for the mirror current (I12) differently. That is, the first voltage-current conversion unit (146) may be set to output a first detection current (I13) proportional to the second mirror current (I12) by the first amplification (A1), and the second voltage-current conversion unit (146') may be set to output a second detection current (I14) proportional to the second mirror current (I12) by the second amplification (A1').

[0112] In this case, the first amplification (A1) can be set to be suitable for small current detection, and the second amplification (A1') can be set to be suitable for large current detection. In the case of small current detection, the load current (I11) can be detected when the first transistor (T11) is conducting a load current (I11) within the normal operating range, and in the case of large current detection, the load current (I11) can be detected when the load current (I11) flows as an overcurrent to the first transistor (T11). For example, in the case of large current detection, a current pulse of several tens of milliseconds (msec) set to 1.5 times the maximum normal load current or an instantaneous current pulse set to 4 times the maximum normal load current can be detected.

[0113] Specifically, when the maximum allowable current of the load (120) is 20A, the amplification for the first detection current (I13) can be set so that the first detection voltage (VA) is output as 5V corresponding to the maximum value of the lower power supply voltage (VSS) when 20A flows through the load (120), and the amplification for the second detection current (I14) can be set so that the second detection voltage (VB) is output as 5V when an overcurrent of 80A, which is four times the maximum allowable current, flows through the load (120).

[0114] If only the first detection voltage (VA) is detected, the overcurrent flowing in the load (120) cannot be detected, and if the normal operating current is measured only with the second detection voltage (VB), the second detection voltage (VB) may be output as 1.25 V even if the maximum normal operating current flows, which may lower the measurement accuracy. Therefore, another embodiment of the present invention can adjust the detection range and accuracy of the load current (I11) by setting the amplification of the first and second voltage-current converters (146, 146') differently.

[0115] Although the embodiments have been described in detail above, the scope of the embodiments is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concepts of the embodiments defined in the claims below also fall within the scope of the embodiments.

[0116] Accordingly, the detailed description described above should not be construed as limiting in any respect, but rather as illustrative. The scope of the embodiments should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the embodiments are intended to be included within the scope of the embodiments.

Claims

1. A first transistor connected between an upper power supply voltage supply terminal and a load to supply a driving voltage to the load according to a switching control signal, and a second transistor forming a current mirror, and generating a mirror current by mirroring the load current flowing to the load through the first transistor; A current-to-voltage converter that converts the mirror current to voltage so that the drain-source voltage of the second transistor follows the drain-source voltage of the first transistor to generate a detection voltage; and A voltage-current converter that converts the above detection voltage into current to generate a detection current. A load current detection device including a .

2. In the first paragraph, the current-voltage conversion unit An operational amplifier including a non-inverting input terminal for receiving the drain-source voltage of the first transistor, an inverting input terminal for receiving the drain-source voltage of the second transistor, and an output terminal for outputting the sensing voltage; and A resistor connected between the second transistor and the output terminal A load current detection device including:

3. In the first paragraph, the voltage-current conversion unit A load current detection device that generates a voltage that follows the detection voltage, converts the voltage that follows the detection voltage into a current, and outputs the detection current.

4. In the third paragraph, the voltage-current conversion unit A third transistor connected between the upper power voltage supply terminal and the resistor and including a gate terminal connected to the gate terminal of the first transistor; A resistor connected between the third transistor and the first node; An operational amplifier that adjusts the voltage of the first node to follow the detection voltage; and A fourth transistor that adjusts and outputs the size of the detection current according to the output of the above operational amplifier. A load current detection device including:

5. In the first paragraph, the voltage-current conversion unit A first voltage-current converter that follows the detection voltage and generates a first detection current having a first amplification factor compared to the mirror current; and A second voltage-current converter that follows the detection voltage and generates a second detection current having a second amplification factor compared to the mirror current. A load current detection device including:

6. In paragraph 1, A load current detection device further comprising a current detection unit that converts the above detection current into voltage and outputs a detection voltage.

7. In the 6th paragraph, the current detection unit A load current detection device that amplifies a voltage proportional to the above-detected current and outputs it as the above-detected voltage.

8. In the 7th paragraph, the current detection unit A detection resistor through which the detection current flows at both ends; and A load current detection device comprising an operational amplifier including a non-inverting input terminal connected to one end of the detection resistor, an inverting input terminal connected to the other end of the detection resistor, and an output terminal for outputting the detection voltage.

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