Power semiconductor element and power semiconductor device

Abstract

This power semiconductor element may comprise: a substrate; a drain electrode on the lower side of the substrate; a drift layer on the upper side of the substrate; a source region in the drift layer; a body region surrounding at least the side portion of the source region; a structure disposed between the source region and the body region and having the same conductive type as the conductive type of the body region; a gate insulating layer on the upper surface of the drift layer; a gate electrode surrounded by the gate insulating layer; and a source electrode on the gate electrode. The body region and the structure may have a second conductive type. The structure may be spaced apart from the gate insulating layer in the vertical direction and may be spaced apart from the drift layer in the horizontal direction.

Description

Power semiconductor devices and power semiconductor devices

[0001] The embodiments relate to power semiconductor devices and power semiconductor devices.

[0002] Unlike system semiconductors or memory that process and store information or signals, power semiconductors are core components that convert, store, distribute, and control the power entering electronic devices, and are widely used in most electronic products.

[0003] In line with the recent global trend toward strengthening environmental protection, electric and hydrogen-powered eco-friendly vehicles are gaining widespread attention as alternatives to conventional fossil fuel-powered vehicles. These eco-friendly vehicles utilize numerous power semiconductor components. These eco-friendly vehicles include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), electric vehicles (EVs), and fuel cell electric vehicles (PCEVs).

[0004] Although Si power semiconductor devices have been widely used in the past, there is a strong demand for the development of new power semiconductor devices due to their low power, low dielectric breakdown characteristics, and low thermal conductivity.

[0005] Accordingly, active research is being conducted on power semiconductor devices based on semiconductor compounds with energy bandgaps approximately three times greater than conventional Si power semiconductor devices. These power semiconductor devices based on these compounds exhibit high power, high dielectric breakdown characteristics, and high thermal conductivity.

[0006] Meanwhile, power semiconductor devices based on semiconductor compounds have relatively poor channel mobility compared to Si power semiconductor devices. To solve this problem, active research is being conducted to improve the sum of resistance values ​​formed in various regions and / or layers, i.e. Ron, in power semiconductor devices based on semiconductor compounds. Among Ron, the resistance value of the body region, i.e. R CH It is very important to optimize .

[0007] R CH As a measure to reduce the channel length, attempts are being made to reduce the channel length. However, when the channel length is reduced, there is a problem that the short channel effect occurs. That is, there is a problem that the threshold voltage is reduced due to drain-induced barrier lowering (DIBL). In addition, there is a problem that the drain-source leakage current increases due to punch through.

[0008] The present invention aims to solve the above-mentioned and other problems.

[0009] Another object of the present invention is to provide a power semiconductor device and a power semiconductor device capable of improving Ron.

[0010] Another object of the present invention is to provide a power semiconductor element and a power semiconductor device that can prevent a decrease in threshold voltage value and reduce size.

[0011] Another object of the present invention is to provide a power semiconductor device and a power semiconductor device capable of reducing power consumption.

[0012] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0013] According to a first aspect of the embodiment to achieve the above or other objects, a power semiconductor device comprises: a substrate; a drain electrode on a lower side of the substrate; a drift layer on an upper side of the substrate; a source region in the drift layer; a body region surrounding at least a side of the source region; a structure disposed between the source region and the body region; a gate insulating layer on an upper surface of the drift layer; a gate electrode surrounded by the gate insulating layer; and a source electrode on the gate electrode; wherein the body region and the structure have a second conductivity type, and the structure is spaced apart from the gate insulating layer in a vertical direction and spaced apart from the drift layer in a horizontal direction.

[0014] The body region may include a first body region and a second body region, the source region may include a first source region and a second source region, the structure may include a first structure and a second structure, and the drift layer may include an extended drift layer between the first body region and the second body region.

[0015] The first structure may be disposed on a side of the first source region and spaced apart from the extended drift layer in the horizontal direction, and the second structure may be disposed on a side of the second source region facing the side of the first source region and spaced apart from the extended drift layer in the horizontal direction.

[0016] The first structure may be spaced apart from the gate insulating layer on a side of the first source region, and the second structure may be spaced apart from the gate insulating layer on a side of the second source region.

[0017] The first body region may form a first channel region in a space between the first structure and the gate insulating layer, and the second body region may form a second channel region in a space between the second structure and the gate insulating layer.

[0018] The first structure may extend laterally from the lower side of the first source region and be spaced apart from the extended drift layer in the horizontal direction, and the second structure may extend laterally from the lower side of the second source region and be spaced apart from the extended drift layer in the horizontal direction.

[0019] The first structure may be spaced apart from the gate insulating layer on a side of the first source region, and the second structure may be spaced apart from the gate insulating layer on a side of the second source region.

[0020] The first body region may form a first channel region in a space between the first structure and the gate insulating layer, and the second body region may form a second channel region in a space between the second structure and the gate insulating layer.

[0021] The above structure can be arranged lengthwise along the length direction of the gate electrode.

[0022] According to a second aspect of the embodiment to achieve the above or other objects, a power semiconductor device comprises: a plurality of power semiconductor modules; each of the plurality of power semiconductor modules comprises a plurality of power semiconductor elements, each of the plurality of power semiconductor elements comprising: a substrate; a drain electrode on a lower side of the substrate; a drift layer on an upper side of the substrate; a source region in the drift layer; a body region surrounding at least a side of the source region; a structure disposed between the source region and the body region; a gate insulating layer on an upper surface of the drift layer; a gate electrode surrounded by the gate insulating layer; and a source electrode on the gate electrode; wherein the body region and the structure have a second conductivity type, and the structure is spaced apart from the gate insulating layer in a vertical direction and spaced apart from the drift layer in a horizontal direction.

[0023] The effects of the power semiconductor element and power semiconductor device according to the embodiment are described as follows.

[0024] As shown in FIGS. 4 and 5, structures (231, 232) can be placed on the side of the source region (216, 217) in the body region (214, 215).

[0025] As illustrated in FIG. 6, the structures (231, 232) can extend laterally from the lower side of the source region (216, 217) in the body region (214, 215).

[0026] As illustrated in FIG. 7, the structures (231, 232) may include two or more structures (231-1 to 231-3, 232-1 to 232-3) on the lower side of the source region (216, 217) in the body region (214, 215).

[0027] The short channel effect can be suppressed by the above-described structure. Specifically, to improve Ron, the channel length (L CH) can be reduced, thereby reducing the size of each of the plurality of semiconductor devices included in the active region (206), thereby miniaturizing the power semiconductor device. In addition, the channel length (L CH ) is reduced, the threshold voltage (Vth) does not decrease, making it possible to implement high-power semiconductor devices. In addition, the channel length (L CH ) can reduce power consumption by suppressing the leakage current between drain and source.

[0028] Further scope of applicability of the embodiments will become apparent from the detailed description below. However, since various changes and modifications within the spirit and scope of the embodiments will be readily apparent to those skilled in the art, it should be understood that the detailed description and specific embodiments, such as preferred embodiments, are given by way of example only.

[0029] Fig. 1 is a circuit diagram illustrating an inverter for automobiles according to an embodiment.

[0030] Fig. 2 is a plan view illustrating a power semiconductor device according to an embodiment.

[0031] Figure 3 is an enlarged plan view showing area A of Figure 2.

[0032] FIG. 4 is a cross-sectional view of a power semiconductor device according to the first embodiment, taken along the C-C' line in area A shown in FIG. 3.

[0033] Figure 5 shows the arrangement relationship between the structure and the channel area of ​​the body area.

[0034] FIG. 6 is a cross-sectional view of a power semiconductor device according to the second embodiment, taken along the C-C' line in area A shown in FIG. 3.

[0035] FIG. 7 is a cross-sectional view of a power semiconductor device according to the third embodiment, taken along the C-C' line in area A shown in FIG. 3.

[0036] Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or similar components will be given the same reference numbers and redundant descriptions thereof will be omitted. The suffixes 'module' and 'part' used for components in the following description are given or used interchangeably in consideration of the ease of writing the specification, and do not have distinct meanings or roles in themselves. In addition, the attached drawings are intended to make it easier to understand the embodiments disclosed in the present specification, and the technical ideas disclosed in the present specification are not limited by the attached drawings. In addition, when an element such as a layer, region, or substrate is referred to as existing 'on' another element, this includes that it may be directly on the other element or that other intermediate elements may exist therebetween.

[0037] In an embodiment, the power semiconductor device is used in an inverter or converter, such as a computer, home appliance, automobile, solar power, or smart grid. In an embodiment, the power semiconductor device may include a single power semiconductor module or multiple power semiconductor modules. Furthermore, the power semiconductor module may include multiple power semiconductor elements.

[0038] The following example (Fig. 1) describes an automotive inverter for driving a motor as a power semiconductor device. However, the power semiconductor device of the example can be applied to inverters, converters, etc. in various technical fields described above. Here, the automobile refers to an environmentally friendly vehicle, and includes a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an electric vehicle (EV), a fuel cell electric vehicle (PCEV), etc.

[0039] In the following examples, the internal pressure and the breakdown voltage may be mixed.

[0040] In the following embodiment (Fig. 1), the switching element and the power semiconductor device may be mixed. In the following embodiment (Fig. 1), the leg and the power semiconductor module may be mixed.

[0041] Fig. 1 is a circuit diagram illustrating an inverter for an automobile according to the first embodiment.

[0042] Referring to FIG. 1, an automotive inverter (1000) according to a first embodiment can convert DC power into AC power and supply the converted AC power to a load (1200) to drive the load. In the automotive inverter (1000) according to the first embodiment, a battery is connected to an input terminal, so that DC power of the battery can be converted into AC power. Although not shown, a converter can be connected to the input terminal of the battery, and the input terminal of the converter can be connected to a charger of a charging station. In this case, AC power supplied through the charger by the converter is converted into DC power, and the converted DC power can be charged to the battery to charge the battery. In addition, the DC power charged to the battery can be converted into AC power by the automotive inverter (1000) according to the first embodiment, so that it can be used to drive the load.

[0043] The circuit configuration of the converter may be similar or identical to the circuit configuration of the inverter.

[0044] The load (1200) may be a motor, but is not limited thereto.

[0045] The automotive inverter (1000) according to the first embodiment may include a three-phase inverter, but is not limited thereto. In this case, a phase difference of 120 degrees may be present between the first phase, the second phase, and the third phase. The automotive inverter (1000) according to the first embodiment may include a plurality of legs (100A, 100B, 100C). For example, the first leg (100A), the second leg (100B), and the third leg (100C) may be connected in parallel to a load (1200), i.e., a motor, through a first node (N1), a second node (N2), and a third node (N3), respectively. The first leg (100A) may include a first arm (100a) and a second arm (100b) that are connected in series to each other, the second leg (100B) may include a third arm (100c) and a fourth arm (100d) that are connected in series to each other, and the third leg (100C) may include a fifth arm (100e) and a sixth arm (100f) that are connected in series to each other. Here, the first arm (100a), the third arm (100c), and the fifth arm (100e) may be referred to as upper arms, and the second arm (100b), the fourth arm (100d), and the sixth arm (100f) may be referred to as lower arms. Each of the first arm (100a) to the sixth arm (100f) may be referred to as a switching module, a submodule, or the like.

[0046] The first arm (100a) to the sixth arm (100f) may each include a switching element (100a-1, 100b-1, 100c-1, 100d-1, 100e-1, 100f-1) and a diode (100a-2, 100b-2, 100c-2, 100d-2, 100e-2, 100f-2). The switching elements (100a-1, 100b-1, 100c-1, 100d-1, 100e-1, 100f-1) and the diodes (100a-2, 100b-2, 100c-2, 100d-2, 100e-2, 100f-2) may be formed simultaneously using the same semiconductor process. The switching elements (100a-1, 100b-1, 100c-1, 100d-1, 100e-1, 100f-1) may include power semiconductor elements.

[0047] In order for DC power to be converted into AC power by the inverter according to the first embodiment, the switching elements (100a-1, 100b-1, 100c-1, 100d-1, 100e-1, 100f-1) of each of the first arm (100a) to the sixth arm (100f) can be turned on / off.

[0048] For example, when the first switching element (100a-1) of the first arm (100a) of the first leg (100A) is in the ON state, the fourth switching element (100d-1) of the fourth arm (100d) of the second leg (100B) and / or the sixth switching element (100f-1) of the sixth arm (100f) of the third leg (100C) may be in the ON state. Accordingly, DC power may be supplied to the first phase inductor of the motor.

[0049] For example, when the second switching element (100b-1) of the second arm (100b) of the second leg (100B) is in the ON state, the sixth switching element (100f-1) of the sixth arm (100f) of the third leg (100C) and / or the second switching element (100b-1) of the second arm (100b) of the first leg (100A) may be in the ON state. Accordingly, DC power may be supplied to the second phase inductor of the motor. The second phase may be 120 degrees behind the first phase.

[0050] For example, when the third switching element (100c-1) of the third arm (100c) of the third leg (100C) is turned on, the second switching element (100b-1) of the second arm (100b) of the first leg (100A) and / or the fourth switching element (100d-1) of the fourth arm (100d) of the second leg (100B) may be turned on. Accordingly, DC power may be supplied to the third phase inductor of the motor. The third phase may be 120 degrees behind the second phase.

[0051] Accordingly, AC power can be generated by the DC power supplied to each of the first phase inductor, the second phase inductor, and the third inductor.

[0052] Meanwhile, although not shown, in order to increase the internal pressure characteristics, the switching elements of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements (100a-1, 100b-1, 100c-1, 100d-1, 100e-1, 100f-1) may be provided in multiple numbers, each connected in series with each other.

[0053] Although not shown, in order to increase the current characteristics, the switching elements of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements (100a-1, 100b-1, 100c-1, 100d-1, 100e-1, 100f-1) may be provided in multiple numbers connected in parallel with each other.

[0054] Meanwhile, the switching elements (100a-1, 100b-1, 100c-1, 100d-1, 100e-1, 100f-1) and diodes (100a-2, 100b-2, 100c-2, 100d-2, 100e-2, 100f-2) constituting the first arm (100a) to the sixth arm (100f) can be packaged to form a power semiconductor module.

[0055] As an example, the first leg (100A), the second leg (100B), and the third leg (100C) can each be configured as power semiconductor modules. That is, the first arm (100a) and the second arm (100b) of the first leg (100A) can be packaged to configure a first power semiconductor module. The third arm (100c) and the fourth arm (100d) of the second leg (100B) can be packaged to configure a second power semiconductor module. The fifth arm (100e) and the sixth arm (100f) of the third leg (100C) can be packaged to configure a third power semiconductor module.

[0056] As another example, the first leg (100A), the second leg (100B), and the third leg (100C) can be configured as a single power semiconductor module. That is, the first arm (100a) and the second arm (100b) of the first leg (100A), the third arm (100c) and the fourth arm (100d) of the second leg (100B), and the fifth arm (100e) and the sixth arm (100f) of the third leg (100C) can be packaged to configure a single power semiconductor module.

[0057] Power semiconductor devices are described below with reference to FIGS. 2 through 7. In the following description, components containing the same dose and formed on the same layer may be formed simultaneously through the same ion implantation process using the same mask. Alternatively, components containing the same dose and formed on the same layer may be formed at different times using different masks.

[0058] The ion implantation process physically implants ions or impurities created using a source gas into a substrate (212). Ions can be collectively referred to as impurities. This ion implantation process can increase the conductivity of an insulating material or change it to quasi-conductivity, thereby forming various regions with different or identical doses.

[0059] Hereinafter, a substrate, a drift layer (213), a body, a contact region (218, 219), a source region (216, 217), a blocking region, a separation region, or two or more sub-regions included in the region may be formed through the ion implantation process described above. Different energies may be used for the various regions into which ions are implanted depending on the dose or location. For example, low energy may be used to implement a shallow junction, and high energy may be used to implement a deep junction, but this is not limited thereto.

[0060] In the following description, dose and dose amount have the same meaning and can be used interchangeably.

[0061] Fig. 2 is a plan view illustrating a power semiconductor device according to an embodiment.

[0062] Referring to FIG. 2, the power semiconductor device according to the embodiment can be divided into an active area (206) and a termination area (207).

[0063] The active region (206) may include a plurality of active cells. Each of the active cells may include a semiconductor device having a gate electrode (221), a source electrode (223), and a drain electrode (211) disposed thereon and capable of performing a predetermined operation. Accordingly, a plurality of semiconductor devices may be configured by the plurality of active cells. The semiconductor device may include a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but is not limited thereto.

[0064] Since multiple active cells are defined in a matrix form, multiple semiconductor devices can also be arranged in a matrix form.

[0065] The termination region (207) may surround the active region (206). The termination region (207) may be positioned along the edge of the active region (206). The termination region (207) may serve to disperse the electric field and secure a high breakdown voltage.

[0066] Although the power semiconductor device according to the embodiment is depicted in the drawing as having a rectangular shape when viewed from above, it may have a different shape.

[0067] A gate pad (201) and a source pad (202) may be positioned in the active region (206). The gate pad (201) is connected to the gate electrode (221) of each of a plurality of active cells through a gate line (208), so that a gate signal can be supplied to the gate electrode (221). The source pad (202) is connected to the source electrode (223) of the active cells, so that a source voltage can be supplied to the source electrode (223). Although not shown, a drain pad may be positioned on the lower side of the power semiconductor device according to the embodiment. The drain pad is connected to the drain electrode (211) of the active cells, so that a drain voltage can be supplied to the drain electrode (211).

[0068] Meanwhile, the gate pad (201) and / or the source pad (202) can have their positions changeable on the plane of the active area (206).

[0069] The gate electrode (221) may be called a gate, a gate poly, a gate contact, etc. The source electrode (223) may be called a source contact, and the gate electrode (221) may be called a gate contact. Although not shown, the source pad (202) may not be distinguished from the source electrode (223) and may be collectively referred to as the source electrode (223), and the drain pad may not be distinguished from the drain electrode (211) and may be collectively referred to as the drain electrode (211).

[0070] The power semiconductor device according to the embodiment may include a plurality of semiconductor devices included in the active region (206). In the following description, for convenience of explanation, reference is made to drawings (FIGS. 4 to 7) illustrating at least one or two power semiconductor devices included in the active region (206), but the power semiconductor device according to the embodiment may include a plurality of semiconductor devices included in the active region (206).

[0071] The power semiconductor device described below may be a planar type power semiconductor device, but is not limited thereto.

[0072] [Example 1]

[0073] Figure 3 is an enlarged plan view showing area A of Figure 2.

[0074] As illustrated in FIG. 3, six semiconductor elements are illustrated in region A, and as described above, the power semiconductor element according to the first embodiment may include a plurality of semiconductor elements included in the active region (206).

[0075] Meanwhile, one active cell may include one semiconductor device, but this is not a limitation. For example, one active cell may include two or more semiconductor devices.

[0076] Referring to FIGS. 4 and 5, the power semiconductor device according to the first embodiment may include a drain electrode (211), a substrate (212), a drift layer (213), a body region (214, 215), a source region (216, 217), a structure (231, 232), a contact region (218, 219), a gate electrode (221), a gate insulating layer (222), and a source electrode (223). The contact region (218, 219) may be omitted. The power semiconductor device according to the first embodiment may include more components than this. A semiconductor device can be configured by a drain electrode (211), a substrate (212), a drift layer (213), a body region (214, 215), a source region (216, 217), a contact region (218, 219), a gate electrode (221), a gate insulating layer (222), and a source electrode (223). A plurality of semiconductor devices configured in this manner can be included in an active region (206).

[0077] The drain electrode (211) may be disposed under the substrate (212). The drain electrode (211) may supply a drain voltage to the substrate (212). The drain electrode (211) may be a drain pad, or a drain pad may be disposed separately under the drain electrode (211). The drain electrode (211) may be formed of Ni or another suitable material that forms an ohmic contact with n-type silicon carbide.

[0078] The substrate (212) and / or the drift layer (213) may include a semiconductor compound such as SiC, GaN, Ga2O3, etc. For example, the substrate (212) and / or the drift layer (213) may include, but is not limited to, a 4H-SiC material. For example, the substrate (212) and / or the drift layer (213) may include 3C-SiC or 6H-SiC.

[0079] The drift layer (213) may be disposed on the substrate (212). The drift layer (213) may be the substrate (212) or an epitaxial layer. At least one of the substrate (212) and the drift layer (213) may constitute a drain region, but this is not limited thereto.

[0080] The drift layer (213) may include at least one drift region, but is not limited thereto. The drift layer (213) may be referred to as a drift region.

[0081] For example, the substrate (212) and the drift layer (213) may have a first conductivity type. The first conductivity type may be n-type, but is not limited thereto. For this purpose, the substrate (212) and the drift layer (213) may include an n-type dopant.

[0082] Meanwhile, the drift layer (213) may include an extended drift layer (213a). The extended drift layer (213a) may extend toward the gate electrode (221).

[0083] The body regions (214, 215) may be formed spaced apart from each other within the drift layer (213). The body regions (214, 215) may have a second conductivity type. The body regions (214, 215) may include, for example, a P-type dopant. When the body regions (214, 215) include a P-type dopant, the body regions (214, 215) may be referred to as a P-well. The body regions (214, 215) may be referred to as a base region.

[0084] For example, the body regions (214, 215) may include a first body region (214) and a second body region (215) that are horizontally spaced apart from each other. The first body region (214) and the second body region (215) may be arranged to face each other horizontally. An extended drift layer (213a) may be arranged between the first body region (214) and the second body region (215). The first body region (214) may be arranged on a first side of the extended drift layer (213a), and the second body region (215) may be arranged on a second side of the extended drift layer (213a). The side surface of the first body region (214) and the first side surface of the extended drift layer (213a) may be in contact, but this is not limited thereto. The side of the second body region (215) and the second side of the extended drift layer (213a) may be in contact, but this is not limited thereto.

[0085] A contact region (218, 219) and a source region (216, 217) may be arranged within the body region (214, 215). The contact region (218, 219) may have a second conductivity type with the body region (214, 215). The source region (216, 217) may have a drift region and a first conductivity type. The source region (216, 217) and the contact region (218, 219) may be arranged adjacent to each other. The dose (P+) of the contact region (218, 219) may be greater than the dose (P-) of the body region (214, 215).

[0086] The body region (214, 215) may surround one side of the source region (216, 217). For example, the body region (214, 215) may surround the lower and side portions of the source region (216, 217).

[0087] For example, the source regions (216, 217) may include a first source region (216) and a second source region (217) that are horizontally spaced from each other. The first body region (214) and the second body region (215) may be arranged to face each other horizontally.

[0088] The first source region (216) may be disposed in the first body region (214), and the second source region (217) may be disposed in the second body region (215). The first source region (216) may be disposed on the first side of the extended drift layer (213a), and the second source region (217) may be disposed on the second side of the extended drift layer (213a).

[0089] As illustrated in FIG. 3, the source regions (216, 217) may have a stripe shape that is arranged long along one direction (Y-axis direction). In contrast, the contact regions (218, 219) may penetrate the source regions (216, 217) and contact the body regions (214, 215). The contact regions (218, 219) may be formed for each active cell, but are not limited thereto.

[0090] The body regions (214, 215) may include a channel region (214a, 215a in FIG. 5). That is, a portion of the body regions (214, 215) may be formed as the channel regions (214a, 215a). The channel regions (214a, 214b) may have a physical structure that is a functional structure. The channel regions (214a, 214b) may be electrical passages between the source regions (216, 217) and the drain region. The channel regions (214a, 214b) may be electrically conductive or blocked depending on the level of the voltage applied to the gate electrode (221). The drain region may be formed by at least one of the substrate (212) and the drift layer (213).

[0091] The channel regions (214a, 214b) may be formed in contact with the gate insulating layer (222) in the body regions (214, 215), but are not limited thereto. For example, the first channel region (214a) may be formed in a predetermined region adjacent to the gate insulating layer (222) in the first body region (214) located on the side of the first source region (216). The side of the first source region (216) may be spaced apart from the extended drift layer (213a) with the first body region (214) interposed therebetween. For example, the second channel region (215a) may be formed in a predetermined region adjacent to the gate insulating layer (222) in the second body region (215) located on the side of the second source region (217). The side of the second source region (217) can be spaced apart from the extended drift layer (213a) with the second body region (215) interposed therebetween.

[0092] For example, the first channel region (214a) and the second channel region (215a) may be formed at a predetermined depth (or thickness (d31 in FIG. 5)) from the surface of the first body region (214) and the second body region (215), respectively, adjacent to the gate insulating layer (222). The thickness (d31) of each of the first channel region (214a) and the second channel region (215a) may be determined by the concentration of the dopant of the first body region (214) and the second body region (215), the voltage of the gate electrode, etc. For example, the thickness (d31) of each of the first channel region (214a) and the second channel region (215a) may be smaller than the thickness of the first source region (216) and the second source region (217). For example, the thickness (d31) of each of the first channel region (214a) and the second channel region (215a) may be the same as the thickness of each of the first source region (216) and the second source region (217). The thickness (d31) of each of the first channel region (214a) and the second channel region (215a) may be greater than the thickness of each of the first source region (216) and the second source region (217).

[0093] Here, the first channel region (214a) and the second channel region (215a) may be regions that perform electrical conduction or blocking between the first source region (216) and the drain region and between the second source region (217) and the drain region, respectively.

[0094] For example, when a voltage is applied to the gate electrode (221), i.e., when a high-level voltage is applied, source carriers, e.g., electrons, of each of the first body region (214) and the second body region (215) may move toward the gate electrode (221) and gather in an adjacent region in contact with the gate insulating layer (222), thereby forming a first channel region (214a) and a second channel region (215a). The electrons included in each of the first channel region (214a) and the second channel region (215a) may electrically conduct between the first source region (216) and the drain region, and between the second source region (217) and the drain region. Accordingly, a first current can flow through a first channel region (214a) between a first source region (216) and a drain region, and a second current can flow through a second channel region (215a) between a second source region (217) and a drain region. The first current and the second current may be the same, but this is not limited thereto.

[0095] For example, when no voltage or a low-level voltage is applied to the gate electrode (221), electrons included in the first channel region (214a) and the second channel region (215a) are not affected by the low-level voltage and can freely move in the first body region (214) and the second body region (215). Accordingly, the first source region (216) and the drain region and the second source region (217) and the drain region are electrically blocked, so that no current flows between the first source region (216) and the drain region and between the second source region (217) and the drain region.

[0096] Meanwhile, in the embodiment, the structure (231, 232) may be provided to improve the Ron resistance. That is, the resistance value (R) of the body area (214, 215) CH ) to reduce the channel length (L) CH ) can be reduced, the occurrence of the short channel effect can be suppressed by the structure (231, 232). Accordingly, the threshold voltage value (Vth) is not reduced, enabling the implementation of a high-power semiconductor device, and power consumption can be reduced by suppressing the drain-source leakage current. In addition, the channel length (L CH ) is reduced, the size of each of the plurality of semiconductor devices included in the active area is reduced, and miniaturization of the power semiconductor device can be realized.

[0097] Structures (231, 232) may be placed in the body regions (214, 215). Structures (231, 232) may be placed between the source regions (216, 217) and the body regions (214, 215). Structures (231, 232) may be placed inside the body regions (214, 215).

[0098] Meanwhile, the body region (214, 215) may have a first thickness (d11) in the downward direction from the lower side of the source region (216, 217) and a second thickness (d12) in the direction of the extended drift layer (213a) from the side of the source region (216, 217).

[0099] The second thickness (d12) is the channel length (L CH ) may be the same. As the second thickness (d12) becomes smaller, the channel length (L CH ) can be reduced. To improve Ron, the channel length (L CH ) is reduced, the second thickness (d12) may become smaller. In this case, as described above, there is a problem that the threshold voltage value (Vth) decreases and leakage current occurs between the source and drain due to the short channel effect.

[0100] When the second thickness (d12) becomes smaller, the first thickness (d11) may also become smaller, but this is not limited thereto.

[0101] To solve this problem, structures (231, 232) may be provided.

[0102] The structures (231, 232) may be arranged lengthwise along the length direction of the gate electrode (222). The structures (231, 232) may be arranged around the periphery of the source region (216, 217). The structures (231, 232) may be arranged on the side of the source region (216, 217). The structures (231, 232) may be spaced apart from the gate insulating layer (222) in the body region (214, 215). The gate insulating layer (222) is disposed on the upper surface of the source region (216, 217), and the structures (231, 232) are disposed on the side of the source region (216, 217), and the body regions (214, 215) are disposed between the gate insulating layer (222) and the structures (231, 232), so that the structures (231, 232) can be spaced apart from the gate insulating layer (222).

[0103] Since the structures (231, 232) are positioned on the side of the source region (216, 217) and the structures (231, 232) are spaced apart from the channel region (214a, 215a), the channel region (214a, 215a) can be formed adjacent to the gate insulating layer (222) in the body region (214, 215) without interference from the structures (231, 232).

[0104] Although the drawings depict structures (231, 232) as being in contact with the lower surface of the source region (216, 217), structures (231, 232) may be spaced apart from the lower surface of the source region (216, 217). Body regions (214, 215) may be positioned in the spaced apart space.

[0105] The structure may have a second challenge type. The concentration of the dopant in the structure (231, 232) may be greater than the concentration of the dopant in the body region (214, 215). The concentration of the dopant in the structure (231, 232) may be equal to or less than the concentration of the dopant in the contact region (218, 219).

[0106] If the structures (231, 232) and the contact areas (218, 219) have the same conductivity type or the same concentration, the structures (231, 232) and the contact areas (218, 219) may be formed through the same ion implantation process using the same mask, but this is not limited thereto.

[0107] Meanwhile, the structures (231, 232) may include a first structure (231) and a second structure (232) that are horizontally spaced apart from each other. The first structure (231) and the second structure (232) may be arranged to face each other with an extended drift layer (213a) therebetween.

[0108] The first structure (231) may be disposed around the first source region (216) in the first body region (214). That is, the first structure (231) may be disposed between the first source region (216) and the first body region (214). The first structure (231) may be disposed on a side of the first source region (216). The structure (231) may be disposed on a side of the first source region (216) adjacent to the first side of the extended drift layer (213a) in the first body region (214).

[0109] The first structure (231) may be disposed on a portion of the side of the first source region (216), and the second structure (232) may be disposed on a portion of the side of the second source region (217). That is, the first structure (231) may not be disposed on an upper portion of the side of the first source region (216), and the second structure (232) may be disposed on an upper portion of the side of the second source region (217). As illustrated in FIG. 5, the first body region (214) may include a first channel region (214a), and the second body region (215) may include a second channel region (215a). The first channel region (214a) may be disposed on the first structure (231). That is, the first channel region (214a) may be disposed on the upper side of the side of the first source region (216). The second channel region (215a) may be disposed on the second structure (232). That is, the second channel region (215a) may be disposed on the upper side of the side of the second source region (217).

[0110] The first structure (231) may be arranged in consideration of the thickness (d31) of the first channel region (214a). As the thickness (d31) of the first channel region (214a) increases, the size (or height) of the first structure (231) may decrease. The second structure (232) may be arranged in consideration of the thickness of the second channel region (215a). As the thickness of the second channel region (215a) increases, the size (or height) of the second structure (232) may decrease. Meanwhile, the second structure (232) may be arranged around the second source region (217) in the second body region (215). That is, the second structure (232) may be arranged between the second source region (217) and the second body region (215). The second structure (232) may be arranged on the side of the second source region (217). The second structure (232) may be placed on the side of the second source region (217) adjacent to the second side of the extended drift layer (213a) in the second body region (215).

[0111] Meanwhile, the first structure (231) may be spaced apart from the gate insulating layer (222) at the side of the first source region (216). The first structure (231) may be spaced apart from the gate insulating layer (222) with the first channel region (214a) therebetween. Since the first channel region (214a), which is an electrical passage between the first source region (216) and the drain region, i.e., the extended drift layer (213a), is formed, the first structure (231) may be spaced apart from the gate insulating layer (222) by the thickness (d31) of the first channel region (214a). In other words, the first structure (231) does not contact the gate insulating layer (222).

[0112] The second structure (232) may be spaced apart from the gate insulating layer (222) at the side of the second source region (217). The second structure (232) may be spaced apart from the gate insulating layer (222) with the second channel region (215a) therebetween. Since the second channel region (215a), which is an electrical passage between the second source region (217) and the drain region, i.e., the extended drift layer (213a), is formed, the second structure (232) may be spaced apart from the gate insulating layer (222) by the thickness of the second channel region (215a). In other words, the second structure (232) does not contact the gate insulating layer (222).

[0113] The first structure (231) may be disposed on a first side of the extended drift layer (213a), and the second structure (232) may be disposed on a second side of the extended drift layer (213a). The first structure (231) may be spaced apart from the first side of the extended drift layer (213a) with a first body region (214) therebetween. The second structure (232) may be spaced apart from the second side of the extended drift layer (213a) with a second body region (215) therebetween.

[0114] Meanwhile, the first body region (214) located on the side of the first source region (216) may have a predetermined thickness (d12). In this case, the channel length (L) of the first channel region (214a) CH ) may be equal to the thickness (d12) of the first body region (214). The thickness (d22) of the first structure (231) may be smaller than the thickness (d12) of the first body region (214). Accordingly, the first structure (231) may not be in contact with the extended drift layer (213a). That is, the first structure (231) may be spaced apart from the first side of the extended drift layer (213a). The first structure (231) may be spaced apart from the first side of the extended drift layer (213a) with the first body region (214) therebetween.

[0115] Similarly, a portion of the second body region (215) positioned on the side of the second source region (217) may have a predetermined thickness. In this case, the channel length of the second channel region (215a) may be the same as the thickness of the second body region (215). The thickness of the second structure (232) may be smaller than the thickness of the second body region (215). Accordingly, the second structure (232) may not be in contact with the extended drift layer (213a). That is, the second structure (232) may be spaced apart from the second side of the extended drift layer (213a). The second structure (232) may be spaced apart from the second side of the extended drift layer (213a) with the second body region (215) therebetween.

[0116] A source electrode (223) may be in contact with the contact areas (218, 219) and the source areas (216, 217). The source electrode (223) may be formed of nickel (Ni), etc. An annealing process may be performed to form an ohmic contact between the source electrode (223) and the contact areas (218, 219) and / or the source areas (216, 217).

[0117] The source electrode (223) may be disposed on the entire area of ​​the active region (206). The source electrode (223) may be disposed on the gate electrode (221). The source electrode (223) may be disposed on the gate insulating layer (222) surrounding the gate electrode (221). Although not shown, the source electrode (223) may not be disposed on the gate electrode (221) but may be disposed only on the contact regions (218, 219) and the source regions (216, 217).

[0118] A gate electrode (221) may be disposed on a drift layer (213) between spaced apart body regions (214, 215). The gate electrode (221) may be disposed on an upper surface of the drift layer (213). The gate electrode (221) may be disposed on an upper surface of an extended drift layer (213a) extending from the drift layer (213) toward the gate electrode (221). The gate electrode (221) may be surrounded by a gate insulating layer (222). The gate insulating layer (222) may be referred to as a gate oxide film. Another insulating layer may be disposed under the source electrode (223), but is not limited thereto.

[0119] In a semiconductor device having a structure as described above, the channel layer between the drift layer (213) and the source region (216, 217) becomes conductive by the gate voltage supplied to the gate electrode (221), so that current can flow between the source region (216, 217) and the drift layer (213). Accordingly, a switching function can be implemented by making the channel layer between the drift layer (213) and the source region (216, 217) conductive or closed depending on the high and low levels of the gate voltage.

[0120] The source region (216, 217) may have a first conductivity type, and the body region (214, 215), the structure (231, 232), or the contact region (218, 219) may have a second conductivity type. The source region (216, 217), like the substrate or the drift layer (213), may have the first conductivity type. For example, the source region (216, 217) may include an N-type dopant.

[0121] The mask (253) can be removed.

[0122] The upper surface of the body area (214, 215) and / or the contact area (218, 219) may be aligned horizontally with the upper surface of the drift layer (213).

[0123] After the body region (214, 215), structure (231, 232), contact region (218, 219) and source region (216, 217) are formed, a heat treatment process is performed so that ions or impurities implanted in the drift layer (213) can be activated.

[0124] According to the first embodiment, structures (231, 232) are arranged around the perimeter of the source region (216, 217), i.e., on the side of the source region (216, 217), so as to improve Ron by increasing the channel length (L). CH ) is reduced, the occurrence of the short channel effect can be suppressed. Accordingly, the threshold voltage (Vth) is not reduced, enabling the implementation of high-power semiconductor devices, and power consumption can be reduced by suppressing the drain-source leakage current. In addition, the channel length (L CH ) is reduced, the size of each of the plurality of semiconductor devices included in the active area is reduced, and miniaturization of the power semiconductor device can be realized.

[0125] [Example 2]

[0126] FIG. 6 is a cross-sectional view of a power semiconductor device according to the second embodiment, taken along the C-C' line in area A shown in FIG. 3.

[0127] The second embodiment is identical to the first embodiment except for the arrangement of the structures (231, 232). In the second embodiment, components having the same structure, shape, and / or function as those in the first embodiment are given the same drawing reference numerals and detailed descriptions are omitted.

[0128] Referring to FIGS. 3 and 6, the power semiconductor device according to the second embodiment may include a drain electrode (211), a substrate (212), a drift layer (213), a body region (214, 215), a source region (216, 217), a structure (231, 232), a contact region (218, 219), a gate electrode (221), a gate insulating layer (222), and a source electrode (223). The contact region (218, 219) may be omitted. The power semiconductor device according to the first embodiment may include more components than this. A semiconductor device can be configured by a drain electrode (211), a substrate (212), a drift layer (213), a body region (214, 215), a source region (216, 217), a contact region (218, 219), a gate electrode (221), a gate insulating layer (222), and a source electrode (223). A plurality of semiconductor devices configured in this manner can be included in an active region (206).

[0129] The structures (231, 232) may be positioned in the body regions (214, 215). The structures (231, 232) may be positioned between the source regions (216, 217) and the body regions (214, 215). The structures (231, 232) may be positioned around the source regions (216, 217). The structures (231, 232) may be positioned on the lower and side portions of the source regions (216, 217). The structures (231, 232) may extend from the lower side to the side portions of the source regions (216, 217).

[0130] The structures (231, 232) may include a first structure (231) and a second structure (232). The first structure (231) may extend laterally from the lower side of the first source region (216). The second structure (232) may extend laterally from the lower side of the second source region (217).

[0131] The first structure (231) may be spaced apart from the first side of the extended drift layer (213a). The first structure (231) may be spaced apart from the gate insulating layer (222). The first structure (231) may be spaced apart from the gate insulating layer (222) with the first channel region (214a) of the first body region (214) interposed therebetween.

[0132] The second structure (232) may be spaced apart from the second side of the extended drift layer (213a). The second structure (232) may be spaced apart from the gate insulating layer (222). The second structure (232) may be spaced apart from the gate insulating layer (222) with the second channel region (215a) of the second body region (215) interposed therebetween.

[0133] Meanwhile, the first structure (231) may include a first-first structure (231-1) on the lower side of the first source region (216) and a first-second structure (231-2) on the side of the first source region (216). For example, the second thickness (d22) of the first-second structure (231-2) may be equal to or greater than the first thickness (d21) of the first-first structure (231-1), but this is not limited thereto.

[0134] Likewise, the second structure (232) may include a second-first structure (232-1) on the lower side of the second source region (217) and a second-second structure (232-2) on the side of the second source region (217). For example, the second thickness of the second-second structure (232-2) may be equal to or greater than the first thickness of the second-first structure (232-1), but is not limited thereto.

[0135] According to the second embodiment, structures (231, 232) are arranged around the perimeter of the source region (216, 217), i.e., on the lower and side surfaces of the source region (216, 217), thereby improving Ron by increasing the channel length (L). CH) is reduced, the occurrence of the short channel effect can be suppressed. Accordingly, the threshold voltage (Vth) is not reduced, enabling the implementation of high-power semiconductor devices, and power consumption can be reduced by suppressing the drain-source leakage current. In addition, the channel length (L CH ) is reduced, the size of each of the plurality of semiconductor devices included in the active area is reduced, and miniaturization of the power semiconductor device can be realized.

[0136] [Example 3]

[0137] FIG. 7 is a cross-sectional view of a power semiconductor device according to the third embodiment, taken along the C-C' line in area A shown in FIG. 3.

[0138] Referring to FIG. 7, a power semiconductor device according to the third embodiment may include a drain electrode (211), a substrate (212), a drift layer (213), a body region (214, 215), a source region (216, 217), a structure (231, 232), a contact region (218, 219), a gate electrode (221), a gate insulating layer (222), and a source electrode (223). The contact region (218, 219) may be omitted. The power semiconductor device according to the first embodiment may include more components than this. A semiconductor device can be configured by a drain electrode (211), a substrate (212), a drift layer (213), a body region (214, 215), a source region (216, 217), a contact region (218, 219), a gate electrode (221), a gate insulating layer (222), and a source electrode (223). A plurality of semiconductor devices configured in this manner can be included in an active region (206).

[0139] Structures (231, 232) may be positioned in body regions (214, 215). Structures (231, 232) may be positioned on the lower side of source regions (216, 217). Structures (231, 232) may include two or more structures (231-1 to 231-3, 232-1 to 232-3). Although three structures are illustrated in FIG. 7, four or more structures may be provided.

[0140] At least one of the two or more structures (231-1 to 231-3, 232-1 to 232-3) may be positioned on the lower side of the contact area (218, 219).

[0141] As illustrated in FIG. 7, a first structure (231-1, 232-1), a second structure (231-2, 232-2), and a third structure (231-3, 232-3) may be included on the lower side of the source region (216, 217). The first structure (231-1, 232-1), the second structure (231-2, 232-2), and the third structure (231-3, 232-3) may be vertically spaced from each other. The body region (214, 215) may be arranged between the first structure (231-1, 232-1), the second structure (231-2, 232-2), and the third structure (231-3, 232-3).

[0142] For example, the size (or width) of the second structure (231-2, 232-2) may be larger than the size (or width) of the first structure (231-1, 232-1). For example, the size (or width) of the third structure (231-3, 232-3) may be larger than the size (or width) of the second structure (231-2, 232-2). For example, one end of the second structure (231-2, 232-2) may be arranged closer to the extended drift layer (213a) than one end of the first structure (231-1, 232-1), but this is not limited thereto. For example, one end of the third structure (231-3, 232-3) may be positioned closer to the extended drift layer (213a) than one end of the second structure (231-2, 232-2), but this is not limited thereto.

[0143] The first structure (231) may include a first-first structure (231-1), a first-second structure (231-2), and a first-third structure (231-3). The first-second structure (231-2) may be positioned below the first-first structure (231-1), and the first-third structure (231-3) may be positioned below the first-second structure (231-2).

[0144] The second structure (232) may include a second-first structure (232-1), a second-second structure (232-2), and a second-third structure (232-3). The second-second structure (232-2) may be positioned below the second-first structure (232-1), and the second-third structure (232-3) may be positioned below the second-second structure (232-2).

[0145] According to the third embodiment, two or more structures (231-1 to 231-3, 232-1 to 232-3) are arranged around the source region (216, 217), i.e., on the lower side of the source region (216, 217), thereby improving the Ron by increasing the channel length (L). CH) is reduced, the occurrence of the short channel effect can be suppressed. Accordingly, the threshold voltage (Vth) is not reduced, enabling the implementation of high-power semiconductor devices, and power consumption can be reduced by suppressing the drain-source leakage current. In addition, the channel length (L CH ) is reduced, the size of each of the plurality of semiconductor devices included in the active area is reduced, and miniaturization of the power semiconductor device can be realized.

[0146] The above detailed description should not be construed as limiting in any respect and should be considered illustrative only. The scope of the embodiments should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalency range of the embodiments are intended to be included within the scope of the embodiments.

Claims

1. Substrate; A drain electrode on the lower side of the substrate; A drift layer on the upper side of the above substrate; Source region in the above drift layer; A body region surrounding at least a side of the source region; A structure disposed between the source region and the body region; A gate insulating layer on the upper surface of the above drift layer; a gate electrode surrounded by the gate insulating layer; and a source electrode on the gate electrode; The above body area and the above structure have a second challenge type, The above structure is spaced apart from the gate insulating layer in the vertical direction and spaced apart from the drift layer in the horizontal direction. Power semiconductor devices.

2. In paragraph 1, The above body region includes a first body region and a second body region, The above source region includes a first source region and a second source region, The above structure includes a first structure and a second structure, The drift layer includes an extended drift layer between the first body region and the second body region, Power semiconductor devices.

3. In paragraph 2, The first structure is arranged on the side of the first source region and is spaced apart from the extended drift layer in the horizontal direction, The second structure is arranged on a side of the second source region facing a side of the first source region, and is spaced apart from the extended drift layer in the horizontal direction. Power semiconductor devices.

4. In paragraph 3, The first structure is spaced apart from the gate insulating layer on the side of the first source region, The second structure is spaced apart from the gate insulating layer on the side of the second source region, Power semiconductor devices.

5. In paragraph 4, The first body region forms a first channel region in a space between the first structure and the gate insulating layer, The second body region forms a second channel region in the space between the second structure and the gate insulating layer, Power semiconductor devices.

6. In paragraph 2, The first structure extends laterally from the lower side of the first source region and is spaced apart from the extended drift layer in the horizontal direction, The second structure extends laterally from the lower side of the second source region and is spaced apart from the extended drift layer in the horizontal direction. Power semiconductor devices.

7. In paragraph 6, The first structure is spaced apart from the gate insulating layer on the side of the first source region, The second structure is spaced apart from the gate insulating layer on the side of the second source region, Power semiconductor devices.

8. In paragraph 7, The first body region forms a first channel region in a space between the first structure and the gate insulating layer, The second body region forms a second channel region in the space between the second structure and the gate insulating layer, Power semiconductor devices.

9. In paragraph 1, The above structure is, Long and arranged along the length direction of the above gate electrode, Power semiconductor devices.

10. Containing multiple power semiconductor modules; Each of the above plurality of power semiconductor modules includes a plurality of power semiconductor elements, Each of the above plurality of power semiconductor devices is substrate; A drain electrode on the lower side of the substrate; A drift layer on the upper side of the above substrate; Source region in the above drift layer; A body region surrounding at least a side of the source region; A structure disposed between the source region and the body region; A gate insulating layer on the upper surface of the above drift layer; a gate electrode surrounded by the gate insulating layer; and a source electrode on the gate electrode; The above body area and the above structure have a second challenge type, The above structure is spaced apart from the gate insulating layer in the vertical direction and spaced apart from the drift layer in the horizontal direction. Power semiconductor devices.

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