Method for determining frequency of clock signal, and apparatus

Abstract

Provided in the embodiments of the present disclosure are a method for determining the frequency of a clock signal, and an apparatus. The method comprises: inputting a clock signal into a frequency meter in a chip and, in response to an enable signal, the frequency meter counting the clock signal; at the end of a measurement window, the frequency meter stopping counting, and reading a count result as the frequency initial value of the clock signal; and, according to the frequency initial value, the reference clock frequency of the frequency meter and the time count value of the measurement window, determining the frequency value of the clock signal.

Description

Method and device for determining clock signal frequency

[0001] Cross-references to related publications

[0002] This disclosure is based on Chinese Patent Publication No. 202310949298X, filed on July 27, 2023, entitled “Method and Apparatus for Determining Clock Signal Frequency,” and claims priority to the patent disclosure, all of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of chip fault diagnosis, and in particular, to a method and apparatus for determining the frequency of a clock signal. Background Art

[0004] In a chip system, the presence or absence of clock frequency and its accuracy are very important parts of the entire chip system, used to ensure that the chip system can work normally. If the clock required by the corresponding chip system cannot be provided, the chip performance may be damaged, and even it may not work normally in many working scenarios. Therefore, clock diagnosis is required to ensure the stable operation of the entire chip system.

[0005] Among the general technical solutions, one solution is to multiplex the clock frequency signal to be measured that is of concern in the chip operation and then pull it to the chip pin. After the chip software configures the corresponding clock output to the chip I / O pin according to the clock selection mapping table, the clock is measured by an external device such as an oscilloscope. On the one hand, the chip software needs to be separately configured to select the clock frequency signal to be measured, which is a relatively cumbersome method. On the other hand, due to the very limited chip pin resources, it can usually only be output to a fixed clock measurement external pin after multiplexing. This is limited to only being able to measure the clock frequency of a single clock to be measured at the same time, which is inefficient and slow. In addition, this solution usually requires the output pin to be connected to an oscilloscope or other precision measuring equipment in order to accurately measure the output clock frequency. However, due to the complexity and diversity of the chip working scenarios, it is very difficult to prepare the corresponding precision time measurement equipment in many scenarios where chip failures require urgent diagnosis. Therefore, the feasibility of using this method for diagnosis is further increased, and its application difficulty and complexity are increased.

[0006] Another solution is to connect a dedicated reference clock externally and use this reference clock to compare with the clock to be tested, thereby realizing the function of diagnosing the clock to be tested. Specifically, it is to judge whether the clock is abnormal by comparing the difference between the two clocks within a certain time interval, or by whether the frequency calculation value exceeds the threshold. This method usually uses a timer to implement clock diagnosis. On the one hand, this method has a high design complexity, and on the other hand, the corresponding diagnostic accuracy and efficiency are low. It can usually only feedback whether the clock is abnormal compared with the judgment criteria, but cannot show specific details, which is not conducive to clock diagnosis and positioning of large-scale complex integrated chips.

[0007] Therefore, there is an urgent need for a clock rapid diagnosis method that does not require the use of external precision time and frequency measurement equipment, but can accurately and efficiently observe multiple key clock frequency values ​​in the chip at the same time, and perform rapid and real-time diagnosis of key clocks to ensure that the chip can work normally and stably.

[0008] Summary of the Invention

[0009] The embodiments of the present disclosure provide a method and device for determining the frequency of a clock signal, so as to at least solve the problem that the methods for determining the frequency of a clock signal in related technologies are relatively complex and inefficient, and solve the problem that the current methods for determining the frequency of a clock signal are relatively complex and inefficient.

[0010] According to one embodiment of the present disclosure, a method for determining the frequency of a clock signal is provided, comprising: connecting the clock signal to a frequency meter inside a chip, the frequency meter counting the clock signal in response to an enable signal; the frequency meter stopping counting after a measurement window ends, and reading the count result as an initial frequency value of the clock signal; and determining the frequency value of the clock signal based on the initial frequency value, a reference clock frequency of the frequency meter, and a time count value of the measurement window.

[0011] According to another embodiment of the present disclosure, a device for determining the frequency of a clock signal is provided, comprising: a counting module configured to connect the clock signal to a frequency meter inside a chip, the frequency meter counting the clock signal in response to an enable signal; a reading module configured to cause the frequency meter to stop counting after a measurement window ends, and read the counting result as an initial frequency value of the clock signal; and a determining module configured to determine the frequency value of the clock signal based on the initial frequency value, a reference clock frequency of the frequency meter, and a time count value of the measurement window.

[0012] According to another embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when running.

[0013] According to another embodiment of the present disclosure, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] 1 is a hardware structure block diagram of a computer terminal according to a method for determining a clock signal frequency according to an embodiment of the present disclosure;

[0015] FIG2 is a flow chart of a method for determining a clock signal frequency according to an embodiment of the present disclosure;

[0016] 3 is a structural block diagram of an apparatus for determining a clock signal frequency according to an embodiment of the present disclosure;

[0017] FIG4 is a structural block diagram of an apparatus for determining a clock signal frequency according to yet another embodiment of the present disclosure;

[0018] 5 is a flowchart of a method for determining a clock signal frequency according to yet another embodiment of the present disclosure;

[0019] FIG6 is a schematic diagram of an application example (I) of a method for determining a clock signal frequency according to an embodiment of the present disclosure;

[0020] FIG7 is a diagram showing the working principle of a frequency meter inside a chip according to an embodiment of the present disclosure;

[0021] 8 is a flowchart of a method for determining a clock signal frequency according to yet another embodiment of the present disclosure;

[0022] FIG9 is a schematic diagram of an application example (II) of the method for determining the frequency of a clock signal according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with the embodiments.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0025] The following is a description of relevant terms in the embodiments of the present disclosure:

[0026] Control status register: A register that can control the internal status of the chip through chip software.

[0027] Serial-to-parallel converter: A converter that converts parallel data into serial data for transmission and converts received serial data into parallel data.

[0028] PCIe bus (Peripheral Component Interconnect Express, PCI-Express): is a high-speed serial computer expansion bus standard that supports high-speed serial point-to-point dual-channel high-bandwidth transmission.

[0029] PX4 subsystem: PCIe X4 controller subsystem, which can support up to 4 lanes (channels) working simultaneously.

[0030] PIPE interface: It is set as a standard protocol interface connecting interfaces such as PCIe, Serial Advanced Technology Attachment, Universal Serial Bus, DisplayPort, etc. and PHY (physical layer).

[0031] The method embodiments provided in the embodiments of the present disclosure can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking operation on a computer terminal as an example, FIG1 is a hardware structure block diagram of a computer terminal of a method for determining a clock signal frequency according to an embodiment of the present disclosure. As shown in FIG1 , the computer terminal may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 configured to store data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input / output device 108 configured to have a communication function. It will be understood by those skilled in the art that the structure shown in FIG1 is only for illustration and does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

[0032] The memory 104 can be configured to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for determining the clock signal frequency in the embodiment of the present disclosure. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0033] The transmission device 106 is configured to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by a communications provider of a computer terminal. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module configured to communicate with the Internet wirelessly.

[0034] In this embodiment, a method for determining the frequency of a clock signal running on the above-mentioned computer terminal is provided. FIG2 is a flow chart of the method for determining the frequency of a clock signal according to an embodiment of the present disclosure. As shown in FIG2 , the flow chart includes the following steps:

[0035] Step S202: Connecting the clock signal to a frequency meter inside the chip, wherein the frequency meter counts the clock signal in response to an enable signal;

[0036] Before the frequency counter counts the clock signal in response to the enable signal in step S202 of this embodiment, the method further includes: the frequency counter starts a mode of measuring the frequency of the clock signal in response to a reset signal; and determines a measurement window of the frequency counter.

[0037] The frequency meter is not always in the mode of measuring the frequency of the clock signal, so a switch is required to turn it on. In the embodiment of the present disclosure, the measurement mode is turned on by the action of the reset signal, and the measurement time is also variable. The frequency meter counts within the measurement window by pre-determining the measurement window.

[0038] In an exemplary embodiment, the frequency meter starts the mode of measuring the frequency of the clock signal in response to the reset signal, comprising: releasing a reset signal to the frequency meter through a first control status register CSR, and the frequency meter starts the mode of measuring the frequency of the clock signal in response to the reset signal, wherein the first CSR is connected to the frequency meter.

[0039] The first CSR releases a reset signal to the frequency meter to start the measurement mode of the frequency meter. The first CSR and the CSRs in other steps are configured through software. Compared with external precision measuring equipment, the method of configuring the CSR in the embodiment of the present disclosure is more convenient and quick. After the CSR connected to the frequency meter is configured, the clock signal can be measured.

[0040] In an exemplary embodiment, determining the measurement window of the frequency meter includes: determining the measurement window of the frequency by a second CSR, wherein the second CSR is connected to the frequency meter.

[0041] In step S202 of this embodiment, the frequency counter counts the clock signal in response to the enable signal, including: releasing the enable signal to the frequency counter through a third CSR, and the frequency counter counts the clock signal in response to the enable signal, wherein the third CSR is connected to the frequency counter.

[0042] After the measurement mode is turned on, it is necessary to determine when the frequency counter starts counting. Therefore, under the action of the enable signal, the frequency counter starts counting.

[0043] Step S204, the frequency counter stops counting after the measurement window ends, and reads the counting result as the initial value of the frequency of the clock signal;

[0044] In step S204 of this embodiment, it includes obtaining an end signal indicating the end of the measurement window released by the fourth CSR, and the frequency counter stops counting in response to the end signal, wherein the fourth CSR is connected to the frequency counter; and reading the initial frequency value of the clock signal through the fifth CSR, wherein the fifth CSR is connected to the frequency counter.

[0045] Step S206 , determining the frequency value of the clock signal according to the initial frequency value, the reference clock frequency of the frequency meter, and the time count value of the measurement window.

[0046] In step S206 of this embodiment, the frequency value of the clock signal is determined based on the initial frequency value, the reference clock frequency of the frequency meter, and the time count value of the measurement window, including: calculating the frequency value of the clock signal based on the initial frequency value, the reference clock frequency of the frequency meter, and the time count value of the measurement window = the reference clock frequency * the initial frequency value / the time count value of the measurement window.

[0047] After obtaining the count value of the frequency counter, the frequency value of the clock signal can be obtained by performing a simple calculation based on the above formula in combination with the known reference clock frequency and the time count value of the measurement window.

[0048] Through the embodiments of the present disclosure, since the clock signal is connected to the frequency meter inside the chip, the frequency meter starts to count the clock signal under the action of the enable signal, and completes the counting within the measurement window and obtains the count value. After obtaining the count value, the frequency value of the clock signal can be determined based on only three numerical values: the count value, the reference clock frequency of the frequency meter itself, and the count value of the time of the pre-set measurement window. Therefore, without introducing external precision time and frequency measurement equipment, the problem that the current method of determining the frequency of the clock signal is relatively complex and inefficient can be solved, and the effect of efficiently and conveniently determining the frequency of the clock signal can be achieved.

[0049] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present disclosure.

[0050] In this embodiment, a device for determining the frequency of a clock signal is also provided. The device is configured to implement the above-mentioned embodiments and preferred embodiments, and the details already described are not repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0051] FIG3 is a structural block diagram of an apparatus for determining a clock signal frequency according to an embodiment of the present disclosure. As shown in FIG3 , the apparatus includes: a counting module 10 , a reading module 20 , and a determining module 30 .

[0052] The counting module 10 is configured to connect the clock signal to a frequency meter inside the chip, and the frequency meter counts the clock signal in response to an enable signal;

[0053] The reading module 20 is configured to stop the frequency counter from counting after the measurement window ends, and read the counting result as the initial value of the frequency of the clock signal;

[0054] The determination module 30 is configured to determine the frequency value of the clock signal according to the initial frequency value, the reference clock frequency of the frequency meter and the time count value of the measurement window.

[0055] FIG4 is a structural block diagram of an apparatus for determining a clock signal frequency according to yet another embodiment of the present disclosure. As shown in FIG4 , in addition to all the modules shown in FIG3 , the determining module 30 further includes:

[0056] The calculation unit 31 is configured to calculate the frequency value of the clock signal = the reference clock frequency * the initial frequency value / the time count value of the measurement window based on the initial frequency value, the reference clock frequency of the frequency meter and the time count value of the measurement window.

[0057] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0058] To facilitate understanding of the technical solutions provided by the present disclosure, embodiments of specific scenarios will be described in detail below.

[0059] FIG5 is a flow chart of a method for determining a clock signal frequency according to yet another embodiment of the present disclosure. As shown in FIG5 , the method includes the following steps:

[0060] Step S502, configuring the control status register (CSR) register A through software to release a reset signal;

[0061] Specifically, register A releases the reset signal of the debug module. The reset signal is low and valid. When configured as 1 and read back, it indicates that the configuration has successfully released the corresponding reset signal, indicating that the debug module is turned on to enter the chip diagnostic mode. Its actual function is the diagnostic start switch of the embodiment of the present disclosure.

[0062] Step S504, configuring the CSR register B through software to perform window configuration on the frequency counter inside the chip;

[0063] Step S506, configuring the CSR register C through software to first pull low and then pull high the start_en enable signal of the frequency counter;

[0064] Specifically, the enable signal is first set to 0 (low level) and then to 1 (high level), thereby releasing the enable signal to ensure that the frequency meter can be triggered normally every time, the frequency meter starts to work and the corresponding clock frequency counting begins.

[0065] Step S508, read the CSR register D through software and wait for the frequency counter completion flag;

[0066] Specifically, when register D is 1, it indicates that the clock frequency measurement is completed.

[0067] Step S510, after detecting that the CSR register D is 1, read the output frequency of the clock frequency to be measured;

[0068] Specifically, after detecting that the CSR register D is 1, that is, after receiving the corresponding freq_done (frequency measurement end) signal (indicating that the frequency diagnostic measurement is completed), the o_freq (output frequency) of the clock frequency to be measured is read, that is, the initial frequency value read out based on the frequency meter inside the chip.

[0069] Step S512: Calculate and obtain a final frequency value.

[0070] Specifically, according to the reference clock frequency, the frequency counter window and the output frequency of the clock frequency to be measured, the calculated value of the final required diagnostic frequency, ie, the actual final clock diagnostic result, can be calculated by calculation formula (1).

[0071] The calculation of the final diagnosis result frequency is related to i_basis_clk and i_window;

[0072] The calculation formula is as follows: final_freq = i_basis_clk * o_freq / i_window (1)

[0073] Among them, i_basis_clk represents the reference clock frequency used by the chip's internal frequency counter;

[0074] o_freq represents the initial frequency value read out based on the chip's internal frequency meter, which is the measured initial frequency value;

[0075] The corresponding i_window is the calculation window of the frequency counter inside the chip;

[0076] final_freq corresponds to the frequency of the final diagnosis result, which is also the final diagnosis result that the embodiments of the present disclosure focus on.

[0077] According to another embodiment of the present disclosure, a method for determining the clock signal frequency can be applied to the PCIe subsystem in the CPU chip shown in Figure 6. As shown in Figure 6, there is a very important clock PCLK between the PCIe controller (PCIe controller) and the SerDes (PCIe physical layer), which is the working clock of the PIPE interface. The presence or absence of this clock affects whether the PCIe controller can work normally, and the specific operating frequency of its clock determines the data transmission rate of the PCIe subsystem. The PCIe subsystem data transmission operates in gen1 / gen2 / gen3 / gen4 / gen5, and the corresponding PCLK operates at 62.5MHz / 125MHz / 250MHz / 500MHz / 1000MHz. The two have a sequential correspondence. In chip design, the key clock, taking PCLK as an example, is diagnosed using the frequency meter inside the chip. On the one hand, the presence or absence of the corresponding clock can be diagnosed, thereby determining whether the corresponding PCIe subsystem is in a normal working state; on the other hand, the specific frequency of the corresponding clock can be measured by diagnosis to determine which transmission rate the PCIe subsystem is currently in, from gen1 to gen5.

[0078] Figure 7 is a working principle diagram of the frequency meter inside the chip. As shown in Figure 7, the reset signal is used to turn on the switch for diagnosing the clock and determining the clock frequency. Under the action of the enable signal, the frequency meter starts counting and displays the specific count value. After the measurement window ends, the count value of the frequency meter is read to determine whether the clock is working normally.

[0079] FIG8 is a flow chart of a method for determining a clock signal frequency according to another embodiment of the present disclosure. As shown in FIG8 , the method includes the following steps:

[0080] Step S802, configuring the internal register A of the CSR module through software and releasing the reset signal;

[0081] Specifically, the chip system software configures the internal register A of the CSR module through the configuration bus and releases the reset signal of the debug module, that is, starts the diagnostic switch.

[0082] Step S804, configuring CSR registers B0, B1, B2, and B3 through software to configure the frequency counters A, B, C, and D inside the chip;

[0083] Step S806, configuring CSR registers C0, C1, C2, and C3 through software to first pull low and then pull high the start_en enable signal of frequency counters A, B, C, and D;

[0084] Step S808, read CSR registers D0, D1, D2, and D3 through software, and wait for the frequency meter completion flags of frequency meters A, B, C, and D;

[0085] Specifically, when registers D0, D1, D2, and D3 are all 1, it indicates that the clock frequency measurement is completed.

[0086] Step S810, after detecting that the CSR registers D0, D1, D2, and D3 are 1, the output frequency of the clock frequency to be measured is read;

[0087] Specifically, after detecting that the CSR register D0 is 1, that is, after receiving the corresponding freq_done_lane0 signal (indicating that the diagnostic measurement of frequency meter A is completed), the output frequency o_freq_lane0 of the clock frequency to be measured is read, that is, the initial frequency value read out by the frequency meter A inside the chip;

[0088] After detecting that the CSR register D1 is 1, that is, after receiving the corresponding freq_done_lane1 signal (indicating that the diagnostic measurement of frequency meter B is completed), the output frequency o_freq_lane1 of the clock frequency to be measured is read, that is, the initial frequency value read based on the frequency meter B inside the chip;

[0089] After detecting that the CSR register D2 is 1, that is, after receiving the corresponding freq_done_lane2 signal (indicating that the diagnostic measurement of the frequency meter C is completed), the output frequency o_freq_lane2 of the clock frequency to be measured is read, that is, the initial frequency value read based on the frequency meter C inside the chip;

[0090] After detecting that CSR register D3 is 1, that is, after receiving the corresponding freq_done_lane3 signal (indicating that the diagnostic measurement of frequency meter D is completed), the output frequency o_freq_lane3 of the clock frequency to be measured is read, that is, the initial frequency value read out based on the frequency meter D inside the chip.

[0091] Step S812: Calculate and obtain a final frequency value.

[0092] Specifically, according to the reference clock frequency configured in lane0 (channel 0), the frequency meter window, and the output frequency o_freq_lane0 of the clock frequency to be measured (based on the initial frequency value read out by the frequency meter A inside the chip), the calculated value of the final required diagnostic frequency, i.e., the actual final clock diagnostic result A, can be calculated by the following corresponding calculation formula (2).

[0093] The calculation of the final diagnosis result A frequency is related to i_basis_clk_lane0 and i_window_lane0;

[0094] The calculation formula is as follows: final_freq_lane0 = i_basis_clk_lane0 × o_freq_lane0 / i_window_lane0 (2)

[0095] Among them, i_basis_clk_lane0 represents the reference clock frequency used by the chip's internal frequency counter;

[0096] o_freq_lane0 represents the initial frequency value read out based on the chip's internal frequency meter, which is the measured initial frequency value;

[0097] The corresponding i_window_lane0 is the calculation window of the frequency counter inside the chip;

[0098] final_freq_lane0 corresponds to the frequency of the final diagnosis result, which is also the final diagnosis result A concerned in this application example, that is, the diagnosis result of the tx_clk0 clock output by lane0 (channel 0).

[0099] According to the reference clock frequency configured in lane 1 (channel 1), the frequency counter window, and the output frequency o_freq_lane1 of the clock frequency to be measured (based on the initial frequency value read out by the frequency counter B inside the chip), the calculated value of the final required diagnostic frequency can be calculated by the following corresponding calculation formula (3), that is, the actual final clock diagnostic result B.

[0100] The calculation of the final diagnosis result B frequency is related to i_basis_clk_lane1 and i_window_lane1 (frequency counter window of frequency counter B);

[0101] The calculation formula is as follows: final_freq_lane1=i_basis_clk_lane1×o_freq_lane1 / i_window_lane1(3)

[0102] Among them, i_basis_clk_lane1 represents the reference clock frequency used by the chip's internal frequency counter;

[0103] o_freq_lane1 represents the initial frequency value read out based on the chip's internal frequency meter, which is the measured initial frequency value;

[0104] The corresponding i_window_lane1 is the calculation window of the frequency counter inside the chip;

[0105] final_freq_lane1 corresponds to the frequency of the final diagnosis result, which is also the final diagnosis result B concerned in this application example, that is, the diagnosis result of the tx_clk1 clock output by lane1 (channel 1).

[0106] According to the reference clock frequency configured in lane 2 (channel 2), the frequency counter window, and the output frequency o_freq_lane2 of the clock frequency to be measured (based on the initial frequency value read out by the frequency counter C inside the chip), the calculated value of the final required diagnostic frequency, i.e., the actual final clock diagnostic result C, can be calculated by the following corresponding calculation formula (4).

[0107] The calculation of the final diagnostic result C frequency is related to i_basis_clk_lane2 and i_window_lane2 (frequency counter window of frequency counter C);

[0108] The calculation formula is as follows: final_freq_lane2=i_basis_clk_lane2×o_freq_lane2 / i_window_lane2(4)

[0109] Among them, i_basis_clk_lane2 represents the reference clock frequency used by the chip's internal frequency counter;

[0110] o_freq_lane2 represents the initial frequency value read out based on the chip's internal frequency meter, which is the measured initial frequency value;

[0111] The corresponding i_window_lane2 is the calculation window of the frequency counter inside the chip;

[0112] final_freq_lane2 corresponds to the frequency of the final diagnosis result, which is also the final diagnosis result C that this application example focuses on, that is, the diagnosis result of the tx_clk2 clock output by lane2 (channel 2).

[0113] According to the reference clock frequency configured in lane 3 (channel 3), the frequency counter window, and the output frequency o_freq_lane3 of the clock frequency to be measured (based on the initial frequency value read out by the frequency counter D inside the chip), the calculated value of the final required diagnostic frequency, i.e., the actual final clock diagnostic result D, can be calculated by the following corresponding calculation formula (5).

[0114] The calculation of the final diagnosis result D frequency is related to i_basis_clk_lane3 and i_window_lane3 (frequency counter window of frequency counter D);

[0115] The calculation formula is as follows: final_freq_lane3=i_basis_clk_lane3×o_freq_lane3 / i_window_lane3(5)

[0116] Among them, i_basis_clk_lane3 represents the reference clock frequency used by the chip's internal frequency counter;

[0117] o_freq_lane3 represents the initial frequency value read out based on the chip's internal frequency meter, which is the measured initial frequency value;

[0118] The corresponding i_window_lane3 is the calculation window of the frequency counter inside the chip;

[0119] final_freq_lane3 corresponds to the frequency of the final diagnosis result, which is also the final diagnosis result D concerned in this application example, that is, the diagnosis result of the tx_clk3 clock output by lane3 (channel 3).

[0120] Finally, the diagnostic results A, B, C, and D of the four clocks to be diagnosed, tx_clk0-tx_clk3, corresponding to lane0-lane3, are fed back to the CSR module. The chip system software can obtain the diagnostic results of the four clocks tx_clk0-tx_clk3 at the same time by reading the register contents of the corresponding addresses, completing the simultaneous measurement and diagnosis of multiple clocks.

[0121] The flowchart of the method for determining the clock signal frequency according to another embodiment of the present disclosure can be applied to the PX4 subsystem in the multi-mode soft baseband expansion chip (Multi-Mode Chip System, MCS) shown in Figure 9. As shown in Figure 9, the PX4 subsystem contains 4 channels, namely lane0, lane1, lane2 and lane3. The 4 channels will respectively send out 4 clock signals (tx_clk0, tx_clk1, tx_clk2, tx_clk3). The 4 clocks will interact with the upstream PIPE Bifurcation module. The presence or absence and specific frequency of the 4 clocks will affect the working conditions of the upstream module. Therefore, the PX4 subsystem in the MCS chip shown in Figure 9 uses the method described in the present disclosure to perform clock diagnosis of multiple clocks simultaneously based on the chip's internal frequency meter.

[0122] An embodiment of the present disclosure further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when run.

[0123] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0124] An embodiment of the present disclosure further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0125] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0126] The method of the embodiment of the present invention is used to perform clock diagnosis on the chip without the need for external precision time and frequency measurement equipment, which can reduce costs and improve measurement efficiency; it can simultaneously measure multiple key clock frequency signals and diagnose multiple clocks; using software to configure the corresponding registers, the chip's internal frequency meter can be used for convenient operation to perform measurements, completing clock diagnosis work efficiently and conveniently.

[0127] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0128] Obviously, those skilled in the art should understand that the various modules or steps of the above-mentioned embodiments of the present disclosure can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented using program codes executable by the computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be made into individual integrated circuit modules, or multiple modules or steps can be made into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any specific combination of hardware and software.

[0129] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure are intended to be within the scope of protection of the present disclosure.

Claims

1. A method for determining a frequency of a clock signal, comprising: Connecting the clock signal to a frequency meter inside the chip, wherein the frequency meter counts the clock signal in response to an enable signal; The frequency meter stops counting after the measurement window ends, and reads the counting result as the initial value of the frequency of the clock signal; The frequency value of the clock signal is determined according to the initial frequency value, the reference clock frequency of the frequency meter and the time count value of the measurement window.

2. The method according to claim 1, wherein: Determining the frequency value of the clock signal according to the initial frequency value, the reference clock frequency of the frequency meter and the time count value of the measurement window comprises: The frequency value of the clock signal is calculated according to the initial frequency value, the reference clock frequency of the frequency meter and the time count value of the measurement window = the reference clock frequency * the initial frequency value / the time count value of the measurement window.

3. The method according to claim 1, wherein: Before the frequency meter counts the clock signal in response to the enable signal, the frequency meter further includes: The frequency meter starts a mode of measuring the frequency of the clock signal in response to a reset signal; A measurement window of the frequency meter is determined.

4. The method according to claim 3, wherein: The frequency meter starts the mode of measuring the frequency of the clock signal in response to the reset signal, comprising: A reset signal is released to the frequency meter through a first control status register CSR, and the frequency meter starts the mode of measuring the frequency of the clock signal in response to the reset signal, wherein the first CSR is connected to the frequency meter.

5. The method according to claim 3, wherein: Determining the measurement window of the frequency meter comprises: The measurement window of the frequency is determined by a second CSR, wherein the second CSR is connected to the frequency meter.

6. The method according to claim 1, wherein: The frequency meter counts the clock signal in response to the enable signal, comprising: The enable signal is released to the frequency meter through a third CSR, and the frequency meter counts the clock signal in response to the enable signal, wherein the third CSR is connected to the frequency meter.

7. The method according to claim 1, wherein: The frequency counter stops counting after the measurement window ends, and reads the initial frequency value of the clock signal, including: Acquire an end signal indicating the end of the measurement window released by the fourth CSR, wherein the frequency meter stops counting in response to the end signal, wherein the fourth CSR is connected to the frequency meter; The initial frequency value of the clock signal is read through a fifth CSR, wherein the fifth CSR is connected to the frequency meter.

8. A device for determining a frequency of a clock signal, comprising: A counting module, configured to connect the clock signal to a frequency meter inside the chip, wherein the frequency meter counts the clock signal in response to an enable signal; A reading module, configured to stop the frequency meter from counting after the measurement window ends, and read the counting result as the initial value of the frequency of the clock signal; The determination module is configured to determine the frequency value of the clock signal according to the initial frequency value, the reference clock frequency of the frequency meter and the time count value of the measurement window.

9. The device according to claim 8, wherein: The determination module also includes: The calculation unit is configured to calculate the frequency value of the clock signal according to the initial frequency value, the reference clock frequency of the frequency meter and the time count value of the measurement window = the reference clock frequency * the initial frequency value / the time count value of the measurement window.

10. A computer-readable storage medium having a computer program stored therein, wherein: When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 7 are implemented.

11. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method described in any one of claims 1 to 7 when executing the computer program.

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