Semiconductor arrangement with a semiconductor element

Abstract

The invention relates to a semiconductor arrangement (2) with a semiconductor element (4) which is arranged on a carrier element (6), wherein the semiconductor element (4) has a first load contact (8) and a second load contact (10) on a side facing away from the carrier element (6), wherein the carrier element (6) comprises a first conductor structure (12) and a second conductor structure (14) which is electrically insulated from the first conductor structure (12). In order to specify a wiring which is improved with respect to the prior art, it is proposed that the second conductor structure (14) is arranged between the semiconductor element (4) and the first conductor structure (12), wherein: the first load contact (8) is arranged between the second load contact (10) and the second conductor structure (14); the first load contact (8) is connected via at least one first wiring element (16) to the first conductor structure (12); the second load contact (10) is connected via at least one second wiring element (18) to the second conductor structure (14); and the second wiring element (18) is arranged at least partially spanning the first wiring element (16).

Description

[0001] Description

[0002] Semiconductor arrangement with a semiconductor element

[0003] The invention relates to a semiconductor device with a semiconductor element.

[0004] Furthermore, the invention relates to a power converter with at least one such semiconductor element.

[0005] Furthermore, the invention relates to a method for producing a semiconductor device.

[0006] Such a semiconductor device is typically used in a power converter. A power converter can be, for example, a rectifier, an inverter, a converter, or a DC-DC converter. The semiconductor elements used in the semiconductor module include transistors, triacs, thyristors, and diodes.

[0007] Typically, the semiconductor elements are bonded to a substrate via bond wires, which leads to additional inductance in the semiconductor device. Due to increasing switching speeds in such semiconductor devices, the effects of parasitic inductances are becoming increasingly significant. Especially when using semiconductor elements with a wide band gap, e.g., GaN or SiC semiconductor elements, it is imperative to minimize parasitic inductance during layout.

[0008] The patent US 11,183,440 B2 describes low inductance power modules for ultrafast wide bandgap semiconductor power switching devices.

[0009] The published patent application EP 4 120 341 A1 relates to a semiconductor arrangement comprising a semiconductor element, a substrate, and bonding means. In order to achieve improved wiring compared to the prior art, it is proposed that the semiconductor element be connected to the substrate, in particular in a materially bonded manner, wherein the semiconductor element has at least one contact surface on a side facing away from the substrate, wherein at least one contact surface of the semiconductor element is connected to the substrate via at least one first bonding means, wherein the at least one first bonding means forms at least one first wedge bond contact on the contact surface, which is arranged between a first loop and a second loop of the at least one first bonding means, wherein the first loop has a first maximum and the second loop has a second maximum,wherein a first transverse loop of a second bonding means is arranged above the first wedge bond contact and extending between the first maximum of the first loop and the second maximum of the second loop.,

[0010] Against this background, the object of the invention is to provide a semiconductor device which, in comparison with the prior art, has improved wiring.

[0011] The object is achieved according to the invention by a semiconductor arrangement with a semiconductor element which is arranged on a carrier element, wherein the semiconductor element is designed as a horizontally conducting power semiconductor, wherein the semiconductor element has a first load contact and a second load contact on a side facing away from the carrier element, wherein the carrier element comprises a first conductor structure and a second conductor structure arranged electrically insulated from the first conductor structure, wherein the second conductor structure is arranged between the semiconductor element and the first conductor structure, wherein the first load contact is arranged between the second load contact and the second conductor structure, wherein the first load contact is connected to the first conductor structure via at least one first wiring element, wherein the second load contact is connected to the second conductor structure via at least one second wiring element,wherein the second wiring element is arranged to at least partially span the first wiring element.,

[0012] Furthermore, the object is achieved according to the invention by a semiconductor arrangement with a semiconductor element and a carrier element, the semiconductor element being designed as a vertical power semiconductor, a first load contact of the semiconductor element being connected, in particular in a materially bonded manner, to a first conductor structure of the carrier element, the semiconductor element having a second load contact on a side facing away from the carrier element, the carrier element comprising a second conductor structure arranged such that it is electrically insulated from the first conductor structure, the second load contact being connected to the second conductor structure via at least one second wiring element, a first wiring element being connected to the first conductor structure, the second wiring element being arranged so as to at least partially span the first wiring element.

[0013] Furthermore, the object is achieved according to the invention by a semiconductor arrangement with a first semiconductor element and a second semiconductor element, which are arranged on a carrier element, wherein the semiconductor elements are designed as vertical power semiconductors, wherein the first semiconductor element has a first load contact on a side facing away from the carrier element and the second semiconductor element has a second load contact on a side facing away from the carrier element, wherein the carrier element comprises a first conductor structure and a second conductor structure arranged electrically insulated from the first conductor structure, wherein the second conductor structure is arranged between the semiconductor element and the first conductor structure, wherein the first load contact is connected to the first conductor structure via at least one first wiring element,wherein the second load contact is connected to the second conductor structure via at least one second wiring element, wherein the second wiring element is arranged at least partially spanning the first wiring element.,

[0014] Moreover, the object is achieved according to the invention by a power converter having at least one such semiconductor arrangement.

[0015] Furthermore, the object is achieved according to the invention by a method for producing a semiconductor arrangement with a semiconductor element which is arranged on a carrier element, wherein the semiconductor element is designed as a horizontally conducting power semiconductor, wherein the semiconductor element has a first load contact and a second load contact on a side facing away from the carrier element, wherein the carrier element comprises a first conductor structure and a second conductor structure arranged electrically insulated from the first conductor structure, wherein the second conductor structure is arranged between the semiconductor element and the first conductor structure, wherein the first load contact is arranged between the second load contact and the second conductor structure, wherein the first load contact is connected to the first conductor structure via at least one first wiring element,wherein in a further step the second load contact is connected to the second conductor structure via at least one second wiring element, wherein the second wiring element is arranged at least partially spanning the first wiring element.,

[0016] The advantages and preferred embodiments listed below with regard to the semiconductor device can be transferred analogously to the power converter and the manufacturing method.

[0017] The invention is based on the idea of ​​minimizing parasitic inductance of wiring elements which are used to contact semiconductor elements on a carrier element, e.g. a substrate, by arranging them so as to at least partially span one another. Such wiring elements can be, for example, bonding wires or bonding strips. An at least partially spanning arrangement of wiring elements is to be understood as meaning that at least one wiring element overlaps another wiring element at a specific distance without the wiring elements touching one another.In particular, in a spanning arrangement, a noticeable magnetic interaction occurs between the wiring elements, so that the parasitic inductances of the wiring elements are reduced, which leads to higher switching speeds being enabled, particularly when using semiconductor elements with a wide band gap, e.g., GaN or SiC semiconductor elements. By adjusting the length and / or spacing of wiring elements that are at least partially arranged in a spanning manner, the inductances can be flexibly adjusted, which is advantageous, among other things, for compensating for inductances of chips connected in parallel.

[0018] The semiconductor element can be designed as a horizontally conducting power semiconductor. Such power semiconductors can also be referred to as lateral power semiconductors. Among other things, power semiconductors with a wide band gap, in particular GaN power semiconductors, can be designed as horizontally conducting power semiconductors. Such lateral power semiconductors can have two load contacts, e.g. a drain contact and a source contact, on one surface. If wiring elements for connecting the two load contacts to a carrier element are guided, in particular in parallel, in the same direction, so that an at least partially spanning arrangement of the wiring elements of the two load contacts is present, parasitic inductance of the wiring is reduced. Furthermore, a space-saving circuit layout is made possible.

[0019] A further embodiment provides that the first load contact is connected to the first conductor structure via a plurality of first wiring elements, wherein the second load contact is connected to the second conductor structure via a plurality of second wiring elements, wherein the second wiring elements are arranged to at least partially span the first wiring elements. By using a plurality of wiring elements, the current-carrying capacity is increased and the parasitic inductance is reduced.

[0020] A further embodiment provides that the first wiring elements and the second wiring elements are arranged parallel to each other. Such a parallel arrangement allows the spacing between the wiring elements to be optimized, thus reducing parasitic inductances and saving installation space.

[0021] A further embodiment provides that the first wiring elements are arranged in a perpendicular projection of the second wiring elements onto a surface of the carrier element. Thus, the first wiring elements are arranged parallel and vertically one above the other relative to the surface of the carrier element, resulting in an optimized reduction of the parasitic inductances.

[0022] A further embodiment provides that a first current flow through the first wiring element occurs in the opposite direction to a second current flow through the second wiring element. This has the effect of balancing or compensating the magnetic fields of the wiring elements.

[0023] A further embodiment provides that a distance between a first wiring element and a second wiring element is at least 200 pm, in particular at least 500 pm. Such distances lead to an optimized reduction of the parasitic inductances and offer sufficient robustness against overvoltage peaks. A further embodiment provides that an insulation element is arranged between at least one first wiring element and at least one second wiring element. The insulation element can be, among other things, an electrically insulating film. Such an insulation element defines a minimum distance and offers sufficient robustness against overvoltage peaks.

[0024] A further embodiment provides that the first conductor structure and the second conductor structure each comprise at least two fingers arranged in a comb shape, with the first fingers of the first conductor structure and the second fingers of the second conductor structure being arranged in an interlocking manner. Such an arrangement saves installation space.

[0025] A further embodiment provides that the semiconductor arrangement has at least two semiconductor elements, wherein the semiconductor elements are each connected, in particular in a materially bonded manner, to a first finger of the first conductor structure, wherein the second load contacts of each two semiconductor elements are connected via second wiring elements to a common second finger of the second conductor structure. The materially bonded connection can be produced, among other things, by soldering or sintering. A common total load current of the two semiconductor elements flows via the common second finger, so that the required area of ​​the semiconductor arrangement is reduced.

[0026] In the following, the invention is described and explained in more detail with reference to the exemplary embodiments shown in the figures.

[0027] It shows :

[0028] FIG 1 shows a schematic three-dimensional representation of a first embodiment of a semiconductor arrangement in a side view, FIG 2 shows a schematic three-dimensional representation of a second embodiment of a semiconductor arrangement in a side view,

[0029] FIG 3 is a schematic three-dimensional representation of a third embodiment of a semiconductor device in a plan view,

[0030] FIG 4 is a schematic representation of a fourth embodiment of a semiconductor device in a plan view,

[0031] FIG 5 is a schematic three-dimensional representation of a fifth embodiment of a semiconductor device in a side view,

[0032] FIG 6 is a schematic three-dimensional representation of a sixth embodiment of a semiconductor device in a side view,

[0033] FIG 7 is a schematic three-dimensional representation of a seventh embodiment of a semiconductor device in a side view,

[0034] FIG 8 is a schematic three-dimensional representation of an eighth embodiment of a semiconductor device in a plan view,

[0035] FIG 9 is a schematic three-dimensional representation of the eighth embodiment of a semiconductor device in a side view and

[0036] FIG 10 is a schematic diagram of a power converter.

[0037] The exemplary embodiments explained below are preferred embodiments of the invention. In the exemplary embodiments, the described components of the embodiments each represent individual features of the invention that are to be considered independently of one another. These also further develop the invention independently of one another and are thus to be regarded as components of the invention, either individually or in a combination other than that shown. Furthermore, the described embodiments can also be supplemented by further features of the invention already described.

[0038] The same reference symbols have the same meaning in the different figures.

[0039] FIG 1 shows a schematic three-dimensional representation of a first embodiment of a semiconductor arrangement 2 in a side view, which comprises a semiconductor element 4 which is contact-connected to a carrier element 6. By way of example, the semiconductor element 4 is designed as a horizontally conducting power semiconductor with a wide band gap, in particular as a GaN-HEMT (gallium nitride high electron-mobility transistor). A horizontally conducting power semiconductor can also be referred to as a lateral power semiconductor. The carrier element 6 is designed, by way of example, as a DGB (direct copper bonded) substrate. The horizontally conducting power semiconductor is bonded to the DGB substrate, e.g. by soldering or sintering, and comprises a first load contact 8 and a second load contact 10 on a side facing away from the DGB substrate.The first load contact 8 is designed as a source contact S and the second load contact 10 is designed as a drain contact D of the semiconductor element 4 designed as a GaN-HEMT.

[0040] The carrier element 6 has a first conductor structure 12 and a second conductor structure 14 which is arranged so as to be electrically insulated from the first conductor structure 12, the second conductor structure 14 being arranged between the semiconductor element 4 and the first conductor structure 12. The conductor structures 12, 14 are designed, for example, as a copper cladding of a DGB substrate. The first load contact 8 or the source contact S is connected to the first conductor structure 12 via a plurality of first wiring elements 16, while the second load contact 10 is connected to the second conductor structure 14 via a plurality of second wiring elements 18. The wiring elements 16, 18 can be designed, among other things, as bonding wires or bonding strips made of aluminum, gold, copper or silver. The wiring elements 16, 18 are connected in a material-to-material manner, for example by means of wire bonding.The first wiring elements 16 and the second wiring elements 18 are each arranged to run parallel to one another. Furthermore, the second wiring elements 18 are arranged such that they span the first wiring elements 16. A distance d between the first wiring elements 16 and the second wiring elements 18 is at least 200 pm, in particular at least 500 pm. The air gap is smaller than the creepage distance on the chip surface. The wiring elements 16, 18 can be connected in a straight line or with a small bonding angle. The parasitic inductance is reduced by the overlap of the first wiring elements 16 with the second wiring elements 18. In addition, a first current II flows through the first wiring element 16 in the opposite direction to a second current flow I2 through the second wiring element 18, so that the magnetic fields balance each other out or compensate each other.

[0041] FIG. 2 shows a schematic three-dimensional representation of a second embodiment of a semiconductor arrangement 2 in a side view, wherein an insulating element 20 is arranged between the first wiring elements 16 and the second wiring elements 18. The insulating element 20 can be, among other things, an electrically insulating film. The further embodiment of the semiconductor arrangement 2 in FIG. 2 corresponds to the embodiment in FIG. 1.

[0042] FIG. 3 shows a schematic three-dimensional representation of a third embodiment of a semiconductor arrangement 2 in a plan view. The first wiring elements 16 are arranged in a perpendicular projection of the second wiring elements 18 onto a surface 22 of the carrier element 6. Alternatively, the first wiring elements 16 and the second wiring elements 18 can be arranged alternately, in particular equidistantly. The further embodiment of the semiconductor arrangement 2 in FIG. 3 corresponds to the embodiment in FIG. 1.

[0043] FIG 4 shows a schematic representation of a fourth embodiment of a semiconductor arrangement 2 in a plan view, wherein the first conductor structure 12 and the second conductor structure 14 comprise fingers 24, 26 which are arranged in a comb shape. The first finger 24 of the first conductor structure 12 and second fingers 26 of the second conductor structure 14 are arranged so as to engage one another. Furthermore, the semiconductor arrangement 2 comprises at least two semiconductor elements 4 which are designed as horizontally conducting power semiconductors with a wide band gap, in particular as GaN-HEMT (gallium nitride high electron mobility transistor) and are each materially connected to one of the first fingers 24. The second load contacts 10 of each two semiconductor elements 4 are connected via second wiring elements 18 to a common second finger 26 of the second conductor structure 14.A common load current IL of the two semiconductor elements 4 flows via the common second finger 26, so that the required area of ​​the semiconductor arrangement 2 is reduced. The further design of the semiconductor arrangement 2 in FIG. 4 corresponds to the design in FIG. 3.

[0044] FIG. 5 shows a schematic three-dimensional representation of a fifth embodiment of a semiconductor arrangement in a side view. The second wiring elements 18 partially span the first wiring elements 16, while the first wiring elements 16 partially project beyond the second wiring elements 18, so that the wiring elements 16, 18 each cross twice. The further embodiment of the semiconductor arrangement 2 in FIG. 5 corresponds to the embodiment in FIG. 1.

[0045] FIG 6 shows a schematic three-dimensional representation of a sixth embodiment of a semiconductor device 2 in a side view, wherein the semiconductor element 4 is designed as a vertical power semiconductor, in particular as a vertical SiC (silicon carbide) power transistor or as

[0046] IGBT (Insulated Gate Bipolar Transistor). The carrier element 6, which is designed as a DGB (direct copper bonded) substrate, for example, has a first conductor structure 12 and a second conductor structure 14 arranged so as to be electrically insulated from the first conductor structure 12. A first load contact 8 of the semiconductor element 4 is connected to the first conductor structure 12 in a materially bonded manner, e.g. by soldering or sintering. Furthermore, the semiconductor element 4 has, on a side facing away from the carrier element 6, a second load contact 10 which is connected to the second conductor structure 14 via at least one second wiring element 18. A first wiring element 16 is connected to the first conductor structure 12 and forms a conductor loop which is short-circuited via the first conductor structure 12 and is therefore currentless.The second wiring element 18 spans the conductor loop of the first wiring element 16, which is at least partially adapted to the shape of the second wiring element 18. By adapting the conductor loop, the inductance of the second wiring element 18 can be adjusted, which can be used, among other things, to compensate for the inductance of chips connected in parallel. The further embodiment of the semiconductor arrangement 2 in FIG. 6 corresponds to the embodiment in FIG. 1.

[0047] FIG 7 shows a schematic three-dimensional representation of a seventh embodiment of a semiconductor arrangement in a side view, wherein the semiconductor element 4 is designed as a vertical power semiconductor. The carrier element 6 comprises a first substrate 28 with a first conductor structure 12, a second substrate 30 with a second conductor structure 14 and a third substrate 32 with a third conductor structure 34. A first load contact 8 of the semiconductor element 4 is materially connected, e.g. by soldering or sintering, to the third conductor structure 34 of the third substrate 32. Furthermore, the semiconductor element 4 has, on a side facing away from the carrier element 6, a second load contact 10 which is connected to the second conductor structure 14 of the second substrate 30 via second wiring elements 18.The first load contact 8 of the semiconductor element 4 is connected to the second conductor structure 14 of the second substrate 30 via first wiring elements 16, which are connected to the third conductor structure 34 of the third substrate 32. The wiring elements 16, 18 are arranged alternately. Furthermore, the second wiring elements 18 partially span the first wiring elements 16, while the first wiring elements 16 partially project beyond the second wiring elements 18, so that the wiring elements 16, 18 each cross once while maintaining a certain distance. The further embodiment of the semiconductor arrangement 2 in FIG. 5 corresponds to the embodiment in FIG. 6.

[0048] FIG 8 shows a schematic three-dimensional representation of an eighth embodiment of a semiconductor arrangement 2 in a plan view, which comprises a first semiconductor element 36 and a second semiconductor element 38. The semiconductor elements 36, 38, which are designed as vertical power semiconductors, are arranged on a common carrier element 6, the first semiconductor element 36 having a first load contact 8 on a side facing away from the carrier element 6 and the second semiconductor element 38 having a second load contact 10 on a side facing away from the carrier element 6. The carrier element 6, which is designed, for example, as a DGB (direct copper bonded) substrate, has a first conductor structure 12 and a second conductor structure 14 arranged so as to be electrically insulated from the first conductor structure 12. The first conductor structure 12 is arranged between the semiconductor elements 36, 38 and the second conductor structure 14.The first load contact 8 is connected to the first conductor structure 12 via first wiring elements 16, wherein the second load contact 10 is connected to the second conductor structure 14 via second wiring elements 18. The second wiring elements 18, which are arranged essentially in parallel, partially span the first wiring elements 16, which are arranged essentially in parallel. The first conductor structure 12 and the second conductor structure 14 can, as shown in FIG. 7, be arranged on different substrates 28, 30. The further embodiment of the semiconductor arrangement 2 in FIG. 5 corresponds to the embodiment in FIG. 1.

[0049] FIG 9 shows a schematic three-dimensional representation of the eighth embodiment of a semiconductor device 2, which is shown in FIG 8, in a side view.

[0050] FIG 10 shows a schematic representation of a power converter 40 with a semiconductor device 2. The power converter 40 can comprise more than one semiconductor device 2.

[0051] In summary, the invention relates to a semiconductor arrangement 2 with a semiconductor element 4 which is arranged on a carrier element 6, wherein the semiconductor element 4 has a first load contact 8 and a second load contact 10 on a side facing away from the carrier element 6, wherein the carrier element 6 comprises a first conductor structure 12 and a second conductor structure 14 arranged electrically insulated from the first conductor structure 12.

[0052] In order to provide improved wiring compared to the prior art, it is proposed that the second conductor structure 14 is arranged between the semiconductor element 4 and the first conductor structure 12, wherein the first load contact 8 is arranged between the second load contact 10 and the second conductor structure 14, wherein the first load contact 8 is connected to the first conductor structure 12 via at least one first wiring element 16, wherein the second load contact 10 is connected to the second conductor structure 14 via at least one second wiring element 18, wherein the second wiring element 18 is arranged at least partially spanning the first wiring element 16.

Claims

Patent claims 1. A semiconductor arrangement (2) comprising a semiconductor element (4) arranged on a carrier element (6), wherein the semiconductor element (4) is designed as a horizontally conducting power semiconductor, wherein the semiconductor element (4) has a first load contact (8) and a second load contact (10) on a side facing away from the carrier element (6), wherein the carrier element (6) comprises a first conductor structure (12) and a second conductor structure (14) arranged electrically insulated from the first conductor structure (12), wherein the second conductor structure (14) is arranged between the semiconductor element (4) and the first conductor structure (12), wherein the first load contact (8) is arranged between the second load contact (10) and the second conductor structure (14), wherein the first load contact (8) is connected to the first conductor structure (12) via at least one first wiring element (16),wherein the second load contact (10) is connected to the second conductor structure (14) via at least one second wiring element (18), wherein the second wiring element (18) is arranged to at least partially span the first wiring element (16).

2. Semiconductor arrangement (2) according to claim 1, wherein the first load contact (8) is connected to the first conductor structure (12) via a plurality of first wiring elements (16), wherein the second load contact (10) is connected to the second conductor structure (14) via a plurality of second wiring elements (18), wherein the second wiring elements (18) are arranged to at least partially span the first wiring elements (16).

3. Semiconductor arrangement (2) according to claim 2, wherein the first wiring elements (16) and the second wiring elements (18) are each arranged parallel to one another.

4. Semiconductor arrangement (2) according to one of claims 2 or 3, wherein the first wiring elements (16) are arranged in a perpendicular projection of the second wiring elements (18) onto a surface (22) of the carrier element (6).

5. Semiconductor arrangement (2) according to one of claims 2 to 4, wherein a first current flow (II) through the first wiring element (16) is opposite to a second current flow (II) through the second wiring element (18).

6. Semiconductor arrangement (2) according to one of the preceding claims, wherein a distance (d) between a first wiring element (16) and a second wiring element (18) is at least 200 pm, in particular at least 500 pm.

7. Semiconductor arrangement (2) according to one of the preceding claims, wherein an insulation element (20) is arranged between at least one first wiring element (16) and at least one second wiring element (18).

8. Semiconductor arrangement (2) according to one of the preceding claims, wherein the first conductor structure (12) and the second conductor structure (14) each comprise at least two fingers (24, 26) which are arranged in a comb shape, wherein the first finger (24) of the first conductor structure (12) and the second finger (26) of the second conductor structure (14) are arranged in an interlocking manner.

9. Semiconductor arrangement (2) according to claim 8, comprising at least two semiconductor elements (4), wherein the semiconductor elements (4) are each connected, in particular materially, to a first finger (24) of the first conductor structure (12), wherein the second load contacts (10) of each two semiconductor elements (4) are connected via second wiring elements (18) to a common second finger (26) of the second conductor structure (14).

10. Semiconductor arrangement (2) with a semiconductor element (4) and a carrier element (6), wherein the semiconductor element (4) is designed as a vertical power semiconductor, wherein a first load contact (8) of the semiconductor element (4) is connected, in particular materially, to a first conductor structure (12) of the carrier element (6), wherein the semiconductor element (4) has a second load contact (10) on a side facing away from the carrier element (6), wherein the carrier element (6) comprises a second conductor structure (14) arranged electrically insulated from the first conductor structure (12), wherein the second load contact (10) is connected to the second conductor structure (14) via at least one second wiring element (18), wherein a first wiring element (16) is connected to the first conductor structure (12), wherein the second wiring element (18) is arranged at least partially spanning the first wiring element (16).

11. Semiconductor arrangement (2) according to claim 10, wherein the second load contact (10) is connected to the second conductor structure (12) via a plurality of second wiring elements (18), wherein a plurality of first wiring elements (16) are contacted on the first conductor structure (12), wherein the second wiring elements (18) are arranged to at least partially span the first wiring elements (16).

12. Semiconductor device (2) according to one of claims 10 or 11, wherein a second wiring element (18) crosses a first wiring element (16).

13. A semiconductor arrangement (2) comprising a first semiconductor element (36) and a second semiconductor element (38), which are arranged on a carrier element (6), wherein the semiconductor elements (36, 38) are designed as vertical power semiconductors, wherein the first semiconductor element (36) has a first load contact (8) on a side facing away from the carrier element (6) and the second semiconductor element (38) has a second load contact (10) on a side facing away from the carrier element (6), wherein the carrier element (6) comprises a first conductor structure (12) and a second conductor structure (14) arranged electrically insulated from the first conductor structure (12), wherein the first conductor structure (12) is arranged between the semiconductor elements (36, 38) and the second conductor structure (14), wherein the first load contact (8) is connected to the first conductor structure (12) via at least one first wiring element (16),wherein the second load contact (10) is connected to the second conductor structure (14) via at least one second wiring element (18), wherein the second wiring element (18) is arranged to at least partially span the first wiring element (16).

14. Semiconductor device (2) according to claim 13 wherein the first load contact (8) is connected to the first conductor structure (12) via a plurality of first wiring elements (16), wherein the second load contact (10) is connected to the second conductor structure (14) via a plurality of second wiring elements (18), wherein the second wiring elements (18) are arranged to at least partially span the first wiring elements (16).

15. Power converter (40) with at least one semiconductor device (2) according to one of the preceding claims.

16. A method for producing a semiconductor arrangement (2) with a semiconductor element (4) which is arranged on a carrier element (6), wherein the semiconductor element (4) is designed as a horizontally conducting power semiconductor, wherein the semiconductor element (4) has a first load contact (8) and a second load contact (10) on a side facing away from the carrier element (6), wherein the carrier element (6) comprises a first conductor structure (12) and a second conductor structure (14) arranged electrically insulated from the first conductor structure (12), wherein the second conductor structure (14) is arranged between the semiconductor element (4) and the first conductor structure (12), wherein the first load contact (8) is arranged between the second load contact (10) and the second conductor structure (14), wherein the first load contact (8) is connected to the first conductor structure (12) via at least one first wiring element (16),wherein in a further step the second load contact (10) is connected to the second conductor structure (14) via at least one second wiring element (18), wherein the second wiring element (18) is arranged to at least partially span the first wiring element (16).

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