Semiconductor laser

Abstract

The present invention comprises: a second groove (122a) which is formed on a cladding layer (102) on a first silicon layer (121a) so as to extend along a Si core (103) and reaches the first silicon layer (121a); and a third groove (122b) which is formed on the cladding layer (102) on a second silicon layer (121b) so as to extend along the Si core (103) and reaches the second silicon layer (121b). A p-type semiconductor layer (108) is formed by means of epitaxial growth from the upper surface of the first silicon layer (121a) on the bottom surface of the second groove (122a), and an n-type semiconductor layer (108) is formed by means of epitaxial growth from the upper surface of the second silicon layer (121b) on the bottom surface of the third groove (122b).

Description

semiconductor laser

[0001] The present invention relates to a semiconductor laser.

[0002] To achieve compact, integrated, low-power, and low-cost optical transceivers, technology that integrates passive elements such as Si waveguides with active elements such as lasers, photodetectors, and modulators on Si substrates, which can be fabricated at low cost and with large diameters, has been attracting attention. Until now, mature Si microfabrication technology has already achieved monolithic integration of small, low-loss Si optical waveguide elements, photodetectors, and modulators on large-diameter Si substrates. Regarding laser integration on Si substrates, it has been difficult to fabricate lasers using indirect transition semiconductors such as Si and Ge, which have traditionally been used on silicon platforms. This necessitated the integration of heterogeneous direct transition semiconductors, such as III-V group compound semiconductors. However, thin-film laser integration has been achieved, as shown in Non-Patent Document 1.

[0003] Incidentally, laser integration with the above-described configuration has been achieved using so-called heterogeneous integration technologies, such as direct bonding and transfer printing. Unlike monolithic integration, these manufacturing technologies require the use of expensive, small-sized III-V compound semiconductor substrates. These create bottlenecks in material costs and throughput. Therefore, there is a demand for monolithic integration of high-performance thin-film semiconductor lasers with the structure proposed in Non-Patent Document 1.

[0004] However, because Si and III-V compound semiconductors have different lattice constants and thermal expansion coefficients, it is difficult to monolithically integrate high-quality III-V compound semiconductors on Si. The most common solution to this problem is to insert a thick buffer layer of several micrometers on the Si. However, the presence of this buffer layer has the fatal drawback of making it difficult to optically couple the active layer to the Si waveguide. For this reason, there is a demand for integrating high-quality III-V compound semiconductors on a thin buffer layer or without a buffer layer.

[0005] A technique called aspect ratio trapping (ART) is known as a method for achieving this (Non-Patent Document 2). This technique uses Si layers 401 and 401a, first selective growth masks 402 and 402a, and second selective growth masks 403 and 403a, as shown in Figure 18. Grooves 404 and 404a are formed by the first selective growth masks 402 and 402a and the second selective growth masks 403 and 403a.

[0006] The groove depth h of the grooves 404, 404a is made larger than the groove width w of the grooves 404, 404a, and III-V compound semiconductor layers 405, 405a are epitaxially grown on the Si layers 401, 401a. During this growth, the growth of defects 406 generated at the interfaces between the Si layers 401, 401a and the III-V compound semiconductor layers 405, 405a is stopped (terminated) by the sidewalls of the grooves 404, 404a, and high-quality III-V compound semiconductor crystals are grown above the defect regions. Using this crystal growth technique, it is possible to grow laser-quality III-V compound semiconductor layers without providing a buffer layer, and this has already been demonstrated in an injection laser (Prior Art Document 3).

[0007] T. Aihara et al., "Membrane III-V / Si DFB Laser Using Uniform Grating and Width-Modulated Si Waveguide", Journal of Lightwave Technology, vol. 38, no. 11, pp. 2961-2967, 2020.JZ Li et al., "Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping", Applied Physics Letters, vol. 91, no. 2, 021114, 2007.Z. Wang et al., "Room-temperature InP distributed feedback laser array directly grown on silicon", Nature Photonics volume, vol. 9, pp. 837-842, 2015.

[0008] However, the above-mentioned technology has not yet demonstrated a current injection type laser, and research is underway to realize this. ART technology is essentially a selective growth technology from a minute Si seed crystal, so it is difficult to form a III-V compound semiconductor layer having the minimum area (typically 5 μm × several tens of μm or more) required to form a current injection type laser from the standpoint of electrode formation, active layer volume, etc. This poses a problem in that it is difficult to integrate a current injection type semiconductor laser using a III-V compound semiconductor layer with a Si waveguide.

[0009] The present invention has been made to solve the above problems, and has as its object to easily integrate a current injection type semiconductor laser using a III-V compound semiconductor layer with a Si waveguide.

[0010] The semiconductor laser according to the present invention includes an optical waveguide formed on a substrate and comprising a Si core and a cladding layer in which the Si core is embedded; first and second silicon layers extending along the Si core and embedded in the cladding layer on both sides of the Si core; a first groove formed in the cladding layer above the Si core and extending along the Si core to reach the Si core; a second groove formed in the cladding layer above the first silicon layer and extending along the Si core to reach the first silicon layer; a third groove formed in the cladding layer above the second silicon layer and extending along the Si core to reach the second silicon layer; a lower semiconductor layer made of a compound semiconductor and extending along the Si core, formed on the cladding layer by epitaxial growth from the top surface of the Si core at the bottom of the first groove to fill the first groove; and a second semiconductor layer on the lower semiconductor layer extending along the Si core in a state capable of optically coupling with the Si core. an active layer made of a compound semiconductor formed on the cladding layer; an upper semiconductor layer made of the compound semiconductor and formed on the active layer; a p-type semiconductor layer made of the compound semiconductor and formed on the cladding layer by epitaxial growth from the top surface of the Si core at the bottom of the second groove, filling the second groove and being formed on the cladding layer in contact with one side surface of the active layer; an n-type semiconductor layer made of the compound semiconductor and formed on the cladding layer by epitaxial growth from the top surface of the Si core at the bottom of the third groove, filling the third groove and being formed on the cladding layer in contact with the other side surface of the active layer; an n-type electrode connected to the n-type semiconductor layer; a p-type electrode connected to the p-type semiconductor layer; and a resonator structure for confining light in the active layer, wherein the p-type semiconductor layer and the n-type semiconductor layer are formed to sandwich the lower semiconductor layer, the active layer, and the upper semiconductor layer in a planar view, and the depth of each of the first groove, the second groove, and the third groove is greater than the groove width.

[0011] The semiconductor laser according to the present invention comprises an optical waveguide comprising a Si core formed on a substrate and a cladding layer in which the Si core is embedded; silicon layers orthogonal to the Si core in a direction parallel to the plane of the substrate at each of a plurality of locations arranged in the waveguiding direction of the Si core; first grooves formed in the cladding layer on each silicon layer and extending along the silicon layer to reach the Si core and the silicon layer; an insulating layer formed on the cladding layer; second grooves arranged on each silicon layer along the silicon layer and formed in the insulating layer to reach the cladding layer; lower semiconductor layers made of a compound semiconductor formed on the cladding layer in each second groove by epitaxial growth from the top surface of the Si core at the bottom of the first groove, filling a portion of the first groove; and a lower semiconductor layer formed on the cladding layer in each second groove in a state capable of being optically coupled to the Si core. an active layer made of a compound semiconductor formed on the cladding layer; in each of the second grooves, an upper semiconductor layer made of a compound semiconductor formed on the active layer; in each of the second grooves, a p-type semiconductor layer and an n-type semiconductor layer made of compound semiconductor formed on the cladding layer and in contact with a side surface of the active layer by epitaxial growth from the upper surface of the silicon layer at the bottom of the first groove, filling a part of the first groove, and being formed on the cladding layer; a p-type electrode connected to the p-type semiconductor layer, an n-type electrode connected to the n-type semiconductor layer, and a resonator structure that confines light in the active layer arranged in the waveguiding direction, the resonator structure comprising a diffraction grating made of periodically arranged partitions by an insulating layer between adjacent second grooves, the p-type semiconductor layer and the n-type semiconductor layer being formed so as to sandwich the lower semiconductor layer, the active layer, and the upper semiconductor layer in a planar view;

[0012] The semiconductor laser according to the present invention includes a first insulating layer formed on a substrate, a second insulating layer formed on the first insulating layer, first grooves arranged in a first direction at a plurality of locations on the second insulating layer and extending in a second direction perpendicular to the first direction to reach the first insulating layer formed in the second insulating layer, second grooves formed in the second insulating layer contiguous with each of the first grooves in the second direction and reaching the first insulating layer with a width that narrows with increasing distance from the first groove, third grooves formed in the second insulating layer contiguous with each of the second grooves in the second direction to reach the first insulating layer, silicon layers formed to fill each of the third grooves, a third insulating layer formed on the second insulating layer covering each of the first grooves, each of the second grooves, and each of the third grooves, and formed by epitaxial growth from the side surfaces of each silicon layer on the side of the first groove. the active layer is made of a compound semiconductor and formed on the first insulating layer of each of the first grooves by epitaxial growth from the side surface of the first semiconductor layer facing the first groove; the active layer is made of a compound semiconductor and formed on the first insulating layer of each of the first grooves by epitaxial growth from the side surface of the first semiconductor layer facing the first groove; the active layer is made of a compound semiconductor and formed on the first insulating layer of each of the first grooves by epitaxial growth from the side surface of the active layer facing the first groove; the active layer is made of a compound semiconductor and formed on the first insulating layer of each of the first grooves by epitaxial growth ... compound semiconductor and formed on the compound semiconductor and formed on the compound

[0013] As described above, according to the present invention, the use of the second groove and the third groove makes it possible to more easily increase the areas of the p-type semiconductor layer and the n-type semiconductor layer on which the electrodes are formed, and thus makes it possible to easily integrate a current injection type semiconductor laser using III-V compound semiconductor layers with a Si waveguide.

[0014] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor laser according to a first embodiment of the present invention. FIG. 2A is a cross-sectional view showing the state of the semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the first embodiment of the present invention. FIG. 2B is a cross-sectional view showing the state of the semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the first embodiment of the present invention. FIG. 2C is a cross-sectional view showing the state of the semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the first embodiment of the present invention. FIG. 2D is a cross-sectional view showing the state of the semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the first embodiment of the present invention. FIG. 2E is a cross-sectional view showing the state of the semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the first embodiment of the present invention. FIG. 2F is a cross-sectional view showing the state of the semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the first embodiment of the present invention. FIG. 3 is a characteristic diagram showing the optical confinement factor dependence of each layer (Si core 103, active layer 106, active layer structure 123) when the distance (adjacent distance L) between active layer 106 and active layer structure 123 adjacent to active layer 106 is changed from 0.1 to 1 μm when the width of Si core 103 is 440 nm. FIG. 4 is a characteristic diagram showing the dependence of the optical confinement factor on each layer (Si core 103, active layer 106, active layer structure 123) when the distance (adjacent distance L) between the active layer 106 and the active layer structure 123 adjacent to the active layer 106 is changed from 0.1 to 1 μm when the width of the Si core 103 is 700 nm. FIG. 5 is a cross-sectional diagram showing the configuration of another semiconductor laser according to the first embodiment of the present invention. FIG. 6 is a characteristic diagram showing the height difference (Δz) between the active layer 106 and the active layer structure 123 and the dependence of the optical confinement factor of the active layer structure 123 on Δz when the width of the Si core 103 is 440 nm and the distance between the active layer 106 and the active layer structure 123 adjacent to the active layer 106 in the horizontal direction of the substrate is 400 nm. FIG. 7 is a cross-sectional diagram showing the configuration of a semiconductor laser according to a second embodiment of the present invention. FIG. 8 is a cross-sectional diagram showing the configuration of a semiconductor laser according to the second embodiment of the present invention. FIG. 9 is a plan view showing the configuration of a semiconductor laser according to the second embodiment of the present invention.FIG. 10A is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the second embodiment of the present invention. FIG. 10B is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the second embodiment of the present invention. FIG. 10C is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the second embodiment of the present invention. FIG. 10D is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the second embodiment of the present invention. FIG. 10E is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the second embodiment of the present invention. FIG. 10F is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the second embodiment of the present invention. FIG. 11 is a cross-sectional view showing a configuration of a semiconductor laser according to a third embodiment of the present invention. FIG. 12 is a cross-sectional view showing a configuration of a semiconductor laser according to the third embodiment of the present invention. FIG. 13 is a plan view showing a configuration of a semiconductor laser according to the third embodiment of the present invention. FIG. 14A is a plan view (a) and a cross-sectional view (b) showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to the third embodiment of the present invention. FIG. 14B is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to embodiment 3 of the present invention. FIG. 14C is a plan view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to embodiment 3 of the present invention. FIG. 14D is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to embodiment 3 of the present invention. FIG. 14E is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to embodiment 3 of the present invention. FIG. 14F is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing a semiconductor laser according to embodiment 3 of the present invention. FIG. 15 is a cross-sectional view showing a configuration of another semiconductor laser according to embodiment 3 of the present invention. FIG. 16 is a cross-sectional view showing a configuration of another semiconductor laser according to embodiment 3 of the present invention.FIG. 17A is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing another semiconductor laser according to embodiment 3 of the present invention. FIG. 17B is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing another semiconductor laser according to embodiment 3 of the present invention. FIG. 17C is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing another semiconductor laser according to embodiment 3 of the present invention. FIG. 17D is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing another semiconductor laser according to embodiment 3 of the present invention. FIG. 17E is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing another semiconductor laser according to embodiment 3 of the present invention. FIG. 17F is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing another semiconductor laser according to embodiment 3 of the present invention. FIG. 17G is a cross-sectional view showing a state of a semiconductor laser in an intermediate step for explaining a method for manufacturing another semiconductor laser according to embodiment 3 of the present invention. FIG. 18 is an explanatory diagram for explaining aspect ratio trapping.

[0015] A semiconductor laser according to an embodiment of the present invention will be described below.

[0016] First Embodiment First, a semiconductor laser according to a first embodiment of the present invention will be described with reference to Fig. 1. This semiconductor laser includes a cladding layer 102 formed on a substrate 101 and a Si core 103 embedded in the cladding layer 102. The cladding layer 102 is made of, for example, silicon oxide (SiO x 1, and the Si core 103 and the cladding layer 102 form an optical waveguide.

[0017] This semiconductor laser also includes a first silicon layer 121a and a second silicon layer 121b extending along the Si core 103 and embedded in the cladding layer 102 on both sides of the Si core 103. The first silicon layer 121a and the second silicon layer 121b are formed in a core shape that is rectangular in cross section. The first silicon layer 121a and the second silicon layer 121b can each be formed in multiple locations. The first silicon layer 121a and the second silicon layer 121b are disposed at the same height as the Si core 103 when viewed from the substrate 101.

[0018] This semiconductor laser also includes a first groove 104 formed in the cladding layer 102. The first groove 104 is disposed on the Si core 103 and extends along the Si core 103. The first groove 104 is formed to reach the Si core 103 in the thickness direction. The bottom surface of the first groove 104 becomes the upper surface of the Si core 103. The first groove 104 is formed so that the groove depth is greater than the groove width.

[0019] This semiconductor laser also includes a second groove 122a formed in the cladding layer 102 on the first silicon layer 121a, extending along the Si core 103 and reaching the first silicon layer 121a. The bottom surface of the second groove 122a is the upper surface of the first silicon layer 121a. The second groove 122a is formed so that its depth is greater than its width.

[0020] Similarly, a third groove 122b is formed in the cladding layer 102 on the second silicon layer 121b, extending along the Si core 103 and reaching the second silicon layer 121b. The bottom surface of the third groove 122b is the upper surface of the first silicon layer 121a. The third groove 122b is formed so that the groove depth is greater than the groove width.

[0021] This semiconductor laser also includes, on the cladding layer 102, a lower semiconductor layer 105, an active layer 106, and an upper semiconductor layer 107, all made of III-V compound semiconductors.

[0022] The lower semiconductor layer 105 is formed on the cladding layer 102 by epitaxial growth from the upper surface of the Si core 103 at the bottom surface of the first groove 104, filling the first groove 104. The lower semiconductor layer 105 is formed by epitaxial growth in a state where there are no defects above the cladding layer 102, by stopping the growth of defects generated from the upper surface of the Si core 103 at the bottom surface of the first groove 104 at the side surface of the first groove 104 using aspect ratio trapping (ART) using the first groove 104. The lower semiconductor layer 105 is also formed extending along the Si core 103. The lower semiconductor layer 105 can be composed of, for example, undoped InP. The lower semiconductor layer 105 can be formed directly on the Si core 103.

[0023] The active layer 106 is formed on the lower semiconductor layer 105 in a state capable of optically coupling with the Si core 103. The active layer 106 is formed to extend along the Si core 103 together with the lower semiconductor layer 105. The active layer 106 may have, for example, a multiple quantum well structure in which well layers and barrier layers made of InGaAsP are alternately stacked. Alternatively, the active layer 106 may have a multiple quantum well structure in which well layers made of InGaAs and barrier layers made of InP are alternately stacked.

[0024] The upper semiconductor layer 107 is formed on the active layer 106. The upper semiconductor layer 107 is formed to extend along the Si core 103 together with the active layer 106. The upper semiconductor layer 107 can be made of, for example, undoped InP (i-InP). The lower semiconductor layer 105 and the upper semiconductor layer 107 serve as cladding layers for confining light in the active layer 106.

[0025] The Si core 103 and the active layer 106 can be roughly matched in effective refractive index, enabling highly efficient optical coupling between the Si core 103 and the active layer 106. Furthermore, by forming a double heterostructure with the lower semiconductor layer 105, the upper semiconductor layer 107, and the active layer 106, carriers can be more efficiently injected into the active layer 106.

[0026] Moreover, a diffraction grating 112 is formed above the active layer 106 as a resonator structure that confines light to the active layer 106. The diffraction grating 112 is composed of, for example, a grating pattern formed on the top surface of the upper semiconductor layer 107.

[0027] This semiconductor laser also includes a p-type semiconductor layer 108 formed on the cladding layer 102 and in contact with one surface of the active layer 106, and an n-type semiconductor layer 109 formed in contact with the other surface.

[0028] The p-type semiconductor layer 108 is made of a compound semiconductor and is formed on the cladding layer 102 by epitaxial growth from the upper surface of the first silicon layer 121a at the bottom of the second groove 122a, filling the second groove 122a.

[0029] The n-type semiconductor layer 109 is made of a compound semiconductor and is formed on the cladding layer 102 by epitaxial growth from the upper surface of the second silicon layer 121b at the bottom of the third groove 122b, filling the third groove 122b.

[0030] The p-type semiconductor layer 108 and the n-type semiconductor layer 109 are formed to sandwich the lower semiconductor layer 105, the active layer 106, and the upper semiconductor layer 107 in a plan view. With this configuration, a current is injected into the active layer 106 in a direction parallel to the plane of the substrate 101. The p-type semiconductor layer 108 has, for example, a Zn concentration of 1×10 18 cm -3 The n-type semiconductor layer 109 can be made of p-type InP doped to a degree of 1×10 18 cm -3 It may be constructed from lightly doped n-type InP.

[0031] The semiconductor laser also includes a p-type electrode 110 electrically connected to the p-type semiconductor layer 108, and an n-type electrode 111 electrically connected to the n-type semiconductor layer 109. In this example, the semiconductor laser also includes a first contact layer 114 formed on the p-type semiconductor layer 108, and a second contact layer 115 formed on the n-type semiconductor layer 109.

[0032] The p-type electrode 110 is formed on the first contact layer 114 in ohmic contact, and the n-type electrode 111 is formed on the second contact layer 115 in ohmic contact. The first contact layer 114 can be made of p-type InGaAs. The second contact layer 115 can be made of n-type InGaAs.

[0033] An insulating layer 113 is formed on and in contact with the upper semiconductor layer 107 , the p-type semiconductor layer 108 , and the n-type semiconductor layer 109 between the first contact layer 114 and the second contact layer 115 .

[0034] As described above, the lower semiconductor layer 105 is formed by epitaxial growth from the upper surface of the Si core 103 at the bottom surface of the first groove 104, using the Si core 103 as a seed crystal, thereby filling the first groove 104. This allows defects (dislocations) that occur at the interface between the lower semiconductor layer 105 and the Si core 103 to be terminated on the inner wall of the first groove 104, making the lower semiconductor layer 105 above the cladding layer 102 a high-quality crystal. For example, if the width w of the first groove 104 is set to 100 (nm) and the height h of the first groove 104 is set to 150 (nm), a sufficient ART effect can be expected, making it possible to grow a high-quality III-V compound semiconductor on the cladding layer 102. This means that a high-quality active layer 106 can be formed at a distance that allows optical coupling with the Si core 103.

[0035] The same applies to the p-type semiconductor layer 108 and the n-type semiconductor layer 109. Furthermore, the p-type semiconductor layer 108 is formed on the cladding layer 102 by epitaxial growth from the upper surface of the first silicon layer 121a at the bottom surface of the second groove 122a, thereby filling the second groove 122a, and thus it is easy to increase the width in the direction away from the active layer 106 in plan view. Similarly, the n-type semiconductor layer 108 is formed on the cladding layer 102 by epitaxial growth from the upper surface of the second silicon layer 121b at the bottom surface of the third groove 122b, thereby filling the third groove 122b, and thus it is easy to increase the width in the direction away from the active layer 106 in plan view.

[0036] For example, pairs of first silicon layers 121a and second grooves 122a are provided at multiple locations in a direction away from the active layer 106 (first groove 104). In this state, layers of III-V compound semiconductor epitaxially grown from the first silicon layers 121a at multiple locations are combined in a direction parallel to the plane of the substrate 101, thereby forming a p-type semiconductor layer 108 with a larger area. The same applies to the n-type semiconductor layer 109. For example, the width of the p-type semiconductor layer 108 and the n-type semiconductor layer 109 in a plan view in a direction away from the active layer 106 can be set to 5 μm or more, which is necessary for electrode formation.

[0037] As described above, when epitaxially grown III-V compound semiconductor layers are combined in a direction parallel to the plane of the substrate 101, defects such as twin planes and anti-phase boundaries (APBs) are expected to occur at the combined interface. However, it is believed that degradation of optical properties can be prevented by forming the active layer 106 at a location sufficiently distant from the combined interface so that such defects do not occur in the active layer 106 region.

[0038] It should be noted that when the active layer 106 has a multiple quantum well structure, unnecessary active layer structures 123 that are not used as the active layer 106 exist (are formed) in the left and right regions sandwiching the active layer 106 in the direction parallel to the plane of the substrate 101.

[0039] Next, a method for manufacturing the semiconductor laser according to the first embodiment of the present invention will be described with reference to FIGS. 2A to 2F.

[0040] 2A, a Si core 103, a first silicon layer 121a, and a second silicon layer 121b are formed on a substrate 101, and a clad layer 102 is formed to embed these layers. The Si core 103 and the clad layer 102 form an optical waveguide.

[0041] 2B , a first groove 104, a second groove 122a, and a third groove 122b are formed in the cladding layer 102. The first groove 104 is formed in the cladding layer 102 above the Si core 103, extending along the Si core 103 to reach the Si core 103. The second groove 122a is formed in the cladding layer 102 above the first silicon layer 121a, extending along the first silicon layer 121a to reach the first silicon layer 121a. The third groove 122b is formed in the cladding layer 102 above the second silicon layer 121a, extending along the second silicon layer 121b to reach the second silicon layer 121b.

[0042] For example, the first groove 104, the second groove 122a, and the third groove 122b can be formed by selectively etching away the cladding layer 102 using a dry etching process that uses a mask pattern formed by known lithography techniques. Each groove is formed so that the groove depth is greater than the groove width. For example, the first groove 104 is formed so that the groove width is 0.1 μm or less.

[0043] 2C , a lower semiconductor layer 105 is formed on the cladding layer 102, filling the first groove 104 and extending along the Si core 103. The lower semiconductor layer 105 is formed by epitaxial growth from the upper surface of the Si core 103 at the bottom of the first groove 104. For example, the lower semiconductor layer 105 is formed by epitaxially growing undoped InP using a well-known metal organic chemical vapor deposition method. At the same time, a lower semiconductor layer 105′ is epitaxially grown from the upper surfaces of the first silicon layer 121a and the second silicon layer 121b at the bottom of the second groove 122a and the third groove 122b.

[0044] The lower semiconductor layer 105 is formed by epitaxial growth in a state where there are no defects above the cladding layer 102, by stopping the growth of defects generated from the upper surface of the Si core 103 at the bottom of the first groove 104 at the side of the first groove 104 during the growth of a III-V compound semiconductor (e.g., InP) by aspect ratio trapping using the first groove 104. In this epitaxial growth, growth in a direction parallel to the plane of the substrate 101 is appropriately controlled, and the width of the lower semiconductor layer 105 in the width direction of the first groove 104 is formed to a set value. The lower semiconductor layer 105' is formed in the same manner as the lower semiconductor layer 105.

[0045] Next, as shown in FIG. 2D , an active layer 106 made of a III-V compound semiconductor is formed on the lower semiconductor layer 105, extending along the Si core 103 and capable of optically coupling to the Si core 103. The active layer 106 is formed by epitaxially growing the III-V compound semiconductor from the upper surface of the lower semiconductor layer 105. The sides of the lower semiconductor layer 105 are the upper surfaces of the cladding layer 102 made of a dielectric material such as silicon oxide. By appropriately setting the growth conditions for the III-V compound semiconductor, the active layer 106 can be selectively grown only on the lower semiconductor layer 105. At the same time, an active layer structure 106' having the same structure as the active layer 106 is formed on the lower semiconductor layer 105'.

[0046] Next, as shown in FIG. 2E , an upper semiconductor layer 107 made of a III-V compound semiconductor is formed on the active layer 106. For example, the lower semiconductor layer 105 and the upper semiconductor layer 107 are formed by epitaxially growing undoped InP using, for example, the well-known metalorganic chemical vapor deposition method. The sides of the lower semiconductor layer 105 are the upper surfaces of the cladding layer 102 made of a dielectric material such as silicon oxide, and by appropriately setting the growth conditions for the III-V compound semiconductor, the upper semiconductor layer 107 can be selectively grown only on the active layer 106. At the same time, an upper semiconductor layer 107' having the same structure as the upper semiconductor layer 107 is formed on the active layer structure 106'.

[0047] Next, as shown in FIG. 2F , semiconductor layers 108a and 109a are formed to fill the sides of the active layer 106 and the active layer structure 106′. For example, a III-V compound semiconductor (e.g., undoped InP) is grown parallel to the plane of the substrate 101 from the side surfaces of the lower semiconductor layer 105 (upper semiconductor layer 107) and the lower semiconductor layer 105′ (upper semiconductor layer 107′) (see References 1 and 2). The grown semiconductor layers 108a and 109a fill both sides of the stacked structure of the lower semiconductor layer 105, the active layer 106, and the upper semiconductor layer 107. The top surfaces of the grown semiconductor layers 108a and 109a may not be flat. In this case, they can be flattened using a technique such as chemical mechanical polishing (CMP).

[0048] As described above, the semiconductor layers 108a and 109a are formed by combining III-V group compound semiconductors grown from multiple locations of the lower semiconductor layer 105' (upper semiconductor layer 107'). As a result, it is easy to form the semiconductor layers 108a and 109a with wide widths for forming electrodes on these layers. However, defects such as twin planes and APBs are expected to occur at the interface where the III-V group compound semiconductors are combined. To address this issue, it is believed that degradation of optical characteristics can be prevented by forming the active layer 106 at a location sufficiently far from the combined interface so that such defects do not occur in the active layer 106 region.

[0049] After the semiconductor layers 108a and 109a are formed as described above, a compound semiconductor layer (e.g., undoped InGaAs) that will become the first contact layer 114 and a compound semiconductor layer (e.g., undoped InGaAs) that will become the second contact layer 115 are formed. Next, the compound semiconductor layer on one side of the stacked structure of the lower semiconductor layer 105, the active layer 106, and the upper semiconductor layer 107 is doped with a p-type impurity to form the p-type semiconductor layer 108 and the first contact layer 114. Furthermore, the compound semiconductor layer on the other side of the stacked structure of the lower semiconductor layer 105, the active layer 106, and the upper semiconductor layer 107 is doped with an n-type impurity to form the n-type semiconductor layer 109 and the second contact layer 115.

[0050] Next, a diffraction grating 112 is formed above the active layer 106 as a resonator structure. Next, an insulating material is deposited to form an insulating film, and openings are made above the first contact layer 114 and the second contact layer 115 using a known technique such as dry etching, and an insulating layer 113 is formed. Thereafter, an n-type electrode 111 electrically connected to the n-type semiconductor layer 109 is formed on the second contact layer 115, and a p-type electrode 110 electrically connected to the p-type semiconductor layer 108 is formed on the first contact layer 114. As a result, the semiconductor laser described with reference to FIG. 1 is fabricated.

[0051] As described above, according to the first embodiment, there is no need for a process such as bonding a III-V compound semiconductor layer formed using a growth substrate made of a III-V compound semiconductor to a Si substrate on which an optical waveguide using a Si core is formed. Furthermore, the core structure of the active layer 106 can be formed without patterning using photolithography and etching techniques, which simplifies the manufacturing process.

[0052] Incidentally, the above-described semiconductor laser has an active layer structure 123 around the active layer 106, which has a high refractive index similar to that of the active layer 106. Therefore, there is a possibility that light generated in the active layer 106 may couple with the active layer structure 123, adversely affecting the laser characteristics. For this reason, it is necessary to design the laser so that the active layer 106 and the unnecessary active layer structure 123 are not optically coupled to each other.

[0053] 3 shows the dependence of the optical confinement coefficient on each layer (Si core 103, active layer 106, active layer structure 123) when the distance (adjacent distance L) between the active layer 106 and the active layer structure 123 adjacent to the active layer 106 is changed from 0.1 to 1 μm, assuming that the width of the Si core 103 is 440 nm. In FIG. 3, (a) shows the change in the optical confinement coefficient of the Si core 103. Also, (b) shows the change in the optical confinement coefficient of the active layer 106. Also, (c) shows the change in the total optical confinement coefficient of the Si core 103 and the active layer 106. Also, (d) shows the change in the optical confinement coefficient of the active layer structures 123 on the left and right sides of the active layer 106.

[0054] 4 shows the dependence of the optical confinement coefficient on each layer (Si core 103, active layer 106, active layer structure 123) when the distance (adjacent distance L) between the active layer 106 and the active layer structure 123 adjacent to the active layer 106 is changed from 0.1 to 1 μm, assuming that the width of the Si core 103 is 700 nm. In FIG. 4, (a) shows the change in the optical confinement coefficient of the Si core 103. (b) shows the change in the optical confinement coefficient of the active layer 106. (c) shows the change in the total optical confinement coefficient of the Si core 103 and the active layer 106. (d) shows the change in the optical confinement coefficient of the active layer structures 123 on the left and right sides of the active layer 106.

[0055] When the width of the Si core 103 is 440 nm, the light intensity distribution in the active layer 106 is strong, and it is found that if the distance between adjacent active layer structures 123 is about 0.5 μm or less, there is a relatively large amount of light leaking into unnecessary active layer structures 123. On the other hand, it is also clear that if the active layer 106 and the adjacent active layer structures 123 are designed to be sufficiently separated, optical interference can be suppressed to a negligible level.

[0056] When the width of the Si core 103 is 700 nm, the light intensity distribution in the active layer 106 is small, and it can be seen that there is almost no light leakage even when the distance to the adjacent active layer structure 123 is short.

[0057] Considering these results, it can be seen that by changing the width of the Si core 103 or the distance between the active layer 106 and the active layer structure 123, it is possible to suppress the amount of light leaking from the active layer 106 to the adjacent active layer structure 123, and to achieve a desired relationship in the optical confinement coefficient between the active layer 106 and the Si core 103.

[0058] While the above description shows a case where all groove widths are uniform, a case where the groove widths of each groove are different will also be described. When the groove width of the first groove 104 differs from the groove widths of the second groove 122a and the third groove 122b, the cross-sectional area within the groove changes depending on the groove width, resulting in a difference in the amount of raw material consumed per unit length in the direction perpendicular to the substrate (thickness direction) during crystal growth. As a result, the growth rate in the thickness direction also changes. By utilizing this effect, it is possible to increase the distance between the active layer 106 and the adjacent active layer structure 123 compared to when the groove widths are uniform.

[0059] For example, if the groove widths of the second groove 122a and the third groove 122b are made larger than the groove width of the first groove 104, the lower semiconductor layer 105′ in the explanation using Fig. 2C is formed thinner than the lower semiconductor layer 105. As a result, the active layer structure 123 is positioned lower than the active layer 106 when viewed from the substrate 101, and the distance between the active layer 106 and the active layer structure 123 can be made larger than when they are formed at the same height (Fig. 5).

[0060] 6 shows the height difference (Δz) between the active layer 106 and the active layer structure 123 and the dependence of the optical confinement factor of the active layer structure 123 on Δz, when the width of the Si core 103 is 440 nm and the distance between the active layer 106 and the active layer structure 123 adjacent to the active layer 106 in the horizontal direction of the substrate is 400 nm. Based on this result, it can be seen that by making the height position of the active layer structure 123 different from that of the active layer 106, it is possible to suppress leakage of light into the active layer structure 123.

[0061] As described above, according to the first embodiment, the use of the second groove and the third groove makes it possible to more easily increase the areas of the p-type semiconductor layer and the n-type semiconductor layer on which the electrodes are formed, and thus makes it possible to easily integrate and form a current injection type semiconductor laser using III-V compound semiconductor layers with a Si waveguide.

[0062] Second Embodiment Next, a semiconductor laser according to a second embodiment of the present invention will be described with reference to Fig. 7, Fig. 8, and Fig. 9. Fig. 7 shows a cross section taken along line AA' in Fig. 9, and Fig. 8 shows a cross section taken along line BB' in Fig. 9.

[0063] This semiconductor laser includes a cladding layer 202 formed on a substrate 201 and a Si core 203 embedded in the cladding layer 202. The cladding layer 202 is made of, for example, silicon oxide (SiO x 7. The Si core 203 extends from the front to the back of the paper in FIG. 7, and the Si core 203 and the cladding layer 202 form an optical waveguide.

[0064] This semiconductor laser also includes silicon layers 203a that are orthogonal to the Si core 203 in a direction parallel to the plane of the substrate 201 at each of a plurality of locations in the Si core 203 that are arranged in the waveguiding direction of the optical waveguide described above. The silicon layers 203a are formed in a rectangular core shape in cross section, and are disposed at the same height as the Si core 203 when viewed from the substrate 201.

[0065] This semiconductor laser also includes a first groove 204 formed in the cladding layer 202. The first groove 204 is disposed on the silicon layer 203a and extends along the silicon layer 203a. The first groove 204 is formed in the thickness direction, reaching the Si core 203 and the silicon layer 203a. The bottom surface of the first groove 204 becomes the upper surfaces of the Si core 203 and the silicon layer 203a. The first groove 204 is formed so that its depth is greater than its width.

[0066] This semiconductor laser also includes an insulating layer 211 formed on the cladding layer 202. Second grooves 212 are formed in the insulating layer 211 and reach the cladding layer 202 (penetrating the insulating layer 211). The second grooves 212 are arranged on and along each of the silicon layers 203a.

[0067] This semiconductor laser also includes a lower semiconductor layer 205, an active layer 206, and an upper semiconductor layer 207 made of a III-V compound semiconductor in each of the second grooves 212 on the cladding layer 202. The stacked structures of the lower semiconductor layer 205, the active layer 206, and the upper semiconductor layer 207 are formed at a plurality of locations (intersection locations) of the Si core 203 that intersect with the silicon layer 203a. The stacked structures formed at the plurality of intersection locations are arranged on the Si core 203 in the extension direction (waveguiding direction) of the Si core 203.

[0068] The lower semiconductor layer 205 is formed on the cladding layer 202 by epitaxial growth from the upper surface of the Si core 203 at the bottom of the first groove 204 in each of the second grooves 212, filling a portion of the first groove 204. The lower semiconductor layer 205 is formed by epitaxial growth in a state where there are no defects above the cladding layer 202, by using aspect ratio trapping (ART) using the first groove 204 to stop the growth of defects generated from the upper surface of the Si core 203 at the bottom of the first groove 204 at the side of the first groove 204. The lower semiconductor layer 205 can be composed of, for example, undoped InP. The lower semiconductor layer 205 can be formed directly on the Si core 203.

[0069] The active layer 206 is formed on the lower semiconductor layer 205 in a state capable of optically coupling with the Si core 203. The active layer 206 may have, for example, a multiple quantum well structure in which well layers and barrier layers made of InGaAsP are alternately stacked, or may have a multiple quantum well structure in which well layers made of InGaAs and barrier layers made of InP are alternately stacked.

[0070] The upper semiconductor layer 207 is formed on the active layer 206. The upper semiconductor layer 207 may be made of, for example, undoped InP (i-InP). The lower semiconductor layer 205 and the upper semiconductor layer 207 may be clad to confine light to the active layer 206.

[0071] The Si core 203 and the active layer 206 can be roughly matched in effective refractive index, enabling highly efficient optical coupling between the Si core 203 and the active layer 206. Furthermore, by forming a double heterostructure from the lower semiconductor layer 205, the upper semiconductor layer 207, and the active layer 206, carriers can be more efficiently injected into the active layer 206.

[0072] This semiconductor laser also has a resonator structure that is configured with a diffraction grating (grating pattern) consisting of periodically arranged partitions by the insulating layer 211 between adjacent second grooves 212, and that confines light to the active layer 206 arranged in the waveguide direction. This resonator structure is a complex-coupling type laser structure in which both the refractive index and gain change periodically with respect to the resonance direction (waveguiding direction). The period of the insulating layer 211 between adjacent second grooves 212 needs to be appropriately designed for the target oscillation wavelength.

[0073] This semiconductor laser also includes a p-type semiconductor layer 208 formed on the cladding layer 202 and in contact with one surface of the active layer 206, and an n-type semiconductor layer 209 formed in contact with the other surface.

[0074] The p-type semiconductor layer 208 is made of a compound semiconductor, and in each of the second grooves 212, it grows epitaxially from the upper surface of the silicon layer 203 a at the bottom of the first groove 204, thereby filling up some of the first grooves 204 and being formed on the cladding layer 202 and contacting the side surface of the active layer 206.

[0075] The n-type semiconductor layer 209 is made of a compound semiconductor, and in each of the second grooves 212, it grows epitaxially from the upper surface of the silicon layer 203 a at the bottom of the first groove 204, thereby filling up some of the first grooves 204 and being formed on the cladding layer 202 and contacting the side surface of the active layer 206.

[0076] The p-type semiconductor layer 208 and the n-type semiconductor layer 209 are formed to sandwich the lower semiconductor layer 205, the active layer 206, and the upper semiconductor layer 207 in a plan view. With this configuration, a current is injected into the active layer 206 in a direction parallel to the plane of the substrate 201. The p-type semiconductor layer 208 has, for example, a Zn concentration of 1×10 18 cm-3 The n-type semiconductor layer 209 may be made of p-type InP doped to a degree of 1×10 18 cm -3 It may be constructed from lightly doped n-type InP.

[0077] The semiconductor laser also includes a p-type electrode 221 electrically connected to the p-type semiconductor layer 208, and an n-type electrode 222 electrically connected to the n-type semiconductor layer 209. In this example, the semiconductor laser also includes a first contact layer 214 formed on the p-type semiconductor layer 208, and a second contact layer 215 formed on the n-type semiconductor layer 209.

[0078] The p-type electrode 221 is formed on the first contact layer 214 in ohmic contact, and the n-type electrode 222 is formed on the second contact layer 215 in ohmic contact. The first contact layer 214 has a Zn concentration of 1×10 19 cm -3 The second contact layer 215 may be made of p-type InP doped to a degree of 1×10 19 cm -3 It may be constructed from lightly doped n-type InP.

[0079] An insulating layer 213 is formed on and in contact with the upper semiconductor layer 207 , the p-type semiconductor layer 208 , and the n-type semiconductor layer 209 between the first contact layer 214 and the second contact layer 215 .

[0080] As described above, the lower semiconductor layer 205 is formed by epitaxially growing from the upper surface of the Si core 203 at the bottom surface of the first groove 204 using the Si core 203 as a seed crystal, thereby filling the first groove 204 above the Si core 203. This allows defects (dislocations) that occur at the interface between the lower semiconductor layer 205 and the Si core 203 to be terminated on the inner wall of the first groove 204, making it possible to form the lower semiconductor layer 205 above the cladding layer 202 as a high-quality crystal. For example, if the width w of the first groove 204 is set to 100 (nm) and the height h of the first groove 204 is set to 150 (nm), a sufficient ART effect can be expected, making it possible to grow a high-quality III-V compound semiconductor on the cladding layer 202. This means that a high-quality active layer 206 can be formed at a distance that allows optical coupling with the Si core 203.

[0081] The same applies to the p-type semiconductor layer 208 and the n-type semiconductor layer 209. Furthermore, the p-type semiconductor layer 208 is formed on the cladding layer 202 by epitaxially growing from the upper surface of the silicon layer 203a at the bottom of the first groove 204, thereby filling the first groove 204 in this region. This facilitates widening the width in the direction away from the active layer 206 in plan view. Similarly, the n-type semiconductor layer 209 is formed on the cladding layer 202 by epitaxially growing from the upper surface of the silicon layer 203a at the bottom of the first groove 204, thereby filling the first groove 204 in this region. This facilitates widening the width in the direction away from the active layer 206 in plan view. Furthermore, in this case, twin planes and APBs are not generated during the crystal growth of the III-V compound semiconductors that form the p-type semiconductor layer 208 and the n-type semiconductor layer 209, and therefore, it is expected that a decrease in internal quantum efficiency due to non-radiative recombination of carriers will not occur.

[0082] Next, a method for manufacturing a semiconductor laser according to the second embodiment of the present invention will be described with reference to FIGS. 10A to 10F.

[0083] 10A, a Si core 203 and a silicon layer 203a (not shown) are formed on a substrate 201, and a clad layer 202 is formed to embed them. The Si core 203 and the clad layer 202 form an optical waveguide. First grooves 204 are formed in the clad layer 202. An insulating layer 211 is then formed on the clad layer 202, and second grooves 212 are formed in multiple locations in the formed insulating layer 211.

[0084] For example, the first groove 204 can be formed by selectively etching away the cladding layer 202 through a dry etching process using a mask pattern formed by a known lithography technique. The second groove 212 can be formed by selectively etching away the insulating layer 211 through a dry etching process using a mask pattern formed by a known lithography technique.

[0085] 10B , a lower semiconductor layer 205 that fills the first groove 204 and extends along the Si core 203 is formed on the cladding layer 202. The lower semiconductor layer 205 is formed by epitaxial growth from the upper surfaces of the Si core 203 and the silicon layer 203a at the bottom of the first groove 204. For example, the lower semiconductor layer 205 is formed by epitaxially growing undoped InP using a well-known metalorganic chemical vapor deposition method or the like.

[0086] The lower semiconductor layer 205 is formed by aspect ratio trapping using the first groove 204, in the process of growing a III-V compound semiconductor (e.g., InP), by stopping the growth of defects generated from the Si core 203 at the bottom of the first groove 204 and the upper surface of the silicon layer 203a at the side of the first groove 204, thereby allowing epitaxial growth without defects above the cladding layer 202.

[0087] 10C , an active layer 206 made of a III-V compound semiconductor is formed on the lower semiconductor layer 205, extending along the Si core 203 in a state capable of being optically coupled to the Si core 203. The III-V compound semiconductor that will form the active layer 206 is epitaxially grown from the upper surface of the lower semiconductor layer 205 to form the active layer 206.

[0088] Subsequently, an upper semiconductor layer 207 made of a III-V group compound semiconductor is formed on the active layer 206. For example, the upper semiconductor layer 207 is formed on the active layer 206 by epitaxially growing undoped InP using a well-known metalorganic chemical vapor deposition method or the like.

[0089] 10D, a mask pattern 220 extending along the Si core 203 is formed on the upper semiconductor layer 207 in the region of the Si core 203. After the mask pattern 220 is formed, the upper semiconductor layer 207, the active layer 206, and the lower semiconductor layer 205 are patterned by a selective etching process using the mask pattern 220 as a mask. By this patterning, the stacked structure of the lower semiconductor layer 205, the active layer 206, and the upper semiconductor layer 207 is shaped into a ridge shape extending in the waveguide direction from the front to the back of the page, as shown in FIG.

[0090] 10F, semiconductor layers 231a and 231b are formed to fill the sides of the active layer 206 in a direction perpendicular to the waveguide direction. For example, a III-V compound semiconductor (e.g., undoped InP) is grown (regrown) from the side of the lower semiconductor layer 205 (upper semiconductor layer 207) in a direction parallel to the plane of the substrate 201 (References 1 and 2). The grown semiconductor layers 231a and 231b fill both sides of the stacked structure of the lower semiconductor layer 205, active layer 206, and upper semiconductor layer 207.

[0091] After forming the semiconductor layers 231a and 231b as described above, a compound semiconductor layer (e.g., undoped InGaAs) that will become the first contact layer 214 and a compound semiconductor layer (e.g., undoped InGaAs) that will become the second contact layer 315 are formed. Next, the compound semiconductor layer on one side of the stacked structure of the lower semiconductor layer 205, the active layer 206, and the upper semiconductor layer 207 is doped with a p-type impurity to form the p-type semiconductor layer 208 and the first contact layer 214. Furthermore, the compound semiconductor layer on the other side of the stacked structure of the lower semiconductor layer 205, the active layer 206, and the upper semiconductor layer 207 is doped with an n-type impurity to form the n-type semiconductor layer 209 and the second contact layer 215.

[0092] Next, an insulating material is deposited to form an insulating film, and openings are made in the upper portions of the first contact layer 214 and the second contact layer 215 using a known technique such as dry etching, to form the insulating layer 213. Thereafter, an n-type electrode 222 electrically connected to the n-type semiconductor layer 209 is formed on the first contact layer 214, and a p-type electrode 221 electrically connected to the p-type semiconductor layer 208 is formed on the second contact layer 215. As a result, the semiconductor laser described with reference to FIGS.

[0093] As described above, according to the second embodiment, there is no need for a step of bonding a III-V compound semiconductor layer formed using a growth substrate made of a III-V compound semiconductor to a Si substrate on which an optical waveguide using a Si core is formed.

[0094] Furthermore, according to the second embodiment, the first groove on the silicon layer that is perpendicular to the Si core is used, so that it is possible to more easily increase the areas of the p-type semiconductor layer and the n-type semiconductor layer on which the electrodes are formed, and it becomes possible to easily integrate and form a current injection type semiconductor laser using III-V compound semiconductor layers with a Si waveguide.

[0095] [Embodiment 3] Next, a semiconductor laser according to embodiment 3 of the present invention will be described with reference to Figures 11, 12, and 13. Note that Figure 11 shows a cross section taken along line AA' in Figure 13, and Figure 12 shows a cross section taken along line BB' in Figure 13. In the following, the left-right direction on the paper surface of Figure 11 is referred to as a first direction, and the left-right direction on the paper surface of Figure 12 is referred to as a second direction.

[0096] This semiconductor laser includes a first insulating layer 302 formed on a substrate 301, and a second insulating layer 311 formed on the first insulating layer 302. The first insulating layer 302 and the second insulating layer 311 are made of, for example, silicon oxide (SiO x ) can be composed of

[0097] This semiconductor laser also includes first grooves 312a arranged in a first direction at a plurality of locations in second insulating layer 311, extending in a second direction perpendicular to the first direction and reaching first insulating layer 302 formed in second insulating layer 311. This semiconductor laser also includes second grooves 312b formed in second insulating layer 311 contiguous with each of first grooves 312a in the second direction and reaching first insulating layer 302, the width of which narrows with increasing distance from first groove 312a. This semiconductor laser also includes third grooves 312c formed in second insulating layer 311 contiguous with each of second grooves 312b in the second direction and reaching first insulating layer 302.

[0098] For example, the first grooves 312a may have the same groove width in the second direction, and the third grooves 312c may have a groove width smaller than that of the first grooves 312a. Note that the second grooves 312b have the same groove width as the first grooves 312a on the side of the first grooves 312a, and the same groove width as the third grooves 312c on the side of the third grooves 312c. For example, the shape of the second grooves 312b in a plan view may be an isosceles trapezoid.

[0099] Each of the third grooves 312c is provided with a silicon layer 303 formed to fill the corresponding one of the third grooves 312c. A third insulating layer 319 is formed on the second insulating layer 311 to cover each of the first grooves 312a, each of the second grooves 312b, and each of the third grooves 312c.

[0100] This semiconductor laser also includes a first semiconductor layer 308 of a first conductivity type made of a compound semiconductor, an active layer 306 made of a compound semiconductor, and a second semiconductor layer 309 of a second conductivity type made of a compound semiconductor.

[0101] The first semiconductor layer 308 is formed by epitaxial growth without defects in the region of the first groove 312 a, by making the growth interface of the Si seed crystal a very small area of ​​about several hundred nanometers square, in order to prevent defects from occurring at the Si / semiconductor interface.

[0102] The active layer 306 is formed on the first insulating layer 302 in each of the first grooves 312a by epitaxial growth from the side surface of the first semiconductor layer 308 on the side of the first groove 312a. The active layer 306 is in contact with the side surface of the first semiconductor layer 308. The active layer 306 may have a multiple quantum well structure in which well layers and barrier layers made of InGaAsP are alternately stacked. Alternatively, the active layer 306 may have a multiple quantum well structure in which well layers made of InGaAs and barrier layers made of InP are alternately stacked in the growth direction. In this case, the growth direction is parallel to the plane of the substrate 301.

[0103] The second semiconductor layer 309 is formed on the first insulating layer 302 of each first groove 312 a by epitaxial growth from the side surface of the first groove 312 a of each active layer 306. The second semiconductor layer 309 is in contact with the side surface of the active layer 306.

[0104] The first semiconductor layer 308 and the second semiconductor layer 309 are formed to sandwich the active layer 306 in a plan view. With this configuration, a current is injected into the active layer 306 in a direction parallel to the plane of the substrate 301. The first semiconductor layer 308 has, for example, Zn of 1×10 18 cm -3 The second semiconductor layer 309 may be made of p-type InP doped to a degree of 1×10 18 cm -3 The first conductivity type may be p-type and the second conductivity type may be n-type. Alternatively, the first conductivity type may be n-type and the second conductivity type may be p-type.

[0105] This semiconductor laser also has a resonator structure that is configured with a diffraction grating (grating pattern) consisting of periodically arranged divisions by the second insulating layer 311 between adjacent first grooves 312a, and that confines light to the active layer 306 arranged in the waveguide direction. This resonator structure is a complex-coupling type laser structure in which both the refractive index and gain change periodically with respect to the resonance direction (waveguiding direction). The period of the second insulating layer 311 between adjacent first grooves 312a needs to be appropriately designed for the target oscillation wavelength.

[0106] The semiconductor laser also includes a first electrode 321 electrically connected to the first semiconductor layer 308 and a second electrode 322 electrically connected to the second semiconductor layer 309 .

[0107] The first electrode 321 is formed on the first semiconductor layer 308 in ohmic contact, and the second electrode 322 is formed on the second semiconductor layer 309 in ohmic contact. An insulating layer 319 is formed on and in contact with the active layer 306 between the first semiconductor layer 308 and the second semiconductor layer 309, the first semiconductor layer 308, and the second semiconductor layer 309.

[0108] Next, a method for manufacturing a semiconductor laser according to the third embodiment of the present invention will be described with reference to FIGS. 14A to 14F.

[0109] First, as shown in FIG. 14A , silicon layers 303 a are formed at multiple locations on a first insulating layer 302 on a substrate 301. The silicon layers 303 a are arranged in a first direction, which is the vertical direction of the page in FIG. 14A (a). As shown in FIG. 14A (a), each silicon layer 303 a has a shape in plan view for forming a portion that will become a first groove 312 a, a portion that will become a second groove 312 b, and a third groove 312 c. For example, a well-known SOI (Silicon on Insulator) substrate can be used, with the base portion of the SOI substrate serving as the substrate 301 and the buried insulating layer of the SOI substrate serving as the first insulating layer. Alternatively, each silicon layer 303 a can be formed by patterning the surface silicon layer of the SOI substrate.

[0110] 14B and 14C, a second insulating layer 311 is formed to fill the periphery of each silicon layer 303a. By forming the second insulating layer 311, a first groove 312a, a second groove 312b, and a third groove 312c are formed. Subsequently, an insulating film 317 is formed on the second insulating layer 311 to cover each silicon layer 303a.

[0111] 14D, openings 317a are formed in insulating film 317 at the ends of first grooves 312a away from second grooves 312b. Next, silicon layers 303a are etched away from the sides through openings 317a, thereby forming silicon layers 303 so as to fill third grooves 312c as shown in FIG.

[0112] Next, as shown in FIG. 14F , semiconductor layer 304, first semiconductor layer 308, active layer 306, and second semiconductor layer 309 are formed by epitaxial growth from the side surface of each silicon layer 303 on the side of first groove 312 a. To prevent defects from occurring at the Si / semiconductor layer interface, semiconductor layer 304 is formed by epitaxial growth in a defect-free state in the region of first groove 312 a by making the growth surface area of ​​the Si seed crystal a small region like third groove 312 c. Note that, during the growth of first semiconductor layer 308 and second semiconductor layer 309, compound semiconductors of impurity elements are simultaneously supplied to achieve the respective conductivity types.

[0113] Thereafter, openings are made in the insulating film 317 directly above the first semiconductor layer 308 and the second semiconductor layer 309, and a first electrode 321 is formed to electrically connect to the second semiconductor layer 309, and a first electrode 322 is formed to electrically connect to the first semiconductor layer 308. As a result, the semiconductor laser described with reference to FIGS.

[0114] 15 and 16 , the semiconductor device may further include a lower semiconductor layer 305 made of a compound semiconductor formed below the active layer 306 on the first insulating layer 302 in each of the first grooves 312 a, and an upper semiconductor layer 307 made of a compound semiconductor formed on the active layer 306 in each of the first grooves 312 a. In this case, the first semiconductor layer 308 and the second semiconductor layer 309 are formed to sandwich the lower semiconductor layer 305, the active layer 306, and the upper semiconductor layer 307 in a planar view. By forming a double heterostructure between the lower semiconductor layer 305, the upper semiconductor layer 307, and the active layer 306, carriers can be more efficiently injected into the active layer 306.

[0115] The method for manufacturing this semiconductor laser is described below. First, as described with reference to Figures 14A to 14E, silicon layers 303 are formed so as to fill each of the third grooves 312c. Next, semiconductor layers 304a made of an undoped III-V compound semiconductor (e.g., InP) are grown by epitaxial growth from the side surfaces of each silicon layer 303 on the first groove 312a side, as shown in Figure 17A.

[0116] Next, as shown in Fig. 17B, an opening is formed in the insulating film 317 in the region of the first groove 312a, and as shown in Fig. 17C, a III-V compound semiconductor that will become the active layer is grown on the semiconductor layer 304a in the region of the first groove 312a to form an active layer structure 306a. Furthermore, a semiconductor layer 307a is formed on the active layer structure 306a.

[0117] Next, the active layer structure 306a and the semiconductor layer 307a are patterned by etching using a mask pattern 320 made of silicon oxide, thereby forming the active layer 306 and the upper semiconductor layer 307 in the region of each first groove 312a, as shown in Fig. 17D. Note that in this patterning, over-etching is performed in the regions on both sides of the active layer 306 so that part of the semiconductor layer 304a is etched in the thickness direction.

[0118] Next, using the mask pattern 320 as a selective growth mask, a III-V compound semiconductor (e.g., InP) is regrown from the upper surface of the semiconductor layer 304a on both sides of the active layer 306, thereby forming a semiconductor layer 304b so as to fill the active layer 306, as shown in Fig. 17E. Next, after removing the mask pattern 320, a semiconductor layer 322 made of, for example, InGaAsP is formed on the semiconductor layer 304b and the upper semiconductor layer 307, as shown in Fig. 17F.

[0119] Next, the semiconductor layer 322 and the semiconductor layer 304b on one side of the stacked structure of the lower semiconductor layer 305 and the active layer 306 are doped with a first conductivity type impurity to form the first semiconductor layer 308 and the first contact layer 314. The semiconductor layer 322 and the regrown layer 321 on the other side of the stacked structure of the lower semiconductor layer 305 and the active layer 306 are doped with a second conductivity type impurity to form the second semiconductor layer 309 and the second contact layer 315. The layer below the active layer 306, between the first semiconductor layer 308 and the second semiconductor layer 309, becomes the lower semiconductor layer 305 made of an undoped compound semiconductor. The layer below the insulating film 317 becomes the semiconductor layer 304 made of an undoped compound semiconductor. After this impurity introduction step, the semiconductor layer 322 on the upper semiconductor layer 307 is removed ( FIG. 17G ).

[0120] Thereafter, a first electrode 321 electrically connected to the second semiconductor layer 309 is formed on the first contact layer 314, and a second electrode 322 electrically connected to the first semiconductor layer 308 is formed on the second contact layer 315. As a result, the semiconductor laser described with reference to FIGS.

[0121] As described above, according to the third embodiment, there is no need for a step of bonding a III-V compound semiconductor layer formed using a growth substrate made of a III-V compound semiconductor to a Si substrate on which an optical waveguide using a Si core is formed.

[0122] Furthermore, according to the third embodiment, the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are formed by growing them in a direction parallel to the plane of the substrate, so that it is possible to more easily increase the areas of these layers, and it becomes possible to easily integrate and form a current injection type semiconductor laser using III-V compound semiconductor layers with a Si waveguide.

[0123] As described above, according to the present invention, the use of the second groove and the third groove makes it possible to more easily increase the areas of the p-type semiconductor layer and the n-type semiconductor layer on which the electrodes are formed, and it becomes possible to easily integrate and form a current injection type semiconductor laser using III-V compound semiconductor layers with a Si waveguide.

[0124] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0125] [References] [Reference 1] R. G. al., "Lateral epipitaxial overgrowth of GaAs by organometallic chemical vapor deposition", Applied Physics Letters, vol. 41, no. 6, pp. 545-547, 1982. [Reference 2] S. Naritsuka and T. Nishinaga, "Epitaxial lateral overgrowth of InP by liquid phase epitaxy", Journal of Crystal Growth, vol. 146, pp. 314-318, 1995.

[0126] 101...substrate, 102...cladding layer, 103...Si core, 104...first groove, 105...lower semiconductor layer, 106...active layer, 107...upper semiconductor layer, 108...p-type semiconductor layer, 109...n-type semiconductor layer, 110...n-type electrode, 111...p-type electrode, 112...diffraction grating, 113...insulating layer, 114...first contact layer, 115...second contact layer, 121a...first silicon layer, 121b...second silicon layer, 122a...second groove, 122b...third groove, 123...active layer structure, 201...substrate, 202...cladding layer, 203...Si core, 203a...silicon layer, 204...first groove, 205...lower partial semiconductor layer, 206...active layer, 207...upper semiconductor layer, 208...p-type semiconductor layer, 209...n-type semiconductor layer, 211...insulating layer, 212...second groove, 213...insulating layer, 214...first contact layer, 215...second contact layer, 301...substrate, 302...first insulating layer, 303...silicon layer, 303a...silicon layer, 304...semiconductor layer, 305...lower semiconductor layer, 306...active layer, 307...upper semiconductor layer, 308...first semiconductor layer, 309...second semiconductor layer, 311...second insulating layer, 312a...first groove, 312b...second groove, 312c...third groove, 321...first electrode, 322...second electrode.

Claims

1. An optical waveguide comprising a Si core formed on a substrate and a cladding layer in which the Si core is embedded; a first silicon layer and a second silicon layer extending along the Si core and embedded in the cladding layer on both sides of the Si core; a first groove formed in the cladding layer above the Si core, extending along the Si core and reaching the Si core; a second groove formed in the cladding layer above the first silicon layer, extending along the Si core and reaching the first silicon layer; a third groove formed in the cladding layer above the second silicon layer, extending along the Si core and reaching the second silicon layer; a lower semiconductor layer made of a compound semiconductor, which is epitaxially grown from the top surface of the Si core at the bottom surface of the first groove to fill the first groove and is formed on the cladding layer, extending along the Si core; an active layer made of a compound semiconductor formed on the lower semiconductor layer, extending along the Si core in a state capable of optically coupling with the Si core; and an upper semiconductor layer made of a compound semiconductor and formed on the active layer. a p-type semiconductor layer made of a compound semiconductor and epitaxially growing from an upper surface of the Si core at a bottom surface of the second groove to fill the second groove, formed on the cladding layer, and in contact with one side surface of the active layer; an n-type semiconductor layer made of a compound semiconductor and epitaxially growing from an upper surface of the Si core at a bottom surface of the third groove to fill the third groove, formed on the cladding layer, and in contact with the other side surface of the active layer; an n-type electrode connected to the n-type semiconductor layer; a p-type electrode connected to the p-type semiconductor layer; and a resonator structure that performs light confinement in the active layer, wherein the p-type semiconductor layer and the n-type semiconductor layer are formed to sandwich the lower semiconductor layer, the active layer, and the upper semiconductor layer in a planar view, and wherein each of the first groove, the second groove, and the third groove has a groove depth greater than a groove width.

2. A semiconductor laser according to claim 1, wherein the second groove and the third groove have a groove width larger than that of the first groove.

3. A semiconductor laser according to claim 1, wherein the second grooves are formed in the cladding layer on the first silicon layer at a plurality of locations along the Si core, and the third grooves are formed in the cladding layer on the second silicon layer at a plurality of locations along the Si core.

4. A semiconductor laser according to any one of claims 1 to 3, wherein the resonator structure is composed of a diffraction grating formed above the active layer.

5. An optical waveguide comprising a Si core formed on a substrate and a cladding layer in which the Si core is embedded; a silicon layer orthogonal to the Si core in a direction parallel to the plane of the substrate at each of a plurality of locations arranged in the Si core in a waveguiding direction of the optical waveguide; a first groove formed in the cladding layer on each of the silicon layers and extending along the silicon layer to reach the Si core and the silicon layer; an insulating layer formed on the cladding layer; a second groove disposed along the silicon layer on each of the silicon layers and reaching the cladding layer to be formed in the insulating layer; a lower semiconductor layer made of a compound semiconductor formed on the cladding layer by epitaxial growth from an upper surface of the Si core at the bottom surface of the first groove in each of the second grooves to fill a portion of the first groove; an active layer made of a compound semiconductor formed on the lower semiconductor layer in a state capable of optically coupling with the Si core in each of the second grooves; and an upper semiconductor layer made of a compound semiconductor formed on the active layer in each of the second grooves. a p-type semiconductor layer and an n-type semiconductor layer made of compound semiconductor formed on the cladding layer to fill a part of the first groove by epitaxial growth from an upper surface of the silicon layer at the bottom surface of the first groove in each of the second grooves and in contact with a side surface of the active layer; a p-type electrode connected to the p-type semiconductor layer; an n-type electrode connected to the n-type semiconductor layer; and a resonator structure composed of a diffraction grating made of periodically arranged partitions made of the insulating layer between adjacent second grooves, and which confines light in the active layer arranged in the waveguide direction, wherein the p-type semiconductor layer and the n-type semiconductor layer are formed to sandwich the lower semiconductor layer, the active layer, and the upper semiconductor layer in a planar view, and the first groove has a groove depth greater than a groove width.

6. A first insulating layer formed on a substrate; a second insulating layer formed on the first insulating layer; first grooves arranged in a first direction at a plurality of locations on the second insulating layer, extending in a second direction perpendicular to the first direction to reach the first insulating layer formed in the second insulating layer; second grooves formed in the second insulating layer contiguous with each of the first grooves in the second direction and reaching the first insulating layer, the width of the second grooves narrowing with increasing distance from the first groove; third grooves formed in the second insulating layer contiguous with each of the second grooves in the second direction to reach the first insulating layer; a silicon layer formed to fill each of the third grooves; a third insulating layer formed on the second insulating layer covering each of the first grooves, each of the second grooves, and each of the third grooves; and a first semiconductor layer of a first conductivity type made of a compound semiconductor formed on the first insulating layer of each of the first grooves by epitaxial growth from a side surface of each of the silicon layers on the side of the first groove. a first insulating layer formed on the first insulating layer of each of the first grooves by epitaxial growth from a side surface of the first semiconductor layer facing the first groove; a second semiconductor layer of a second conductivity type formed on the first insulating layer of each of the first grooves by epitaxial growth from a side surface of the first semiconductor layer facing the first groove; a first electrode connected to the first semiconductor layer through an opening formed in the third insulating layer; a second electrode connected to the second semiconductor layer through an opening formed in the third insulating layer; and a resonator structure configured with a diffraction grating formed of periodically arranged partitions made of the second insulating layer between adjacent first grooves, and which confines light in the active layer arranged in the first direction.

7. A semiconductor laser as defined in claim 6, further comprising: a lower semiconductor layer made of a compound semiconductor formed under the active layer on the first insulating layer in each of the first grooves by epitaxial growth from the side surface of each of the silicon layers facing the first groove; and an upper semiconductor layer made of a compound semiconductor formed on the active layer in each of the first grooves, wherein the first semiconductor layer and the second semiconductor layer are formed to sandwich the lower semiconductor layer, the active layer, and the upper semiconductor layer in a planar view.

8. A semiconductor laser according to claim 6 or 7, wherein the first groove has the same groove width in the second direction, the third groove has a groove width smaller than that of the first groove, and the second groove has the same groove width as the first groove on the side of the first groove and the same groove width as the third groove on the side of the third groove.

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