Driving circuit, driving method, and display apparatus

Abstract

A driving circuit, a driving method, and a display apparatus. The driving circuit comprises an inverter circuit (11), a first output node control circuit (12), a second output node control circuit (14) and an output circuit (15), wherein the inverter circuit (11) inverts the potential of a first output node (N1) in at least part of a display period, so as to obtain the potential of a first node (N2); the first output node control circuit (12) controls the potential of the first output node; the second output node control circuit (14) obtains the potential of a second output node (N4) on the basis of the potential of the first node (N2); and under the control of the potential of the first output node (N1) and the potential of the second output node (N4), the output circuit controls a driving output end to output a driving signal (O1).

Description

Driving circuit, driving method and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310946523.4 filed in China on July 28, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, and a display device. Background Art

[0004] In recent years, the development of displays has shown a trend of high integration and low cost. One of the very important technologies is the mass production of GOA (English full name: Gate Driver on Array, Chinese full name: integrated gate drive circuit) technology. GOA technology is used to integrate the gate drive circuit on the array substrate of the display panel, thereby eliminating the gate drive integrated circuit part, thereby reducing product costs in terms of both material cost and manufacturing process. This gate switch circuit integrated on the array substrate using GOA technology is also called a GOA circuit or a shift register circuit, where each shift register in the gate switch circuit is also called a GOA unit.

[0005] Summary of the Invention

[0006] In one aspect, the driving circuit according to the embodiment of the present disclosure includes an inverter circuit, a first output node control circuit, a second output node control circuit, and an output circuit;

[0007] The inverting circuit is electrically connected to the first output node and the first node respectively, and is used to invert the potential of the first output node during at least a part of the display period to obtain the potential of the first node;

[0008] The first output node control circuit is electrically connected to the first output node and is used to control the potential of the first output node;

[0009] The second output node control circuit is electrically connected to the first node and the second output node respectively, and is used to obtain the potential of the second output node according to the potential of the first node;

[0010] The output circuit is electrically connected to the first output node, the second output node and the driving output end respectively, and is used to control the driving output end to output a driving signal under the control of the potential of the first output node and the potential of the second output node.

[0011] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a first energy storage circuit;

[0012] The first energy storage circuit is electrically connected to the first output node and the driving output terminal respectively, and is used for storing electric energy.

[0013] Optionally, the inverting circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor;

[0014] The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0015] The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0016] The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node;

[0017] A first terminal of the storage capacitor is electrically connected to the first clock signal terminal, and a second terminal of the storage capacitor is electrically connected to the second node.

[0018] Optionally, the inverting circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0019] The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0020] The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0021] The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node;

[0022] The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the first control terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0023] Optionally, the first control terminal is a second voltage terminal, a first clock signal terminal, a second clock signal terminal or a frame reset terminal.

[0024] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a second energy storage circuit and an on-off control circuit;

[0025] The on-off control circuit is electrically connected to the first output node, the first clock signal terminal, and the first terminal of the second energy storage circuit, respectively, and is used to control the connection or disconnection between the first terminal of the second energy storage circuit and the first clock signal terminal under the control of the potential of the first output node;

[0026] The second end of the second energy storage circuit is electrically connected to the first output node, and the second energy storage circuit is used to store electrical energy.

[0027] Optionally, the on-off control circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor;

[0028] The gate of the fifth transistor is electrically connected to the first output node, the first electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first terminal of the second capacitor;

[0029] The second end of the second capacitor is electrically connected to the first output node.

[0030] Optionally, the first output node control circuit is also electrically connected to the input terminal, the first node, the first clock signal terminal, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first output node and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal and the potential of the first node, and to control the connection or disconnection between the first output node and the input terminal under the control of the second clock signal provided by the second clock signal terminal.

[0031] Optionally, the first output node control circuit is also electrically connected to the third node, the input terminal, the second clock signal terminal, the first node, the first voltage terminal, the first clock signal terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the third node and the input terminal under the control of the second clock signal provided by the second clock signal terminal, control the connection or disconnection between the third node and the first voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal, and control the connection or disconnection between the third node and the first output node under the control of the third voltage signal provided by the third voltage terminal.

[0032] Optionally, the driving circuit also includes a first node control circuit; the first node control circuit is electrically connected to the first node, the fourth voltage terminal and the first clock signal terminal, respectively, and is used to control the connection or disconnection between the first node and the fourth voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal.

[0033] Optionally, the second output node control circuit is also electrically connected to the first output node, the first clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the second output node under the control of the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the second output node and the first voltage terminal under the control of the potential of the first output node.

[0034] Optionally, the output circuit is further electrically connected to the first voltage terminal and the second voltage terminal respectively;

[0035] The output circuit is used to control the connection or disconnection between the drive output terminal and the second voltage terminal under the control of the potential of the first output node, and to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the potential of the second output node.

[0036] Optionally, the first output node control circuit includes a sixth transistor, a seventh transistor and an eighth transistor;

[0037] The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal;

[0038] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the first output node;

[0039] A gate of the eighth transistor is electrically connected to the second clock signal terminal, a first electrode of the eighth transistor is electrically connected to the input terminal, and a second electrode of the eighth transistor is electrically connected to the first output node.

[0040] Optionally, the eighth transistor is a dual-gate transistor.

[0041] Optionally, the first output node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor;

[0042] The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal;

[0043] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the third node;

[0044] The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first electrode of the eighth transistor is electrically connected to the input terminal, and the second electrode of the eighth transistor is electrically connected to the third node;

[0045] A gate of the ninth transistor is electrically connected to the third voltage terminal, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is electrically connected to the first output node.

[0046] Optionally, the first node control circuit includes a tenth transistor and an eleventh transistor;

[0047] The gate of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0048] A gate of the eleventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

[0049] Optionally, the second output node control circuit includes a twelfth transistor and a thirteenth transistor;

[0050] The gate of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the second output node;

[0051] A gate of the thirteenth transistor is electrically connected to the first output node, a first electrode of the thirteenth transistor is electrically connected to the first voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second output node.

[0052] Optionally, the output circuit includes a fourteenth transistor and a fifteenth transistor;

[0053] The gate of the fourteenth transistor is electrically connected to the first output node, the first electrode of the fourteenth transistor is electrically connected to the driving output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage terminal;

[0054] The gate of the fifteenth transistor is electrically connected to the second output node, the first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the driving output terminal.

[0055] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a third energy storage circuit;

[0056] A first end of the third energy storage circuit is electrically connected to the second output node, a second end of the third energy storage circuit is electrically connected to the first voltage end, and the third energy storage circuit is used to store electrical energy.

[0057] The present disclosure also provides a driving method, which is applied to the above-mentioned driving circuit. The driving method includes:

[0058] The inverting circuit inverts the potential of the first output node to obtain the potential of the first node;

[0059] A first output node control circuit controls the potential of the first output node;

[0060] The second output node control circuit obtains the potential of the second output node according to the potential of the first node;

[0061] The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first output node and the potential of the second output node.

[0062] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0064] FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0065] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0066] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0067] FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0068] FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0069] FIG7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0070] FIG8 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0071] FIG9 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0072] FIG10 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0073] FIG11 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0074] FIG12 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0075] FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0076] FIG14 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG13 of the present disclosure;

[0077] FIG15A is a schematic diagram illustrating the operating state of at least one embodiment of the driving circuit shown in FIG13 of the present disclosure during a first time period;

[0078] FIG15B is a schematic diagram illustrating the operating state of at least one embodiment of the driving circuit shown in FIG13 of the present disclosure during a second time period;

[0079] FIG15C is a schematic diagram illustrating the operating state of at least one embodiment of the driving circuit shown in FIG13 of the present disclosure during a third time period;

[0080] FIG15D is a schematic diagram illustrating the operating state of at least one embodiment of the driving circuit shown in FIG13 of the present disclosure during a fourth time period;

[0081] FIG15E is a schematic diagram illustrating the operating state of at least one embodiment of the driving circuit shown in FIG13 of the present disclosure during a fifth time period;

[0082] FIG15F is a schematic diagram illustrating the operating state of at least one embodiment of the driving circuit shown in FIG13 of the present disclosure during a sixth time period;

[0083] FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0084] FIG17 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG16 of the present disclosure;

[0085] FIG18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0086] FIG19 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG18 of the present disclosure;

[0087] FIG. 20 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0088] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0089] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0090] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0091] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes an inverting circuit 11 , a first output node control circuit 12 , a second output node control circuit 14 and an output circuit 15 ;

[0092] The inverting circuit 11 is electrically connected to the first output node N1 and the first node N2, respectively, and is used to invert the potential of the first output node N1 during at least a portion of the display period to obtain the potential of the first node N2;

[0093] The first output node control circuit 12 is electrically connected to the first output node N1 and is used to control the potential of the first output node N1;

[0094] The second output node control circuit 14 is electrically connected to the first node N2 and the second output node N4 respectively, and is used to obtain the potential of the second output node N4 according to the potential of the first node N2;

[0095] The output circuit 15 is electrically connected to the first output node N1, the second output node N4 and the driving output terminal O1 respectively, and is used to control the driving output terminal O1 to output a driving signal under the control of the potential of the first output node N1 and the potential of the second output node N4.

[0096] The driving circuit described in the embodiment of the present disclosure adopts an inverting circuit 11. The inverting circuit 11 inverts the potential of the first output node N1 during at least part of the display period to obtain the potential of the first node N2. The embodiment of the present disclosure provides a new driving circuit structure to enable driving signal output.

[0097] The driving circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit;

[0098] The first energy storage circuit is electrically connected to the first output node and the driving output terminal respectively, and is used for storing electric energy.

[0099] In a specific implementation, the driving circuit may further include a first energy storage circuit, wherein a first end of the first energy storage circuit is electrically connected to the first output node, and a second end of the first energy storage circuit is electrically connected to the driving output end.

[0100] As shown in FIG2 , based on the embodiment of the driving circuit shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit 21 ;

[0101] A first end of the first energy storage circuit 21 is electrically connected to the first output node N1 , a second end of the first energy storage circuit 21 is electrically connected to the driving output end O1 , and the first energy storage circuit 21 is used for storing electrical energy.

[0102] In at least one embodiment of the driving circuit shown in FIG. 2 of the present disclosure, when the potential of the driving signal provided by the driving output terminal O1 drops from a high voltage to a low voltage, the potential of the first output node N1 drops only once due to the voltage bootstrapping effect of the first energy storage circuit 21, thereby ensuring that the falling edge of the driving signal provided by the driving output terminal O1 is step-free.

[0103] Optionally, the inverting circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor;

[0104] The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0105] The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0106] The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node;

[0107] A first terminal of the storage capacitor is electrically connected to the first clock signal terminal, and a second terminal of the storage capacitor is electrically connected to the second node.

[0108] Optionally, the inverting circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0109] The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0110] The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal;

[0111] The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node;

[0112] The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the first control terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0113] In at least one embodiment of the present disclosure, the first control terminal is a second voltage terminal, a first clock signal terminal, a second clock signal terminal, or a frame reset terminal.

[0114] Optionally, the frame reset signal provided by the frame reset terminal may be in phase opposite to the start signal.

[0115] The driving circuit according to at least one embodiment of the present disclosure further includes a second energy storage circuit and an on-off control circuit;

[0116] The on-off control circuit is electrically connected to the first output node, the first clock signal terminal, and the first terminal of the second energy storage circuit, respectively, and is used to control the connection or disconnection between the first terminal of the second energy storage circuit and the first clock signal terminal under the control of the potential of the first output node;

[0117] The second end of the second energy storage circuit is electrically connected to the first output node, and the second energy storage circuit is used to store electrical energy.

[0118] In a specific implementation, the driving circuit may further include a second energy storage circuit and an on-off control circuit. The on-off control circuit controls the connection or disconnection between the first end of the second energy storage circuit and the first clock signal end under the control of the potential of the first output node. The second end of the second energy storage circuit is electrically connected to the first output node for storing electrical energy.

[0119] As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure further includes a second energy storage circuit 31 and an on-off control circuit 32 ;

[0120] The on-off control circuit 32 is electrically connected to the first output node N1, the first clock signal terminal CKB, and the first terminal of the second energy storage circuit 31, respectively, and is used to control the connection or disconnection between the first terminal of the second energy storage circuit 31 and the first clock signal terminal CKB under the control of the potential of the first output node N1;

[0121] A second end of the second energy storage circuit 31 is electrically connected to the first output node N1 , and the second energy storage circuit 31 is used to store electrical energy.

[0122] When at least one embodiment of the driving circuit shown in FIG3 of the present disclosure is in operation, the potential of the first output node N1 can be pulled down multiple times within one frame time through the second energy storage circuit 31 and the on-off control circuit 32, thereby stabilizing the output of the transistor whose gate is electrically connected to the first output node in the output circuit, reducing the influence of the parasitic capacitance of the transistor on the voltage of the first output node N1, and effectively improving the reliability of the driving circuit.

[0123] Optionally, the on-off control circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor;

[0124] The gate of the fifth transistor is electrically connected to the first output node, the first electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first terminal of the second capacitor;

[0125] The second end of the second capacitor is electrically connected to the first output node.

[0126] In at least one embodiment of the present disclosure, the first output node control circuit is also electrically connected to the input terminal, the first node, the first clock signal terminal, the second clock signal terminal, the first voltage terminal and the first output node, respectively, and is used to control the connection or disconnection between the first output node and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal and the potential of the first node, and to control the connection or disconnection between the first output node and the input terminal under the control of the second clock signal provided by the second clock signal terminal.

[0127] Optionally, the first voltage end may be a high voltage end, but is not limited thereto.

[0128] As shown in Figure 4, based on at least one embodiment of the driving circuit shown in Figure 2, the first output node control circuit 12 is also electrically connected to the input terminal STV, the first node N2, the first clock signal terminal CKB, the second clock signal terminal CK and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the first output node N1 and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal CKB and the potential of the first node N2, and to control the connection or disconnection between the first output node N1 and the input terminal STV under the control of the second clock signal provided by the second clock signal terminal CK.

[0129] As shown in Figure 5, based on at least one embodiment of the driving circuit shown in Figure 3, the first output node control circuit 12 is also electrically connected to the input terminal STV, the first node N2, the first clock signal terminal CKB, the second clock signal terminal CK and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the first output node N1 and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal CKB and the potential of the first node N2, and to control the connection or disconnection between the first output node N1 and the input terminal STV under the control of the second clock signal provided by the second clock signal terminal CK.

[0130] In at least one embodiment of the present disclosure, the first output node control circuit is also electrically connected to the third node, the input terminal, the second clock signal terminal, the first node, the first voltage terminal, the first clock signal terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the third node and the input terminal under the control of the second clock signal provided by the second clock signal terminal, control the connection or disconnection between the third node and the first voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal, and control the connection or disconnection between the third node and the first output node under the control of the third voltage signal provided by the third voltage terminal.

[0131] As shown in Figure 6, based on at least one embodiment of the driving circuit shown in Figure 3, the first output node control circuit 12 is also electrically connected to the third node N3, the input terminal STV, the second clock signal terminal CK, the first node N2, the first voltage terminal V1, the first clock signal terminal CKB and the third voltage terminal V3, respectively, and is used to control the connection or disconnection between the third node N3 and the input terminal I1 under the control of the second clock signal provided by the second clock signal terminal CK, control the connection or disconnection between the third node N3 and the first voltage terminal V1 under the control of the potential of the first node N2 and the first clock signal provided by the first clock signal terminal CKB, and control the connection or disconnection between the third node N3 and the first output node N1 under the control of the third voltage signal provided by the third voltage terminal V3.

[0132] In at least one embodiment of the driving circuit shown in Figure 6, the first output node control circuit 12 is directly electrically connected to the third node N3, and is used to control the connection or disconnection between the third node N3 and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal CKB and the potential of the first node N2, and to control the connection or disconnection between the third node N3 and the input terminal STV under the control of the second clock signal provided by the second clock signal terminal CK.

[0133] In at least one embodiment of the driving circuit shown in FIG6 , the first output node may be electrically connected to the third node via a normally-on transistor.

[0134] Optionally, the third voltage end may be the first low voltage end, but is not limited thereto.

[0135] In at least one embodiment of the present disclosure, the driving circuit further includes a first node control circuit;

[0136] The first node control circuit is electrically connected to the first node, the fourth voltage terminal and the first clock signal terminal, respectively, and is used to control the connection or disconnection between the first node and the fourth voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal.

[0137] In a specific implementation, the first node control circuit can also control the connection or disconnection between the first node and the fourth voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal.

[0138] Optionally, the fourth voltage end may be the second low voltage end, but is not limited thereto.

[0139] As shown in FIG7 , based on at least one embodiment of the driving circuit shown in FIG4 , at least one embodiment of the driving circuit further includes a first node control circuit 13 ;

[0140] The first node control circuit 13 is electrically connected to the first node N2, the fourth voltage terminal V4 and the first clock signal terminal CKB, respectively, and is used to control the connection or disconnection between the first node N2 and the fourth voltage terminal V4 under the control of the potential of the first node N2 and the first clock signal provided by the first clock signal terminal CKB.

[0141] As shown in FIG8 , based on at least one embodiment of the driving circuit shown in FIG5 , at least one embodiment of the driving circuit may further include a first node control circuit 13 ;

[0142] The first node control circuit 13 is electrically connected to the first node N2, the fourth voltage terminal V4 and the first clock signal terminal CKB, respectively, and is used to control the connection or disconnection between the first node N2 and the fourth voltage terminal V4 under the control of the potential of the first node N2 and the first clock signal provided by the first clock signal terminal CKB.

[0143] As shown in FIG9 , based on at least one embodiment of the driving circuit shown in FIG6 , at least one embodiment of the driving circuit may further include a first node control circuit 13 ;

[0144] The first node control circuit 13 is electrically connected to the first node N2, the fourth voltage terminal V4 and the first clock signal terminal CKB, respectively, and is used to control the connection or disconnection between the first node N2 and the fourth voltage terminal V4 under the control of the potential of the first node N2 and the first clock signal provided by the first clock signal terminal CKB.

[0145] In at least one embodiment of the present disclosure, the second output node control circuit is also electrically connected to the first output node, the first clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the second output node under the control of the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the second output node and the first voltage terminal under the control of the potential of the first output node.

[0146] In a specific implementation, the second output node control circuit can also control the connection or disconnection between the first node and the second output node under the control of the first clock signal, and control the connection or disconnection between the second output node and the first voltage terminal under the control of the potential of the first output node.

[0147] In at least one embodiment of the present disclosure, the output circuit is further electrically connected to the first voltage terminal and the second voltage terminal respectively;

[0148] The output circuit is used to control the connection or disconnection between the drive output terminal and the second voltage terminal under the control of the potential of the first output node, and to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the potential of the second output node.

[0149] Optionally, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal.

[0150] Optionally, the first output node control circuit includes a sixth transistor, a seventh transistor and an eighth transistor;

[0151] The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal;

[0152] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the first output node;

[0153] A gate of the eighth transistor is electrically connected to the second clock signal terminal, a first electrode of the eighth transistor is electrically connected to the input terminal, and a second electrode of the eighth transistor is electrically connected to the first output node.

[0154] Optionally, the eighth transistor is a dual-gate transistor.

[0155] Optionally, the first output node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor;

[0156] The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal;

[0157] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the third node;

[0158] The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first electrode of the eighth transistor is electrically connected to the input terminal, and the second electrode of the eighth transistor is electrically connected to the third node;

[0159] A gate of the ninth transistor is electrically connected to the third voltage terminal, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is electrically connected to the first output node.

[0160] Optionally, the first node control circuit includes a tenth transistor and an eleventh transistor;

[0161] The gate of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0162] A gate of the eleventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

[0163] Optionally, the second output node control circuit includes a twelfth transistor and a thirteenth transistor;

[0164] The gate of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the second output node;

[0165] A gate of the thirteenth transistor is electrically connected to the first output node, a first electrode of the thirteenth transistor is electrically connected to the first voltage terminal, and a second electrode of the thirteenth transistor is electrically connected to the second output node.

[0166] Optionally, the output circuit includes a fourteenth transistor and a fifteenth transistor;

[0167] The gate of the fourteenth transistor is electrically connected to the first output node, the first electrode of the fourteenth transistor is electrically connected to the driving output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage terminal;

[0168] The gate of the fifteenth transistor is electrically connected to the second output node, the first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the driving output terminal.

[0169] The driving circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit;

[0170] The first end of the third energy storage circuit is electrically connected to the second output node, the third energy storage circuit is electrically connected to the first voltage end respectively, and the third energy storage circuit is used to store electrical energy.

[0171] In a specific implementation, the driving circuit further includes a third energy storage circuit, and the third energy storage circuit is used to maintain the potential of the second output node.

[0172] As shown in FIG10 , based on at least one embodiment of the driving circuit shown in FIG7 , the driving circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit 101 ;

[0173] The second output node control circuit 14 is further electrically connected to the first output node N1, the first clock signal terminal CKB, and the first voltage terminal V1, respectively, and is configured to control the connection or disconnection between the first node N2 and the second output node N4 under the control of the first clock signal provided by the first clock signal terminal CKB, and to control the connection or disconnection between the second output node N4 and the first voltage terminal V1 under the control of the potential of the first output node N1;

[0174] The output circuit 15 is also electrically connected to the first voltage terminal V1 and the second voltage terminal V2 respectively;

[0175] The output circuit 15 is used to control the connection or disconnection between the driving output terminal O1 and the second voltage terminal V2 under the control of the potential of the first output node N1, and to control the connection or disconnection between the driving output terminal O1 and the first voltage terminal V1 under the control of the potential of the second output node N4;

[0176] A first end of the third energy storage circuit 101 is electrically connected to the second output node N4 , a second end of the third energy storage circuit 101 is electrically connected to the first voltage terminal V1 , and the third energy storage circuit 101 is used to store electrical energy.

[0177] As shown in FIG11 , based on at least one embodiment of the driving circuit shown in FIG8 , the driving circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit 101 ;

[0178] The second output node control circuit 14 is further electrically connected to the first output node N1, the first clock signal terminal CKB, and the first voltage terminal V1, respectively, and is configured to control the connection or disconnection between the first node N2 and the second output node N4 under the control of the first clock signal provided by the first clock signal terminal CKB, and to control the connection or disconnection between the second output node N4 and the first voltage terminal V1 under the control of the potential of the first output node N1;

[0179] The output circuit 15 is also electrically connected to the first voltage terminal V1 and the second voltage terminal V2 respectively;

[0180] The output circuit 15 is used to control the connection or disconnection between the driving output terminal O1 and the second voltage terminal V2 under the control of the potential of the first output node N1, and to control the connection or disconnection between the driving output terminal O1 and the first voltage terminal V1 under the control of the potential of the second output node N4;

[0181] The first end of the third energy storage circuit 101 is electrically connected to the second output node N4 , and the third energy storage circuit 101 is electrically connected to the first voltage end V1 . The third energy storage circuit 101 is used to store electrical energy.

[0182] As shown in FIG12 , based on at least one embodiment of the driving circuit shown in FIG9 , the driving circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit 101 ;

[0183] The second output node control circuit 14 is further electrically connected to the first output node N1, the first clock signal terminal CKB, and the first voltage terminal V1, respectively, and is configured to control the connection or disconnection between the first node N2 and the second output node N4 under the control of the first clock signal provided by the first clock signal terminal CKB, and to control the connection or disconnection between the second output node N4 and the first voltage terminal V1 under the control of the potential of the first output node N1;

[0184] The output circuit 15 is also electrically connected to the first voltage terminal V1 and the second voltage terminal V2 respectively;

[0185] The output circuit 15 is used to control the connection or disconnection between the driving output terminal O1 and the second voltage terminal V2 under the control of the potential of the first output node N1, and to control the connection or disconnection between the driving output terminal O1 and the first voltage terminal V1 under the control of the potential of the second output node N4;

[0186] The first end of the third energy storage circuit 101 is electrically connected to the second output node N4 , and the third energy storage circuit 101 is electrically connected to the first voltage end V1 . The third energy storage circuit 101 is used to store electrical energy.

[0187] As shown in FIG13, based on at least one embodiment of the driving circuit shown in FIG10,

[0188] The inverting circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor C0;

[0189] The gate of the first transistor T1 is electrically connected to the first output node N1, the source of the first transistor T1 is electrically connected to the second node N7, and the drain of the first transistor T1 is electrically connected to the high voltage terminal VGH;

[0190] The gate of the second transistor T2 is electrically connected to the first output node N1, the source of the second transistor T2 is electrically connected to the first node N2, and the drain of the second transistor T2 is electrically connected to the high voltage terminal VGH;

[0191] The gate of the third transistor T3 is electrically connected to the second node N7, the source of the third transistor T3 is electrically connected to the low voltage terminal VGL, and the drain of the third transistor T3 is electrically connected to the first node N2;

[0192] A first end of the storage capacitor C0 is electrically connected to the first clock signal terminal CKB, and a second end of the storage capacitor C0 is electrically connected to the second node N7;

[0193] The first output node control circuit includes a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8;

[0194] The gate of the sixth transistor T6 is electrically connected to the first clock signal terminal CKB, and the source of the sixth transistor T6 is electrically connected to the high voltage terminal VGH;

[0195] The gate of the seventh transistor T7 is electrically connected to the first node N2, the source of the seventh transistor T7 is electrically connected to the drain of the sixth transistor T6, and the drain of the seventh transistor T7 is electrically connected to the first output node N1;

[0196] The gate of the eighth transistor T8 is electrically connected to the second clock signal terminal CK, the source of the eighth transistor T8 is electrically connected to the input terminal STV, and the drain of the eighth transistor T8 is electrically connected to the first output node N1;

[0197] The first node control circuit includes a tenth transistor T10 and an eleventh transistor T11;

[0198] The gate of the tenth transistor T10 is electrically connected to the first node N2, the source of the tenth transistor T10 is electrically connected to the second low voltage terminal VGL2, and the drain of the tenth transistor T10 is electrically connected to the source of the eleventh transistor T11;

[0199] The gate of the eleventh transistor T11 is electrically connected to the first clock signal terminal CKB, and the drain of the eleventh transistor T11 is electrically connected to the first node N2;

[0200] The second output node control circuit includes a twelfth transistor T12 and a thirteenth transistor T13;

[0201] The gate of the twelfth transistor T12 is electrically connected to the first clock signal terminal CKB, the source of the twelfth transistor T12 is electrically connected to the first node N2, and the second electrode of the twelfth transistor T12 is electrically connected to the second output node N4;

[0202] The gate of the thirteenth transistor T13 is electrically connected to the first output node N1, the source of the thirteenth transistor T13 is electrically connected to the high voltage terminal VGH, and the drain of the thirteenth transistor T13 is electrically connected to the second output node N4;

[0203] The output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15;

[0204] The gate of the fourteenth transistor T14 is electrically connected to the first output node N1, the source of the fourteenth transistor T14 is electrically connected to the driving output terminal O1, and the drain of the fourteenth transistor T14 is electrically connected to the low voltage terminal VGL;

[0205] The gate of the fifteenth transistor T15 is electrically connected to the second output node N4, the source of the fifteenth transistor T15 is electrically connected to the high voltage terminal VGH, and the drain of the fifteenth transistor T15 is electrically connected to the driving output terminal O1;

[0206] The first energy storage circuit includes a first capacitor C1;

[0207] A first end of the first capacitor C1 is electrically connected to the first output node N1, and a second end of the first capacitor C1 is electrically connected to the driving output terminal O1;

[0208] The third energy storage circuit includes a third capacitor C3;

[0209] A first terminal of the third capacitor C3 is electrically connected to the second output node N4 , and the third capacitor C3 is electrically connected to the high voltage terminal VGH.

[0210] In at least one embodiment of the present disclosure, the voltage value of the second low voltage signal provided by VGL2 may be greater than the voltage value of the first low voltage signal provided by VGL1. For example, the voltage value of the first low voltage signal may be -7V, and the voltage value of the second low voltage signal may be -9V, but the present invention is not limited thereto.

[0211] In at least one embodiment of the driving circuit shown in FIG. 13 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0212] In at least one embodiment of the driving circuit shown in FIG. 13 , the fifth node N5 is a node between T6 and T7 , and the sixth node N6 is a node between T10 and T11 .

[0213] In at least one embodiment of the driving circuit shown in FIG. 13 , T8 may be a dual-gate transistor to reduce leakage of T8 and prevent C1 from leaking through T8 .

[0214] In at least one embodiment of the driving circuit shown in FIG13 , in order to prevent C1 from leaking through T8, a normally-on transistor may be added. The gate of the normally-on transistor may be electrically connected to the low voltage end. The normally-on transistor is disposed between N1 and the gate of T14, which may stabilize the potential of N1 and effectively improve leakage of N1.

[0215] As shown in FIG14 , when at least one embodiment of the driving circuit shown in FIG13 of the present disclosure is in operation, the display cycle includes a first time period S1 , a second time period S2 , a third time period S3 , a fourth time period S4 , a fifth time period S5 and a sixth time period S6 , which are sequentially set;

[0216] In the first time period S1, CK provides a high voltage signal, CKB provides a low voltage signal, STV provides a low voltage signal, the potential of N1 is maintained at a low voltage, as shown in FIG15A , T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, T12 is turned on, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal;

[0217] In the second time period S2, CK provides a low voltage signal, CKB provides a high voltage signal, and STV provides a high voltage signal. As shown in FIG15B , T8 is turned on, the potential of N1 is high voltage, T4 is turned off, T1, T2, and T3 are all turned off, T12 is turned off, T14 and T15 are turned off, and O1 outputs a low voltage signal.

[0218] In the third time period S3, when CK provides a high voltage signal and CKB provides a low voltage signal, STV provides a high voltage signal. As shown in FIG15C , since the potential of the first clock signal provided by CKB decreases from a high voltage to a low voltage, the potential of N7 is low, T3 is turned on, the potential of N2 is low, T10 and T11 are turned on, N2 is connected to VGL2, T12 is turned on, the potential of N4 is low, T15 is turned on, O1 outputs a high voltage signal, T8 is turned off, T6 and T7 are turned on, the potential of N1 is high, and T14 is turned off.

[0219] In the fourth time period S4, when CK provides a low voltage signal, CKB provides a high voltage signal, and STV provides a high voltage signal, as shown in FIG15D , T8 is turned on, the potential of N1 is a high voltage, T14 is turned off, T1 and T2 are turned off, the potential of N7 is a high voltage, T3 is turned off, the potential of N2 is maintained at the first voltage, T10 is turned on, T11 is turned off, T12 is turned off, the potential of N4 is maintained at a low voltage, T15 is turned on, and O1 outputs a high voltage signal;

[0220] In the fifth time period S5, CK provides a low voltage signal, CKB provides a high voltage signal, and STV provides a low voltage signal. As shown in FIG15E , T8 is turned on, the potential of N1 is a low voltage, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, the potential of N2 is a high voltage, T10 and T11 are turned off, T6 and T7 are turned off, T13 is turned on, the potential of N4 is a high voltage, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal.

[0221] In the sixth time period S6, CK provides a high voltage signal, CKB provides a low voltage signal, and STV provides a low voltage signal, as shown in Figure 15F, T8 is turned off, the potential of N1 is maintained at a low voltage, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, the potential of N2 is a high voltage, T10 is turned off, T11 is turned off, T12 is turned on, the potential of N4 is a high voltage, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal.

[0222] As shown in FIG. 14 , when at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is in operation, the falling edge of the driving signal output by O1 has no steps.

[0223] At least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is in operation.

[0224] In the first time period S1, the potential of N1 is low voltage, the potential of N2 is high voltage, the potential of N4 is high voltage, the potential of N5 is high voltage, the potential of N6 is low voltage, and O1 outputs a low voltage signal;

[0225] In the second time period S2, the potential of N1 is high voltage, the potential of N2 is high voltage, the potential of N4 is high voltage, the potential of N5 is high voltage, the potential of N6 is low voltage, and O1 outputs a low voltage signal;

[0226] In the third time period S3, the potential of N1 is high voltage, the potential of N2 is low voltage, the potential of N4 is low voltage, the potential of N5 is high voltage, the potential of N6 is low voltage, and O1 outputs a high voltage signal;

[0227] In the fourth time period S4, the potential of N1 is low voltage, the potential of N2 is high voltage, the potential of N4 is high voltage, the potential of N5 is high voltage, the potential of N6 is low voltage, and O1 outputs a low voltage signal;

[0228] In the fifth time period S5 , the potential of N1 is low voltage, the potential of N2 is high voltage, the potential of N4 is high voltage, the potential of N5 is high voltage, the potential of N6 is high voltage, and O1 outputs a low voltage signal.

[0229] The difference between at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is that:

[0230] Storage capacitor C0 is not included;

[0231] At least one embodiment of the driving circuit shown in FIG16 of the present disclosure further includes a fourth transistor T4;

[0232] The gate of the fourth transistor T4 and the source of the fourth transistor T4 are both electrically connected to the low voltage terminal VGL, and the drain of the fourth transistor T4 is electrically connected to the second node N7;

[0233] T4 is a p-type transistor.

[0234] In at least one embodiment of the driving circuit shown in FIG. 16 , T8 may be a dual-gate transistor to reduce leakage of T8 and prevent C1 from leaking through T8 .

[0235] In at least one embodiment of the driving circuit shown in FIG16 , in order to prevent C1 from leaking through T8, a normally-on transistor may be added. The gate of the normally-on transistor may be electrically connected to the low voltage end. The normally-on transistor is disposed between N1 and the gate of T14, which may stabilize the potential of N1 and effectively improve leakage of N1.

[0236] When at least one embodiment of the driving circuit shown in FIG16 of the present disclosure is in operation, the display cycle includes a first time period, a second time period, a third time period, a fourth time period, a fifth time period, and a sixth time period which are set in sequence;

[0237] In the first time period, CK provides a high voltage signal, CKB provides a low voltage signal, STV provides a low voltage signal, the potential of N1 is maintained at a low voltage, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, T12 is turned on, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal;

[0238] In the second time period, CK provides a low voltage signal, CKB provides a high voltage signal, STV provides a high voltage signal, T8 is turned on, the potential of N1 is high voltage, T4 is turned off, T1 and T2 are turned off, T12 is turned off, T14 and T15 are turned off, and O1 outputs a low voltage signal;

[0239] In the third time period S3, when CK provides a high voltage signal, CKB provides a low voltage signal, STV provides a high voltage signal, the potential of N1 is high, T1 and T2 are off, T4 is on, the potential of N7 is low, T3 is on, the potential of N2 is low, T10 and T11 are on, T12 is on, the potential of N4 is low, T15 is on, O1 outputs a high voltage signal, T8 is off, and T14 is off;

[0240] In the third time period, when CK provides a low voltage signal, CKB provides a high voltage signal, STV provides a high voltage signal, T8 is turned on, the potential of N1 is high voltage, T14 is turned off, T1 and T2 are turned off, T4 is turned on, the potential of N7 is low voltage, T3 is turned on, the potential of N2 is low voltage, T10 is turned on, T11 is turned off, T12 is turned off, the potential of N4 is maintained at low voltage, T15 is turned on, and O1 outputs a high voltage signal;

[0241] In the fourth time period, CK provides a low voltage signal, CKB provides a high voltage signal, STV provides a low voltage signal, T8 is turned on, the potential of N1 is a low voltage, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, the potential of N2 is a high voltage, T10 and T11 are turned off, T6 and T7 are turned off, T13 is turned on, the potential of N4 is a high voltage, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal;

[0242] In the fifth time period, CK provides a high voltage signal, CKB provides a low voltage signal, STV provides a low voltage signal, T8 is turned off, the potential of N1 is maintained at a low voltage, T1 and T2 are turned on, the potential of N7 is a high voltage, T3 is turned off, the potential of N2 is a high voltage, T10 is turned off, T11 is turned off, T12 is turned on, the potential of N4 is a high voltage, T15 is turned off, T14 is turned on, and O1 outputs a low voltage signal.

[0243] FIG. 17 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure.

[0244] In at least one embodiment of the driving circuit shown in Figure 16, the gate of T4 and the source of T4 can also be electrically connected to the first clock signal terminal; or, the gate of T4 and the source of T4 can also be electrically connected to the second clock signal terminal; or, the gate of T4 and the source of T4 can also be electrically connected to the control terminal.

[0245] In at least one embodiment of the present disclosure, the control signal provided by the control terminal may be in phase opposite to the input signal provided by the STV.

[0246] In at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure, when in operation, the falling edge of the driving signal output by O1 has no steps.

[0247] The difference between at least one embodiment of the driving circuit shown in FIG. 18 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is that:

[0248] At least one embodiment of the driving circuit shown in FIG18 of the present disclosure further includes a fifth transistor T5, a second capacitor C2, and a ninth transistor T9; at least one embodiment of the driving circuit shown in FIG18 of the present disclosure does not include C1;

[0249] The gate of the fifth transistor T5 is electrically connected to the first output node N1, the source of the fifth transistor T5 is electrically connected to the first clock signal terminal CKB, and the drain of the fifth transistor T5 is electrically connected to the first end of the second capacitor C2;

[0250] The second end of the second capacitor C2 is electrically connected to the first output node N1;

[0251] The gate of the ninth transistor T9 is electrically connected to the low voltage terminal VGL, the source of the ninth transistor T9 is electrically connected to the third node N3, and the drain of the ninth transistor T9 is electrically connected to the first output node N1;

[0252] The drain of the seventh transistor T7 is electrically connected to the third node N3;

[0253] A drain of the eighth transistor T8 is electrically connected to the third node N3.

[0254] In at least one embodiment of the driving circuit shown in FIG. 18 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0255] In at least one embodiment of the driving circuit shown in FIG. 18 , T9 may not be provided.

[0256] At least one embodiment of the driving circuit shown in FIG18 of the present disclosure adds T5 and C2; each time the potential of the first clock signal provided by CKB drops from a high level to a low level, the potential of N1 will be pulled down, and the driving signal output by O1 will be more stable.

[0257] As shown in FIG19 , at least one embodiment of the driving circuit shown in FIG18 of the present disclosure is in operation.

[0258] In the first time period S1, STV provides a low voltage signal, CK provides a high voltage signal, CKB provides a low voltage signal, the potential of N1 is low voltage, T14 is turned on, and O1 outputs a low voltage signal;

[0259] In the second time period S2, STV provides a high voltage signal, CK provides a low voltage signal, CKB provides a high voltage signal, T8 is turned on, the potential of N1 is a high voltage signal, T1 and T2 are turned off, the potential of N7 is a high voltage signal, T3 is turned off, T12 is turned off, T9 is turned on, T14 and T15 are turned off, and O1 outputs a low voltage signal;

[0260] In the third time period S3, STV provides a high voltage signal, CK provides a high voltage signal, CKB provides a low voltage signal, T8 is turned off, the potential of N1 is maintained at a high voltage signal, T1 and T2 are turned off, the potential of N7 is a low voltage, T3 is turned on, the potential of N2 is a low voltage, T10 and T11 are turned on, T12 is turned on, the potential of N4 is a low voltage, and O1 outputs a high voltage signal;

[0261] In the fourth time period S4, STV provides a low voltage signal, CK provides a high voltage signal, CKB provides a low voltage signal, T8 is turned off, the potential of N1 is maintained at a high voltage signal, T1 and T2 are turned off, the potential of N7 is a low voltage signal, T3 is turned on, the potential of N2 is a low voltage, T10 and T11 are turned on, T12 is turned on, the potential of N4 is a low voltage, T15 is turned on, and O1 outputs a high voltage signal;

[0262] In the fifth time period S5, STV provides a low voltage signal, CK provides a low voltage signal, CKB provides a high voltage signal, T8 is turned on, the potential of N1 is low voltage, T14 is turned on, and O1 outputs a low voltage signal; T1 and T2 are turned on, the potential of N2 is high voltage, T12 is turned off, T13 is turned on, the potential of N4 is high voltage, and T15 is turned on;

[0263] In the sixth time period S6, STV provides a low voltage signal, CK provides a high voltage signal, CKB provides a low voltage signal, T5 is turned on, the potential of N1 is pulled down again by C2 coupling, T14 is turned on, and O1 outputs a low voltage signal.

[0264] The difference between at least one embodiment of the driving circuit shown in FIG. 20 and at least one embodiment of the driving circuit shown in FIG. 18 is that the tenth transistor and the eleventh transistor are not included.

[0265] In a specific implementation, since the inverter circuit can control the potential of N2, at least one embodiment of the driving circuit shown in FIG20 can also work normally without including the tenth transistor and the eleventh transistor.

[0266] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes:

[0267] The inverting circuit inverts the potential of the first output node to obtain the potential of the first node;

[0268] A first output node control circuit controls the potential of the first output node;

[0269] The second output node control circuit obtains the potential of the second output node according to the potential of the first node;

[0270] The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first output node and the potential of the second output node.

[0271] The display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.

[0272] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit, comprising an inverting circuit, a first output node control circuit, a second output node control circuit and an output circuit; The inverting circuit is electrically connected to the first output node and the first node respectively, and is used to invert the potential of the first output node in at least a part of the display period to obtain the potential of the first node; The first output node control circuit is electrically connected to the first output node and is used to control the potential of the first output node; The second output node control circuit is electrically connected to the first node and the second output node respectively, and is used to obtain the potential of the second output node according to the potential of the first node; The output circuit is electrically connected to the first output node, the second output node and the driving output end respectively, and is used to control the driving output end to output a driving signal under the control of the potential of the first output node and the potential of the second output node.

2. The driving circuit according to claim 1, wherein: Also included is a first energy storage circuit; The first energy storage circuit is electrically connected to the first output node and the driving output terminal respectively, and is used for storing electric energy.

3. The driving circuit according to claim 1, wherein: The inverting circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor; The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal; The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal; The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node; The first end of the storage capacitor is electrically connected to the first clock signal end, and the second end of the storage capacitor is electrically connected to the second node.

4. The driving circuit according to claim 1, wherein: The inverter circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor is electrically connected to the first output node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first voltage terminal; The gate of the second transistor is electrically connected to the first output node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the first voltage terminal; The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the first node; The gate of the fourth transistor and the first electrode of the fourth transistor are both electrically connected to the first control terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

5. The driving circuit according to claim 4, wherein: The first control terminal is a second voltage terminal, a first clock signal terminal, a second clock signal terminal or a frame reset terminal.

6. The driving circuit according to claim 1, wherein: Also includes a second energy storage circuit and an on-off control circuit; The on-off control circuit is electrically connected to the first output node, the first clock signal terminal and the first terminal of the second energy storage circuit respectively, and is used to control the connection or disconnection between the first terminal of the second energy storage circuit and the first clock signal terminal under the control of the potential of the first output node; The second end of the second energy storage circuit is electrically connected to the first output node, and the second energy storage circuit is used to store electric energy.

7. The driving circuit according to claim 6, wherein: The on-off control circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor; The gate of the fifth transistor is electrically connected to the first output node, the first electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first terminal of the second capacitor; The second end of the second capacitor is electrically connected to the first output node.

8. The driving circuit according to any one of claims 1 to 7, wherein: The first output node control circuit is also electrically connected to the input terminal, the first node, the first clock signal terminal, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first output node and the first voltage terminal under the control of the first clock signal provided by the first clock signal terminal and the potential of the first node, and to control the connection or disconnection between the first output node and the input terminal under the control of the second clock signal provided by the second clock signal terminal.

9. The driving circuit according to any one of claims 1 to 7, wherein: The first output node control circuit is also electrically connected to the third node, the input terminal, the second clock signal terminal, the first node, the first voltage terminal, the first clock signal terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the third node and the input terminal under the control of the second clock signal provided by the second clock signal terminal, control the connection or disconnection between the third node and the first voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal, and control the connection or disconnection between the third node and the first output node under the control of the third voltage signal provided by the third voltage terminal.

10. The driving circuit according to any one of claims 1 to 7, wherein: The driving circuit also includes a first node control circuit; The first node control circuit is electrically connected to the first node, the fourth voltage terminal and the first clock signal terminal, respectively, and is used to control the connection or disconnection between the first node and the fourth voltage terminal under the control of the potential of the first node and the first clock signal provided by the first clock signal terminal.

11. The driving circuit according to any one of claims 1 to 7, wherein: The second output node control circuit is also electrically connected to the first output node, the first clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the second output node under the control of the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the second output node and the first voltage terminal under the control of the potential of the first output node.

12. The driving circuit according to any one of claims 1 to 7, wherein: The output circuit is also electrically connected to the first voltage terminal and the second voltage terminal respectively; The output circuit is used to control the connection or disconnection between the drive output terminal and the second voltage terminal under the control of the potential of the first output node, and to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the potential of the second output node.

13. The driving circuit according to claim 8, wherein: The first output node control circuit includes a sixth transistor, a seventh transistor and an eighth transistor; The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal; The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the first output node; A gate of the eighth transistor is electrically connected to the second clock signal terminal, a first electrode of the eighth transistor is electrically connected to the input terminal, and a second electrode of the eighth transistor is electrically connected to the first output node.

14. The driving circuit according to claim 13, wherein: The eighth transistor is a dual-gate transistor.

15. The driving circuit according to claim 9, wherein: The first output node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor; The gate of the sixth transistor is electrically connected to the first clock signal terminal, and the first electrode of the sixth transistor is electrically connected to the first voltage terminal; The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is electrically connected to the third node; The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first electrode of the eighth transistor is electrically connected to the input terminal, and the second electrode of the eighth transistor is electrically connected to the third node; A gate of the ninth transistor is electrically connected to the third voltage terminal, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is electrically connected to the first output node.

16. The driving circuit according to claim 10, wherein: The first node control circuit includes a tenth transistor and an eleventh transistor; The gate of the tenth transistor is electrically connected to the first node, the first electrode of the tenth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor; A gate of the eleventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

17. The driving circuit according to claim 11, wherein: The second output node control circuit includes a twelfth transistor and a thirteenth transistor; The gate of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the second output node; The gate of the thirteenth transistor is electrically connected to the first output node, and the first electrode of the thirteenth transistor is electrically connected to the The first voltage terminal is electrically connected, and the second electrode of the thirteenth transistor is electrically connected to the second output node.

18. The driving circuit according to claim 12, wherein: The output circuit includes a fourteenth transistor and a fifteenth transistor; The gate of the fourteenth transistor is electrically connected to the first output node, the first electrode of the fourteenth transistor is electrically connected to the driving output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage terminal; A gate of the fifteenth transistor is electrically connected to the second output node, a first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifteenth transistor is electrically connected to the driving output terminal.

19. The driving circuit according to any one of claims 1 to 6, wherein: Also included is a third tank circuit; The first end of the third energy storage circuit is electrically connected to the second output node, the second end of the third energy storage circuit is electrically connected to the first voltage end, and the third energy storage circuit is used to store electrical energy.

20. A driving method, applied to the driving circuit according to any one of claims 1 to 19, the driving method comprising: The inverting circuit inverts the potential of the first output node to obtain the potential of the first node; A first output node control circuit controls the potential of the first output node; The second output node control circuit obtains the potential of the second output node according to the potential of the first node; The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first output node and the potential of the second output node.

21. A display device comprising the driving circuit according to any one of claims 1 to 19.

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