Preparation method for n-type topcon cell, and n-type topcon cell

Abstract

An N-type TOPCon cell and a preparation method therefor. The method comprises: step 1, using an alkaline solution to perform texturing on an N-type silicon wafer; step 2, performing boron diffusion and laser micro-doping on a front face of the N-type silicon wafer, so as to form a micro-doped region, and then performing diffusion to form a front-face mask; step 3, performing a polishing treatment on a back face of the N-type silicon wafer; step 4, performing three-in-one multi-layer thin film deposition on the back face of the N-type silicon wafer, so as to grow a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer and a back-face mask; step 5, performing high-temperature annealing under preset high-temperature conditions, so as to form a doped polycrystalline silicon layer and to activate doping phosphorus; step 6, cleaning the front-face mask on the front face of the N-type silicon wafer and the back-face mask on the back face of the N-type silicon wafer; step 7, depositing passivation films on the front face and back face of the N-type silicon wafer; and step 8, performing printing and sintering.

Description

Preparation method of N-type TOPCon battery, N-type TOPCon battery Technical Field

[0001] The present invention relates to the technical field of crystalline silicon solar cell processing, and in particular to a preparation method of an N-type TOPCon cell and an N-type TOPCon cell. Background Art

[0002] At present, with the gradual consumption of fossil energy, the development of renewable clean energy such as solar energy is a development trend. Solar cells are electronic devices that use the photovoltaic effect to convert solar energy into electrical energy.

[0003] In some related technologies, the conversion efficiency of photovoltaic cells has not been significantly improved, which is not conducive to the photovoltaic industry's need to continuously reduce production costs. Therefore, how to simplify the process and improve the conversion efficiency of photovoltaic cells is an urgent problem that needs to be solved.

[0004] Summary of the Invention

[0005] To achieve the above object, the present invention discloses a method for preparing an N-type TOPCon battery, comprising: step 1: using an alkaline solution to texture an N-type silicon wafer, so that the weight of the N-type silicon wafer is controlled to be 0.25g-0.45g, and the surface reflectivity of the silicon wafer is controlled to be 7%-10%; step 2: boron diffusion and laser micro-doping are performed on the front side of the N-type silicon wafer to form a micro-doping area, and then diffused to form a front mask; step 3: polishing the back side of the N-type silicon wafer; step 4: performing a three-in-one multi-layer thin film deposition on the back side of the N-type silicon wafer to grow A tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer and a back mask, wherein the thickness of the tunneling silicon oxide thin film layer is less than 2nm, the thickness of the amorphous silicon thin film layer is 50nm-200nm, and the thickness of the back mask is 5nm-30nm; Step 5: Performing high-temperature annealing under preset high-temperature conditions to form a doped polycrystalline silicon layer to activate the doped phosphorus; Step 6: Cleaning the front mask on the front side of the N-type silicon wafer and the back mask on the back side; Step 7: Depositing a passivation film on the front and back sides of the N-type silicon wafer; Step 8: Printing and sintering.

[0006] The present invention also discloses a preparation method of an N-type TOPCon battery, comprising: texturing an N-type silicon wafer; performing boron diffusion and laser micro-doping on the front side of the N-type silicon wafer to form a micro-doped area; re-diffusion on the front side of the N-type silicon wafer to form a front mask; polishing the back side of the N-type silicon wafer; performing three-in-one multi-layer thin film deposition on the back side of the N-type silicon wafer to grow a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer, and a back mask in one process step; performing high-temperature annealing under preset high-temperature conditions to form a doped polycrystalline silicon layer to activate the doped phosphorus; cleaning the front mask on the front side of the N-type silicon wafer and the back mask on the back side; depositing a passivation film on the front and back sides of the N-type silicon wafer; printing, and sintering.

[0007] The present invention also discloses an N-type TOPCon battery, which is an N-type TOPCon battery prepared according to the preparation method of the N-type TOPCon battery disclosed in the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Fig. 1 is a workflow diagram of the present invention.

[0009] FIG2 is a schematic structural diagram of the cleaning equipment of the present invention.

[0010] FIG3 is a schematic structural diagram of a turbulent cleaning unit according to the present invention.

[0011] FIG4 is an enlarged view of the portion labeled A in FIG3 .

[0012] FIG5 is a schematic diagram of the internal structure of the fixing assembly of the present invention.

[0013] FIG6 is a schematic diagram of the battery structure of the present invention.

[0014] Explanation of the accompanying symbols: 1. N-type silicon wafer; 3. Micro-doped region; 4. Aluminum oxide film; 5. Front silicon nitride film; 6. Silver-aluminum grid line; 7. Tunneling silicon oxide thin film layer; 8. Polysilicon layer; 9. Back passivation film; 10. Silver grid line; 11. Ultrasonic cleaning tank; 12. Silicon wafer placement rack; 13. Cleaning seat; 14. Bayonet; 15. Movable beam; 16. Movable trolley; 17. Track; 18. Driving motor; 19. Rotating drum; 20. Vortex plate; 21. Fan-shaped fixing seat; 22. Limiting plate; 23. Action chamber; 24. Center rod; 25. Side connecting rod; 26. Clamping rod; 27. Block; 28. Side mounting shell; 29. ​​Screw; 30. Screw sleeve; 31. Bottom connecting seat; 32. Spring rod; 33. Slot; 34. Rotating rod; 35. Bow-shaped mounting frame; 36. Lever. DETAILED DESCRIPTION

[0015] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] Example 1

[0017] The present invention will be further described below with reference to the accompanying drawings.

[0018] As shown in Figures 1 to 6, a method for preparing an N-type TOPCon battery provided in this embodiment includes the following steps: Step 1: Texturing an N-type silicon wafer using an alkaline solution to control the weight loss of the N-type silicon wafer to 0.25g-0.45g and the surface reflectivity of the silicon wafer to 7%-10%; Step 2: Boron diffusion and laser micro-doping are performed on the front side of the N-type silicon wafer to form a micro-doped area, which is then diffused to form a front mask; Step 3: Polishing the back side of the N-type silicon wafer; Step 4: Three-in-one multi-layer thin film deposition is performed on the back side of the N-type silicon wafer. , grow a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer and a back mask, the thickness of the tunneling silicon oxide thin film layer is less than 2nm, the thickness of the amorphous silicon thin film layer is 50nm-200nm, and the thickness of the back mask is 5nm-30nm; Step 5: Perform high-temperature annealing under preset high-temperature conditions to form a doped polysilicon layer to activate the doped phosphorus; Step 6: Clean the front mask on the front side of the N-type silicon wafer and the back mask on the back side; Step 7: Deposit a passivation film on the front and back sides of the N-type silicon wafer; Step 8: Print and sinter.

[0019] The working principle and beneficial effects of the above technical solution are as follows: The present invention discloses a method for preparing an N-type TOPCon battery, comprising the following steps: texturing of an N-type silicon wafer 1, boron diffusion and laser micro-doping of an emitter, re-diffusion to form a front mask, polishing of the back of the N-type silicon wafer, three-in-one coating (growth of a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer and a back mask on the back of the battery, the three film layers are deposited in the same device), annealing, cleaning of the front and back masks, deposition of a passivation film on the front and back, and printing and sintering to form a battery. The present invention provides a method for preparing an N-type TOPCon battery, which can complete the preparation of a tunneling silicon oxide thin film layer and an amorphous silicon thin film layer in one step, without the need for a complex process of forming a tunneling silicon oxide thin film layer by tubular oxidation and then doping, thereby greatly simplifying the process flow; in addition, the boron diffusion followed by laser micro-doping and re-diffusion in the present invention can greatly improve the doping conditions in the emitter region, which is beneficial to improving battery efficiency.

[0020] The present invention provides a method for preparing an N-type TOPCon battery, which fully utilizes the characteristics of PECVD single-sided coating and the flexibility of growing multiple thin films in a single cavity. The contact passivation structure film layer and the battery mask film layer are completed in a single process step, which can effectively reduce the number of process steps, reduce the consumption of silver paste, and improve the battery efficiency.

[0021] Among them, the three-in-one coating specifically adopts a single-sided deposition PECVD tube or plate equipment to perform three-in-one multi-layer thin film deposition on the back of the N-type silicon wafer to grow a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer and a back mask. The thickness of the tunneling silicon oxide thin film layer is less than 2nm, the doped amorphous silicon thin film layer is an in-situ phosphorus-doped thin film with a thickness of 50nm-200nm, and the thickness of the back mask is 5nm-30nm, and its material is any one of SiONx, SiOx or SiNx.

[0022] Based on the above three-in-one coating process, the following beneficial effects are achieved: (1) the growth of the tunneling silicon oxide thin film layer, the doped amorphous silicon thin film layer and the back mask on the back of the battery is completed in one step. Compared with some related technologies in which the deposition of the tunneling silicon oxide thin film, the intrinsic polycrystalline silicon thin film and the silicon nitride thin film needs to be completed in different equipment, this one-step completion is more advantageous; (2) the number of automated actions such as loading and unloading of the battery is reduced during the preparation process, which will greatly improve the preparation yield; (3) because it is completed in one step, the thermal process and the temperature rise / fall process during the preparation of the battery are reduced, thereby reducing the impact on the battery efficiency.

[0023] In one embodiment, in step 1, the N-type silicon wafer 1 is textured using a KOH or NaOH solution with a mass fraction of 40%-60%, the temperature of the texture treatment is 60° C.-80° C., and the texture time is 400s-600s.

[0024] In one embodiment, in step 2, the process of re-diffusion to form a front mask includes: placing the textured N-type silicon wafer into a quartz boat, pushing the quartz boat into a diffusion furnace quartz furnace tube with an internal temperature of 800°C-900°C, wherein the diffusion furnace quartz furnace tube adopts a low-pressure diffusion method; introducing O2 gas with a flow rate of 1000sccm-5000sccm to perform pre-oxidation before deposition, and the pre-oxidation time is 100s-500s; heating to 850°C-900°C, and evacuating the atmosphere of the diffusion furnace quartz furnace tube to a low pressure state below 100mbar; introducing BCl3 gas with a flow rate of 50sccm-500sccm and BCl3 gas with a flow rate of 200sccm-20 00sccm O2 gas is introduced for the first boron source deposition, and the deposition time is 100s-500s; BCl3 gas with a flow rate of 60sccm-600sccm and O2 gas with a flow rate of 300sccm-3000sccm are introduced for the second boron source deposition, and the deposition time is 100s-500s; the temperature is raised to 950℃-1050℃, and the process of push-in is carried out, and the push-in time is 500s-2000s; after the push-in is completed, 1L-10L nitrogen is introduced and the pressure is backed; the temperature is cooled and the boat is removed: when the temperature drops to 700℃-800℃, the quartz boat is taken out of the quartz furnace tube of the diffusion furnace; wafer unloading: the silicon wafer is removed from the quartz boat; wherein, the square resistance is controlled at 90Ω / m-160Ω / m.

[0025] In one embodiment, in step 2, in the laser micro-doping process, the laser device uses the diffused boron atoms to process the printed grid line area to form a micro-doped area, the laser wavelength is controlled at 500nm-1100nm, the laser power is controlled at 30W-100W, the laser processing speed is 10m / s-50m / s, the laser width acting on the printed grid line area is 50μm-100μm, and the square resistance of the laser area after laser micro-doping is 70Ω / m-120Ω / m.

[0026] The process of re-diffusion to form a front mask includes: loading the textured N-type silicon wafer into a quartz boat, pushing the quartz boat into a diffusion furnace quartz tube with an internal temperature of 950-1100°C, the diffusion furnace quartz tube adopts a low-pressure diffusion method, and is evacuated by a vacuum pump to make the diffusion furnace quartz tube atmosphere a low-pressure state below 100mbar; introducing O2 gas with a flow rate of 10000sccm-50000sccm, the deposition time is 3000s-6000s, oxidation to form a front mask, and the thickness of the front mask is 60nm-120nm; after the oxide layer mask is completed, 1L-20L nitrogen is introduced to back pressure; cooling and taking out the boat: when the temperature drops to 700℃-800℃, the quartz boat is taken out of the diffusion furnace quartz tube; unloading the wafer: the silicon wafer is removed from the quartz boat.

[0027] In one embodiment, in step 3, the back side of the N-type silicon wafer is polished using 2-3 parts of an alkali metal hydroxide solution having a mass fraction of 40%-60% and 1 part of a polishing additive. The polishing temperature is 50° C.-70° C., and the polishing time is 100 s-300 s. The slightly doped region 3 on the front side of the N-type silicon wafer is protected from polishing by a front mask.

[0028] In one example, in step 4, in a tubular PECVD furnace tube with a low frequency power of 20KHz-50KHz, the temperature is 300°C-500°C, and laughing gas with a flow rate of 5000sccm-15000sccm is introduced. The laughing gas is ionized into a plasma to oxidize the back side of the N-type silicon wafer to form a silicon dioxide layer. The thickness of the silicon dioxide layer is controlled to be 0.5nm-2.5nm; in the process of depositing the doped amorphous silicon thin film layer on the back side, in a tubular PECVD furnace tube with a low frequency power of 20KHz-50KHz, the temperature is 300°C-500°C, the silane flow rate is 500sccm-5000sccm, and the phosphine flow rate is 100sccm-5000sccm. At the same time, hydrogen is introduced as a catalyst gas to prepare the doped amorphous silicon thin film layer. The concentration of phosphorus doping is 1E19 / cm3-1E21 / cm3, and the thickness of the doped amorphous silicon thin film layer is 20nm-200nm.

[0029] In one embodiment, in step 4, in the process of preparing the back mask, in a tubular PECVD furnace tube with a low-frequency power of 20KHz-50KHz, the temperature is 300°C-500°C, nitrous oxide with a flow rate of 2000sccm-10000sccm and a silane flow rate of 500sccm-5000sccm are introduced, and plasma deposition is performed to form a back mask, and the thickness of the back mask is controlled to be 3nm-8nm.

[0030] In one embodiment, the tunneling silicon oxide film layer 7, the polysilicon layer 8, and the back mask are deposited in the same process step using PECVD.

[0031] In one embodiment, in step 5, nitrogen gas is introduced and high-temperature annealing is performed under high-temperature conditions to form a doped polysilicon layer to activate the doped phosphorus. The nitrogen flow rate is controlled at 10,000 sccm-50,000 sccm, the high-temperature annealing temperature is 800°C-1000°C, and the high-temperature annealing time is 3,000s-6,000s.

[0032] In one embodiment, in step 6, in a cleaning device, a HF solution with a mass fraction of 30%-60% is used and a cleaning temperature of 20°C-50°C is used to perform a cleaning process to remove the front mask on the front side of the N-type silicon wafer and the back mask on the back side of the N-type silicon wafer. The cleaning process time is 100s-500s. As shown in Figures 2 and 3, the cleaning device includes an ultrasonic cleaning tank 11, a plurality of turbulent cleaning units movably mounted at the slot end of the ultrasonic cleaning tank 11, and two sets of silicon wafer placement racks 12 are mounted on the turbulent cleaning units in opposite directions through a fixing component.

[0033] The working principle and beneficial effects of the above technical solution are as follows: the silicon wafer is placed on the silicon wafer placement rack 12, the hand-held fixing component is installed on the turbulent cleaning unit, the ultrasonic cleaning tank 11 is filled with an HF solution with a mass fraction of 30%-60%, the silicon wafer placement rack 12 is immersed in the HF solution, the ultrasonic cleaning tank 11 works and the turbulent cleaning unit to quickly complete the cleaning and removal of the oxide layer mask on the front and back sides of the silicon wafer.

[0034] In one embodiment, as shown in Figures 2 and 3, the turbulent cleaning unit includes: a cleaning seat 13, the side ends of the cleaning seat 13 are evenly provided with bayonet holes 14 for facilitating the clamping of fixed components, the top of the cleaning seat 13 is symmetrically installed with a movable beam 15, the movable beam 15 is installed with a movable trolley 16 at the end away from the cleaning seat 13, and the notch end of the ultrasonic cleaning tank 11 is installed with a track 17 for facilitating the movement of the movable trolley 16; a drive motor 18, the drive motor 18 is installed at the top of the cleaning seat 13; a rotating drum 19, the bottom end of the rotating drum 19 is open, the output end of the drive motor 18 passes through the cleaning seat 13 and is connected to the top of the rotating drum 19, the surface of the rotating drum 19 is evenly distributed with hollow holes, and a vortex plate 20 is spirally installed.

[0035] The working principle and beneficial effects of the above technical solution are as follows: the movable trolley 16 works, thereby driving the cleaning seat 13 to move along the track 17 in the ultrasonic cleaning tank 11 through the movable beam 15, thereby achieving uniform distribution of the silicon wafer placement rack 12 in the ultrasonic cleaning tank 11, and the drive motor 18 works, thereby driving the rotating drum 19 installed at the output end of the drive motor 18 to rotate at the bottom end of the cleaning seat 13, and the vortex plate 20 installed on the surface of the rotating drum 19 drives the HF solution to rotate in a vortex, washing the silicon wafers placed in the silicon wafer placement rack 12, thereby quickly completing the cleaning and removal of the oxide layer mask on the front and back sides of the silicon wafers.

[0036] In one embodiment, as shown in Figures 3, 4 and 5, the fixing assembly includes: a fan-shaped fixing seat 21, the top of the fan-shaped fixing seat 21 is provided with a card slot for facilitating the clamping of the side end of the cleaning seat 13, the slot end is covered with a limit plate 22 clamped with the top of the cleaning seat 13, and the silicon wafer placement rack 12 is installed at the bottom end of the fan-shaped fixing seat 21 through a connecting assembly; an action chamber 23, the action chamber 23 is located in the fan-shaped fixing seat 21, the action chamber 23 is composed of a bottom chamber and a side chamber, the bottom chamber is located at the bottom of the card slot, the two side chambers are symmetrically arranged with the card slot as the center, and the two side mounting shells 28 are symmetrically installed on the fan-shaped fixing seat 21 and are connected to the side chamber; a center rod 24, the center rod 24 is located in the bottom chamber Inside, the connecting assembly extends into the bottom chamber and is connected to the center rod 24; the side connecting rod 25, the two side connecting rods 25 are respectively hinged at both ends of the center rod 24; the clamping rod 26, the clamping rod 26 is bent at an obtuse angle and is located in the side chamber, one end of the clamping rod 26 is rotatably installed in the action chamber 23 through a rotating shaft, and the other end of the clamping rod 26 is installed with a block 27 that adapts to the bayonet 14, and the other end of the clamping rod 26 extends into the side mounting shell 28; the screw 29, the screw 29 extends into the bottom chamber from the fan-shaped fixing seat 21 away from the slot position, and is rotatably installed on the center rod 24, and the fan-shaped fixing seat 21 is fixedly installed with a screw sleeve 30 sleeved on the screw 29 away from the slot position.

[0037] The working principle and beneficial effects of the above technical solution are as follows: a silicon wafer is placed on the silicon wafer placement rack 12, and the fan-shaped fixing seat 21 is carried by hand. The fan-shaped fixing seat 21 is clamped to the side end of the cleaning seat 13 by using the card slot. The screw 29 is manually rotated, thereby driving the screw 29 to rotate in the screw sleeve 30. The screw 29 pulls the center rod 24 located in the bottom chamber to move toward the screw sleeve 30. The center rod 24 pulls the clamping rod 26 located in the side chamber through the side connecting rod 25, and the block 27 installed on the clamping rod 26 is clamped on the bayonet 14 at the side end of the cleaning seat 13, thereby completing the fixing of the fan-shaped fixing seat 21 on the cleaning seat 13. When the silicon wafer cleaning is completed, the screw 29 is rotated in the opposite direction to release the connection between the fan-shaped fixing seat 21 and the cleaning seat 13. At this time, the fan-shaped fixing seat 21 is manually lifted to lift the silicon wafer placement rack 12 out of the ultrasonic cleaning tank 11. In this way, the disassembly and assembly of the fan-shaped fixing seat 21 and the cleaning seat 13 can be completed quickly.

[0038] In one embodiment, as shown in Figures 3, 4, and 5, the connecting assembly includes: a bottom connecting seat 31, the top of the bottom connecting seat 31 is hinged to the bottom end of the fan-shaped fixing seat 21 through two symmetrically arranged spring rods 32, and the silicon wafer placement rack 12 is installed at the bottom end of the bottom connecting seat 31; a card slot 33, the card slot 33 is opened through the bottom connecting seat 31; a rotating rod 34, the middle section of the rotating rod 34 is arranged as a square rod, and is slidably connected in the card slot 33, and the two ends of the rotating rod 34 are rotatably installed on the bow-shaped mounting bracket 35, and the bow-shaped mounting bracket 35 extends into the bottom chamber away from the end of the rotating rod 34 and is connected to the center rod 24; a dial plate 36, and the dial plate 36 is vertically installed at both ends of the rotating rod 34.

[0039] The working principle and beneficial effects of the above technical solution are as follows: when the fan-shaped fixing seat 21 needs to be fixed on the cleaning seat 13, the screw 29 is manually rotated, thereby driving the screw 29 to rotate in the screw sleeve 30, and the screw 29 pulls the center rod 24 located in the bottom chamber to move toward the direction close to the screw sleeve 30, and the center rod 24 drives the bow-shaped mounting bracket 35 connected thereto and the rotating rod 34 installed on the bow-shaped mounting bracket 35 to move toward the direction close to the screw sleeve 30. As shown in Figure 4, the rotating rod 34 moves in the slot 33 toward the left end of the slot 33, and the rotating rod 34 is eccentrically located at the left end of the slot 33, driving the rotating drum 19 at the output end of the motor 18 to rotate at the bottom end of the cleaning seat 13, and installing The vortex plate 20 on the surface of the rotating drum 19 drives the HF solution to rotate in a vortex, which impacts the silicon wafers placed in the silicon wafer placement rack 12 and at the same time impacts the paddles 36 vertically mounted at both ends of the rotating rod 34. The paddles 36 drive the rotating rod 34 to rotate on the bow-shaped mounting frame 35. The middle section of the rotating rod 34 is arranged as a square rod. When the rotating rod 34 rotates, it cooperates with the slot 33 to drive the bottom connecting seat 31 to flip at a small angle away from the rotating drum 19, that is, the spring rod 32 at the right end of the bottom connecting seat 31 is stretched, and the spring rod 32 at the left end of the bottom connecting seat 31 is contracted, so that the bottom connecting seat 31 is oscillated at a small angle to accelerate the shedding of the oxide layer on the front and back sides of the silicon wafers.

[0040] In one embodiment, as shown in FIG5 , a handle is installed on the limiting plate 22 , and a rotating handle is installed on the screw rod 29 .

[0041] In one embodiment, in step 7, the front passivation film is composed of an aluminum oxide film 4 and a front silicon nitride film 5 stacked together, the aluminum oxide passivation film is deposited by self-catalytic reaction of trimethylaluminum and water, and the thickness of the aluminum oxide passivation film is controlled at 3nm-15nm; the silicon nitride passivation film is deposited by PECVD using silane and ammonia ionization, and the thickness of the front passivation film is controlled at 60nm-100nm; the back passivation film 9 is composed of a back silicon nitride film, and the thickness of the back passivation film 9 is controlled at 70nm-110nm.

[0042] In one embodiment, in step 8, a positive electrode silver-aluminum grid line 6 is printed on the front of the N-type silicon wafer using silver-aluminum paste, and a negative electrode silver grid line 10 is printed on the back of the N-type silicon wafer using silver paste, and then dried and sintered to obtain an N-type TOPCon battery. The silver-aluminum paste can form a good metal contact with the micro-doped area, and the silver paste can be sintered to the polysilicon layer to form a good passivation metal contact. The sintering temperature is 500°C-900°C.

[0043] Example 2

[0044] As shown in Figures 1 to 6, this embodiment provides a method for preparing an N-type TOPCon cell, including: texturing an N-type silicon wafer; performing boron diffusion and laser micro-doping on the front side of the N-type silicon wafer to form a micro-doped region; re-diffusion on the front side of the N-type silicon wafer to form a front mask; polishing the back side of the N-type silicon wafer; performing a three-in-one multi-layer thin film deposition on the back side of the N-type silicon wafer to grow a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer, and a back mask in one process step; performing high-temperature annealing under preset high-temperature conditions to form a doped polycrystalline silicon layer to activate the doped phosphorus; cleaning the front mask on the front side of the N-type silicon wafer and the back mask on the back side; depositing a passivation film on the front and back sides of the N-type silicon wafer; printing, and sintering.

[0045] The method for preparing an N-type TOPCon cell disclosed in this embodiment can complete the preparation of a tunneling silicon oxide thin film layer, an amorphous silicon thin film layer, and a back mask in a single process step, greatly simplifying the process flow. In this embodiment, boron diffusion, laser micro-doping, and re-diffusion are sequentially performed on the front side of the N-type silicon wafer, which can greatly improve the doping conditions in the emitter region and is beneficial to improving cell efficiency.

[0046] In one embodiment, the thickness of the tunneling silicon oxide film layer is less than 2 nm; the doped amorphous silicon film layer is an in-situ phosphorus-doped film with a thickness of 50 nm-200 nm; the thickness of the back mask is 5 nm-30 nm, and its material is any one of SiONx, SiOx or SiNx.

[0047] In this embodiment, the preparation of the tunneling silicon oxide thin film layer, the amorphous silicon thin film layer, and the back mask is completed through a single process step, which has the following beneficial effects: (1) the process flow is simplified; (2) the number of automated actions such as loading and unloading the wafer during battery preparation is reduced, which can greatly improve the preparation yield; (3) the thermal process and the temperature rise / fall process during battery preparation are reduced, thereby reducing the impact on battery efficiency.

[0048] In one embodiment, in the process of texturing an N-type silicon wafer, a KOH or NaOH solution with a mass fraction of 40%-60% is used for texturing, the texturing temperature is 60° C.-80° C., and the texturing time is 400s-600s.

[0049] After texturing treatment, the weight loss of N-type silicon wafer is controlled at 0.25g-0.45g, and the surface reflectivity of the silicon wafer is controlled at 7%-10%.

[0050] In one embodiment, the process of re-diffusion to form a front mask includes: introducing O2 gas with a flow rate of 1000sccm-5000sccm at a temperature of 800°C-900°C to pre-oxidize the N-type silicon wafer for a pre-oxidation time of 100s-500s; introducing BCl3 gas with a flow rate of 50-500sccm and O2 gas with a flow rate of 200sccm-2000sccm at a temperature of 850°C-900°C and an atmosphere of less than 100mbar to perform a first boron source deposition for a deposition time of 10s-100s. The process is as follows: the first step is to introduce BCl3 gas with a flow rate of 60sccm-600sccm and O2 gas with a flow rate of 300sccm-3000sccm to carry out the second boron source deposition, and the deposition time is 100s-500s; the process is pushed in an environment with a temperature of 950℃-1050℃, and the push-in time is 500s-2000s; 1L-10L nitrogen is introduced and the pressure is backed; the temperature is lowered and the boat is removed: when the temperature drops to 700℃-800℃, the quartz boat containing the N-type silicon wafer is taken out; the wafer is unloaded: the N-type silicon wafer is removed from the quartz boat.

[0051] In one embodiment, the laser micro-doping process includes: utilizing diffused boron atoms to perform laser micro-doping on the printed grid line region to form a micro-doped region, wherein the laser wavelength is 500 nm to 1100 nm, the laser power is 30 W to 100 W, the laser processing speed is 10 m / s to 50 m / s, and the laser width acting on the printed grid line region is 50 μm to 100 μm. After laser micro-doping, the sheet resistance of the laser region is 70 Ω / m to 120 Ω / m.

[0052] The process of re-diffusion to form a front mask includes: introducing O2 gas with a flow rate of 10,000 sccm-50,000 sccm and a deposition time of 3,000 s-6,000 s in an environment with a temperature of 950°C-1100°C and an atmosphere of less than 100 mbar to form a front mask; introducing 1L-20L nitrogen gas and back pressure; cooling and removing from the boat: when the temperature drops to 700°C-800°C, the quartz boat containing the N-type silicon wafer is taken out; and unloading the wafer: the N-type silicon wafer is removed from the quartz boat.

[0053] In one embodiment, the process of polishing the back side of an N-type silicon wafer includes: polishing the back side of the N-type silicon wafer using 2-3 parts of an alkali metal hydroxide solution having a mass fraction of 40%-60% and 1 part of a polishing additive, wherein the polishing temperature is 50° C.-70° C. and the polishing time is 100 s-300 s.

[0054] In one embodiment, the process of growing a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer, and a back mask through one process step includes: using PECVD to prepare the tunneling silicon oxide thin film layer, the doped amorphous silicon thin film layer, and the back mask in one process step.

[0055] In this embodiment, the PECVD equipment may be a PECVD tube-type equipment or a PECVD plate-type equipment.

[0056] In this embodiment, the PECVD method is used to prepare the tunneling silicon oxide thin film layer, the doped amorphous silicon thin film layer, and the back mask in one process step, which fully utilizes the characteristics of the PECVD equipment for single-sided coating and the flexibility to grow multiple thin films in a single cavity. It can effectively reduce the number of process steps, reduce the consumption of silver paste, and improve battery efficiency.

[0057] In one embodiment, a process for preparing a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer, and a back mask in one process step using a PECVD method includes: in a PECVD device, the temperature is 300° C.-500° C., and nitrous oxide is introduced at a flow rate of 5000 sccm-15000 sccm. The nitrous oxide is ionized into plasma to oxidize the back side of an N-type silicon wafer to form a tunneling silicon oxide thin film layer. The thickness of the tunneling silicon oxide thin film layer is 0.5 nm-2.5 nm; in the PECVD device, the temperature is 300° C.-500° C., The silane flow rate is 500sccm-5000sccm, the phosphine flow rate is 100sccm-5000sccm, and hydrogen is introduced to form a doped amorphous silicon thin film layer. The phosphorus doping concentration is 1E19 / cm3-1E21 / cm3, and the thickness of the doped amorphous silicon thin film layer is 20nm-200nm; in the PECVD equipment, the temperature is 300℃-500℃, and nitrous oxide with a flow rate of 2000sccm-10000sccm and silane with a flow rate of 500sccm-5000sccm are introduced to form a back mask. The thickness of the back mask is controlled at 3nm-8nm.

[0058] In one embodiment, high-temperature annealing is performed under preset high-temperature conditions to form a doped polysilicon layer. During the process of activating the doped phosphorus, nitrogen is introduced, and the nitrogen flow rate is controlled at 10,000 sccm-50,000 sccm. The high-temperature annealing temperature is 800°C-1000°C, and the high-temperature annealing time is 3,000s-6,000s.

[0059] In one embodiment, the process of cleaning the front mask on the front side and the back mask on the back side of an N-type silicon wafer includes: in a cleaning device, using an HF solution with a mass fraction of 30%-60% to perform a cleaning treatment to remove the front mask on the front side and the back mask on the back side of the N-type silicon wafer, the cleaning temperature is 20°C-50°C, and the cleaning time is 100s-500s; wherein, as shown in Figures 2 and 3, the cleaning device includes an ultrasonic cleaning tank, a plurality of turbulent cleaning units are movably mounted at the slot end of the ultrasonic cleaning tank, and two sets of silicon wafer placement racks are mounted opposite to each other on the turbulent cleaning units.

[0060] In one embodiment, as shown in Figures 2 and 3, the turbulent cleaning unit includes: a cleaning seat 13, the side ends of the cleaning seat 13 are evenly provided with bayonet holes 14 for facilitating the clamping of fixed components, the top of the cleaning seat 13 is symmetrically installed with a movable beam 15, the movable beam 15 is installed with a movable trolley 16 at the end away from the cleaning seat 13, and the notch end of the ultrasonic cleaning tank 11 is installed with a track 17 for facilitating the movement of the movable trolley 16; a drive motor 18, the drive motor 18 is installed at the top of the cleaning seat 13; a rotating drum 19, the bottom end of the rotating drum 19 is open, the output end of the drive motor 18 passes through the cleaning seat 13 and is connected to the top of the rotating drum 19, the surface of the rotating drum 19 is evenly distributed with hollow holes, and a vortex plate 20 is spirally installed.

[0061] In one embodiment, as shown in Figures 3, 4 and 5, the fixing assembly includes: a fan-shaped fixing seat 21, the top of the fan-shaped fixing seat 21 is provided with a card slot for facilitating the clamping of the side end of the cleaning seat 13, the slot end is covered with a limit plate 22 clamped with the top of the cleaning seat 13, and the silicon wafer placement rack 12 is installed at the bottom end of the fan-shaped fixing seat 21 through a connecting assembly; an action chamber 23, the action chamber 23 is located in the fan-shaped fixing seat 21, the action chamber 23 is composed of a bottom chamber and a side chamber, the bottom chamber is located at the bottom of the card slot, the two side chambers are symmetrically arranged with the card slot as the center, and the two side mounting shells 28 are symmetrically installed on the fan-shaped fixing seat 21 and are connected to the side chamber; a center rod 24, the center rod 24 is located in the bottom chamber Inside, the connecting assembly extends into the bottom chamber and is connected to the center rod 24; the side connecting rod 25, the two side connecting rods 25 are respectively hinged at both ends of the center rod 24; the clamping rod 26, the clamping rod 26 is bent at an obtuse angle and is located in the side chamber, one end of the clamping rod 26 is rotatably installed in the action chamber 23 through a rotating shaft, and the other end of the clamping rod 26 is installed with a block 27 that adapts to the bayonet 14, and the other end of the clamping rod 26 extends into the side mounting shell 28; the screw 29, the screw 29 extends into the bottom chamber from the fan-shaped fixing seat 21 away from the slot position, and is rotatably installed on the center rod 24, and the fan-shaped fixing seat 21 is fixedly installed with a screw sleeve 30 sleeved on the screw 29 away from the slot position.

[0062] In one embodiment, as shown in Figures 3, 4, and 5, the connecting assembly includes: a bottom connecting seat 31, the top of the bottom connecting seat 31 is hinged to the bottom end of the fan-shaped fixing seat 21 through two symmetrically arranged spring rods 32, and the silicon wafer placement rack 12 is installed at the bottom end of the bottom connecting seat 31; a card slot 33, the card slot 33 is opened through the bottom connecting seat 31; a rotating rod 34, the middle section of the rotating rod 34 is arranged as a square rod, and is slidably connected in the card slot 33, and the two ends of the rotating rod 34 are rotatably installed on the bow-shaped mounting bracket 35, and the bow-shaped mounting bracket 35 extends into the bottom chamber away from the end of the rotating rod 34 and is connected to the center rod 24; a dial plate 36, and the dial plate 36 is vertically installed at both ends of the rotating rod 34.

[0063] In one embodiment, as shown in FIG5 , a handle is installed on the limiting plate 22 , and a rotating handle is installed on the screw rod 29 .

[0064] In one embodiment, in the process of depositing a passivation film on the front and back sides of an N-type silicon wafer, the front passivation film is composed of an aluminum oxide film 4 and a front silicon nitride film 5 stacked together. The aluminum oxide passivation film is deposited by self-catalytic reaction of trimethylaluminum and water, and the thickness of the aluminum oxide passivation film is controlled at 3nm-15nm; the silicon nitride passivation film is deposited by PECVD using silane and ammonia ionization, and the thickness of the front passivation film is controlled at 60nm-100nm; the back passivation film 9 is composed of a back silicon nitride film, and the thickness of the back passivation film 9 is controlled at 70nm-110nm.

[0065] In one embodiment, during the printing and sintering process, silver-aluminum paste is used to print the positive electrode silver-aluminum grid line 6 on the front of the N-type silicon wafer, and silver paste is used to print the negative electrode silver grid line 10 on the back of the N-type silicon wafer, and then dried and sintered to obtain an N-type TOPCon battery. The silver-aluminum paste can form a good metal contact with the micro-doped area, and the silver paste can be sintered to the polysilicon layer to form a good passivation metal contact. The sintering temperature is 500°C-900°C.

[0066] Example 3

[0067] As shown in FIG6 , this embodiment provides an N-type TOPCon battery. The N-type TOPCon battery is an N-type TOPCon battery manufactured according to the method for manufacturing the N-type TOPCon battery in the above embodiment.

[0068] In one embodiment, the N-type TOPCon cell includes an N-type silicon wafer 1, and a tunneling silicon oxide thin film layer 7, a doped polysilicon layer 8, and a back passivation film 9 are sequentially provided on the back side of the N-type silicon wafer 1; the thickness of the tunneling silicon oxide thin film layer 7 is less than 2nm, the thickness of the polysilicon layer 8 is 20nm-200nm, and the thickness of the back passivation film 9 is 70nm-110nm.

[0069] In one embodiment, the front side of the N-type silicon wafer 1 includes a slightly doped region 3, and the square resistance of the slightly doped region 3 is 70Ω / m-120Ω / m; the front side of the N-type silicon wafer 1 also includes a front passivation film, which is composed of an aluminum oxide film 4 and a front silicon nitride film 5 stacked together, and the thickness of the front passivation film is 60nm-100nm.

[0070] In one embodiment, the N-type TOPCon cell further includes a silver-aluminum grid line 6 disposed on the front surface of the N-type silicon wafer 1 and a silver grid line 10 disposed on the back surface of the N-type silicon wafer 1 .

[0071] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A method for preparing an N-type TOPCon battery, comprising: Step 1: Use an alkaline solution to texturize the N-type silicon wafer so that the weight loss of the N-type silicon wafer is controlled within 0.25g-0.45g and the surface reflectivity of the silicon wafer is controlled within 7%-10%; Step 2: Boron diffusion and laser micro-doping are performed on the front side of the N-type silicon wafer to form a micro-doped area, and then diffused to form a front mask; Step 3: Polishing the back side of the N-type silicon wafer; Step 4: performing three-in-one multilayer thin film deposition on the back side of the N-type silicon wafer to grow a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer and a back mask, wherein the thickness of the tunneling silicon oxide thin film layer is less than 2nm, the thickness of the amorphous silicon thin film layer is 50nm-200nm, and the thickness of the back mask is 5nm-30nm; Step 5: performing high temperature annealing under a preset high temperature condition to form a doped polysilicon layer to activate the doped phosphorus; Step 6: Clean the front mask on the front side of the N-type silicon wafer and the back mask on the back side; Step 7: Deposit a passivation film on the front and back sides of the N-type silicon wafer; Step 8: Printing and sintering.

2. The preparation method according to claim 1, wherein In step 2, the process of re-diffusion to form a front mask includes: Put the textured N-type silicon wafer into a quartz boat, and push the quartz boat into a diffusion furnace quartz tube with an internal temperature of 800°C-900°C, wherein the diffusion furnace quartz tube adopts a low-pressure diffusion method; Passing O2 gas with a flow rate of 1000sccm-5000sccm for pre-oxidation before deposition, the pre-oxidation time is 100s-500s; The temperature is raised to 850℃-900℃, and a vacuum pump is used to evacuate the atmosphere of the diffusion furnace quartz furnace tube to a low pressure state below 100mbar; BCl3 gas with a flow rate of 50 sccm-500 sccm and O2 gas with a flow rate of 200 sccm-2000 sccm are introduced to perform the first boron source deposition, and the deposition time is 100 s-500 s; BCl3 gas with a flow rate of 60 sccm-600 sccm and O2 gas with a flow rate of 300 sccm-3000 sccm are introduced to perform a second boron source deposition, and the deposition time is 100 s-500 s; Raise the temperature to 950℃-1050℃ and carry out the process of pushing and bonding. The pushing and bonding time is 500s-2000s; After the knot is pushed, 1L-10L of nitrogen is introduced to back-pressure; Cooling down and taking out the boat: When the temperature drops to 700℃-800℃, take the quartz boat out of the quartz furnace tube of the diffusion furnace; Unloading: Remove the N-type silicon wafer from the quartz boat; Among them, the square resistance is controlled in 90Ω / m-160Ω / m.

3. The preparation method according to claim 1, wherein In step 2, in the laser micro-doping process, the laser device uses the diffused boron atoms to process the printed grid line area to form a micro-doped area, the laser wavelength is controlled at 500nm-1100nm, the laser power is controlled at 30W-100W, the laser processing speed is 10m / s-50m / s, the laser width acting on the printed grid line area is 50μm-100μm, and the laser area square resistance after laser micro-doping is 70Ω / m-120Ω / m; The process of re-diffusion to form a front mask includes: The N-type silicon wafers to be textured are loaded into a quartz boat, and the quartz boat is pushed into a diffusion furnace quartz tube with an internal temperature of 950℃-1100℃. The diffusion furnace quartz tube adopts a low-pressure diffusion method and is evacuated by a vacuum pump to make the atmosphere of the diffusion furnace quartz tube a low-pressure state below 100mbar. O2 gas with a flow rate of 10000sccm-50000sccm is introduced, and the deposition time is 3000s-6000s to oxidize and form a front mask with a thickness of 60nm-120nm; After the oxide layer mask is completed, 1L-20L nitrogen is introduced to back-pressure; Cooling down and taking out the boat: When the temperature drops to 700℃-800℃, take the quartz boat out of the quartz furnace tube of the diffusion furnace; Unloading: Remove the N-type silicon wafer from the quartz boat.

4. The preparation method according to claim 1, wherein In step 3, the back side of the N-type silicon wafer is polished using 2-3 parts of a 40%-60% alkali metal hydroxide solution and 1 part of a polishing additive, the polishing temperature is 50° C.-70° C., and the polishing time is 100s-300s; The slightly doped area on the front side of the N-type silicon wafer is protected by a front mask and is not polished.

5. The preparation method according to any one of claims 1 to 4, wherein: In step 4, in a furnace tube with a tubular PECVD low-frequency power of 20KHz-50KHz, the temperature is 300°C-500°C, and laughing gas with a flow rate of 5000sccm-15000sccm is introduced, and the laughing gas is ionized into plasma to oxidize the back side of the N-type silicon wafer to form a silicon dioxide layer, and the thickness of the silicon dioxide layer is controlled to be 0.5nm-2.5nm; in the process of back-depositing doped amorphous silicon thin film layer, in a furnace tube with a tubular PECVD low-frequency power of 20KHz-50KHz, the temperature is 300°C-500°C, the silane flow rate is 500sccm-5000sccm, and the phosphine flow rate is 100sccm-5000sccm, and hydrogen is introduced as a catalyst gas at the same time to prepare the doped amorphous silicon thin film layer, the concentration of phosphorus doping is 1E19 / cm3-1E21 / cm3, and the thickness of the amorphous silicon thin film layer is 20nm-200nm.

6. The preparation method according to any one of claims 1 to 4, wherein: In step 6, in the cleaning equipment, a HF solution with a mass fraction of 30%-60% is used for cleaning treatment to remove the front mask on the front side of the N-type silicon wafer and the back mask on the back side of the N-type silicon wafer. The cleaning temperature is 20°C-50°C and the cleaning time is 100s-500s. The cleaning equipment includes an ultrasonic cleaning tank, a plurality of turbulent cleaning units are movably installed at the slot end of the ultrasonic cleaning tank, and two sets of silicon wafer placement racks are installed on the turbulent cleaning units opposite to each other through a fixed component.

7. The preparation method according to claim 6, wherein: The turbulent cleaning unit includes: a cleaning seat, the side ends of the cleaning seat are evenly provided with snap-ons for facilitating the fixing of components, movable beams are symmetrically installed on the top of the cleaning seat, a movable trolley is installed on the end of the movable beam away from the cleaning seat, a track is installed on the slot end of the ultrasonic cleaning tank for facilitating the movement of the movable trolley, a driving motor is installed on the top of the cleaning seat, the bottom end of the rotating drum is open, the output end of the driving motor passes through the cleaning seat and is connected to the top of the rotating drum, hollow holes are evenly distributed on the surface of the rotating drum, and a vortex plate is spirally installed.

8. The preparation method according to claim 7, wherein: The fixing assembly includes: a fan-shaped fixing seat, a slot is provided at the top of the fan-shaped fixing seat for facilitating the clamping of the side end of the cleaning seat, the slot end is covered with a limit plate clamped with the top end of the cleaning seat, the silicon wafer placement rack is installed at the bottom end of the fan-shaped fixing seat through a connecting assembly, the action chamber is located in the fan-shaped fixing seat, the action chamber is composed of a bottom chamber and a side chamber, the bottom chamber is located at the bottom of the slot, the two side chambers are symmetrically arranged with the slot as the center, the two side mounting shells are symmetrically installed on the fan-shaped fixing seat, and are connected to the side chamber, and the center rod is located in the bottom chamber The connecting assembly extends into the bottom chamber and is connected to the center rod. The two side connecting rods are respectively hinged at both ends of the center rod. The clamping rod is bent at an obtuse angle and is located in the side chamber. One end of the clamping rod is rotatably installed in the action chamber through a rotating shaft. A block matching the bayonet is installed at the other end of the clamping rod. The other end of the clamping rod extends into the side mounting shell. The screw extends from the fan-shaped fixing seat away from the slot into the bottom chamber and is rotatably installed on the center rod. The fan-shaped fixing seat is fixedly installed away from the slot with a screw sleeve sleeved on the screw.

9. The preparation method according to claim 7, wherein: The connecting assembly includes: a bottom connecting seat, the top of the bottom connecting seat is hinged to the bottom end of the fan-shaped fixing seat through two symmetrically arranged spring rods, the silicon wafer placement rack is installed at the bottom end of the bottom connecting seat, a slot is opened through the bottom connecting seat, the middle section of the rotating rod is arranged as a square rod, and is slidably connected in the slot, the two ends of the rotating rod are rotatably installed on the bow-shaped mounting frame, the bow-shaped mounting frame extends into the bottom chamber away from the rotating rod end, and is connected to the center rod, and the dial plate is vertically installed at both ends of the rotating rod.

10. The preparation method according to claim 8, wherein: A handle is installed on the limit plate, and a rotating handle is installed on the screw rod.

11. A method for preparing an N-type TOPCon battery, comprising: Texturing of N-type silicon wafers; Boron diffusion and laser micro-doping are performed on the front side of the N-type silicon wafer to form a micro-doped area; Re-diffusion is performed on the front side of the N-type silicon wafer to form a front mask; Polishing the back side of the N-type silicon wafer; Perform three-in-one multi-layer thin film deposition on the back side of the N-type silicon wafer, growing a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer, and a back mask in one process step; Performing high temperature annealing under a preset high temperature condition to form a doped polysilicon layer to activate the doped phosphorus; Clean the front mask on the front side of the N-type silicon wafer and the back mask on the back side; Depositing a passivation film on the front and back sides of an N-type silicon wafer; Printing and sintering.

12. The preparation method according to claim 11, wherein The process of re-diffusion to form a front mask includes: In an environment of a temperature of 800° C. to 900° C., introducing O2 gas with a flow rate of 1000 sccm to 5000 sccm to pre-oxidize the N-type silicon wafer for a pre-oxidation time of 100 s to 500 s; In an environment of 850°C-900°C and an atmosphere of less than 100 mbar, a BCl3 gas with a flow rate of 50-500 sccm and an O2 gas with a flow rate of 200 sccm-2000 sccm are introduced to perform the first boron source deposition for a deposition time of 100s-500s; BCl3 gas with a flow rate of 60 sccm-600 sccm and O2 gas with a flow rate of 300 sccm-3000 sccm are introduced to perform a second boron source deposition, and the deposition time is 100 s-500 s; The process is pushed at a temperature of 950℃-1050℃, and the pushing time is 500s-2000s; Pass 1L-10L nitrogen and back pressure.

13. The preparation method according to claim 11, wherein The laser micro-doping process includes: The printed grid line area is treated with laser micro-doping by using the diffused boron atoms to form a micro-doped area, wherein the laser wavelength is 500nm-1100nm, the laser power is 30W-100W, the laser processing speed is 10m / s-50m / s, and the laser width acting on the printed grid line area is 50μm-100μm; The process of re-diffusion to form a front mask includes: In an environment where the temperature is 950°C-1100°C and the atmosphere is less than 100 mbar, O2 gas with a flow rate of 10000sccm-50000sccm is introduced for a deposition time of 3000s-6000s to form a front mask; Introduce 1L-20L nitrogen and back pressure.

14. The preparation method according to any one of claims 11 to 13, wherein: The process of polishing the back side of an N-type silicon wafer includes: The back side of the N-type silicon wafer is polished using 2-3 parts of alkali metal hydroxide solution with a mass fraction of 40%-60% and 1 part of a polishing additive, wherein the polishing temperature is 50° C.-70° C. and the polishing time is 100s-300s.

15. The preparation method according to any one of claims 11 to 13, wherein: The process of growing a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer, and a back mask through one process step includes: The PECVD method is used to prepare a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer, and a back mask in one process step.

16. The preparation method according to claim 15, wherein: In the process of preparing a tunneling silicon oxide thin film layer, a doped amorphous silicon thin film layer, and a back mask in one process step by using a PECVD method, the process includes: In the PECVD equipment, the temperature is 300℃-500℃, and 5000sccm-15000sccm of laughing gas is introduced. The laughing gas is ionized into plasma to oxidize the back of the N-type silicon wafer to form a tunneling silicon oxide film layer; In the PECVD equipment, the temperature is 300°C-500°C, the silane flow rate is 500sccm-5000sccm, the phosphine flow rate is 100sccm-5000sccm, and hydrogen is introduced to form a doped amorphous silicon thin film layer; In the PECVD equipment, the temperature is 300°C-500°C, and nitrous oxide with a flow rate of 2000sccm-10000sccm and silane with a flow rate of 500sccm-5000sccm are introduced to form a back mask.

17. The preparation method according to any one of claims 11 to 13, wherein: The process of cleaning the front mask on the front side of the N-type silicon wafer and the back mask on the back side includes: In the cleaning equipment, a HF solution with a mass fraction of 30%-60% is used for cleaning treatment to remove the front mask on the front side and the back mask on the back side of the N-type silicon wafer. The cleaning temperature is 20°C-50°C and the cleaning time is 100s-500s. The cleaning equipment includes an ultrasonic cleaning tank, a plurality of turbulent cleaning units can be movably installed at the slot end of the ultrasonic cleaning tank, and two groups of silicon wafer placement racks are installed opposite to each other on the turbulent cleaning units. 18 . An N-type TOPCon battery, wherein the N-type TOPCon battery is an N-type TOPCon battery prepared by the method for preparing an N-type TOPCon battery according to any one of claims 1 to 17.

19. The N-type TOPCon battery according to claim 18, wherein: The N-type TOPCon cell includes an N-type silicon wafer, and the back side of the N-type silicon wafer is sequentially provided with a tunneling silicon oxide thin film layer, a doped polysilicon layer, and a back passivation film; the thickness of the tunneling silicon oxide thin film layer is less than 2nm, the thickness of the doped polysilicon layer is 20nm-200nm, and the thickness of the back passivation film is 70nm-110nm.

20. The N-type TOPCon battery according to claim 18 or 19, wherein: The front side of the N-type silicon wafer includes a micro-doped region, and the sheet resistance of the micro-doped region is 70Ω / m-120Ω / m; The front side of the N-type silicon wafer further comprises a front side passivation film, which is composed of a stack of an aluminum oxide film and a front side silicon nitride film, and has a thickness of 60nm-100nm.

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