High-speed high-voltage fully-differential power amplifier for beam deflection driver

Abstract

The present disclosure provides a deflector driver for driving a deflector of a charged-particle inspection apparatus. The deflector driver may comprise a fully-differential amplifier that is configured to generate fully-differential outputs of which absolute value is greater than 100V. Wherein the fully-differential outputs may enable a plurality of deflector electrodes of the deflector to influence a charged particle beam of the charged-particle inspection apparatus based on the fully-differential outputs.

Description

HIGH-SPEED HIGH-VOLTAGE FULLY -DIFFERENTIAL POWER AMPLIFIER FOR BEAM DEFLECTION DRIVERCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of US application 63 / 530,241 which was filed on August 01, 2023 and which is incorporated herein in its entirety by reference.TECHNICAL FIELD

[0002] The embodiments provided herein generally relate to an inspection apparatus, and more particularly, to a beam manipulation system of an inspection apparatus.BACKGROUND

[0003] In manufacturing processes of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and are free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes, such as a scanning electron microscope (SEM) can be employed. As the physical sizes of IC components continue to shrink, accuracy and yield in defect detection becomes more and more important. However, image resolution and throughput of inspection tools struggle to keep pace with ever-decreasing feature size of IC components. The accuracy, resolution and throughput of such inspection tools may be limited by the lack of driving mechanisms of the deflectors that meet desired criteria in the industry.SUMMARY

[0004] Some embodiments provide a charged-particle inspection apparatus. The apparatus can comprise a charged-particle beam source configured to generate a primary charged-particle beam for sample scanning; a deflector driver comprising a fully-differential amplifier that is configured to generate fully-differential outputs of which absolute value is greater than 100V; and a plurality of deflector electrodes coupled to the fully-differential outputs and configured to influence the charged particle beam based on the fully-differential outputs.

[0005] Some embodiments provide a deflector driver for driving a deflector of a charged-particle inspection apparatus. The deflector driver can comprise a fully-differential amplifier that is configured to generate fully-differential outputs of which absolute value is greater than 100V. Wherein the fully- differential outputs can enable a plurality of deflector electrodes of the deflector to influence a charged particle beam of the charged-particle inspection apparatus based on the fully-differential outputs.

[0006] Some embodiments provide a method of operating a deflector driver for driving a deflector of a charged-particle inspection apparatus. The method can comprise: generating, by a fully-differentialamplifier included in the deflector driver, fully-differential outputs of which absolute value is greater than 100V; measuring, by a common- mode control circuit included in the deflector driver, a commonmode voltage of the fully-differential outputs of the fully-differential amplifier; providing, by the common-mode control circuit, a difference between the common-mode voltage and a reference voltage to the fully-differential amplifier; and adjusting the fully-differential outputs of the differential amplifier based on the difference. Wherein the adjusted fully-differential outputs can enable a plurality of deflector electrodes of the deflector to influence a charged particle beam of the charged- particle inspection apparatus based on the fully-differential outputs. Wherein the fully-differential amplifier and the common-mode control circuit can be integrated into a single integrated circuit (IC) chip.

[0007] Other advantages of the embodiments of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.BRIEF DESCRIPTION OF FIGURES

[0008] The above and other aspects of the present disclosure will become more apparent from the description of exemplary embodiments, taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a schematic diagram illustrating an exemplary charged-particle beam inspection system, consistent with embodiments of the present disclosure.

[0010] FIG. 2A is a schematic diagram illustrating an exemplary multi-beam tool, consistent with embodiments of the present disclosure that can be a part of the exemplary charged-particle beam inspection system of FIG. 1.

[0011] FIG. 2B is a schematic diagram illustrating an exemplary single-beam tool, consistent with embodiments of the present disclosure that can be a part of the exemplary charged-particle beam inspection system of FIG. 1.

[0012] FIG. 3A is a diagram illustrating an exemplary configuration of a scanning deflection system, consistent with embodiments of the present disclosure.

[0013] FIG. 3B is a diagrammatic representation of deflection of a charged particle beam, consistent with embodiments of the present disclosure.

[0014] FIG. 3C is a diagram illustrating a configuration of exemplary deflection elements, consistent with embodiments of the present disclosure.

[0015] FIG. 4 is a schematic diagram illustrating an exemplary configuration of a deflection control unit associated with charged-particle beam deflectors, consistent with embodiments of the present disclosure.

[0016] FIG. 5 is a diagram illustrating a driver system architecture with a pseudo-differential amplifier utilizing dual single-ended power amplifiers.

[0017] FIG. 6 is a diagram illustrating a single-ended power amplifier circuit configuration.

[0018] FIG. 7 is a diagram illustrating an exemplary driver system architecture with a fully - differential power amplifier, consistent with embodiments of the present disclosure.

[0019] FIG. 8 is a diagram illustrating an exemplary fully-differential power amplifier circuit configuration along with a common-mode control circuit, consistent with embodiments of the present disclosure.

[0020] FIG. 9 is a flow chart illustrating an exemplary method for operating a deflector driver with a fully-differential power amplifier, consistent with embodiments of the present disclosure.DETAILED DESCRIPTION

[0021] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the disclosed embodiments as recited in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, the disclosure is not so limited. Other types of charged particle beams (e.g., including protons, ions, muons, or any other particle carrying electric charges) may be similarly applied. Furthermore, other imaging systems may be used, such as optical imaging, photon detection, x-ray detection, ion detection, etc.

[0022] Electronic devices are constructed of circuits formed on a piece of semiconductor material called a substrate. The semiconductor material may include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium, or the like. Many circuits may be formed together on the same piece of silicon and are called integrated circuits or ICs. The size of these circuits has decreased dramatically so that many more of them can be fit on the substrate. For example, an IC chip in a smartphone can be as small as a thumbnail and yet may include over 2 billion transistors, the size of each transistor being less than 1 / 1000th the size of a human hair.

[0023] Making these ICs with extremely small structures or components is a complex, timeconsuming, and expensive process, often involving hundreds of individual steps. Errors in even one step have the potential to result in defects in the finished IC, rendering it useless. Thus, one goal of the manufacturing process is to avoid such defects to maximize the number of functional ICs made in the process; that is, to improve the overall yield of the process.

[0024] One component of improving yield is monitoring the chip-making process to ensure that it is producing a sufficient number of functional integrated circuits. One way to monitor the process is to inspect the chip circuit structures at various stages of their formation. Inspection can be carried out using a scanning charged-particle microscope (“SCPM”). For example, an SCPM may be a scanning electron microscope (SEM). A SCPM can be used to image these extremely small structures, ineffect, taking a “picture” of the structures of the wafer. The image can be used to determine if the structure was formed properly in the proper location. If the structure is defective, then the process can be adjusted, so the defect is less likely to recur.

[0025] As the physical sizes of IC components continue to shrink, accuracy and yield in defect detection becomes more and more important. Additionally, as the world’s computing demand increases, so does the need to improve the manufacturing speed or inspection speed of ICs. However, increasing the IC inspection speed may introduce technical challenges in maintaining high defect detection accuracy. The accuracy, resolution and throughput of IC inspection may be limited by the lack of driving mechanisms of the deflectors that meet desired criteria demanded in the industry. Currently, a deflection driver system having differential driving capability has been utilized to achieve a better signal to noise ratio (SNR). Specifically, when transmitting signals in a single PCB or between PCBs, electromagnetic impedance (EMI) may be coupled to each signal and such EMI coupling can cause additional noise issue. By transmitting signals in differential signals, the EMI commonly coupled to two differential signals can be canceled out. There is a demand in the industry to provide a deflection driver system having the differential driving capability with the following specifications.

[0026] It is desired that a deflection driver system operates at higher speeds with a power bandwidth greater than 1MHz so to meet the industry demand for scanning rate, e.g., 1.2 giga samples per second. There is an obstacle in increasing a bandwidth of the deflection driver system because the bandwidth of a power amplifier, which is one of the main components of a deflection driver system, is limited by a trade-off between scanning speed and stability. The higher the bandwidth of the power amplifier is, the higher scanning speed the deflection driver system achieves, which can also improve the yield of the system. However, under the same gain bandwidth product (GBW), increasing the circuit bandwidth results in the power amplifier operating at a lower phase margin region, which leads to lower circuit stability and resultant degradation of inspection image resolution. Accordingly, it is desired to design a power amplifier to have higher bandwidth or GBW to achieve higher throughput with sufficient circuit stability. It is also desired that a power amplifier is designed to have unity gain stability with phase margin greater than 60 degrees to provide sufficient deflection driving system design flexibility. However, increasing a bandwidth of a power amplifier may introduce more noise into the system and thus signal quality and image resolution are degraded. Therefore, there exists a need in the art to provide an increased power bandwidth without sacrificing signal quality, e.g., by keeping a lower noise level.

[0027] It is desired that a deflection driver system drives higher voltage outputs for fast scan rate. There is a tradeoff between output voltage level and SNR. When a deflection driving signal has a higher voltage level, a SNR can decrease as noise floor can also be amplified when amplifying the driving signal. To improve a SNR, a lower voltage level may be considered. However, a lower voltage driving signal may not be capable of deflecting the beam across the entire inspection range.Further, a lower voltage driving signal may not be able to achieve the required inspection sensitivity at the edges of the inspection area. In order to increase the inspection area and improve edge sensitivity when using a lower voltage driving signal, a deflector with higher sensitivity may be utilized to compensate electric field intensity diminution and thereby to ensure the desired electric field intensity level with lower voltage. Deflector’s sensitivity can usually be improved by designing a deflector to be bulky or longer, which ultimately results in degrading image resolution, especially at the edges of the inspection area. Therefore, there exists a need in the art to provide higher voltage deflection driver system without sacrificing signal quality. In this disclosure, a higher voltage level may refer to a voltage level greater than 100V, which can support the industry scan rate demand, e.g., 1.2 giga samples per second without sacrificing signal quality, e.g., by keeping a lower noise level.

[0028] It is also desired that a deflection driver system provide a higher slew rate, e.g., greater than 500V / ps to achieve the desired scanning throughput. As a scanning rate continuously increases, a higher slew rate becomes more and more important to reduce scanning overhead. Further, the output cabling of a deflection driver system is likely to be longer in future products by utilizing a dynamic link, and thus increasing a slew rate becomes more important to improving throughput. When a slew rate is greater than 500V / ps, the excessive overhead resulting from the longer cabling may be avoided and thus throughput can be improved.

[0029] It is also desired that a noise level of a deflection driver system is kept less than 2.5nV / sqrt(Hz). The noise specification (e.g., 3nV / sqart(Hz) of a conventional deflection driver system may have met the industry noise criteria in the past. However, the demand for a deflection driver system with a lower noise level is ever increasing as the newly developed products utilizing a smaller pixel size are emerging.

[0030] Because conventional fully-differential amplifiers cannot fulfill the above design criteria, a pseudo-differential power amplifier constructed by dual single-ended power amplifiers has been utilized in a conventional deflection driver system. However, a pseudo-differential power amplifier is comprised of multiple discrete power amplifiers, e.g., two single-ended power amplifiers each integrated into its own IC chip. Thereby, element mismatch between two separate amplifiers is unavoidable even with selection of the highest practical accurate components and extensively optimized printed circuit board (PCB) design. Such element mismatch limits common-mode rejection ratio (CMRR) leading to higher noise level, which result in lower image resolution. As discussed, the conventional deflection driver system utilizing a pseudo differential power amplifier suffers from a high noise level at least partly stemming from low common-mode rejection ratio due to element mismatch between two single-ended power amplifiers. Therefore, while a conventional deflection driver system comprising a pseudo-differential power amplifier may drive high voltage signals, it could not satisfy the noise criteria demanded for next generation systems, such as less than 2.5nV / sqrt(Hz).

[0031] According to some embodiments of the present disclosure, a deflector driver system utilizing a fully-differential power amplifier instead of a pseudo-differential power amplifier can be provided. According to some embodiments of the present disclosure, a deflector driver system can drive higher- voltage deflector driving signals with high speed that meet the criteria listed above. According to some embodiments of the present disclosure, a differential power amplifier that is configured to generate fully-differential outputs of which absolute value is greater than 100V is provided.According to some embodiments of the present disclosure, a deflector driver system having an improved common-mode rejection ratio can be provided. According to some embodiments of the present disclosure, a differential power amplifier can be fully integrated into a single IC chip along with a common-mode feedback circuit, which improves the scanning speed as well as the throughput meeting the criteria listed above. According to some embodiments of the present disclosure, a fully- differential power amplifier can be integrated into a single IC chip, which may reduce noise stemming from element mismatch. According to some embodiments of the present disclosure, a deflector driver system including a fully-differential power amplifier and multiple digital to analog converters (DACs) can be mounted on one PCB board, which can save the PCB area and improves PCB design efficiency. According to some embodiments of the present disclosure, a deflector driver system with high speed, low noise, high voltage, and high slew rate drive differential drive capability can be provided.

[0032] Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings, the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described. Other objects and advantages of the disclosure may be realized by the elements and combinations as set forth in the embodiments discussed herein. However, embodiments of the present disclosure are not necessarily required to achieve such exemplary objects or advantages, and some embodiments may not achieve any of the stated objects or advantages.

[0033] Without limiting the scope of the present disclosure, some embodiments may be described in the context of providing scanning deflection systems and scanning deflection methods in systems utilizing electron beams (“e-beams”). Some scanning deflection systems may use electric fields to influence a charged particle beam. However, the disclosure is not so limited. Other types of charged particle beams may be similarly applied. For example, systems and methods may be applicable with optics, photons, x-rays, and ions, etc. Deflection may be used to scan a beam over a surface in, for example, cathode ray tubes (CRTs), lithography machines, scanning charged-particle microscopes (SCPMs), or other analytical instruments. While some embodiments are discussed with reference to deflection systems that use electric field to influence a beam, deflection may also be achieved with magnetic fields, for example.

[0034] As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a component includes A or B,then, unless specifically stated otherwise or infeasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component includes A, B, or C, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C. Expressions such as “at least one of’ do not necessarily modify an entirety of a following list and do not necessarily modify each member of the list, such that “at least one of A, B, and C” should be understood as including only one of A, only one of B, only one of C, or any combination of A, B, and C. The phrase “one of A and B” or “any one of A and B” shall be interpreted in the broadest sense to include one of A, or one of B.

[0035] FIG. 1 illustrates an exemplary electron beam inspection (EBI) system 100 consistent with embodiments of the present disclosure. EBI system 100 may be used for imaging. As shown in FIG. 1, EBI system 100 includes a main chamber 101, a load / lock chamber 102, a beam tool 104, and an equipment front end module (EFEM) 106. Beam tool 104 is located within main chamber 101.EFEM 106 includes a first loading port 106a and a second loading port 106b. EFEM 106 may include additional loading port(s). First loading port 106a and second loading port 106b receive wafer front opening unified pods (FOUPs) that contain wafers (e.g., semiconductor wafers or wafers made of other material(s)) or samples to be inspected (wafers and samples may be used interchangeably). A “lot” is a plurality of wafers that may be loaded for processing as a batch.

[0036] One or more robotic arms (not shown) in EFEM 106 may transport the wafers to load / lock chamber 102. Load / lock chamber 102 is connected to a load / lock vacuum pump system (not shown) which removes gas molecules in load / lock chamber 102 to reach a first pressure below the atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) may transport the wafer from load / lock chamber 102 to main chamber 101. Main chamber 101 is connected to a main chamber vacuum pump system (not shown) which removes gas molecules in main chamber 101 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer is subject to inspection by beam tool 104. Beam tool 104 may be a single-beam system or a multi-beam system.

[0037] A controller 109 is electronically connected to beam tool 104. Controller 109 may be a computer configured to execute various controls of EBI system 100. While controller 109 is shown in FIG. 1 as being outside of the structure that includes main chamber 101, load / lock chamber 102, and EFEM 106, it is appreciated that controller 109 may be a part of the structure.

[0038] In some embodiments, controller 109 may include one or more processors (not shown). A processor may be a generic or specific electronic device capable of manipulating or processing information. For example, the processor may include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), an optical processor, a programmable logic controllers, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), and any type circuit capable of data processing. The processor may also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.

[0039] In some embodiments, controller 109 may further include one or more memories (not shown). A memory may be a generic or specific electronic device capable of storing codes and data accessible by the processor (e.g., via a bus). For example, the memory may include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or any type of storage device. The codes and data may include an operating system (OS) and one or more application programs (or “apps”) for specific tasks. The memory may also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.

[0040] FIG. 2A illustrates a schematic diagram of an exemplary multi-beam beam tool 104A (also referred to herein as apparatus 104A) and an image processing system 290 that may be configured for use in EBI system 100 (FIG. 1), consistent with embodiments of the present disclosure.

[0041] Beam tool 104 A comprises a charged-particle source 202, a gun aperture 204, a condenser lens 206, a primary charged-particle beam 210 emitted from charged-particle source 202, a source conversion unit 212, a plurality of beamlets 214, 216, and 218 of primary charged-particle beam 210, a primary projection optical system 220, a motorized wafer stage 280, a wafer holder 282, multiple secondary charged-particle beams 236, 238, and 240, a secondary optical system 242, and a charged- particle detection device 244. Primary projection optical system 220 can comprise a beam separator 222, a deflection scanning unit 226, and an objective lens 228. Charged-particle detection device 244 can comprise detection sub-regions 246, 248, and 250.

[0042] Charged-particle source 202, gun aperture 204, condenser lens 206, source conversion unit 212, beam separator 222, deflection scanning unit 226, and objective lens 228 can be aligned with a primary optical axis 260 of apparatus 104A. Secondary optical system 242 and charged-particle detection device 244 can be aligned with a secondary optical axis 252 of apparatus 104A.

[0043] Charged-particle source 202 can emit one or more charged particles, such as electrons, protons, ions, muons, or any other particle carrying electric charges. In some embodiments, charged- particle source 202 may be an electron source. For example, charged-particle source 202 may include a cathode, an extractor, or an anode, wherein primary electrons can be emitted from the cathode and extracted or accelerated to form primary charged-particle beam 210 (in this case, a primary electron beam) with a crossover (virtual or real) 208. For ease of explanation without causing ambiguity, electrons are used as examples in some of the descriptions herein. However, it should be noted that any charged particle may be used in any embodiment of this disclosure, not limited to electrons. Primary charged-particle beam 210 can be visualized as being emitted from crossover 208. Gunaperture 204 can block off peripheral charged particles of primary charged-particle beam 210 to reduce Coulomb effect. The Coulomb effect may cause an increase in size of probe spots.

[0044] Source conversion unit 212 can comprise an array of image-forming elements and an array of beam-limit apertures. The array of image-forming elements can comprise an array of microdeflectors or micro-lenses. The array of image-forming elements can form a plurality of parallel images (virtual or real) of crossover 208 with a plurality of beamlets 214, 216, and 218 of primary charged-particle beam 210. The array of beam-limit apertures can limit the plurality of beamlets 214, 216, and 218. While three beamlets 214, 216, and 218 are shown in FIG. 2A, embodiments of the present disclosure are not so limited. For example, in some embodiments, the apparatus 104A may be configured to generate a first number of beamlets. In some embodiments, the first number of beamlets may be in a range from 1 to 1000. In some embodiments, the first number of beamlets may be in a range from 200-500. In an exemplary embodiment, an apparatus 104 A may generate 400 beamlets.

[0045] Condenser lens 206 can focus primary charged-particle beam 210. The electric currents of beamlets 214, 216, and 218 downstream of source conversion unit 212 can be varied by adjusting the focusing power of condenser lens 206 or by changing the radial sizes of the corresponding beam-limit apertures within the array of beam-limit apertures. Objective lens 228 can focus beamlets 214, 216, and 218 onto a wafer 230 for imaging, and can form a plurality of probe spots 270, 272, and 274 on a surface of wafer 230.

[0046] Beam separator 222 can be a beam separator of Wien filter type generating an electrostatic dipole field and a magnetic dipole field. In some embodiments, if they are applied, the force exerted by the electrostatic dipole field on a charged particle (e.g., an electron) of beamlets 214, 216, and 218 can be substantially equal in magnitude and opposite in a direction to the force exerted on the charged particle by magnetic dipole field. Beamlets 214, 216, and 218 can, therefore, pass straight through beam separator 222 with zero deflection angle. However, the total dispersion of beamlets 214, 216, and 218 generated by beam separator 222 can also be non-zero. Beam separator 222 can separate secondary charged-particle beams 236, 238, and 240 from beamlets 214, 216, and 218 and direct secondary charged-particle beams 236, 238, and 240 towards secondary optical system 242.

[0047] Deflection scanning unit 226 can deflect beamlets 214, 216, and 218 to scan probe spots 270, 272, and 274 over a surface area of wafer 230. In response to the incidence of beamlets 214, 216, and 218 at probe spots 270, 272, and 274, secondary charged-particle beams 236, 238, and 240 may be emitted from wafer 230. Secondary charged-particle beams 236, 238, and 240 may comprise charged particles (e.g., electrons) with a distribution of energies. For example, secondary charged-particle beams 236, 238, and 240 may be secondary electron beams including secondary electrons (energies < 50 eV) and backscattered electrons (energies between 50 eV and landing energies of beamlets 214, 216, and 218). Secondary optical system 242 can focus secondary charged-particle beams 236, 238, and 240 onto detection sub-regions 246, 248, and 250 of charged-particle detection device 244.Detection sub-regions 246, 248, and 250 may be configured to detect corresponding secondary charged-particle beams 236, 238, and 240 and generate corresponding signals (e.g., voltage, current, or the like) used to reconstruct an inspection image of structures on or underneath the surface area of wafer 230.

[0048] The generated signals may represent intensities of secondary charged-particle beams 236, 238, and 240 and may be provided to image processing system 290 that is in communication with charged-particle detection device 244, primary projection optical system 220, and motorized wafer stage 280. The movement speed of motorized wafer stage 280 may be synchronized and coordinated with the beam deflections controlled by deflection scanning unit 226, such that the movement of the scan probe spots (e.g., scan probe spots 270, 272, and 274) may orderly cover regions of interests on the wafer 230. The parameters of such synchronization and coordination may be adjusted to adapt to different materials of wafer 230. For example, different materials of wafer 230 may have different resistance-capacitance characteristics that may cause different signal sensitivities to the movement of the scan probe spots.

[0049] The intensity of secondary charged-particle beams 236, 238, and 240 may vary according to the external or internal structure of wafer 230, and thus may indicate whether wafer 230 includes defects. Moreover, as discussed above, beamlets 214, 216, and 218 may be projected onto different locations of the top surface of wafer 230, or different sides of local structures of wafer 230, to generate secondary charged-particle beams 236, 238, and 240 that may have different intensities. Therefore, by mapping the intensity of secondary charged-particle beams 236, 238, and 240 with the areas of wafer 230, image processing system 290 may reconstruct an image that reflects the characteristics of internal or external structures of wafer 230.

[0050] In some embodiments, image processing system 290 may include an image acquirer 292, a storage 294, and a controller 296. Image acquirer 292 may comprise one or more processors. For example, image acquirer 292 may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, or the like, or a combination thereof. Image acquirer 292 may be communicatively coupled to charged-particle detection device 244 of beam tool 104A through a medium such as an electric conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, or a combination thereof. In some embodiments, image acquirer 292 may receive a signal from charged-particle detection device 244 and may construct an image. Image acquirer 292 may thus acquire inspection images of wafer 230. Image acquirer 292 may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, or the like. Image acquirer 292 may be configured to perform adjustments of brightness and contrast of acquired images. In some embodiments, storage 294 may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), other types of computer-readable memory, or the like. Storage 294 may be coupled with image acquirer 292 and may be used for saving scanned raw image data as original images, and post-processed images. Image acquirer 292 and storage 294 may be connected to controller 296. In some embodiments, image acquirer 292, storage 294, and controller 296 may be integrated together as one control unit.

[0051] In some embodiments, image acquirer 292 may acquire one or more inspection images of a wafer based on an imaging signal received from charged-particle detection device 244. An imaging signal may correspond to a scanning operation for conducting charged particle imaging. An acquired image may be a single image comprising a plurality of imaging areas. The single image may be stored in storage 294. The single image may be an original image that may be divided into a plurality of regions. Each of the regions may comprise one imaging area containing a feature of wafer 230. The acquired images may comprise multiple images of a single imaging area of wafer 230 sampled multiple times over a time sequence. The multiple images may be stored in storage 294. In some embodiments, image processing system 290 may be configured to perform image processing steps with the multiple images of the same location of wafer 230.

[0052] In some embodiments, image processing system 290 may include measurement circuits (e.g., analog-to-digital converters) to obtain a distribution of the detected secondary charged particles (e.g., secondary electrons). The charged-particle distribution data collected during a detection time window, in combination with corresponding scan path data of beamlets 214, 216, and 218 incident on the wafer surface, can be used to reconstruct images of the wafer structures under inspection. The reconstructed images can be used to reveal various features of the internal or external structures of wafer 230, and thereby can be used to reveal any defects that may exist in the wafer.

[0053] In some embodiments, the charged particles may be electrons. When electrons of primary charged-particle beam 210 are projected onto a surface of wafer 230 (e.g., probe spots 270, 272, and 274), the electrons of primary charged-particle beam 210 may penetrate the surface of wafer 230 for a certain depth, interacting with particles of wafer 230. Some electrons of primary charged-particle beam 210 may elastically interact with (e.g., in the form of elastic scattering or collision) the materials of wafer 230 and may be reflected or recoiled out of the surface of wafer 230. An elastic interaction conserves the total kinetic energies of the bodies (e.g., electrons of primary charged-particle beam 210) of the interaction, in which the kinetic energy of the interacting bodies does not convert to other forms of energy (e.g., heat, electromagnetic energy, or the like). Such reflected electrons generated from elastic interaction may be referred to as backscattered electrons (BSEs). Some electrons of primary charged-particle beam 210 may inelastically interact with (e.g., in the form of inelastic scattering or collision) the materials of wafer 230. An inelastic interaction does not conserve the total kinetic energies of the bodies of the interaction, in which some or all of the kinetic energy of the interacting bodies convert to other forms of energy. For example, through the inelastic interaction, the kinetic energy of some electrons of primary charged-particle beam 210 may cause electron excitation and transition of atoms of the materials. Such inelastic interaction may also generate electrons exiting the surface of wafer 230, which may be referred to as secondary electrons (SEs).Yield or emission rates of BSEs and SEs depend on, e.g., the material under inspection and the landing energy of the electrons of primary charged-particle beam 210 landing on the surface of the material, among others. The energy of the electrons of primary charged-particle beam 210 may be imparted in part by its acceleration voltage (e.g., the acceleration voltage between the anode and cathode of charged-particle source 202 in FIG. 2A). The quantity of BSEs and SEs may be more or fewer (or even the same) than the injected electrons of primary charged-particle beam 210.

[0054] Another example of a charged particle beam apparatus will now be discussed with reference to FIG. 2B. Beam tool 104B (also referred to herein as apparatus 104B) may be an example of beam tool 104 and may be similar to beam tool 104A shown in FIG. 2A. However, different from apparatus 104A, apparatus 104B may be a single-beam tool that uses only one primary electron beam to scan one location on the wafer at a time.

[0055] As shown in FIG. 2B, apparatus 104B includes a wafer holder 136 supported by motorized stage 134 to hold a wafer 150 to be inspected. Beam tool 104B includes an electron emitter, which may comprise a cathode 103, an anode 121, and a gun aperture 122. Beam tool 104B further includes a beam limit aperture 125, a condenser lens 126, a column aperture 135, an objective lens assembly 132, and a detector 144. Objective lens assembly 132, in some embodiments, may be a modified SORIL lens, which includes a pole piece 132a, a control electrode 132b, a deflector unit 132c, and an exciting coil 132d. In a detection or imaging process, an electron beam 161 emanating from the tip of cathode 103 may be accelerated by anode 121 voltage, pass through gun aperture 122, beam limit aperture 125, condenser lens 126, and be focused into a probe spot 170 by the modified SORIL lens and impinge onto the surface of wafer 150. Probe spot 170 may be scanned across the surface of wafer 150 by a deflector, such as deflector unit 132c or other deflectors in the SORIL lens. Secondary or scattered particles, such as secondary electrons or scattered primary electrons emanated from the wafer surface may be collected by detector 144 to determine intensity of the beam and so that an image of an area of interest on wafer 150 may be reconstructed.

[0056] There may also be provided an image processing system 199 that includes an image acquirer 120, a storage 130, and controller 109. Image acquirer 120 may comprise one or more processors. For example, image acquirer 120 may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, and the like, or a combination thereof. Image acquirer 120 may connect with detector 144 of beam tool 104B through a medium such as an electrical conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, or a combination thereof. Image acquirer 120 may receive a signal from detector 144 and may construct an image. Image acquirer 120 may thus acquire images of wafer 150. Image acquirer 120 may also perform various post-processing functions, such as image averaging, generating contours, superimposing indicators on an acquired image, and the like. Image acquirer 120 may be configured to perform adjustments of brightness and contrast, etc. of acquired images.Storage 130 may be a storage medium such as a hard disk, random access memory (RAM), cloudstorage, other types of computer readable memory, and the like. Storage 130 may be coupled with image acquirer 120 and may be used for saving scanned raw image data as original images, and postprocessed images. Image acquirer 120 and storage 130 may be connected to controller 109. In some embodiments, image acquirer 120, storage 130, and controller 109 may be integrated together as one electronic control unit.

[0057] In some embodiments, image acquirer 120 may acquire one or more images of a sample based on an imaging signal received from detector 144. An imaging signal may correspond to a scanning operation for conducting charged particle imaging. An acquired image may be a single image comprising a plurality of imaging areas that may contain various features of wafer 150. The single image may be stored in storage 130. Imaging may be performed on the basis of imaging frames.

[0058] The condenser and illumination optics of the electron beam tool may comprise or be supplemented by electromagnetic quadrupole electron lenses. For example, as shown in FIG. 2B, electron beam tool 104B may comprise a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses may be used for controlling the electron beam. For example, first quadrupole lens 148 may be controlled to adjust the beam current and second quadrupole lens 158 may be controlled to adjust the beam spot size and beam shape.

[0059] FIB. 2B illustrates a charged particle beam apparatus that may use a single primary beam configured to generate secondary electrons by interacting with wafer 150. Detector 144 may be placed along optical axis 105, as in the embodiment shown in FIG. 2B. The primary electron beam may be configured to travel along optical axis 105. Accordingly, detector 144 may include a hole at its center so that the primary electron beam may pass through to reach wafer 150. FIG. 2B shows an example of detector 144 having an opening at its center. However, some embodiments may use a detector placed off-axis relative to the optical axis along which the primary electron beam travels. For example, as in the embodiment shown in FIG. 2B, discussed above, a beam separator 222 may be provided to direct secondary electron beams toward a detector placed off-axis. Beam separator 222 may be configured to divert secondary electron beams toward an electron detection device 244, as shown in FIG. 2A.

[0060] The images generated by SCPM may be used for defect inspection. For example, a generated image capturing a test device region of a wafer may be compared with a reference image capturing the same test device region. The reference image may be predetermined (e.g., by simulation) and include no known defect. If a difference between the generated image and the reference image exceeds a tolerance level, a potential defect may be identified. For another example, the SCPM may scan multiple regions of the wafer, each region including a test device region designed as the same, and generate multiple images capturing those test device regions as manufactured. The multiple images may be compared with each other. If a difference between the multiple images exceeds a tolerance level, a potential defect may be identified.

[0061] Reference is now made to FIG. 3A, which illustrates a configuration of deflectors and objective lens assembly, consistent with embodiments of the present disclosure. As shown in FIG. 3A, deflectors 309-1 and 309-2 may be disposed within the magnetic field of a magnetic objective lens assembly 310, wherein deflectors 309-1 and 309-2 may be implemented in a deflection scanning unit (e.g., deflection scanning unit 226 of FIG. 2A) or as a deflector unit (e.g., deflector unit 132c of FIG. 2B). Deflectors 309-1 and 309-2 may be configured to dynamically deflect an electron beam to scan a desired area on the surface of a sample 308. The dynamic deflection of an electron beam may cause a desired area or a desired region of interest to be scanned iteratively, for example in a raster scan pattern, to generate secondary electron beams (e.g., 236, 238, and 240 of FIG. 2A) for sample inspection. Deflectors 309-1 or 309-2 can be configured to deflect an electron beam in X- or Y-axis directions. As used herein, X-axis and Y-axis form Cartesian coordinates of an arbitrary reference frame, where the electron beam may propagate along a Z-axis or primary optical axis 304. The X- axis refers to the horizontal axis or the lateral axis extending along the width of the paper, and the Y- axis refers to the vertical axis extending in-and-out of the plane of the paper in the view of FIG. 2A, FIG. 2B, or FIG. 3A.

[0062] Reference is now made to FIG. 3B, which shows a representation of a charged particle beam passing through a deflector, consistent with embodiments of the present disclosure. In some embodiments, a charged particle beam may be deflected as it passes through a region between a pair of electrodes 335 and 345 of a deflector (such as electrodes e2 and e4 in subsequent FIG. 3C). As shown in FIG. 3B, a charged particle beam 320 may travel along an axis 350. Axis 350 may align with the Z-axis of a charged particle beam system. Electrodes 335 and 345 may be disposed on either side of axis 350. Voltages may be applied to electrodes 335 and 345. Electric field may be formed between the electrodes, the components of the electric field being substantially perpendicular to the direction of travel of charged particle beam 320. As charged particle beam 320 travels through the resulting electric field, it may be influenced by the electric field. For example, its trajectory may be altered. A deflection scanning unit may use deflectors to deflect a beam so as to scan the beam across a region on a sample.

[0063] Reference is now made to FIG. 3C, which is a diagram illustrating a configuration of electrodes of a deflector, consistent with embodiments of the present disclosure. FIG. 3C shows a multi-pole structure with four electrodes el-e4 that can be configured to function in different ways based on the voltages applied to each of the electrodes. A deflector (e.g., deflector 309-1 or 309-2 of FIG. 3A) may be formed using electrodes el-e4. In some embodiments, a deflection voltage may be formed between opposing pairs of electrodes (e.g., the pair formed by electrodes e2 and e4; or the pair formed by electrodes el and e3). Multiple pairs of electrodes may be combined so that deflection in a two-dimensional plane is possible. For example, a first pair of electrodes (e.g., electrodes e2 and e4) can operate to deflect a beam in an X-direction and a second pair of electrodes (e.g., electrodes el and e3) can operate to deflect a beam in a Y-direction. A deflector may be located in the region of anobjective lens in a SEM system. The deflector may be used to dynamically direct a beam to a desired location on a sample surface. In some embodiments, there may be multiple beams that may be directed to multiple locations on the sample surface.

[0064] As illustrated in FIG. 3A, a deflection scanning unit can comprise two deflectors 309-1 and 309-2 that are stacked in a z-direction and are configured to cooperate with each other to precisely manipulate a beam. Because a minor error in one or both of the deflectors in this configuration could cause the trajectory of the beam to be deviated further from an intended trajectory, accurate and precise manipulation of deflectors is more critical. While a deflection scanning unit (e.g., deflection scanning unit 226 of FIG. 2A) or a deflector unit (e.g., deflector unit 132c of FIG. 2B) is illustrated to comprise two deflectors 309-1 and 309-2 each having four electrodes el-e4, it should be noted that any number of deflectors with any number of electrodes may be used in embodiments of this disclosure, not limited to the configuration illustrated in FIGs. 3A-3C. It is also appreciated that any pair of electrodes can be controlled to deflect a beam in any direction other than an X-direction or a Y-direction.

[0065] Reference is now made to FIG. 4, which illustrates an exemplary configuration of a deflection control unit 400 associated with charged-particle beam deflectors (e.g., primary electron beam deflectors 309-1 and 309-2), consistent with embodiments of the present disclosure. As illustrated, each primary electron beam deflector may be electronically driven by a corresponding driver system. As an example, deflection control unit 400 may comprise a driver system 425-1 associated with primary electron beam deflector 309-1, and a driver system 425-2 associated with primary electron beam deflector 309-2. As shown in FIG. 4, deflector 309-1 can be implemented to comprise four electrodes 401-404, and deflector 309-2 can be implemented to comprise four electrodes 405-408.

[0066] As shown in FIG. 4, deflection control unit 400 may further comprise a scan control unit 450. Scan control unit 450 may be configured to generate a deflection signal 430-1 to 430-4 configured to be applied to primary electron beam deflectors 309-1 and 309-2. Deflection signal 430-1 to 430-4 may comprise a voltage / current signal applied to a corresponding electrode(s) of a primary electron beam deflector. While FIG. 4 illustrates that deflection control unit 400 comprises a single scan control unit 450 configured to generate and to supply deflection signals for multiple driver systems (e.g., 425-1 and 425-2), it should be appreciated that any number of scan control unit 450 may be used in embodiments of this disclosure, such as a separate scan control unit can be utilized for each driver system.

[0067] In some embodiments, scan control unit 450 can generate a plurality of deflection signals corresponding to a plurality of electrodes 401 to 408 of deflectors 309-1 and 309-2. As shown in FIG. 4, scan control unit 450 can generate deflection signals 430-1 to 430-4 for manipulating electrodes 401-408 of deflectors 309-1 and 309-2. In some embodiments, a driver system (e.g., driver system 425-01 or 425-2) can comprise a plurality of DACs to convert digital deflection signals (e.g.,deflection signals 430-1 to 430-4) to analog deflection signals when deflection signals 430-1 to 430-4 are digital signals. In some embodiments, a driver system (e.g., driver system 425-1 or 425-2) can further comprise one or more power amplifiers that are configured to generate driving signals (e.g., driving signals 431 to 438) corresponding to the deflection signals (e.g., deflection signals 430-1 to 430-4). It is to be appreciated that although not illustrated, driver system (e.g., driver system 425-1 or 425-2) may include other components and circuitry such as variable gain amplifiers, power supplies, timing circuits, etc. as appropriately needed to manipulate primary electron beam traveling along primary optical axis (e.g., primary optical axis 304 of FIG. 3A). In some embodiments, driver system 425-1 or 425-2 may also include circuitry for calibration, offset and gain adjustments, scanning pattern generation, or diagnostics, which may not be described in the present disclosure for simplicity. In some embodiments, a pair of electrodes can be controlled to deflect a beam in a predetermined direction. For example, a first pair of electrodes 402 and 404 can be controlled to deflect a beam in an X-direction and a second pair of electrodes 401 and 403 can be controlled to deflect a beam in a Y- direction. To deflect a beam in an X-direction, driving signals 432 and 434 having a same absolute value and opposite polarity (e.g., +Vx and -Vx) can be applied to the first pair of electrodes 402 and 404. Similarly, to deflect a beam in a Y-direction, driving signals 431 and 433 having a same absolute value and opposite polarity (e.g., +VY and -VY) can be applied to the second pair of electrodes 401 and 403. It will be appreciated that the other pairs of electrodes (e.g., a third pair of electrodes 406 and 408 and a fourth pair of electrodes 405 and 407) can be controlled in a similar way to deflect a beam in a certain direction.

[0068] Reference is now made to FIG. 5, which illustrates a deflector driver system architecture with a pseudo-differential amplifier utilizing dual single-ended power amplifiers. In some embodiments, driver system 500 may be driver system 425-1 or 425-2 of FIG. 4 for driving deflector electrodes, e.g., deflector electrodes 401-408. Driver system 500 can be configured to receive deflection signals and to generate high voltage driving signals for deflector electrodes. As shown in FIG. 5, driver system 500 may comprise a pattern generator 510 and a deflection driver 520.

[0069] In some embodiments, deflection pattern generator 510 may include one or more digital-to- analog converters (DAC) that convert digital deflection signal(s) to analog deflection signal(s). FIG.5 illustrates that deflection pattern generator 510 includes two DACs 511-1 and 511-2. As shown in FIG. 5, first DAC 511-1 is configured to receive a first digital deflection signal 501-1 and to generate differential analog deflection signals 502-1 and 502-2. First and second differential analog deflection signals 502-1 and 502-2 can have a same absolute value with opposite polarity, e.g., +S and -S. In some embodiments, first digital deflection signal 501-1 can be a signal to manipulate a beam in a certain direction, e.g., an X-direction. First and second differential analog deflection signals 502-1 and 502-2 can have values +Sx and -Sx respectively. Similarly, as shown in FIG. 5, second DAC 511-2 is configured to receive a second digital deflection signal 501-2 and to generate differential analog deflection signals 502-3 and 502-4. Second digital deflection signal 501-2 can be a signal tomanipulate a beam in a different direction, e.g., a Y-direction. Third and fourth differential analog deflection signals 502-3 and 502-4 can have values +Sy and -Sy respectively.

[0070] As shown in FIG. 5, pattern generator 510 may further include other components and circuitry such as various amplifiers. For example, pattern generator 510 can include a transimpedance amplifier 512-1 to 512-4 to convert impedance of analog deflection signals 502-1 to 502-4. In some embodiments, analog deflection signals 502-1 to 502-4 can be in the form of +Vx, -Vx, +Vy, and -Vy respectively after transimpedance amplifier 512-1 to 512-4 converts impedance, e.g., from a current to a voltage. As shown in FIG. 5, pattern generator 510 can further include an additional amplifier 513 that is configured to amplify the deflection signals. Amplifier 513 can be configured to correct a common-mode voltage of the deflection signals to be transmitted to deflection driver 520. As shown in FIG. 5, amplifier 513 can be a fully differential amplifier that receives differential inputs and has differential outputs. By using a fully differential amplifier, an EMI coupling issue along the transmission path can be reduced. In some embodiments, some of deflection signals can be superimposed before being provided as an input to amplifier 513. In some embodiments, deflection signals having a positive polarity can be superimposed and provided as one differential input to amplifier 513, and deflection signals having a negative polarity can be superimposed and provided as another differential input to amplifier 513. In FIG. 5, first analog deflection signal 502-1 (+Vx) and third analog deflection signal 502-3 (+Vy) are superimposed to form a first superimposed signal 503-1 (summation of +Vx and +Vy) and provided as a first differential input to amplifier 513. Similarly, second analog deflection signal 502-2 (-Vx) and fourth analog deflection signal 502-4 (-Vy) are superimposed to form a second superimposed signal 503-2 (summation of -Vx and -Vy) and provided as a second differential input to amplifier 513.

[0071] As shown in FIG. 5, deflection signals 502-1 to 502-4 can be provided to deflection driver 520 after deflection signals 502-1 to 502-4 are impedance converted, superimposed, or amplified by pattern generator 510. In some embodiments, deflection driver 520 may include a pseudo-differential power amplifier 515 that is configured to generate high voltage differently driving signals. As shown in FIG. 5, pseudo-differential power amplifier 515 can be implemented with two separate single- ended power amplifiers 515-1 and 515-2. In FIG. 5, first single-ended power amplifier 515-1 can be configured to receive first superimposed signal 503-1 (e.g., summation of +Vx and +Vy) and to output first superimposed driving signal 504-1, e.g., as summation of +Vox and +VOY. Similarly, second single-ended power amplifier 515-2 can be configured to receive second superimposed signal 503-2 (e.g., summation of -Vx and -VY) and to output second superimposed driving signal 504-2, e.g., as summation of -Vox and -Voy. In some embodiments, first single-ended power amplifier 515-1 and second single-ended power amplifier 515-2 can be configured to generate differential output signals having a same absolute value with opposite polarity when inputs to first single-ended power amplifier 515-1 and second single-ended power amplifier 515-2 are differential signals having a same absolute value with opposite polarity. In FIG. 5, as the inputs to first single-ended power amplifier 515-1 andsecond single-ended power amplifier 515-2 are differential signals having the same absolute value (summation of Vx and VY) with opposite polarity, first single-ended power amplifier 515-1 and second single-ended power amplifier 515-2 can function as if they were a single differential amplifier that generates differential output signals. In this regard, first single-ended power amplifier 515-1 and second single-ended power amplifier 515-2 are collectively called a pseudo-differential amplifier in the present disclosure.

[0072] In some embodiments, the outputs of deflection driver 520 can be divided before being applied to corresponding electrodes because the outputs are superimposed output signals. For example, first superimposed driving signal 504-1 can be used to generate two driving signals +Vox and +VOY before being applied to corresponding electrodes, e.g., driving signal +Vox to electrode e2 of FIG. 3C or electrode 402 of FIG. 4 and driving signal +VOY to electrode el of FIG. 3C or electrode 401 of FIG. 4. Similarly, second superimposed driving signal 504-2 can be used to generate two driving signals -Vox and -VOY before being applied to corresponding electrodes, e.g., driving signal -Vox to electrode e4 of FIG. 3C or electrode 404 of FIG. 4 and driving signal -VOY to electrode e3 of FIG. 3C or electrode 403 of FIG. 4. As shown in FIG. 5, deflection driver 520 may further include another differential amplifier 514 to cancel or minimize common-mode noise injected along the path from pattern generator 510 to pseudo-differential power amplifier 515.

[0073] While it has been illustrated that driver system 500 is configured to generate driving signals for manipulating a beam both in an X-direction and a Y-direction, it will be appreciated that driver system 500 can be configured to generate driving signals for manipulating a beam in one direction. For example, driver system 500 can be configured to generate driving signals for manipulating a beam in an X-direction. In these implementations, first and second superimposed signals 503-1 and 503-2 can be modified before being inputted into power amplifiers 515-1 and 515-2 by considering coordinates of a wafer on a wafer stage compared to coordinates of deflector electrodes. For example, first and second superimposed signals 503-1 and 503-2 can be modified to generate differential signals that represent an actual deflection control signal in an X-direction. In some embodiments, first and second superimposed signals 503-1 and 503-2 can be modified based on coordinates of a wafer on a wafer stage, coordinates of deflector electrodes, and rotation angles for the wafer coordinates and deflector electrodes coordinates. In these implementations, the outputs of power amplifiers 515-1 and 515-2 can be differential driving signals for electrodes that are controlled to deflect a beam in an X- direction, e.g., a first pair of electrodes e2 and e4 of FIG. 3C or a first pair of electrodes 402 and 404 of FIG. 4. Similarly, in some embodiments, an additional driver system similar to driver system 500 can be utilized to generate driving signals to manipulate a beam in a Y-direction. In these implementations, the outputs of power amplifiers of an additional driver system can be differential driving signals for electrodes that are controlled to deflect a beam in a Y-direction, e.g., a second pair of electrodes el and e3 of FIG. 3C or a second pair of electrodes 401 and 403 of FIG. 4.

[0074] Reference is now made to FIG. 6, which illustrates a single-ended power amplifier circuit configuration. Single-ended power amplifier 600 can be any one of first single-ended power amplifier 515-1 and second single-ended power amplifier 515-2 of FIG. 5. Single-ended power amplifier 600 can include an input stage 610, a bias stage 620, a gain stage 630, and an output stage 640. Bias stage 620 provides single-ended power amplifier 600 with a current for driving all transistors included in single-ended power amplifier 600. The current from bias stage 620 is delivered to input stage 610. In input stage 610, first input signal 601-1 and second input signal 601-2 are inputted into input stage 610. As shown in FIG. 6, input stage 610 can be implemented by including various transistors such as QI, Q2, Q6, Q7, Q10A, Q10B, and Q13 and is configured to measure a difference signal between two input signals 601-1 and 601-2 and to deliver the difference signal to gain stage 630. In gain stage 630, the difference signal can be amplified with a predetermined gain. In some embodiments, the difference signal can be amplified in gain stage 630 to a high voltage greater than 100V. In some embodiments, the high voltage greater than 100V can be accomplished by utilizing cascaded multiple transistors operating at a lower voltage. While it is not shown in FIG. 6, gain stage 630 may further include a phase compensation capacitance to prevent internal oscillation. The amplified difference signal proceeds to output stage 640, which functions as a buffer to prevent variations in characteristics of single-ended power amplifier 600 based on load effects, e.g., resistance connected to the output terminal. In output stage 640, a high current can be provided to improve a slew rate of the power amplifier. In FIG. 6, output stage 640 further includes a current limiter comprising transistors Q12 and Q17 to protect the circuitry from high currents while improving a slew rate by using the high currents. As shown in FIG. 6, supply power +Vs and -Vs is provided to single-ended power amplifier circuitry and a single output signal 603 is taken from output terminal OUT. Single-ended power amplifier 600 can be integrated into one IC chip.

[0075] Referring back to FIG. 5, driver system 500 is implemented utilizing first single-ended power amplifier 515-1 and second single-ended power amplifier 515-2 each of which constitutes one IC chip. Using separate IC chips results in unavoidable element mismatch even though with selection of the highest practical accurate components and extensively optimized PCB design. Element mismatch further limits common-mode rejection ratio (CMRR) leading to higher noise level and lower image resolution, and further limits signal linearity that results in higher image distortion. The multi-chip implementation also results in increased design complexity as well as extra circuit adjustment efforts, which limits high volume production. The multi-chip implementation also suffers from lower design integrity between two separate chips, and such design integrity makes it difficult to troubleshoot to solve problems caused by the mismatch between two chips. Further, driver system 500 utilizing a pseudo differential power amplifier suffers from a high noise level at least partly stemming from low common-mode rejection ratio due to element mismatch between two single-ended power amplifiers. Further, because two IC chips takes up space on the PCB having a limited area, deflection driver 520 is mounted on a separate PCB from pattern generator 510 including multiple DACs 511-1 and 511-2,which leads to additional components (e.g., amplifiers 513 and 514) to be mounted on PCBs. The longer signal transmission distance caused by using two separate PCBs may also introduces additional noise into the system and thus worsen the noise issue of driver system 500. Therefore, driver system 500 does not meet the noise criteria demanded for current and next generation systems, such as less than 2.5nV / sqrt(Hz).

[0076] Reference is now made to FIG. 7, which illustrates a driver system architecture with a fully - differential power amplifier, consistent with embodiments of the present disclosure. In some embodiments, driver system 700 may be driver system 425-1 or 425-2 of FIG. 4 for driving deflector electrodes, e.g., deflector electrodes 401-408. Driver system 700 can be configured to receive deflection signals and to generate high voltage fully differential driving signals. According to some embodiments of the present disclosure, driver system 700 may comprise a pattern generator 710 and a deflection driver 720.

[0077] According to some embodiments of the present disclosure, pattern generator 710 may include one or more DACs (e.g., DACs 511-1 and 511-2) that convert digital deflection signal(s) to analog deflection signal(s). In some embodiments, pattern generator 710 may further include a transimpedance amplifier 512-1 to 512-4 to convert impedance of analog deflection signals 502-1 to 502-4. As indicated by the same reference numbers, DACs 511-1 and 511-2 and transimpedance amplifier 512-1 to 512-4 of pattern generator 710 in FIG. 7 may be the same or similar to DACs 511- 1 and 511-2 and transimpedance amplifier 512-11 to 512-4 of pattern generator 510 in FIG. 5. Therefore, overlapping descriptions as to operations and functions of DACs 511-1 and 511-2 and transimpedance amplifier 512-1 to 512-4 of pattern generator 710 in FIG. 7 will be omitted here for simplicity.

[0078] According to some embodiments, deflection driver 720 may include a fully-differential power amplifier 715 that is configured to receive differential inputs and to generate high voltage differential outputs. As shown in FIG. 7, differential power amplifier 715 can be configured to receive first superimposed signal 503-1 (e.g., summation of +Vx and +Vy) and second superimposed signal 503-2 (e.g., summation of -Vxand -VY) as differential inputs. In some embodiments, differential power amplifier 715 can also be configured to output first superimposed driving signal 704-1 (e.g., summation of +Vox and +VOY) and second superimposed driving signal 704-2 (e.g., summation of - Vox and -VOY) as differential outputs. As shown in FIG. 7, first superimposed signal 503-1 and second super imposed signal 503-2 may be provided to differential power amplifier 715 without having to utilize an additional low voltage fully differential amplifier because deflection driver 720 is positioned adjacent to pattern generator 710 on the same PCB 701. Further, because deflection driver 720 is positioned adjacent to generator 710, common-mode noise that could be injected along the path between deflection driver 720 and pattern generator 710 can be minimized or reduced.

[0079] In some embodiments, the outputs of deflection driver 720 can be divided before being applied to corresponding electrodes because the outputs are superimposed output signals. Forexample, first superimposed driving signal 704-1 can be used to generate two driving signals +Vox and +VOY before being applied to corresponding electrodes, e.g., driving signal +Vox to electrode e2 of FIG. 3C or electrode 402 of FIG. 4 and driving signal +VOY to electrode el of FIG. 3C or electrode 401 of FIG. 4. Similarly, second superimposed driving signal 704-2 can be used to generate two driving signals -Vox and -VOY before being applied to corresponding electrodes, e.g., driving signal -Vox to electrode e4 of FIG. 3C or electrode 404 of FIG. 4 and driving signal -VOY to electrode e3 of FIG. 3C or electrode 403 of FIG. 4.

[0080] While it has been illustrated that driver system 700 is configured to generate driving signals for manipulating a beam both in an X-direction and a Y-direction, it will be appreciated that driver system 700 can be configured to generate driving signals for manipulating a beam in one direction. For example, driver system 700 can be configured to generate driving signals for manipulating a beam in an X-direction. In these implementations, first and second superimposed signals 503-1 and 503-2 can be modified before being inputted into differential power amplifier 715 by considering coordinates of a wafer on a wafer stage compared to coordinates of deflector electrodes. For example, first and second superimposed signals 503-1 and 503-2 can be modified to generate differential signals that represent an actual deflection control signal in an X-direction. In some embodiments, first and second superimposed signals 503-1 and 503-2 can be modified based on coordinates of a wafer on a wafer stage, coordinates of deflector electrodes, and rotation angles for the wafer coordinates and deflector electrodes coordinates. In these implementations, the outputs of differential power amplifier 715 can be differential driving signals for electrodes that are controlled to deflect a beam in an X- direction, e.g., a first pair of electrodes e2 and e4 of FIG. 3C or a first pair of electrodes 402 and 404 of FIG. 4. Similarly, in some embodiments, an additional driver system similar to driver system 700 can be utilized to generate driving signals to manipulate a beam in a Y-direction. In these implementations, outputs of a differential power amplifier of the additional driver system can be differential driving signals for electrodes that are controlled to deflect a beam in a Y-direction, e.g., a second pair of electrodes el and e3 of FIG. 3C or a second pair of electrodes 401 and 403 of FIG. 4.

[0081] Reference is now made to FIG. 8, which illustrates a fully-differential power amplifier circuit configuration, consistent with embodiments of the present disclosure. In some embodiments, differential power amplifier circuitry 715 may be fully-differential power amplifier 715 included in deflection driver 720 of FIG. 7. According to some embodiments of the present disclosure, differential power amplifier 715 may include one input stage 610, two bias stages 620 and 820, two gain stages 630 and 830, and two output stages 640 and 840. Similar to single-ended power amplifier 600 of FIG. 6, input stage 610, first bias stage 620, first gain stage 630, and first output stage 640 of FIG. 8 can be configured to generate a first output 603-1 among differential outputs 603-1 and 603-2 in response to differential input signals 601-1 and 601-2. For example, input stage 610, first bias stage 620, first gain stage 630, and first output stage 640 of FIG. 8 can be configured to generate positive output +Vo by amplifying a difference signal between two input signals 601-1 and 601-2inputted to input stage 610. Similarly, input stage 610, second bias stage 820, second gain stage 830, and second output stage 840 of FIG. 8 can be configured to generate a second output 603-2 among differential outputs 603-1 and 603-2 in response to differential input signals 601-1 and 601-2. For example, input stage 610, second bias stage 820, second gain stage 830, and second output stage 840 of FIG. 8 can be configured to generate negative output -Vo by amplifying a difference signal between two input signals 601-1 and 601-2 inputted to input stage 610. As indicated by the same reference numbers, input stage 610, first bias stage 620, first gain stage 630, and first output stage 640 in FIG. 8 may be the same or similar to input stage 610, bias stage 620, gain stage 630, and output stage 640 in FIG. 6. Further, as shown from FIG. 6 and FIG. 8, second bias stage 820, second gain stage 830, and second output stage 840 of differential power amplifier 715 in FIG. 8 can be implemented by mirroring first bias stage 620, first gain stage 630, and first output stage 640 with some modifications such that second bias stage 820, second gain stage 830, and second output stage 840 are to generate second output 603-2 having the same absolute value with opposite polarity to first output signal 603-1. Therefore, as described referring to FIG. 6, two differential outputs 603-1 and 603-2 can be high voltage differential signals that meet the criteria demanded in the industry, such as greater than 100V.

[0082] According to some embodiments of the present disclosure, differential power amplifier 715 may further include a common-mode control circuit 810. According to some embodiments, commonmode control circuit 810 may include an error amplifier 811. In some embodiments, error amplifier 811 can be configured to compare a common-mode voltage of differential outputs 603-1 and 603-2 with a reference voltage VREF- AS shown in FIG. 8, error amplifier 811 is coupled to differential outputs 603-1 and 603-2 and is configured to receive a common-mode voltage of two differential outputs 603-1 and 603-2 as a feedback input via a first input terminal 812. In some embodiments, common-mode control circuit 810 may further include two resistors 814 and 815. In FIG. 8, first resistor 814 is coupled between first input terminal 812 of error amplifier 811 and first output terminal +OUT, and second resistor 815 is coupled between first input terminal 812 of error amplifier 811 and second output terminal -OUT. In some embodiments, first resistor 814 and second resistor 815 may have the same resistance value such that the common-mode voltage as a median value of two differential output signals 603-1 and 603-2 can be measured and inputted as the feedback input at first input terminal 812. As shown in FIG. 8, error amplifier 811 may be configured to receive reference voltage VREF as a reference input via a second input terminal 813. According to some embodiments of the present disclosure, error amplifier 811 is configured to compare a feedback input and a reference input and to output a difference 816 between the feedback input and the reference input. As shown in FIG. 8, difference 816 is provided back to differential power amplifier 715 to adjust output signals 603-1 and 603-2 so to cancel difference 816. For example, output signals 603-1 and 603-2 can be adjusted according to difference 816 such that the common-mode voltage of two output signals 603-1 and 603-2 can be equal to reference voltage VREF- In some embodiments, reference voltageVREF can be set to value OV. As shown in FIG. 8, difference 816 can be provided back to first gain stage 630 to adjust first output signal 603-1 and to second gain stage 830 to adjust second output signal 603-2. In some embodiments, when a non-zero value as difference 816 is provided to gain stages 630 and 830, the output signals 603-1 and 603-2 can be adjusted to cancel out the difference. In some embodiments, common-mode control circuit 810 is closed loop feedback circuit and is configured to adjust the outputs automatically.

[0083] According to some embodiments of the present disclosure, fully-differential power amplifier 715 can be manufactured utilizing a high voltage semiconductor manufacturing process that support high voltage greater than 100V. In some embodiments, fully-differential power amplifier 715 can be manufactured with semiconductor materials that can endure high voltage, such as gallium nitride, silicon carbide, etc. In some embodiments, fully-differential power amplifier 715 can be manufactured without utilizing a complementary metal-oxide semiconductor (CMOS), which is generally for low voltage device. In some embodiments, fully-differential power amplifier 715 that operates at a high voltage greater than 100V can be accomplished by utilizing cascaded multiple transistors each operating at a lower voltage. According to some embodiments of the present disclosure, fully-differential power amplifier 715 can be integrated into a single IC chip, which does not have an element mismatch issue between two separate components. Thereby, fully-differential power amplifier 715 can show improved common-mode rejection ratio (CMSS) without needing to resolve element mismatch issues. Because fully-differential power amplifier 715 is a true differential amplifier, not a pseudo-differential amplifier, fully-differential power amplifier 715 having better element matching can improve linearity, which results in reduced image distortion. In fully- differential power amplifier 715, even order distortion term can be canceled with fully differential outputs. As shown in FIG and FIG. 8, because fully-differential power amplifier 715 is implemented to have two differential outputs utilizing a common input stage (e.g., input stage 610), the area taken by fully-differential power amplifier 715 can be reduced compared to two single-ended power amplifiers. Thus, fully-differential power amplifier 715 can be integrated in one IC chip, which can be mounted on a same PCB along with pattern generator 710, which can prevent additional components (such as additional amplifiers 513 and 514 of FIG. 5) from having to be included in driver system 700. Such reduction of components on driver system 700 and of signal transmission distance can also attribute to reducing noise of the system. According to some embodiments of the present disclosure, driver system 700 can meet the noise criteria demanded for current and next generation systems, such as less than 2.5nV / sqrt(Hz) while high voltage driving signals, which meet the demanded criteria of high voltage (greater than 100V), high speed (power bandwidth greater than IMhz), slew rate (greater than 500V / ps), so on. If a driving signal is maintained to be lower than 100V, the industry scan rate demand (e.g., 1.2 giga samples per second) may not be achieved without sacrificing signal quality. For example, when a driving signal lower than 100V is used, 1.2 giga samples per second can be achieved by using a deflector with higher sensitivity, which ultimatelyresults in degrading image resolution. Therefore, in this disclosure, a higher voltage level may refer to a voltage level greater than 100V, which can support the industry scan rate demand, e.g., 1.2 giga samples per second without sacrificing signal quality.

[0084] Further, according to some embodiments of the present disclosure, driver system 700 can provide higher design integrity and increased circuit component commonality, which leading to a simplified PCB design and benefiting future RACK-based deflection driver design. According to some embodiments of the present disclosure, increased circuit component commonality results in a reduced volume of circuitry required to deliver a higher voltage than conventional systems. According to some embodiments of the present disclosure, driver system 700 can provide lower power consumption, which results in a simplified heatsinking design and can also aid in achieving a higher slew rate. According to some embodiments of the present disclosure, driver system 700 can provide a simplified circuit adjustment strategy, which results in improved production capacity for high volume production. According to some embodiments of the present disclosure, common-mode control circuit 800 is also integrated into the same IC chip of fully-differential amplifier, a slew rate can be improved compared to implementation having a feedback loop in the PCB area.

[0085] FIG. 9 is a flow chart illustrating an exemplary method for operating a deflector driver with a fully-differential power amplifier, consistent with embodiments of the present disclosure. The steps of method 900 can be performed by a deflector driver system, e.g., driver system 700 of FIG. 7 including fully-differential power amplifier 715. It is appreciated that the illustrated method 900 can be altered to modify the order of steps and to include additional steps.

[0086] In step S910, fully-differential outputs are generated by fully-differential power amplifier 715. In some embodiments, the fully-differential outputs may have an absolute value greater than 100V. In step S920, a common-mode voltage of the differential outputs of the differential amplifier is measured by common-mode control circuit 810. In step S930, a difference between the commonmode voltage and a reference voltage is provided back to the differential amplifier. In some embodiments, the difference can be provided to gain stages of the differential amplifier. In step S940, the differential-outputs can be adjusted based on the difference such that the difference can be canceled. In some embodiments, the adjusted fully-differential outputs can be applied to a plurality of deflector electrodes to influence a charged particle beam of the charged-particle inspection apparatus based on the fully-differential outputs.

[0087] A non-transitory computer readable medium may be provided that stores instructions for a processor of a controller (e.g., controller 109 of FIG. 1) to carry out, among other things, image inspection, image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, condenser lens adjusting, activating charged-particle source, beam deflecting, and method 900. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc Read Only Memory (CD-ROM), any other optical data storage medium, any physical medium withpatterns of holes, a Random Access Memory (RAM), a Programmable Read Only Memory (PROM), and Erasable Programmable Read Only Memory (EPROM), a FLASH-EPROM or any other flash memory, Non-Volatile Random Access Memory (NVRAM), a cache, a register, any other memory chip or cartridge, and networked versions of the same.

[0088] The embodiments may further be described using the following clauses:1. A charged-particle inspection apparatus, comprising: a charged-particle beam source configured to generate a primary charged-particle beam for sample scanning; a deflector driver comprising a fully-differential amplifier that is configured to generate fully- differential outputs of which absolute value is greater than 100V; and a plurality of deflector electrodes coupled to the fully-differential outputs and configured to influence the charged particle beam based on the fully-differential outputs.2. The apparatus of clause 1, wherein the differential amplifier is manufactured utilizing a high voltage semiconductor manufacturing process that supports a voltage level greater than 100V.3. The apparatus of clause 1 or 2, wherein the deflector driver further comprises: a plurality of digital to analog converters (DACs) of which outputs are utilized to generate input differential signals for the fully-differential amplifier, wherein the plurality of DACs and the fully-differential amplifier are mounted on one printed circuit board.4. The apparatus of any one of clauses 1-3, wherein the deflector driver further comprises: a common-mode control circuit configured to measure a common-mode voltage of the fully- differential outputs of the fully-differential amplifier and to provide a difference between the common-mode voltage and a reference voltage to the fully-differential amplifier such that the fully- differential outputs of the differential amplifier are adjusted based on the difference, wherein the fully-differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.5. The apparatus of any one of clauses 1-4, wherein the fully-differential amplifier is configured to operate with a power bandwidth greater than IMhz.6. The apparatus of any one of clauses 1-5, wherein the fully-differential amplifier is configured to operate at a slew rate greater than 500V / ps.7. The apparatus of any one of clauses 1-6, wherein the fully-differential amplifier is configured to operate at a noise level less than 2.5nV / sqrt(Hz).8. A deflector driver for driving a deflector of a charged-particle inspection apparatus, the deflector driver comprising: a fully-differential amplifier that is configured to generate fully-differential outputs of which absolute value is greater than 100V,wherein the fully-differential outputs enable a plurality of deflector electrodes of the deflector to influence a charged particle beam of the charged-particle inspection apparatus based on the fully- differential outputs.9. The deflector driver of clause 8, wherein the fully-differential amplifier is manufactured utilizing a high voltage semiconductor manufacturing process that supports a voltage level greater than 100V.10. The deflector driver of clause 8 or 9, wherein the deflector driver further comprises: a plurality of digital to analog converters (DACs) of which outputs are utilized to generate input differential signals for the fully-differential amplifier, wherein the plurality of DACs and the fully-differential amplifier are mounted on one printed circuit board.11. The deflector driver of any one of clauses 8-10, wherein the deflector driver further comprises: a common-mode control circuit configured to measure a common-mode voltage of the fully- differential outputs of the fully-differential amplifier and to provide a difference between the common-mode voltage and a reference voltage to the fully-differential amplifier such that the fully- differential outputs of the fully-differential amplifier are adjusted based on the difference, wherein the fully-differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.12. The deflector driver of any one of clauses 8-11, wherein the fully-differential amplifier is configured to operate with a power bandwidth greater than IMhz.13. The deflector driver of any one of clauses 8-12, wherein the fully-differential amplifier is configured to operate at a slew rate greater than 500V / ps.14. The deflector driver of any one of clauses 8-13, wherein the fully-differential amplifier is configured to operate at a noise level less than 2.5nV / sqrt(Hz).15. A method of operating a deflector driver for driving a deflector of a charged-particle inspection apparatus, the method comprising: generating, by a fully-differential amplifier included in the deflector driver, fully-differential outputs of which absolute value is greater than 100V; measuring, by a common-mode control circuit included in the deflector driver, a commonmode voltage of the fully-differential outputs of the fully-differential amplifier; providing, by the common-mode control circuit, a difference between the common-mode voltage and a reference voltage to the fully-differential amplifier; and adjusting the fully-differential outputs of the differential amplifier based on the difference, wherein the adjusted fully-differential outputs enable a plurality of deflector electrodes of the deflector to influence a charged particle beam of the charged-particle inspection apparatus based on the fully-differential outputs, andwherein the fully-differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.16. The method of clause 15, further comprising: generating, input differential signals for the fully-differential amplifier by utilizing a plurality of digital to analog converters (DACs) included in the deflector driver, wherein the plurality of DACs and the fully-differential amplifier are mounted on one printed circuit board.17. The method of clause 15 or 16, wherein the fully-differential amplifier is manufactured utilizing a high voltage semiconductor manufacturing process that supports a voltage level greater than 100V.18. The method of any one of clauses 15-17, wherein the fully-differential amplifier is configured to operate with a power bandwidth greater than IMhz.19. The method of any one of clauses 15-18, wherein the fully-differential amplifier is configured to operate at a slew rate greater than 500V / ps.20. The method of any one of clauses 15-19, wherein the fully-differential amplifier is configured to operate at a noise level less than 2.5nV / sqrt(Hz).21. A deflector driver assembly comprising : a fully-differential amplifier configured to generate fully-differential outputs of which absolute value is greater than 100V; and a common-mode control circuit configured to measure a common-mode voltage of the fully- differential outputs of the fully-differential amplifier, and to provide a difference between the common-mode voltage and a reference voltage to the fully-differential amplifier, wherein the fully-differential amplifier is further configured to adjust the fully-differential outputs of the differential amplifier based on the difference, the adjusted fully-differential outputs enable a plurality of deflector electrodes of a deflector to influence a charged particle beam of a charged-particle inspection apparatus based on the fully-differential outputs, and wherein the fully-differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.22. The deflector driver assembly of clause 21, further comprising: a plurality of digital to analog converters (DACs) configured to generate input differential signals for the fully-differential amplifier, wherein the plurality of DACs and the fully-differential amplifier are mounted on one printed circuit board.23. The deflector driver assembly of clauses 21 or 22, wherein the fully-differential amplifier is manufactured utilizing a high voltage semiconductor manufacturing process that supports a voltage level greater than 100V.24. The deflector driver assembly of any one of clauses 21-23, wherein the fully-differential amplifier is configured to operate with a power bandwidth greater than IMhz.25. The deflector driver assembly of any one of clauses 21-24, wherein the fully-differential amplifier is configured to operate at a slew rate greater than 500V / ps.26. The deflector driver assembly of any one of clauses 21-25, wherein the fully-differential amplifier is configured to operate at a noise level less than 2.5nV / sqrt(Hz).

[0089] Block diagrams in the figures may illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In this regard, each block in a schematic diagram may represent certain arithmetical or logical operation processing that may be implemented using hardware such as an electronic circuit. Blocks may also represent a module, segment, or portion of code that comprises one or more executable instructions for implementing the specified logical functions. It should be understood that in some alternative implementations, functions indicated in a block may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed or implemented substantially concurrently, or two blocks may sometimes be executed in reverse order, depending upon the functionality involved.Some blocks may also be omitted. It should also be understood that each block of the block diagrams, and combination of the blocks, may be implemented by special purpose hardware-based systems that perform the specified functions or acts, or by combinations of special purpose hardware and computer instructions.

[0090] It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The present disclosure has been described in connection with various embodiments, other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims

CLAIMS1. A charged-particle inspection apparatus, comprising: a charged-particle beam source configured to generate a primary charged-particle beam for sample scanning; a deflector driver comprising a fully-differential amplifier that is configured to generate fully- differential outputs of which absolute value is greater than 100V; and a plurality of deflector electrodes coupled to the fully-differential outputs and configured to influence the charged particle beam based on the fully-differential outputs.

2. The apparatus of claim 1, wherein the differential amplifier is manufactured utilizing a high voltage semiconductor manufacturing process that supports a voltage level greater than 100V.

3. The apparatus of claim 1, wherein the deflector driver further comprises: a plurality of digital to analog converters (DACs) of which outputs are utilized to generate input differential signals for the fully-differential amplifier, wherein the plurality of DACs and the fully-differential amplifier are mounted on one printed circuit board.

4. The apparatus of claim 1, wherein the deflector driver further comprises: a common-mode control circuit configured to measure a common-mode voltage of the fully- differential outputs of the fully-differential amplifier and to provide a difference between the common-mode voltage and a reference voltage to the fully-differential amplifier such that the fully- differential outputs of the differential amplifier are adjusted based on the difference, wherein the fully-differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.

5. The apparatus of claim 1, wherein the fully-differential amplifier is configured to operate with a power bandwidth greater than IMhz.

6. The apparatus of claim 1, wherein the fully-differential amplifier is configured to operate at a slew rate greater than 500V / ps.

7. The apparatus of claim 1, wherein the fully-differential amplifier is configured to operate at a noise level less than 2.5nV / sqrt(Hz).

8. A deflector driver for driving a deflector of a charged-particle inspection apparatus, the deflector driver comprising: a fully-differential amplifier that is configured to generate fully-differential outputs of which absolute value is greater than 100V, wherein the fully-differential outputs enable a plurality of deflector electrodes of the deflector to influence a charged particle beam of the charged-particle inspection apparatus based on the fully- differential outputs.

9. The deflector driver of claim 8, wherein the fully-differential amplifier is manufactured utilizing a high voltage semiconductor manufacturing process that supports a voltage level greater than 100V.

10. The deflector driver of claim 8, wherein the deflector driver further comprises: a plurality of digital to analog converters (DACs) of which outputs are utilized to generate input differential signals for the fully-differential amplifier, wherein the plurality of DACs and the fully-differential amplifier are mounted on one printed circuit board.

11. The deflector driver of claim 8, wherein the deflector driver further comprises: a common-mode control circuit configured to measure a common-mode voltage of the fully- differential outputs of the fully-differential amplifier and to provide a difference between the common-mode voltage and a reference voltage to the fully-differential amplifier such that the fully- differential outputs of the fully-differential amplifier are adjusted based on the difference, wherein the fully-differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.

12. The deflector driver of claim 8, wherein the fully-differential amplifier is configured to operate with a power bandwidth greater than IMhz.

13. The deflector driver of claim 8, wherein the fully-differential amplifier is configured to operate at a slew rate greater than 500V / ps.

14. The deflector driver of claim 8, wherein the fully-differential amplifier is configured to operate at a noise level less than 2.5nV / sqrt(Hz).

15. A method of operating a deflector driver for driving a deflector of a charged-particle inspection apparatus, the method comprising:generating, by a fully-differential amplifier included in the deflector driver, fully-differential outputs of which absolute value is greater than 100V; measuring, by a common-mode control circuit included in the deflector driver, a commonmode voltage of the fully-differential outputs of the fully-differential amplifier; providing, by the common-mode control circuit, a difference between the common-mode voltage and a reference voltage to the fully-differential amplifier; and adjusting the fully-differential outputs of the differential amplifier based on the difference, wherein the adjusted fully-differential outputs enable a plurality of deflector electrodes of the deflector to influence a charged particle beam of the charged-particle inspection apparatus based on the fully-differential outputs, and wherein the fully-differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.

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