Semiconductor substrate and power conversion device

Abstract

In the present invention, a first conductor layer includes a pair of first switch connection sections disposed so as to sandwich a third conductor layer therebetween in an orthogonal direction that is the direction orthogonal to a reference axis along a surface of one side of an insulation substrate. The third conductor layer includes: a pair of second switch connection sections arranged so as to sandwich a second conductor layer therebetween in the orthogonal direction; and a pad forming section sandwiched between the pair of first switch connection sections in the orthogonal direction and provided with an output terminal pad. A plurality of first switches are disposed symmetrically with respect to the reference axis more to an output terminal pad side than a center position between the output terminal pad and a negative electrode terminal pad in a reference axis direction that is the direction along the reference axis, and the first switches connect the first switch connection sections and the pad forming section. A plurality of second switches are disposed symmetrically with respect to the reference axis more to the negative electrode terminal pad side than the center position in the reference axis direction, and the second switches connect the second switch connection sections and the second conductor layer.

Description

Semiconductor substrate and power conversion device

[0001] The present invention relates to a semiconductor substrate and a power conversion device.

[0002] For example, Patent Document 1 discloses a semiconductor module including semiconductor elements. The semiconductor module disclosed in Patent Document 1 includes a first semiconductor element and a second semiconductor element connected in parallel to form an upper arm. The semiconductor module also includes a third semiconductor element and a fourth semiconductor element connected in parallel to form a lower arm.

[0003] Japanese Patent Application Laid-Open No. 2021-141221

[0004] The semiconductor module disclosed in Patent Document 1 is generally rectangular and includes an output terminal located at one end and a negative terminal located at the other end. The output terminal and negative terminal are located at the center of the semiconductor module's width. The first and second semiconductor elements are arranged to sandwich the center of the width. The third and fourth semiconductor elements are also arranged to sandwich the center of the width. In Patent Document 1, the first and second semiconductor elements pass current toward the center of the width, while the third and fourth semiconductor elements pass current from the center of the width toward the outside. Therefore, the path from the third semiconductor element to the fourth semiconductor element is longer than the path from the first semiconductor element to the second semiconductor element, resulting in a larger parasitic inductance in the lower arm than in the upper arm. As a result, the semiconductor module of Patent Document 1 has a structure that is prone to oscillation.

[0005] The present invention has been made in view of the above-mentioned problems, and has an object to suppress the occurrence of oscillation in a semiconductor substrate on which an upper arm and a lower arm are formed.

[0006] The present invention employs the following configuration as a means for solving the above problems.

[0007] A first aspect of the present invention is a semiconductor substrate provided with upper and lower arms that form legs, the semiconductor substrate comprising: an insulating substrate; a conductor layer formed on one surface of the insulating substrate; and a semiconductor element mounted on the conductor layer, the semiconductor element including a first conductor layer that is the conductor layer having a positive terminal pad to which a positive terminal is connected; a second conductor layer that is the conductor layer having a negative terminal pad to which a negative terminal is connected; and a third conductor layer that is the conductor layer having an output terminal pad to which an output terminal is connected. a plurality of first switch sections connecting the first conductor layer and the third conductor layer and having the semiconductor element; and a plurality of second switch sections connecting the second conductor layer and the third conductor layer and having the semiconductor element, the output terminal pad and the negative terminal pad are arranged on a reference axis, the first conductor layer has a pair of first switch section connection parts arranged to sandwich the third conductor layer therebetween in an orthogonal direction that is a direction perpendicular to the reference axis along one side surface of the insulating substrate, the third conductor layer has a pair of second switch section connection parts arranged to sandwich the second conductor layer therebetween in the orthogonal direction, and a pad forming portion sandwiched between a pair of the first switch portion connection portions and on which the output terminal pad is provided, the plurality of first switch portions are arranged symmetrically with respect to the reference axis on the output terminal pad side of a center position between the output terminal pad and the negative terminal pad in a reference axial direction that is a direction along the reference axis, connecting the first switch portion connection portion and the pad forming portion, and the plurality of second switch portions are arranged symmetrically with respect to the reference axis on the negative terminal pad side of the center position in the reference axial direction, connecting the second switch portion connection portion and the second conductor layer.

[0008] A second aspect of the present invention is a power conversion device having a power conversion circuit formed by a semiconductor element, and employs a configuration including the semiconductor substrate according to the first aspect of the present invention having the semiconductor element.

[0009] The present invention can suppress the occurrence of oscillation in the semiconductor substrate on which the upper arm and the lower arm are formed.

[0010] FIG. 1 is an exploded perspective view schematically showing the general configuration of a power conversion device according to one embodiment of the present invention. FIG. 2 is a circuit diagram showing the general electrical configuration of a power conversion device according to one embodiment of the present invention. FIG. 3 is a schematic exploded perspective view of a power module of an intelligent power module provided in a power conversion device according to one embodiment of the present invention. FIG. 4 is a schematic plan view of a power module of an intelligent power module provided in a power conversion device according to one embodiment of the present invention. FIG. 5 is a schematic enlarged view of a power module including one power device according to the present embodiment. FIG. 6 is a plan view showing the general configuration of a power device according to the present embodiment. FIG. 7 is a schematic view showing an insulating substrate and a conductor layer provided in a power device according to the present embodiment. FIG. 8 is a schematic view showing the flow of current in a power device according to the present embodiment when a drive current is supplied from a battery to a motor.

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor substrate and a power conversion device according to the present invention will be described below with reference to the drawings.

[0012] FIG. 1 is an exploded perspective view showing a schematic configuration of a power conversion device 1 according to one embodiment of the present invention. The power conversion device 1 according to this embodiment is mounted on a vehicle such as an electric automobile, and is provided between a motor M (see FIG. 3) and a battery B (see FIG. 3). The power conversion device 1 according to this embodiment performs power conversion between the motor M and the battery B. As shown in FIG. 1, the power conversion device 1 according to this embodiment includes an inverter case 2, an intelligent power module 3, and a capacitor module 4. The power conversion device 1 may also include other components, such as a DC-DC converter and a reactor (not shown).

[0013] The inverter case 2 is a case that houses the intelligent power module 3, the capacitor module 4, etc., and includes a central case 2a and a case cover 2b. The central case 2a and the case cover 2b are formed as separate parts that can be detached from each other. In FIG. 1, the case cover 2b is shown separated from the central case 2a and positioned above it. However, the installation position of the power conversion device 1 is not particularly limited. In other words, the power conversion device 1 may be mounted on a vehicle so that the case cover 2b is located to the side of the central case 2a.

[0014] The central case 2a has a bottom wall to which the intelligent power modules 3 and the capacitor modules 4 are fixed, and side walls that surround the intelligent power modules 3 and the capacitor modules 4. In other words, the central case 2a is formed in the shape of a container that is open on the case cover 2b side. Such a central case 2a is provided with water channels as necessary, and is formed to be able to guide the coolant that cools the intelligent power modules 3 and the capacitor modules 4.

[0015] The case cover 2b is fixed to the central case 2a and covers the intelligent power module 3 and the capacitor module 4. That is, the intelligent power module 3 and the capacitor module 4 are exposed when the case cover 2b is detached from the central case 2a.

[0016] Such an inverter case 2 is fixed to, for example, a housing (not shown) that covers the motor M or a gear case that houses a gear that transmits power generated by the motor M to the outside. In such a case, for example, the central case 2a is fastened to the motor housing or the gear case using bolts (not shown) or the like.

[0017] The inverter case 2 also holds a connector (not shown) for connecting the battery B. Such a connector is electrically connected to the intelligent power module 3. The inverter case 2 also holds a bus bar (not shown) that connects the connector to the intelligent power module 3, and a bus bar (not shown) that connects the intelligent power module 3 to the motor M.

[0018] The intelligent power module 3 includes a power module 3a and a substrate unit 3b. The power module 3a is a module provided with a plurality of power devices D, which will be described later. The configuration of the power module 3a will be described later.

[0019] The board unit 3b is stacked on the power module 3a. This board unit 3b includes, for example, a gate driver board and an ECU (Electronic Control Unit) board. The gate driver board is a board provided with a gate driver that generates a drive signal for the inverter formed by the power module. The ECU board is a board provided with an ECU that controls the gate driver board.

[0020] 2 is a circuit diagram showing a schematic electrical configuration of the power conversion device 1 of this embodiment. The power conversion device 1 of this embodiment includes an inverter circuit E. The power conversion device 1 of this embodiment also includes a bus bar BU that connects the inverter circuit E to a battery B and to a motor M. The power conversion device 1 also includes a smoothing capacitor C that is connected in parallel with the inverter circuit E to the bus bar BU. The inverter circuit E is formed by a power module 3a. The smoothing capacitor C is formed by a capacitor module 4.

[0021] The power conversion device 1 of this embodiment converts the power supplied from the battery B into three-phase AC power and supplies it to the motor M. The power conversion device 1 also supplies regenerated power from the motor M to the battery B.

[0022] As shown in Fig. 2, the inverter circuit E has three legs R corresponding to the respective phases of the motor M. Each leg R has an upper arm HA and a lower arm LA. The upper arm HA is connected to the positive electrode side of a battery B via a bus bar BU. The lower arm LA is connected to the negative electrode side of the battery B via a bus bar BU. The upper arm HA and the lower arm LA are connected in series. An output terminal that connects the leg R and the motor M is connected between the upper arm HA and the lower arm LA.

[0023] 2, the power conversion device 1 of this embodiment includes power devices D (semiconductor substrates) corresponding to each leg R. That is, in this embodiment, the power conversion device 1 includes three power devices D (semiconductor substrates). Each power device D has a power transistor corresponding to the upper arm HA and a power transistor corresponding to the lower arm. Each of these power transistors is formed using a plurality of semiconductor elements.

[0024] 3 is a schematic exploded perspective view of a power module 3a included in the intelligent power module 3. As shown in this figure, the power module 3a includes a module case 3a1, the above-mentioned power devices D, and a heat sink 3a2. The module case 3a1 is a resin case that houses the power devices D and the like. The module case 3a1 includes an opening for each power device D to house the power device D. The module case 3a1 is fixed onto the heat sink 3a2, for example, via an adhesive.

[0025] Each power device D is placed on a heat sink 3a2 and accommodated in an opening of the module case 3a1. The heat sink 3a2 supports the module case 3a1 and the power devices D. The heat sink 3a2 also absorbs heat from the power devices D to cool them. The heat sink 3a2 is fixed to the central case 2a so that the bottom surface thereof is exposed to the flow path of the central case 2a. The heat sink 3a2 may have a plurality of fins formed on the bottom surface.

[0026] Fig. 4 is a schematic plan view of the power module 3a. As shown in Fig. 4, the power module 3a includes a positive bus bar 3a3, a negative bus bar 3a4, an output bus bar 3a5, a lead frame 3a6, a control terminal 3a7, and a control terminal wire 3a8.

[0027] The positive bus bar 3a3 is a bus bar connected to the positive electrode of battery B. The positive bus bar 3a3 is connected to the positive electrode of battery B and is also connected to one end of the capacitor module 4. The negative bus bar 3a4 is a bus bar connected to the negative electrode of battery B. The negative bus bar 3a4 is connected to the negative electrode of battery B and is also connected to the other end of the capacitor module 4.

[0028] An output bus bar 3a5 is provided for each power device D. That is, in this embodiment, the same number (three) of output bus bars 3a5 as the number of power devices D are provided. Each output bus bar 3a5 is connected to the motor M and guides current between the power device D and the motor M.

[0029] The positive bus bar 3a3, the negative bus bar 3a4, and the output bus bar 3a5 are held in the module case 3a1. The lead frame 3a6 connects the power device D to the bus bar (the positive bus bar 3a3, the negative bus bar 3a4, or the output bus bar 3a5) via a brazing material such as solder.

[0030] The control terminal 3a7 is a terminal for connecting the power module 3a and the board unit 3b. A plurality of control terminals 3a7 are provided. One end of each control terminal 3a7 protrudes toward the board unit 3b, and the other end is connected to the power device D via a control terminal wire 3a8. In other words, by connecting the control terminal 3a7 to the board unit 3b, each power device D is electrically connected to the board unit 3b. The control terminal wire 3a8 is a wire-like wiring that connects the control terminal 3a7 and the power device D, and a plurality of control terminal wires 3a8 are connected to one power device D.

[0031] 5 is a schematic enlarged view of a power module 3a including one power device D. As shown in FIG. 5, the power module 3a includes a plurality of lead frames 3a6 connected to one power device D.

[0032] In this embodiment, the power module 3a includes four lead frames 3a6 connected to one power device D. These four lead frames 3a6 include two positive electrode side lead frames 10 (positive electrode terminals), one negative electrode side lead frame 11 (negative electrode terminal), and one output side lead frame 12.

[0033] The positive electrode side lead frame 10 is a positive electrode terminal that connects the power device D and the positive electrode side bus bar 3a3. The power device D is connected to the positive electrode of the battery B via the positive electrode side lead frame 10. The two positive electrode side lead frames 10 may be integrated on the outside of the power device D. The negative electrode side lead frame 11 is a negative electrode terminal that connects the power device D and the negative electrode side bus bar 3a4. The power device D is connected to the negative electrode of the battery B via the negative electrode side lead frame 11.

[0034] 5 , the power module 3a includes a plurality of control terminal wires 3a8 connected to one power device D. The plurality of control terminal wires 3a8 connected to one power device D include a first conductor layer connecting wire 20, a second conductor layer connecting wire 21, a third conductor layer connecting wire 22, a first gate wiring connecting conductor layer wire 23, and a second gate wiring connecting conductor layer wire 24.

[0035] The first conductor layer connecting wire 20 is a control terminal wire 3a8 connected to a first conductor layer 40 (described later) of the power device D. In this embodiment, two first conductor layer connecting wires 20 are connected to one power device D. The second conductor layer connecting wire 21 is a control terminal wire 3a8 connected to a second conductor layer 50 (described later) of the power device D. The third conductor layer connecting wire 22 is a control terminal wire 3a8 connected to a third conductor layer 60 (described later) of the power device D.

[0036] The first gate wiring connecting conductor layer wire 23 is a control terminal wire 3a8 connected to a first gate wiring connecting conductor layer 70 (described later) of the power device D. The second gate wiring connecting conductor layer wire 24 is a control terminal wire 3a8 connected to a second gate wiring connecting conductor layer 80 (described later) of the power device D. In addition, when the power device D is equipped with a sensor such as a temperature sensor, the power module 3a may be equipped with a control terminal wire 3a8 that connects the sensor and the control terminal 3a7.

[0037] Next, the power device D will be described. Fig. 6 is a plan view showing a schematic configuration of the power device D. Note that a reference axis L shown in Fig. 6 will be used to explain the shape of the power device D. The reference axis L is a straight imaginary line. A direction parallel to the reference axis L will be referred to as the reference axis direction. A direction perpendicular to the reference axis L will be referred to as the orthogonal direction.

[0038] As shown in Fig. 6 , each power device D is formed in a substantially rectangular shape. Each power device D is formed in a rectangular shape with the orthogonal direction as the width direction and a reference axis L located at the center of the width direction. That is, in this embodiment, the reference axis L is formed in the shape of a rectangular plate located at the center of the width direction of the power device D. As shown in Fig. 6 , each power device D includes an insulating substrate 30, a conductor layer 31, a first switch section 32, a second switch section 33, a first gate wiring 34, and a second gate wiring 35.

[0039] The insulating substrate 30 is a substrate formed using an insulating material (e.g., silicon nitride), and supports the conductor layer 31, the first switch section 32, and the second switch section 33. The conductor layer 31 is formed on one surface of the insulating substrate 30.

[0040] The conductor layer 31 is made of, for example, copper. The conductor layer 31 is a wiring layer through which current flows between the battery B and the motor M and signals are transmitted and received between the power module 3a and the substrate unit 3b. A conductor layer may also be provided on the other surface of the insulating substrate 30. In this embodiment, a plurality of conductor layers 31 are provided at intervals so as to be spaced apart from each other.

[0041] The first switch section 32 and the second switch section 33 are provided to connect the conductor layers 31 that are disposed apart from each other. The first switch section 32 is a semiconductor switch that connects a first conductor layer 40 (described below), which is one of the conductor layers 31, to a third conductor layer 60 (described below), which is also one of the conductor layers 31, and a plurality of first switch sections 32 are provided. The second switch section 33 is a semiconductor switch that connects a second conductor layer 50 (described below), which is one of the conductor layers 31, to the third conductor layer 60, and a plurality of second switch sections 33 are provided.

[0042] Each first switch section 32 includes a first semiconductor element 32a (semiconductor element) and a first ribbon 32b (first connection wiring). The first semiconductor element 32a is, for example, a SiC-MOSFET type semiconductor chip made of SiC (silicon carbide). Note that the first semiconductor element 32a may also be a semiconductor chip made of other materials such as Si (silicon) or GaN (gallium nitride). A gate electrode 32c is provided on the top surface of the first semiconductor element 32a.

[0043] The first ribbon 32b connects the first semiconductor element 32a and the third conductor layer 60. In the present embodiment, the first ribbon 32b is connected to a pad formation portion 61 (described later) of the third conductor layer 60. As shown in FIG. 6 , the first ribbon 32b is formed so as to extend linearly in the orthogonal direction.

[0044] In this embodiment, as shown in FIG. 6 , the power device D includes four first switch sections 32. That is, four first semiconductor elements 32a are provided. Two of these four first semiconductor elements 32a are arranged closer to the output terminal pad 67 formed in the pad formation region 61 than the other two first semiconductor elements 32a. These two first semiconductor elements 32a arranged relatively closer to the output terminal pad 67 are arranged in orthogonal directions with the reference axis line L sandwiched between them, with the reference axis line L positioned at the center between them. Similarly, the two first semiconductor elements 32a arranged relatively farther from the output terminal pad 67 are also arranged in orthogonal directions with the reference axis line L sandwiched between them, with the reference axis line L positioned at the center between them.

[0045] The first ribbons 32b connected to the first semiconductor elements 32a relatively closer to the output terminal pad 67 are formed longer than the first ribbons 32b connected to the first semiconductor elements 32a relatively farther from the output terminal pad 67. As a result, the first ribbons 32b connected to the first semiconductor elements 32a relatively farther from the output terminal pad 67 have a larger inductance than the first ribbons 32b connected to the first semiconductor elements 32a relatively closer to the output terminal pad 67. When all the first switch units 32 have the same shape, the current may flow more unevenly through the first switch unit 32 that is relatively closer to the output terminal pad 67. As described above, by increasing the inductance of the first ribbons 32b connected to the first semiconductor elements 32a relatively farther from the output terminal pad 67, the current flowing through each first switch unit 32 can be made uniform.

[0046] However, the first ribbons 32b connected to the first semiconductor elements 32a that are relatively close to the output terminal pads 67 may be formed to have the same length as the first ribbons 32b connected to the first semiconductor elements 32a that are relatively far from the output terminal pads 67. When an abnormal current that is greater than the normal current flows, by making all of the first ribbons 32b the same length, it is possible to prevent the abnormal current from flowing unevenly through some of the first ribbons 32b.

[0047] Each second switch section 33 includes a second semiconductor element 33a (semiconductor element) and second ribbons 33b (second connection wiring). The second semiconductor element 33a is, for example, a SiC-MOSFET type semiconductor chip. Note that the second semiconductor element 33a may also be a semiconductor chip formed of other materials such as Si (silicon) or GaN (gallium nitride). A gate electrode 33c is provided on the upper surface of the second semiconductor element 33a.

[0048] The second ribbon 33b connects the second semiconductor element 33a and the second conductor layer 50. As shown in FIG. 6, the second ribbon 33b is formed so as to extend linearly in the orthogonal direction.

[0049] In this embodiment, the power device D includes four second switch units 33 as shown in FIG. 6 . That is, four second semiconductor elements 33 a are provided. Two of these four second semiconductor elements 33 a are arranged closer to the negative terminal pad 51 of the second conductor layer 50 than the other two second semiconductor elements 33 a. These two second semiconductor elements 33 a arranged relatively closer to the negative terminal pad 51 are arranged in an orthogonal direction with the reference axis L sandwiched between them, so that the reference axis L is located at the center between them. Furthermore, the two second semiconductor elements 33 a arranged relatively farther from the negative terminal pad 51 are also arranged in an orthogonal direction with the reference axis L sandwiched between them, so that the reference axis L is located at the center between them.

[0050] The second ribbons 33b connected to the second semiconductor elements 33a relatively closer to the negative terminal pad 51 are formed longer than the second ribbons 33b connected to the second semiconductor elements 33a relatively farther from the negative terminal pad 51. As a result, the second ribbons 33b connected to the second semiconductor elements 33a relatively farther from the negative terminal pad 51 have a larger inductance than the second ribbons 33b connected to the second semiconductor elements 33a relatively closer to the negative terminal pad 51. When all the second switch units 33 have the same shape, the current may flow more unevenly through the second switch unit 33 that is relatively closer to the negative terminal pad 51. As described above, by increasing the inductance of the second ribbons 33b connected to the second semiconductor elements 33a relatively farther from the negative terminal pad 51, the current flowing through each second switch unit 33 can be made uniform.

[0051] However, the second ribbons 33b connected to the second semiconductor elements 33a that are relatively closer to the negative terminal pad 51 may be formed to have the same length as the second ribbons 33b connected to the second semiconductor elements 33a that are relatively farther from the negative terminal pad 51. When an abnormal current that is greater than the normal current flows, by making all the second ribbons 33b the same length, it is possible to prevent the abnormal current from flowing unevenly through some of the second ribbons 33b.

[0052] 6, the first semiconductor element 32a and the second semiconductor element 33a located on one side (e.g., the right side) of the reference axis L in the orthogonal direction are arranged to overlap when viewed along the reference axis direction. The first semiconductor element 32a and the second semiconductor element 33a located on the other side (e.g., the left side) of the reference axis L in the orthogonal direction are arranged to overlap when viewed along the reference axis direction.

[0053] By arranging the first semiconductor element 32a and the second semiconductor element 33a in this manner, the semiconductor elements are linearly arranged in the reference axis direction on both sides of the reference axis L. Therefore, for example, compared to a case where the distances from the reference axis L of the first semiconductor element 32a and the second semiconductor element 33a are uneven, distortion caused by stress when the power device D expands and contracts due to heat can be suppressed.

[0054] The first gate wiring 34 is provided for each first semiconductor element 32a. That is, the first gate wiring 34 is provided corresponding to each first semiconductor element 32a. In this embodiment, four first gate wirings 34 are provided, the same number as the number of first semiconductor elements 32a. Each first gate wiring 34 is connected to the gate electrode 32c of the first semiconductor element 32a and a first gate wiring connection conductor layer 70 (described later) which is one of the conductor layers 31. That is, one end of each first gate wiring 34 is connected to the gate electrode 32c, and the other end is connected to the first gate wiring connection conductor layer 70.

[0055] The second gate wiring 35 is provided for each second semiconductor element 33a. That is, the second gate wiring 35 is provided corresponding to each second semiconductor element 33a. In this embodiment, four second gate wirings 35 are provided, the same number as the number of second semiconductor elements 33a. Each second gate wiring 35 is connected to the gate electrode 33c of the second semiconductor element 33a and to a second gate wiring connection conductor layer 80 (described later) which is one of the conductor layers 31. That is, one end of each second gate wiring 35 is connected to the gate electrode 33c, and the other end is connected to the second gate wiring connection conductor layer 80.

[0056] Fig. 7 is a schematic diagram showing the insulating substrate 30 and the conductor layers 31 in Fig. 6. As shown in Fig. 7, the power device D includes five conductor layers 31: a first conductor layer 40, a second conductor layer 50, a third conductor layer 60, a first gate wiring-connecting conductor layer 70, and a second gate wiring-connecting conductor layer 80.

[0057] The first conductor layer 40 is the conductor layer 31 to which the positive electrode lead frame 10 is connected. As shown in Fig. 7 , the first conductor layer 40 is divided into a first portion 41 and a second portion 42. The first portion 41 and the second portion 42 are formed to have line-symmetric shapes with respect to the reference axis L as the axis of symmetry.

[0058] In this embodiment, the first portion 41 and the second portion 42 are spaced apart from each other to provide a gap therebetween. In the orthogonal direction, the second conductor layer 50, the third conductor layer 60, the first gate wiring-connecting conductor layer 70, and the second gate wiring-connecting conductor layer 80 are located between the first portion 41 and the second portion 42.

[0059] For ease of explanation, in this embodiment, the first portion 41 is located on the left side of the reference axis L, and the second portion 42 is located on the right side of the reference axis L. Also, for ease of explanation, in the reference axis direction, the side to which the positive electrode side lead frame 10 is connected is referred to as the front side, and the side opposite to the front side is referred to as the back side.

[0060] As shown in FIG. 7 , the first portion 41 includes a positive terminal pad 43, a first switch unit connection portion 44, and a connection portion 45. The positive terminal pad 43 is connected to one of the positive lead frames 10 and is located at the frontmost side of the first conductor layer 40. The first switch unit connection portion 44 is connected to the first ribbon 32b of the first switch unit 32 and is located at the rearmost side of the first conductor layer 40. The connection portion 45 is formed to extend along the reference axis direction and connects the positive terminal pad 43 to the first switch unit connection portion 44. The first switch unit connection portion 44 is connected to the first semiconductor element 32a of the first switch unit 32. A first conductor layer connecting wire 20 (control terminal wire 3a8) is connected to the first switch unit connection portion 44. This allows, for example, an ECU of the board unit 3b to detect the voltage of the first portion 41.

[0061] The second portion 42 has a positive terminal pad 46, a first switch unit connection portion 47, and a connection portion 48. The positive terminal pad 46 is the portion to which the other positive electrode lead frame 10 is connected and is located at the frontmost side of the first conductor layer 40. The first switch unit connection portion 47 is the portion to which the first ribbon 32b of the first switch unit 32 is connected and is located at the rearmost side of the first conductor layer 40. The connection portion 48 is formed to extend along the reference axis direction and connects the positive terminal pad 46 and the first switch unit connection portion 47. The first switch unit connection portion 47 is the portion to which the first semiconductor element 32a of the first switch unit 32 is joined. A first conductor layer connecting wire 20 (control terminal wire 3a8) is connected to the first switch unit connection portion 47. This allows, for example, an ECU of the board unit 3b to detect the voltage of the second portion 42.

[0062] The first conductor layer 40 has a pair of first switch unit connection parts (first switch unit connection part 44 and first switch unit connection part 47) arranged in the orthogonal direction so as to sandwich the third conductor layer 60 therebetween. The third conductor layer 60 has a pad formation part 61, which will be described later. The pair of first switch unit connection parts (first switch unit connection part 44 and first switch unit connection part 47) are arranged so as to sandwich the pad formation part 61 of the third conductor layer 60 therebetween.

[0063] The second conductor layer 50 is the conductor layer 31 to which the negative lead frame 11 is connected. The second conductor layer 50 has a negative terminal pad 51 to which the negative lead frame 11 is connected. As shown in FIG. 7 , the negative terminal pad 51 is located at the frontmost side of the conductor layer 31, between the positive terminal pad 43 of the first section 41 and the positive terminal pad 46 of the second section 42. The second ribbon 33b of the second switch section 33 is connected to the second conductor layer 50. The second conductor layer connecting wire 21 (control terminal wire 3a8) is connected to the second conductor layer 50. This allows, for example, an ECU of the board unit 3b to detect the voltage of the second conductor layer 50.

[0064] The third conductor layer 60 is the conductor layer 31 to which the output-side lead frame 12 is connected. The third conductor layer 60 has a pad forming portion 61, two second switch section connection portions (second switch section connection portion 62 and second switch section connection portion 63), an intermediate connection portion 64, and two protruding portions (protruding portion 65 and protruding portion 66).

[0065] The pad forming portion 61 is a portion having an output terminal pad 67. The pad forming portion 61 is formed so that the output terminal pad 67 is located at the innermost side in the reference axis direction. As shown in Fig. 7 , the pad forming portion 61 is disposed between the first switch unit connection portion 44 and the first switch unit connection portion 47 in the orthogonal direction.

[0066] The second switch section connection portion 62 is located on the left side of the reference axis L, and is located between the connection portion 45 of the first conductor layer 40 and the second conductor layer 50. The second switch section connection portion 62 is the portion to which the second semiconductor element 33a of the second switch section 33 is joined.

[0067] The second switch section connection portion 63 is located to the right of the reference axis L, and is located between the connection portion 48 of the first conductor layer 40 and the second conductor layer 50. The second switch section connection portion 63 is the portion to which the second semiconductor element 33a of the second switch section 33 is joined.

[0068] The third conductor layer 60 includes a pair of second switch unit connection parts (second switch unit connection parts 62 and 63) arranged to sandwich the second conductor layer 50 therebetween in the orthogonal direction. The third conductor layer 60 also includes a pad formation part 61 sandwiched between a pair of first switch unit connection parts (first switch unit connection parts 44 and 47) in the orthogonal direction and provided with an output terminal pad 67.

[0069] The intermediate connection portion 64 connects the pad forming portion 61 to each of the second switch unit connection portions (the second switch unit connection portion 62 and the second switch unit connection portion 63). The intermediate connection portion 64 is formed so as to branch into two portions as it moves from the pad forming portion 61 toward the front, with one of the branched portions connected to the second switch unit connection portion 62 and the other of the branched portions connected to the second switch unit connection portion 63.

[0070] The protruding portion 65 protrudes toward the front from the second switch unit connection portion 62 along the reference axial direction. The protruding portion 66 protrudes toward the front from the second switch unit connection portion 63 along the reference axial direction. The third conductor layer connecting wire 22 (control terminal wire 3a8) is connected to one of the protruding portions 65 and 66. This enables, for example, an ECU of the board unit 3b to detect the voltage of the third conductor layer 60.

[0071] In such a conductor layer 31, as shown in Fig. 7, the output terminal pad 67 and the negative electrode terminal pad 51 are arranged on the reference axis L. Furthermore, as shown in Fig. 6, the plurality of (four) first switch sections 32 are arranged symmetrically with respect to the reference axis L on the output terminal pad 67 side (rear side) of the center position P between the output terminal pad 67 and the negative electrode terminal pad 51 in the reference axis direction.

[0072] Furthermore, each first switch section 32 connects its first switch section connection portion to the pad forming portion 61. The first switch section 32 located on the left side of the reference axis L connects its first switch section connection portion 44 located on the left side of the reference axis L to the pad forming portion 61. The first switch section 32 located on the right side of the reference axis L connects its first switch section connection portion 47 located on the right side of the reference axis L to the pad forming portion 61.

[0073] Furthermore, the multiple (four) second switch units 33 are arranged symmetrically with respect to the reference axis L on the negative terminal pad 51 side (near side) of the center position P. Each second switch unit 33 connects a second switch unit connection portion with the second conductor layer 50. The second switch unit 33 located on the left side of the reference axis L connects a second switch unit connection portion 62 located on the left side of the reference axis L with the second conductor layer 50. The second switch unit 33 located on the right side of the reference axis L connects a second switch unit connection portion 63 located on the right side of the reference axis L with the second conductor layer 50.

[0074] The first gate wiring connection conductor layer 70 is a conductor layer 31 to which a plurality of first gate wirings 34 are connected. In addition, first gate wiring connection conductor layer wires 23 (control terminal wires 3a8) are connected to the first gate wiring connection conductor layer 70. This allows a drive voltage to be applied to all of the first gate wirings 34 (i.e., the first semiconductor elements 32a) from the substrate unit 3b via the first gate wiring connection conductor layer 70.

[0075] 7 , the first gate wiring-connecting conductor layer 70 is formed in a shape that extends linearly along the reference axis direction and is disposed so as to overlap the reference axis L. Furthermore, the pad-forming portion 61 of the third conductor layer 60 is formed so as to surround the entire first gate wiring-connecting conductor layer 70 via a gap S1. That is, in this embodiment, the portion of the pad-forming portion 61 on the right side of the reference axis L and the portion on the left side of the reference axis L are connected to each other on both the front and rear sides of the first gate wiring-connecting conductor layer 70. Therefore, the current flowing in the pad-forming portion 61 is prevented from flowing unevenly.

[0076] The second gate wiring connection conductor layer 80 is a conductor layer 31 to which a plurality of second gate wirings 35 are connected. In addition, second gate wiring connection conductor layer wires 24 (control terminal wires 3a8) are connected to the second gate wiring connection conductor layer 80. This allows a drive voltage to be applied to all of the second gate wirings 35 (i.e., second semiconductor elements 33a) from the substrate unit 3b via the second gate wiring connection conductor layer 80.

[0077] 7 , the second gate wiring-connecting conductor layer 80 is formed in a shape that extends linearly along the reference axis direction and is disposed so as to overlap the reference axis L. The second conductor layer 50 is also formed so as to surround the entire second gate wiring-connecting conductor layer 80 via a gap S2. That is, in this embodiment, the portion of the second conductor layer 50 on the right side of the reference axis L and the portion on the left side of the reference axis L are connected to each other on both the front and rear sides of the second gate wiring-connecting conductor layer 80. This prevents the current flowing in the second conductor layer 50 from being biased.

[0078] The power device D of this embodiment forms the above-mentioned leg R. The first conductor layer 40, the third conductor layer 60, the first switch section 32, etc. of the power device D form an upper arm HA. The second conductor layer 50, the third conductor layer 60, the second switch section 33, etc. of the power device D form a lower arm LA.

[0079] In the power conversion device 1 of this embodiment equipped with such a power device D, when power is supplied from the battery B to the motor M, the DC power output from the battery B is converted into AC power by the inverter circuit E (power conversion circuit) of the power conversion device 1. Then, the AC power generated by the inverter circuit E is supplied to the motor M.

[0080] 8 is a schematic diagram showing the flow of current in the power device D when a drive current is supplied from the battery B to the motor M. When a drive voltage is applied to the first semiconductor element 32a of the first switch section 32, a current flows from the first conductor layer 40 to the third conductor layer 60. In other words, when a drive voltage is applied to the first semiconductor element 32a of the first switch section 32, a current flows in the first switch section 32 toward the reference axis L.

[0081] Furthermore, when a drive voltage is applied to the second semiconductor element 33 a of the second switch portion 33, a current flows from the third conductor layer 60 to the second conductor layer 50. In other words, when a drive voltage is applied to the second semiconductor element 33 a of the second switch portion 33, a current flows in the second switch portion 33 toward the reference axis L.

[0082] At this time, the distance from the output terminal (source) of the second switch section 33 to the negative side lead frame 11 is as short as the distance from the output terminal (source) of the first switch section 32 to the output side lead frame 12.

[0083] The power device D of this embodiment as described above is a semiconductor substrate provided with an upper arm HA and a lower arm LA that form a leg R. The power device D of this embodiment also includes an insulating substrate 30, a conductor layer 31 formed on one surface of the insulating substrate 30, and semiconductor elements (a first semiconductor element 32 a and a second semiconductor element 33 a) mounted on the conductor layer 31.

[0084] The power device D of this embodiment also includes a first conductor layer 40, a second conductor layer 50, a third conductor layer 60, a plurality of first switch sections 32, and a plurality of second switch sections 33. The first conductor layer 40 is a conductor layer 31 having a positive terminal pad 43 to which the positive lead frame 10 is connected. The second conductor layer 50 is a conductor layer 31 having a negative terminal pad 51 to which the negative lead frame 11 is connected. The third conductor layer 60 is a conductor layer 31 having an output terminal pad 67 to which the output lead frame 12 is connected. The first switch section 32 connects the first conductor layer 40 and the third conductor layer 60 and includes a first semiconductor element 32a. The second switch section 33 connects the second conductor layer 50 and the third conductor layer 60 and includes a second semiconductor element 33a.

[0085] The output terminal pad 67 and the negative electrode terminal pad 51 are arranged on the reference axis L. The first conductor layer 40 has a pair of first switch unit connection portions (the first switch unit connection portion 44 and the first switch unit connection portion 47) arranged to sandwich the third conductor layer 60 therebetween in the orthogonal direction, which is a direction perpendicular to the reference axis L along one surface of the insulating substrate 30. The third conductor layer 60 has a pair of second switch unit connection portions 63 arranged to sandwich the second conductor layer 50 therebetween in the orthogonal direction, and a pad formation portion 61 sandwiched between the pair of first switch unit connection portions (the first switch unit connection portion 44 and the first switch unit connection portion 47) in the orthogonal direction and on which the output terminal pad 67 is provided.

[0086] The plurality of first switch units 32 are arranged symmetrically with respect to the reference axis L on the output terminal pad 67 side of a center position P between the output terminal pad 67 and the negative terminal pad 51 in the reference axial direction, which is the direction along the reference axis L, and connect the first switch unit connection parts (the first switch unit connection parts 44 and the first switch unit connection parts 47) to the pad forming part 61. The plurality of second switch units 33 are arranged symmetrically with respect to the reference axis L on the negative terminal pad 51 side of the center position P in the reference axial direction, and connect the second switch unit connection parts 63 to the second conductor layer 50.

[0087] According to the power device D of this embodiment, the plurality of first switch sections 32 connect the first conductor layer 40 having the positive terminal pad 43 to the third conductor layer 60 having the output terminal pad 67, and function as part of the upper arm HA. The plurality of second switch sections 33 connect the second conductor layer 50 having the negative terminal pad 51 to the third conductor layer 60, and function as part of the lower arm LA.

[0088] Furthermore, according to the power device D of this embodiment, the output terminal pad 67 and the negative terminal pad 51 are disposed on the reference axis L, and the first switch unit connection parts (the first switch unit connection parts 44 and 47) of the first conductor layer 40 are arranged to sandwich the pad formation part 61 of the third conductor layer 60. Therefore, in the first switch unit 32, the current flows from the side farther from the reference axis L toward the reference axis L.

[0089] Furthermore, according to the power device D of this embodiment, the second switch unit connection site 63 of the third conductor layer 60 is provided so as to sandwich the second conductor layer 50 having the negative terminal pad 51. Therefore, in the second switch unit 33 as well, the current flows from the side farther from the reference axis L toward the reference axis L.

[0090] This shortens both the paths of currents that pass through the plurality of first switch units 32 arranged on either side of the reference axis L until they join together, and the paths of currents that pass through the plurality of second switch units 33 arranged on either side of the reference axis L until they join together. Therefore, the power device D of this embodiment has a structure that can prevent either the parasitic inductance of the upper arm HA or the parasitic inductance of the lower arm LA from increasing, making oscillation less likely to occur. Therefore, the power device D of this embodiment can prevent oscillation from occurring.

[0091] Furthermore, in the power device D of this embodiment, each first switch section 32 includes a first semiconductor element 32a and a first ribbon 32b. The first semiconductor element 32a is a semiconductor element mounted on the first switch section connection portion (first switch section connection portion 44 and first switch section connection portion 47). The first ribbon 32b connects the first semiconductor element 32a to the pad formation portion 61. Each second switch section 33 includes a second semiconductor element 33a and a second ribbon 33b. The second semiconductor element 33a is a semiconductor element mounted on the second switch section connection portion 63. The second ribbon 33b connects the second semiconductor element 33a to the second conductor layer 50.

[0092] In the power device D of this embodiment, the inductance of the first switch section 32 and the second switch section 33 can be adjusted by adjusting the lengths of the first ribbon 32b and the second ribbon 33b.

[0093] The power device D of this embodiment also includes a plurality of first gate wirings 34, a first gate wiring connection conductor layer 70, a plurality of second gate wirings 35, and a second gate wiring connection conductor layer 80. The first gate wirings 34 are provided corresponding to each first semiconductor element 32a and are connected to the gate electrodes 32c of the first semiconductor elements 32a. The first gate wiring connection conductor layer 70 is a conductor layer 31 to which the plurality of first gate wirings 34 are connected. The second gate wirings 35 are provided corresponding to each second semiconductor element 33a and are connected to the gate electrodes 33c of the second semiconductor elements 33a. The second gate wiring connection conductor layer 80 is a conductor layer 31 to which the plurality of second gate wirings 35 are connected.

[0094] According to the power device D of this embodiment, the plurality of first gate wirings 34 are connected to a single first gate wiring-connecting conductor layer 70. Therefore, by applying a drive voltage to the first gate wiring-connecting conductor layer 70, it becomes possible to drive the plurality of first switch sections 32 at once.

[0095] Furthermore, according to the power device D of this embodiment, the plurality of second gate wirings 35 are connected to a single second gate wiring-connecting conductor layer 80. Therefore, by applying a drive voltage to the second gate wiring-connecting conductor layer 80, it becomes possible to drive the plurality of second switch sections 33 at once.

[0096] In the power device D of this embodiment, the first gate wiring-connecting conductor layer 70 is disposed so as to overlap the reference axis L. The pad forming portion 61 of the third conductor layer 60 is formed so as to surround the entire first gate wiring-connecting conductor layer 70 with a gap therebetween.

[0097] In the power device D of this embodiment, the pad forming portion 61 has a portion on the right side of the reference axis L and a portion on the left side of the reference axis L connected to each other on both the front and rear sides of the first gate wiring-connecting conductor layer 70. This prevents the current flowing in the pad forming portion 61 from being biased.

[0098] In the power device D of this embodiment, the second gate wiring-connecting conductor layer 80 is disposed so as to overlap the reference axis line L. The second conductor layer 50 is formed so as to surround the entire second gate wiring-connecting conductor layer 80 with a gap therebetween.

[0099] In the power device D of this embodiment, the second conductor layer 50 has a portion on the right side of the reference axis L and a portion on the left side of the reference axis L connected to each other on both the front and rear sides of the second gate wiring-connecting conductor layer 80. This prevents the current flowing in the second conductor layer 50 from being biased.

[0100] Furthermore, in the power device D of this embodiment, among the multiple first semiconductor elements 32a, the first ribbons 32b connected to the first semiconductor elements 32a that are relatively closer to the output terminal pad 67 have a larger inductance than the first ribbons 32b connected to the first semiconductor elements 32a that are relatively farther from the output terminal pad 67.

[0101] According to the power device D of this embodiment, the inductance of the first ribbon 32b connected to the first semiconductor element 32a, which is relatively far from the output terminal pad 67, is large, so that the current flowing through each first switch section 32 can be made uniform.

[0102] Furthermore, in the power device D of this embodiment, the second ribbons 33b connected to the second semiconductor elements 33a that are relatively closer to the negative terminal pad 51 among the multiple second semiconductor elements 33a have a larger inductance than the second ribbons 33b connected to the second semiconductor elements 33a that are relatively farther from the negative terminal pad 51.

[0103] According to the power device D of this embodiment, the inductance of the second ribbon 33b connected to the second semiconductor element 33a, which is relatively far from the output terminal pad 67, is large, so that the current flowing through each second switch section 33 can be made uniform.

[0104] In the power device D of this embodiment, the first semiconductor element 32a and the second semiconductor element 33a located on one side of the reference axis L in the orthogonal direction are arranged so as to overlap when viewed from the direction along the reference axis. In addition, the first semiconductor element 32a and the second semiconductor element 33a located on the other side of the reference axis L in the orthogonal direction are arranged so as to overlap when viewed from the direction along the reference axis.

[0105] According to the power device D of this embodiment, distortion caused by stress when the power device D expands and contracts thermally can be suppressed compared to when the distances from the reference axis L of the first semiconductor element 32a and the second semiconductor element 33a are uneven.

[0106] In the power device D of this embodiment, the first conductor layer 40 has a first portion 41 and a second portion 42. The first portion 41 has one of a pair of first switch connection portions (first switch connection portion 44 and first switch connection portion 47). The second portion 42 has the other of the pair of first switch connection portions (first switch connection portion 44 and first switch connection portion 47) and is formed spaced apart from the first portion 41.

[0107] According to the power device D of this embodiment, the first portion 41 and the second portion 42 are spaced apart, and the first conductor layer 40 does not need to have a portion that connects the first portion 41 and the second portion 42. This allows the first conductor layer 40 to be miniaturized, and further allows the power device D to be miniaturized.

[0108] In addition, in the power device D of this embodiment, the third conductor layer 60 has protruding portions (protruding portions 65 and protruding portions 66) that protrude from each second switch section connection portion 63 along the reference axis direction toward the opposite side of the second switch section 33.

[0109] According to the power device D of this embodiment, it is possible to shorten the third conductor layer connecting wire 22. Furthermore, by forming a protruding portion at each of the second switch section connecting portion 62 and the second switch section connecting portion 63, it is possible to form the third conductor layer 60 in a symmetrical shape. This makes it possible to suppress distortion caused by stress when the power device D thermally expands and contracts.

[0110] Furthermore, the power conversion device 1 of this embodiment includes a power device D. Therefore, the power conversion device 1 of this embodiment can suppress the occurrence of oscillation in the power device D.

[0111] While the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to the above-described embodiments. The shapes and combinations of the components shown in the above-described embodiments are merely examples, and various modifications can be made based on design requirements, etc., without departing from the spirit of the present invention.

[0112] For example, in the above embodiment, an example has been described in which the semiconductor substrate of the present invention is applied to the power device D. However, the present invention is not limited to this. For example, the semiconductor substrate can also be applied to semiconductor substrates other than power devices.

[0113] In the above embodiment, the power device D is provided in the power conversion device 1 including the inverter circuit E. However, the present invention is not limited to this. For example, the power device D can be applied to a power conversion device such as a DC / DC converter.

[0114] In the above embodiment, the power module 3 a is configured to include three power devices D. However, the present invention is not limited to this. For example, the power module 3 a may be configured to include even more power devices D.

[0115] In the above embodiment, a configuration in which at least one motor is connected to the power conversion device 1 of this embodiment has been described. However, the present invention is not limited to this. For example, a configuration in which two motors are connected to the power conversion device 1 can be adopted. In such a case, the power conversion device includes two inverter circuits. Therefore, for example, the power module 3a can include a total of six power devices D, equivalent to the two inverter circuits.

[0116] In the above embodiment, the power module 3 a does not include a step-up / step-down circuit. However, the present invention is not limited to this. For example, the power module 3 a may include a step-up / step-down circuit between the battery B and the inverter circuit E.

[0117] For example, in the above embodiment, a configuration has been described in which the first semiconductor element 32a and the second semiconductor element 33a located on one side of the reference axis L in the orthogonal direction are arranged to overlap when viewed from the direction along the reference axis. Also, in the above embodiment, a configuration has been described in which the first semiconductor element 32a and the second semiconductor element 33a located on the other side of the reference axis L in the orthogonal direction are arranged to overlap when viewed from the direction along the reference axis. However, the present invention is not limited to this. It is also possible to employ a configuration in which the first semiconductor element 32a and the second semiconductor element 33a are arranged without overlapping when viewed from the direction along the reference axis.

[0118] The above embodiment can also be described as follows, for example:

[0119] (Supplementary Note 1) A semiconductor substrate provided with upper and lower arms that form legs, comprising: an insulating substrate; a conductor layer formed on one surface of the insulating substrate; and a semiconductor element mounted on the conductor layer; a first conductor layer being the conductor layer having a positive terminal pad to which a positive terminal is connected; a second conductor layer being the conductor layer having a negative terminal pad to which a negative terminal is connected; a third conductor layer being the conductor layer having an output terminal pad to which an output terminal is connected; a plurality of first switch units connecting the first conductor layer and the third conductor layer and having the semiconductor elements; and a plurality of second switch units connecting the second conductor layer and the third conductor layer and having the semiconductor elements, wherein the output terminal pad and the negative terminal pad are arranged on a reference axis, and the first conductor layer has a pair of first switch unit connection sites arranged to sandwich the third conductor layer between them in an orthogonal direction that is orthogonal to the reference axis along the one surface of the insulating substrate, the third conductor layer has a pair of second switch unit connection sites arranged to sandwich the second conductor layer therebetween in the orthogonal direction, and a pad formation site sandwiched between the pair of first switch unit connection sites in the orthogonal direction and on which the output terminal pad is provided; the multiple first switch units are arranged symmetrically with respect to the reference axis on the output terminal pad side of a center position between the output terminal pad and the negative terminal pad in a reference axial direction that is a direction along the reference axis, and connect the first switch unit connection sites and the pad formation site; and the multiple second switch units are arranged symmetrically with respect to the reference axis on the negative terminal pad side of the center position in the reference axial direction, and connect the second switch unit connection sites and the second conductor layer.

[0120] (Supplementary Note 2) The semiconductor substrate according to Supplementary Note 1, characterized in that each of the first switch sections comprises: a first semiconductor element which is the semiconductor element mounted on the first switch section connection portion; and a first connection wiring which connects the first semiconductor element and the pad formation portion; and each of the second switch sections comprises: a second semiconductor element which is the semiconductor element mounted on the second switch section connection portion; and a second connection wiring which connects the second semiconductor element and the second conductor layer.

[0121] (Supplementary Note 3) A semiconductor substrate according to Supplementary Note 2, comprising: a plurality of first gate wirings provided corresponding to each of the first semiconductor elements and each connected to a gate electrode of the first semiconductor element; a first gate wiring connection conductor layer which is the conductor layer to which the plurality of first gate wirings are connected; a plurality of second gate wirings provided corresponding to each of the second semiconductor elements and each connected to a gate electrode of the second semiconductor element; and a second gate wiring connection conductor layer which is the conductor layer to which the plurality of second gate wirings are connected.

[0122] (Appendix 4) The semiconductor substrate according to appendix 3, characterized in that the first gate wiring connection conductor layer is arranged so as to overlap the reference axis line, and the pad formation portion of the third conductor layer is formed so as to surround the entire first gate wiring connection conductor layer via a gap.

[0123] (Appendix 5) The semiconductor substrate according to appendix 3 or 4, characterized in that the second gate wiring connection conductor layer is arranged so as to overlap the reference axis line, and the second conductor layer is formed so as to surround the entire second gate wiring connection conductor layer via a gap.

[0124] (Appendix 6) A semiconductor substrate according to any one of Appendices 2 to 5, characterized in that the first connection wiring connected to a first semiconductor element, among the plurality of first semiconductor elements, that is relatively close to the output terminal pad has a larger inductance than the first connection wiring connected to a first semiconductor element that is relatively far from the output terminal pad.

[0125] (Appendix 7) The semiconductor substrate according to any one of Appendices 2 to 6, wherein the second connection wiring connected to the second semiconductor element relatively closer to the negative terminal pad among the plurality of second semiconductor elements has a larger inductance than the second connection wiring connected to the second semiconductor element relatively farther from the negative terminal pad.

[0126] (Appendix 8) A semiconductor substrate according to any one of Appendices 2 to 7, characterized in that the first semiconductor element and the second semiconductor element located on one side of the reference axis in the orthogonal direction are arranged so as to overlap when viewed from a direction along the reference axis, and the first semiconductor element and the second semiconductor element located on the other side of the reference axis in the orthogonal direction are arranged so as to overlap when viewed from a direction along the reference axis.

[0127] (Appendix 9) The semiconductor substrate according to any one of Appendices 1 to 8, wherein the first conductor layer has: a first portion having one of the pair of first switch section connection portions; and a second portion having the other of the pair of first switch section connection portions and formed spaced apart from the first portion.

[0128] (Appendix 10) A semiconductor substrate according to any one of Appendices 1 to 9, characterized in that the third conductor layer has a protruding portion that protrudes from each of the second switch section connection portions toward the opposite side of the second switch section along the reference axis direction.

[0129] (Supplementary Note 11) A power conversion device having a power conversion circuit formed by a semiconductor element, characterized in that the power conversion device comprises the semiconductor substrate according to any one of Supplementary Notes 1 to 10, which has the semiconductor element.

[0130] REFERENCE SIGNS LIST 1 Power conversion device 2 Inverter case 3 Intelligent power module 3a Power module 3a1 Module case 3a2 Heat sink 3a3 Positive bus bar 3a4 Negative bus bar 3a5 Output bus bar 3a6 Lead frame 3a7 Control terminal 3a8 Control terminal wire 3b Substrate unit 4 Capacitor module 10 Positive lead frame (positive terminal) 11 Negative lead frame (negative terminal) 12 Output lead frame (output terminal) 20 First conductor layer connecting wire 21 Second conductor layer connecting wire 22 Third conductor layer connecting wire 23 First gate wiring connecting conductor layer wire 24 Second gate wiring connecting conductor layer wire 30 Insulating substrate 31 Conductive layer 32 First switch section 32a First semiconductor element (semiconductor element) 32b First ribbon (first connecting wiring) 32c Gate electrode 33 Second switch section 33a Second semiconductor element (semiconductor element) 33b Second ribbon (first connection wiring) 33c Gate electrode 34 First gate wiring 35 Second gate wiring 40 First conductor layer 41 First portion 42 Second portion 43 Positive electrode terminal pad 44 First switch unit connection portion 45 Connection portion 46 Positive electrode terminal pad 47 First switch unit connection portion 48 Connection portion 50 Second conductor layer 51 Negative electrode terminal pad 60 Third conductor layer 61 Pad formation portion 62 Second switch unit connection portion 63 Second switch unit connection portion 64 Intermediate connection portion 65 Protruding portion 66 Protruding portion 67 Output terminal pad 70 First gate wiring connection conductor layer 80 Second gate wiring connection conductor layer B Battery BU Bus bar D Power device (semiconductor substrate) E Inverter circuit HA Upper arm L Reference axis LA Lower arm M Motor P Center position R Leg S1 Gap S2 Gap

Claims

1. A semiconductor substrate provided with upper and lower arms forming legs, comprising: an insulating substrate; a conductor layer formed on one surface of the insulating substrate; and a semiconductor element mounted on the conductor layer; a first conductor layer being the conductor layer having a positive terminal pad to which a positive terminal is connected; a second conductor layer being the conductor layer having a negative terminal pad to which a negative terminal is connected; a third conductor layer being the conductor layer having an output terminal pad to which an output terminal is connected; a plurality of first switch units connecting the first conductor layer and the third conductor layer and having the semiconductor elements; and a plurality of second switch units connecting the second conductor layer and the third conductor layer and having the semiconductor elements; the output terminal pad and the negative terminal pad are arranged on a reference axis; and the first conductor layer has a pair of first switch unit connection sites arranged to sandwich the third conductor layer between them in an orthogonal direction that is orthogonal to the reference axis along the one surface of the insulating substrate; the third conductor layer has a pair of second switch unit connection sites arranged to sandwich the second conductor layer between them in the orthogonal direction, and a pad forming site sandwiched between the pair of first switch unit connection sites in the orthogonal direction and on which the output terminal pad is provided, the multiple first switch units are arranged symmetrically with respect to the reference axis on the output terminal pad side of a central position between the output terminal pad and the negative terminal pad in a reference axial direction that is a direction along the reference axis, and connect the first switch unit connection sites and the pad forming site, and the multiple second switch units are arranged symmetrically with respect to the reference axis on the negative terminal pad side of the central position in the reference axial direction, and connect the second switch unit connection sites and the second conductor layer.

2. The semiconductor substrate according to claim 1, characterized in that each of the first switch sections comprises: a first semiconductor element which is the semiconductor element mounted on the first switch section connection portion; and a first connection wiring which connects the first semiconductor element and the pad formation portion; and each of the second switch sections comprises: a second semiconductor element which is the semiconductor element mounted on the second switch section connection portion; and a second connection wiring which connects the second semiconductor element and the second conductor layer.

3. A semiconductor substrate as claimed in claim 2, comprising: a plurality of first gate wirings provided corresponding to each of the first semiconductor elements and each connected to a gate electrode of the first semiconductor element; a first gate wiring connection conductor layer which is the conductor layer to which the plurality of first gate wirings are connected; a plurality of second gate wirings provided corresponding to each of the second semiconductor elements and each connected to a gate electrode of the second semiconductor element; and a second gate wiring connection conductor layer which is the conductor layer to which the plurality of second gate wirings are connected.

4. The semiconductor substrate according to claim 3, characterized in that the first gate wiring connection conductor layer is arranged so as to overlap the reference axis line, and the pad forming portion of the third conductor layer is formed so as to surround the entire first gate wiring connection conductor layer via a gap.

5. A semiconductor substrate according to claim 3 or 4, characterized in that the second gate wiring connection conductor layer is arranged so as to overlap the reference axis line, and the second conductor layer is formed so as to surround the entire second gate wiring connection conductor layer with a gap therebetween.

6. A semiconductor substrate as described in any one of claims 2 to 4, characterized in that the first connection wiring connected to a first semiconductor element among the multiple first semiconductor elements that is relatively closer to the output terminal pad has a larger inductance than the first connection wiring connected to a first semiconductor element that is relatively farther from the output terminal pad.

7. A semiconductor substrate as described in any one of claims 2 to 4, characterized in that the second connection wiring connected to one of the second semiconductor elements that is relatively closer to the negative terminal pad among the multiple second semiconductor elements has a larger inductance than the second connection wiring connected to the second semiconductor element that is relatively farther from the negative terminal pad.

8. A semiconductor substrate as described in any one of claims 2 to 4, characterized in that the first semiconductor element and the second semiconductor element located on one side of the reference axis in the orthogonal direction are arranged so as to overlap when viewed from a direction along the reference axis, and the first semiconductor element and the second semiconductor element located on the other side of the reference axis in the orthogonal direction are arranged so as to overlap when viewed from a direction along the reference axis.

9. A semiconductor substrate as claimed in any one of claims 1 to 4, characterized in that the first conductor layer has a first portion having one of a pair of the first switch section connection portions, and a second portion having the other of the pair of the first switch section connection portions and formed spaced apart from the first portion.

10. A semiconductor substrate as described in any one of claims 1 to 4, characterized in that the third conductor layer has a protruding portion protruding from each of the second switch section connection portions along the reference axis direction toward the opposite side to the second switch section.

11. A power conversion device having a power conversion circuit formed by a semiconductor element, the power conversion device comprising the semiconductor substrate according to any one of claims 1 to 4 having the semiconductor element.

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