Solar cell and manufacturing method therefor

Abstract

A solar cell and a preparation method therefor. The preparation method for a solar cell comprises: forming an amorphous silicon layer on a tunneling oxide layer (120) at a first side; by means of a diffusion doping treatment, forming a doped polycrystalline silicon layer (130) in a first procedure, and forming a doped oxide layer (131) on the doped polycrystalline silicon layer in a second procedure; and after forming the doped oxide layer (131), using a laser doping process to perform selective heavy doping on the first side, and forming a selective emitter in a heavily doped region.

Description

Solar cell and preparation method thereof

[0001] Related applications

[0002] [Corrected 10.11.2023 according to Rule 91] This application claims priority to Chinese patent application No. 202311007485.2 filed on August 10, 2023, entitled “Solar Cell and Method for Making Same”, the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a method for preparing the same. Background Art

[0004] In the photovoltaic field, the front surface of the TOPCon cell (Tunnel Oxide Passivated Contact cell) is similar to that of the conventional PERC cell (Passivated Emitter and Rear Cell). The characteristic of the TOPCon cell is that a tunnel oxide layer is provided on the back, and a doped polysilicon layer is provided on the tunnel oxide layer. The two together form a passivation contact structure, providing good interface passivation for the back surface of the silicon wafer.

[0005] The SE (Selective Emitter) process is a selective emitter technology that performs high-concentration doping (i.e., heavy doping) at the contact point between the gate line and the silicon wafer, and low-concentration doping (i.e., light doping) in areas outside the electrode. Selective emitter technology can reduce the contact resistance between the silicon wafer and the gate line, lowering the series resistance of the battery. Furthermore, the low-concentration doping area can reduce surface recombination and increase the minority carrier lifetime, thereby improving the battery's short-circuit current and open-circuit voltage.

[0006] In the prior art, a lightly doped first silicon layer is deposited, followed by a heavily doped second silicon layer. The second silicon layer is then removed from areas not covered by the metallization pattern according to the metallization pattern. Because the second silicon layer and the first silicon layer are essentially silicon, differing only in doping concentration, the process window is difficult to control regardless of the method used to remove the second silicon layer. This can easily lead to the removal of the first silicon layer, exposing the silicon substrate and losing the backside passivation structure.

[0007] Summary of the Invention

[0008] Based on this, it is necessary to provide a solar cell and a preparation method thereof to solve the problem that the related process easily removes the silicon layer, exposes the silicon substrate, and loses the back passivation structure.

[0009] A method for preparing a solar cell comprises the following steps:

[0010] forming a tunnel oxide layer on the first side of the silicon substrate;

[0011] forming an amorphous silicon layer on the tunnel oxide layer;

[0012] Performing a diffusion doping process, including: a first process of introducing a doping source and an oxygen source into the diffusion chamber and heating the amorphous silicon layer so that the amorphous silicon layer forms a doped polysilicon layer and a doped oxide layer located on the doped polysilicon layer; a second process of stopping the introduction of the doping source and maintaining the introduction of the oxygen source to increase the thickness of the doped oxide layer;

[0013] A heavily doped region is formed on the doped polysilicon layer by a laser doping process.

[0014] In one embodiment, the preparation method meets at least one of the following characteristics (1)-(2):

[0015] (1) In the first process, the process temperature is 820°C-880°C;

[0016] (2) In the second process, the process temperature is 850°C-920°C.

[0017] In one embodiment, the preparation method meets at least one of the following characteristics (1)-(2):

[0018] (1) The doping concentration of the doped polysilicon layer is 1×10 20 atoms / cm 3 -3×10 21 atoms / cm 3 The doping concentration of the doped polysilicon layer is 1×10 20 atoms / cm 3 -3×10 21 atoms / cm 3 ;

[0019] (2) The square resistance of the doped polysilicon layer is 25ohm-45ohm.

[0020] In one embodiment, in the second process, the thickness of the doped oxide layer is controlled to be 80 nm-120 nm.

[0021] In one embodiment, the preparation method meets at least one of the following characteristics (1)-(2):

[0022] (1) The thickness of the tunnel oxide layer is 0.5 nm to 2 nm;

[0023] (2) The thickness of the amorphous silicon layer is 15nm-40nm.

[0024] In one embodiment, the preparation method meets at least one of the following characteristics (1)-(3):

[0025] (1) The wavelength of the light source used in the laser doping process is 350nm-700nm;

[0026] (2) The width of the light spot formed by the laser doping process is 60nm-120nm;

[0027] (3) The doping concentration of the heavily doped region is 2×10 20 atoms / cm 3 -2×10 21 atoms / cm 3 ;

[0028] (4) The square resistance of the heavily doped region is 10 ohm-25 ohm.

[0029] In one embodiment, after the laser doping process, the preparation method further includes the following steps:

[0030] A thermal oxide layer is formed on the back side by a thermal oxidation process.

[0031] In one embodiment, the preparation method meets at least one of the following characteristics (1)-(3):

[0032] (1) The temperature of the thermal oxidation process is 1000°C-1200°C;

[0033] (2) The thermal oxidation process time is 4000s-10000s;

[0034] (3) The thickness of the thermal oxidation layer is 60nm-200nm.

[0035] In one embodiment, the preparation method further comprises the following steps:

[0036] An emitter is formed on a second side of the silicon substrate, wherein the second side is opposite to the first side.

[0037] In one embodiment, the preparation method further comprises the following steps:

[0038] preparing a first electrode in contact with the heavily doped region; and / or

[0039] A second electrode is prepared in contact with the emitter.

[0040] A solar cell is prepared by the preparation method described in any one of the above embodiments.

[0041] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0043] FIG1 is a schematic structural diagram of a solar cell prepared by a preparation method according to an embodiment.

[0044] FIG2 is a schematic structural diagram of a solar cell prepared by a preparation method according to an embodiment.

[0045] Description of reference numerals:

[0046] 100. Solar cell; 110. Silicon substrate; 120. Tunneling oxide layer; 130. Doped polysilicon layer; 131. Doped oxide layer; 140. Heavily doped region; 150. Emitter; 160. First passivation layer; 161. Aluminum oxide layer; 162. First silicon nitride layer; 170. Thermal oxide layer; 180. Second passivation layer; 191. First electrode; 192. Second electrode. DETAILED DESCRIPTION

[0047] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0049] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0051] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0052] The present application provides a method for preparing a solar cell. FIG1 and FIG2 show a solar cell 100 prepared by the method according to an embodiment.

[0053] The method for preparing the solar cell 100 according to an embodiment of the present application includes the following steps.

[0054] A tunnel oxide layer 120 is formed on a first side of the silicon substrate 110 .

[0055] An amorphous silicon layer is formed on the tunnel oxide layer 120 .

[0056] The diffusion doping treatment includes: a first process of introducing a doping source and an oxygen source into the diffusion chamber and heating the amorphous silicon layer so that the amorphous silicon layer forms a doped polysilicon layer 130 and a doped oxide layer 131 located on the doped polysilicon layer 130; a second process of stopping the introduction of the doping source and keeping the introduction of the oxygen source to increase the thickness of the doped oxide layer 131.

[0057] A heavily doped region 140 is formed on the doped polysilicon layer 130 by a laser doping process.

[0058] The above-described method for fabricating the solar cell 100 forms an amorphous silicon layer on the back tunneling oxide layer 120, forms a doped polysilicon layer 130 in a first process through a diffusion doping process, and forms a doped oxide layer 131 on the doped polysilicon layer 130 in a second process. After forming the doped oxide layer 131, a laser doping process is used to achieve back-side selective heavy doping, and the heavily doped region 140 forms a selective emitter. On the one hand, the doped oxide layer 131 can provide sufficient impurity ions for SE doping. On the other hand, the doped oxide layer 131 can protect the tunneling oxide layer 120, reducing or preventing damage to the tunneling oxide layer 120 during the laser SE doping process, thereby achieving a good passivation effect.

[0059] In addition, due to the protective effect of the doped oxide layer 131 , it is beneficial to thin the doped polysilicon layer 130 . Reducing the thickness of the doped polysilicon layer 130 can significantly reduce parasitic absorption in the long-wave band and improve the short-circuit current of the solar cell 100 .

[0060] In one exemplary fabrication method, the emitter 150 is formed on a second side of the silicon substrate 110 , where the second side is opposite to the first side.

[0061] The emitter 150 can be formed by doping impurity ions on the second side, forming a PN junction between the emitter 150 and the silicon substrate 110. For example, if the silicon substrate 110 is N-type silicon, the emitter 150 can be a P+ doped layer formed by a boron diffusion process.

[0062] In one example, before forming the emitter 150 , the silicon substrate 110 is textured and cleaned to form a textured structure on the second side, which can achieve an anti-reflection effect.

[0063] In one example of the fabrication method, a first passivation layer 160 is formed on the emitter 150. In one example, the first passivation layer 160 includes an aluminum oxide layer 161 and a first silicon nitride layer 162, wherein the aluminum oxide layer 161 is located between the emitter 150 and the first silicon nitride layer 162.

[0064] Because high-concentration doping in the amorphous silicon layer on the back of solar cell 100 can cause significant parasitic absorption, the doped polysilicon layer 130 needs to be thinned. This also requires considering the sintering window of the slurry to prevent burn-through. Therefore, the relevant deposition and diffusion processes, as well as laser parameters, are key to SE technology on the back of solar cell 100.

[0065] In one example, the tunnel oxide layer 120 is deposited using a CVD process; in another example, it is deposited using an LPCVD (Low Pressure Chemical Vapor Deposition) process. It is understood that the precursor of the tunnel oxide layer 120 can be O2.

[0066] In one example, the tunnel oxide layer 120 deposition process parameters include: a pressure of 740 torr to 780 torr; in one example, 755 torr to 765 torr; and in one example, more preferably 760 torr; a temperature of 550° C. to 650° C.; in one example, 590° C. to 610° C.; and in one example, 600° C.; an oxygen source flow rate of 20,000 sccm to 40,000 sccm; in one example, 25,000 sccm to 35,000 sccm; and in one example, 30,000 sccm; and a deposition time of 500 s to 1500 s; in one example, 900 s to 1100 s; and in one example, 1000 s.

[0067] In one example, the thickness of the tunnel oxide layer 120 is 0.5 nm to 2 nm. In one example, the thickness of the tunnel oxide layer 120 is 1.5 nm.

[0068] In one example, the amorphous silicon layer is deposited using a CVD process; in another example, the amorphous silicon layer is deposited using an LPCVD process. It is understood that the precursor of the amorphous silicon layer can be SiH4.

[0069] In one example, the amorphous silicon layer deposition process parameters include: pressure of 0.1 torr to 1 torr; in another example, 0.2 torr to 0.4 torr; and in another example, 0.3 torr. Temperature of 550°C to 650°C; in another example, 590°C to 610°C; and in another example, 600°C. SiH4 flow rate of 500 sccm to 2000 sccm; in another example, 1300 sccm to 1500 sccm; and in another example, 1400 sccm. Deposition time of 150 seconds to 400 seconds; in another example, 180 seconds to 220 seconds; and in another example, 200 seconds.

[0070] In one of the examples, the thickness of the amorphous silicon layer is greater than 15nm, for example, 15nm-40nm. Studies have shown that an amorphous silicon layer with a thickness of about 15nm can meet the passivation requirements of the battery. Increasing the thickness of the amorphous silicon layer can avoid burning through the amorphous silicon layer during the metallization process. In one of the examples, the thickness of the amorphous silicon layer is 15nm-20nm. In one of the examples, the thickness of the amorphous silicon layer is 20nm. In this example, setting the thickness of the amorphous silicon layer within the range of 15nm-40nm can significantly reduce parasitic absorption in the long-wave band and increase the short-circuit current of the solar cell 100.

[0071] In the first process of the diffusion doping treatment, a doping source and an oxygen source are introduced for deposition, and thermal diffusion is performed to dope the amorphous silicon layer to form a doped polysilicon layer 130 .

[0072] In one example, the doping source is a phosphorus source, such as phosphorus oxychloride, to dope the amorphous silicon layer with phosphorus.

[0073] In the first process, the doping source is introduced by introducing nitrogen gas, which brings the liquid doping source such as phosphorus oxychloride in the source bottle into the furnace tube.

[0074] In one example, the process temperature during the first step was 820°C-880°C; in another example, it was 860°C-880°C; and in another example, it was 870°C. In this example, compared to conventional processes, the diffusion temperature was lowered to prevent excessive inward diffusion of the dopant source during thinning of the amorphous silicon layer, which could damage the passivation structure.

[0075] In one example, the process parameters of the first process further include:

[0076] The nitrogen flow rate is 500-1500 sccm; in one example, 800 sccm-1200 sccm; and in one example, 1000 sccm. The oxygen source flow rate is 500-1500 sccm; in one example, 900 sccm-1100 sccm; and in one example, 1000 sccm. The pressure is 100-500 Torr; in one example, 150 Torr-250 Torr; and in one example, 200 Torr. The duration is 400 s-2000 s; in one example, 600 s-1000 s; and in one example, 800 s.

[0077] In the second step of the diffusion doping process, an oxygen source is introduced to form a doped oxide layer 131 on the doped polysilicon layer 130. In the second step, no more doping source is introduced, and the main purpose is to form a thicker doped oxide layer 131.

[0078] If the doping source is a phosphorus source, specifically phosphorus oxychloride, the formed doped oxide layer 131 is a phosphosilicate glass layer (PSG layer).

[0079] In one example, the process parameters of the second process include: a temperature of 850°C to 920°C; in one example, 865°C to 875°C; and in one example, 870°C. An oxygen source flow rate of 1000 sccm to 4000 sccm; in one example, 1500 sccm to 2500 sccm; and in one example, 2000 sccm. A pressure of 100 torr to 500 torr to 350 torr to 450 torr to 400 torr to 400 torr to 400 torr to 400 torr to 400 torr to 5000 seconds to 2500 seconds to 3500 seconds to 30 ...

[0080] In one example, the thickness of the doped oxide layer 131 is 80 nm to 120 nm. In another example, the thickness of the doped oxide layer 131 is 90 nm to 110 nm. In another example, the thickness of the doped oxide layer 131 is 100 nm. On the one hand, the thicker doped oxide layer 131 can provide sufficient impurity ions for laser doping to form the SE cell. On the other hand, the doped oxide layer 131 of this thickness can protect the tunneling oxide layer 120 from being damaged during the laser doping process, thereby achieving a good passivation effect.

[0081] In one example, the doping concentration of the doped polysilicon layer 130 is 1×10 20 atoms / cm 3 -3×10 21 atoms / cm 3 ; in one example, 1.5×10 21 atoms / cm 3 -2.5×10 21 atoms / cm 3 ; in one example, 2×10 21 atoms / cm 3 .

[0082] In one example, the sheet resistance of the doped polysilicon layer 130 is 25 ohms to 45 ohms; in one example, it is 32 ohms to 38 ohms; and in one example, it is 35 ohms.

[0083] After the doped oxide layer 131 is formed, the back side of the silicon substrate is selectively heavily doped by laser, and the heavily doped region 140 forms a selective emitter.

[0084] In one example, the wavelength of the light source used in the laser doping process is 350nm-700nm. In one example, the wavelength of the light source used in the laser doping process is 532nm (green light). In one example, the wavelength of the light source used in the laser doping process is 355nm (violet light).

[0085] In one example, the width of the light spot formed by the laser doping process is 60 nm to 120 nm. In one example, the light spot formed by the laser doping process is a square light spot with a width of 80 nm.

[0086] In one example, the doping concentration of the heavily doped region 140 is 2×10 20 atoms / cm 3 -2×10 21 atoms / cm 3 ; in one example, 6×10 20 atoms / cm 3 -1×10 21 atoms / cm 3 ; in one example, 8×10 20 atoms / cm 3 .

[0087] In one example, the sheet resistance of the heavily doped region 140 is 10 ohms to 25 ohms; in one example, it is 13 ohms to 17 ohms; and in one example, it is 15 ohms.

[0088] In one example of the preparation method, after the laser doping process, the method further includes the step of forming a thermal oxide layer on the back side of the silicon substrate through a thermal oxidation process.

[0089] In the above example, a thermal oxide layer 170 is generated by thermal oxidation on the basis of the back SE. On the one hand, the thermal oxide layer 170 can serve as a barrier layer for the metal slurry to prevent the doped polysilicon layer 130 from being burned through. On the other hand, the thermal oxide layer 170 obtained by thermal oxidation growth is also an excellent passivation material, which can play an auxiliary passivation effect.

[0090] In one example, process parameters of the thermal oxidation process include: temperature of 1000° C.-1200° C.; time of 4000s-10000s.

[0091] The thermal oxide layer has a certain thickness to prevent the doped polysilicon layer 130 from being burned through. In one example, the thickness of the thermal oxide layer is 60 nm-200 nm; in another example, it is 70 nm-100 nm; in another example, it is 80 nm.

[0092] In one exemplary preparation method, an etching and cleaning process is performed to remove the doped oxide layer 131 and the doped polysilicon layer 130 on the second side and side surfaces of the silicon substrate 110. The etching and cleaning process can be performed after the laser doping process or after the thermal oxidation process.

[0093] In one exemplary fabrication method, a second passivation layer 180 is deposited on the back surface. In one exemplary embodiment, the second passivation layer 180 comprises a second silicon nitride layer. The step of depositing the second passivation layer 180 may be performed after the aforementioned laser doping process, after the aforementioned thermal oxidation process, or after the etching and cleaning process.

[0094] The solar cell 100 may be, but is not limited to, a TOPCon cell.

[0095] The above-described method for preparing the solar cell 100 forms an amorphous silicon layer on the back tunneling oxide layer 120, forms a doped polysilicon layer 130 through a diffusion doping process in a first step, and forms a doped oxide layer 131 on the doped polysilicon layer 130 in a second step. After forming the doped oxide layer 131, a laser doping process is used to achieve selective backside heavy doping, and the heavily doped region 140 forms a selective emitter. On the one hand, the doped oxide layer 131 can provide sufficient impurity ions for laser doping. On the other hand, the doped oxide layer 131 can protect the tunneling oxide layer 120, reducing or preventing damage to the tunneling oxide layer 120 during the laser doping process, thereby achieving a good passivation effect.

[0096] In addition, due to the protective effect of the doped oxide layer 131 , it is beneficial to thin the doped polysilicon layer 130 . Reducing the thickness of the doped polysilicon layer 130 can significantly reduce parasitic absorption in the long-wave band and improve the short-circuit current of the solar cell 100 .

[0097] The application has simple steps and the process is easy to control. The above preparation process does not involve complicated masks or related graphic steps. It meets the mass production requirements, improves efficiency and can significantly reduce production costs.

[0098] Furthermore, the present application also provides a solar cell, which is prepared by any of the preparation methods described above.

[0099] The following specific examples are provided to further illustrate the present application.

[0100] Example 1

[0101] This embodiment provides a method for preparing a solar cell, comprising the following steps:

[0102] S1, texturing and cleaning: Provide N-type silicon wafers and use alkaline cleaning process to form a pyramid texturing surface on the front side of the N-type silicon wafers.

[0103] S2, Boron diffusion: Boron diffusion process is performed on the front side of the N-type silicon wafer to prepare the emitter and form a PN junction.

[0104] S3, back etching: clean the PN junction plating on the back of the N-type silicon wafer and polish the back of the N-type silicon wafer.

[0105] S4, LPCVD: using LPCVD to sequentially deposit a tunneling silicon oxide layer and an amorphous silicon layer.

[0106] When depositing the tunneling silicon oxide layer, process parameters include: pressure of 760 Torr, temperature of 600° C., oxygen flow rate of 30,000 sccm, and time of 1,000 s.

[0107] The thickness of the formed tunnel oxide layer is 1.5 nm.

[0108] When depositing the amorphous silicon layer, the process parameters include: pressure of 0.3 torr, temperature of 600° C., SiH 4 flow rate of 1400 sccm, and time of 200 s.

[0109] The thickness of the formed amorphous silicon layer was 20 nm.

[0110] S5, phosphorus diffusion: a phosphorus diffusion process is performed on the back side of the N-type silicon wafer to form an N-type doped polysilicon layer (n-poly).

[0111] Phosphorus expansion is mainly divided into the first process and the second process.

[0112] In the first process, a phosphorus source and oxygen are introduced for deposition, while high temperature is used to promote phosphorus doping. The phosphorus source is introduced by nitrogen gas, which brings liquid phosphorus oxychloride from a source bottle into the furnace tube.

[0113] The process parameters of the first process include: deposition temperature of 860° C., nitrogen flow rate of 1000 sccm, oxygen flow rate of 1000 sccm, pressure of 200 torr, and time of 800 s.

[0114] In the second process, oxygen is introduced without a phosphorus source, the main purpose of which is to form a thicker PSG layer.

[0115] The process parameters of the second process include: deposition temperature of 870° C., oxygen flow rate of 2000 sccm, pressure of 400 torr, and time of 3000 s.

[0116] The thickness of the PSG layer formed in this phosphorus diffusion step is 100 nm, and the doping concentration is 2×10 20 atoms / cm 3 , the square resistance is 35ohm.

[0117] S6, back laser SE: Use laser to perform heavy doping at the back gate line to form a selective emitter.

[0118] The process uses a 532nm green laser. The spot is a square spot with a width of 80nm. The doping concentration in the heavily doped area is 8×10 20 atoms / cm 3 The sheet resistance of the heavily doped region is 15 ohms.

[0119] S7, thermal oxidation: A thermal oxide layer is grown on the back side of the N-type silicon wafer using a tubular thermal oxidation furnace.

[0120] The process parameters include: temperature of 1100°C and time of 8000s.

[0121] The thickness of the thermal oxide layer is 80 nm.

[0122] S8, etching and cleaning: using the chain polishing method and the groove polishing method to clean and remove the PSG layer and the amorphous silicon layer on the front and side surfaces.

[0123] S9, coating: depositing an aluminum oxide layer and a first silicon nitride layer on the front side of the N-type silicon wafer in sequence, and depositing a second silicon nitride layer on the back side.

[0124] S10, metallization: printing silver-aluminum paste on the front side of the N-type silicon wafer and silver paste on the back side, sintering at high temperature to obtain gate lines.

[0125] Example 2

[0126] This embodiment provides a method for preparing a solar cell, comprising the following steps:

[0127] S1, texturing and cleaning: provide a single crystal silicon wafer and use an alkaline washing process to form a pyramid texture surface on the front of the single crystal silicon wafer.

[0128] S2, Boron diffusion: Boron diffusion process is performed on the front side of the single crystal silicon wafer to prepare the emitter and form a PN junction.

[0129] S3, back etching: clean the PN junction plating on the back of the single crystal silicon wafer and polish the back of the single crystal silicon surface.

[0130] S4, LPCVD: using LPCVD to sequentially deposit a tunneling silicon oxide layer and an amorphous silicon layer.

[0131] When depositing the tunneling silicon oxide layer, process parameters include: pressure of 760 Torr, temperature of 600° C., oxygen flow rate of 30,000 sccm, and time of 1,000 s.

[0132] The thickness of the formed tunnel oxide layer is 1.5 nm.

[0133] When depositing the amorphous silicon layer, the process parameters include: pressure of 0.3 torr, temperature of 600° C., SiH 4 flow rate of 1400 sccm, and time of 200 s.

[0134] The thickness of the formed amorphous silicon layer was 20 nm.

[0135] S5, phosphorus diffusion: a phosphorus diffusion process is performed on the back side of the single crystal silicon wafer to form an N-type doped polysilicon layer (n-poly).

[0136] Phosphorus expansion is mainly divided into the first process and the second process.

[0137] In the first process, a phosphorus source and oxygen are introduced for deposition, while high temperature is used to promote phosphorus doping. The phosphorus source is introduced by nitrogen gas, which brings liquid phosphorus oxychloride from a source bottle into the furnace tube.

[0138] The process parameters of the first process include: deposition temperature of 860° C., nitrogen flow rate of 1000 sccm, oxygen flow rate of 1000 sccm, pressure of 200 torr, and time of 800 s.

[0139] In the second process, oxygen is introduced without a phosphorus source, the main purpose of which is to form a thicker PSG layer.

[0140] The process parameters of the second process include: deposition temperature of 870° C., oxygen flow rate of 2000 sccm, pressure of 400 torr, and time of 1000 s.

[0141] The thickness of the PSG layer formed in this phosphorus diffusion step is 30 nm and the doping concentration is 2×10 20 atoms / cm 3 , the square resistance is 35ohm.

[0142] S6, back laser SE: Use laser to perform heavy doping at the back gate line to form a selective emitter.

[0143] The process uses a 532nm green laser. The spot is a square spot with a width of 80nm. The doping concentration in the heavily doped area is 8×10 20 atoms / cm 3 The sheet resistance of the heavily doped region is 15 ohms.

[0144] S7, thermal oxidation: A thermal oxide layer is grown on the back of the single crystal silicon wafer using a tubular thermal oxidation furnace.

[0145] The process parameters include: temperature of 1100°C and time of 8000s.

[0146] The thickness of the thermal oxide layer is 80 nm.

[0147] S8, etching and cleaning: using the chain polishing method and the groove polishing method to clean and remove the PSG layer and the amorphous silicon layer on the front and side surfaces.

[0148] S9, coating: depositing an aluminum oxide layer and a first silicon nitride layer on the front side in sequence, and depositing a second silicon nitride layer on the back side.

[0149] S10, metallization: printing silver-aluminum paste on the front and silver paste on the back, sintering at high temperature to obtain gate lines.

[0150] Comparative Example 1

[0151] The preparation method of the solar cell of this comparative example comprises the following steps:

[0152] S1, texturing and cleaning: provide a single crystal silicon wafer and use an alkaline washing process to form a pyramid texture surface on the front side of the single crystal silicon wafer.

[0153] S2, Boron diffusion: Boron diffusion process is performed on the front side of the single crystal silicon wafer to prepare the emitter and form a PN junction.

[0154] S3, back etching: cleaning the PN junction plating on the back side of the single crystal silicon wafer and polishing the back side of the single crystal silicon wafer.

[0155] S4, LPCVD: using LPCVD to sequentially deposit a tunneling silicon oxide layer and an amorphous silicon layer.

[0156] When depositing the tunneling silicon oxide layer, process parameters include: pressure of 760 Torr, temperature of 600° C., oxygen flow rate of 30,000 sccm, and time of 1,000 s.

[0157] The thickness of the formed tunnel oxide layer is 1.5 nm.

[0158] When depositing the amorphous silicon layer, the process parameters include: pressure of 0.3 torr, temperature of 600° C., SiH 4 flow rate of 1400 sccm, and time of 1200 s.

[0159] The thickness of the formed amorphous silicon layer was 120 nm.

[0160] S5, phosphorus diffusion: a phosphorus diffusion process is performed on the back side of the N-type silicon wafer to form an N-type doped polysilicon layer (n-poly).

[0161] Phosphorus expansion is mainly divided into the first process and the second process.

[0162] In the first process, a phosphorus source and oxygen are introduced for deposition, while high temperature is used to promote phosphorus doping. The phosphorus source is introduced by nitrogen gas, which brings liquid phosphorus oxychloride from a source bottle into the furnace tube.

[0163] The process parameters of the first process include: deposition temperature of 860° C., nitrogen flow rate of 1000 sccm, oxygen flow rate of 1000 sccm, pressure of 200 torr, and time of 800 s.

[0164] In the second process, oxygen is introduced without a phosphorus source.

[0165] The process parameters of the second process include: deposition temperature of 870° C., oxygen flow rate of 2000 sccm, pressure of 400 torr, and time of 1000 s.

[0166] The thickness of the PSG layer formed in this phosphorus diffusion step is 30 nm and the doping concentration is 2×10 20 atoms / cm 3 , the square resistance is 35ohm.

[0167] S6, etching and cleaning: using the chain polishing method and the groove polishing method to clean and remove the PSG layer and the amorphous silicon layer on the front and side surfaces.

[0168] S7, coating: depositing an aluminum oxide layer and a first silicon nitride layer on the front surface in sequence, and depositing a second silicon nitride layer on the back surface.

[0169] S8, metallization: printing silver-aluminum paste on the front and silver paste on the back, sintering at high temperature to obtain gate lines.

[0170] Comparative Example 2

[0171] The preparation method of the solar cell of this comparative example comprises the following steps:

[0172] S1, texturing and cleaning: provide a single crystal silicon wafer and use an alkaline washing process to form a pyramid texture surface on the front side of the single crystal silicon wafer.

[0173] S2, Boron diffusion: Boron diffusion process is performed on the front side of the single crystal silicon wafer to prepare the emitter and form a PN junction.

[0174] S3, back etching: cleaning the PN junction plating on the back of the single crystal silicon wafer and polishing the back of the single crystal silicon wafer.

[0175] S4, LPCVD: using LPCVD to sequentially deposit a tunneling silicon oxide layer and an amorphous silicon layer.

[0176] When depositing the tunneling silicon oxide layer, process parameters include: pressure of 760 Torr, temperature of 600° C., oxygen flow rate of 30,000 sccm, and time of 1,000 s.

[0177] The thickness of the formed tunnel oxide layer is 1.5 nm.

[0178] When depositing the amorphous silicon layer, the process parameters include: pressure of 0.3 torr, temperature of 600° C., SiH 4 flow rate of 1400 sccm, and time of 200 s.

[0179] The thickness of the formed amorphous silicon layer was 20 nm.

[0180] S5, phosphorus diffusion: a phosphorus diffusion process is performed on the back side of the single crystal silicon wafer to form an N-type doped polysilicon layer (n-poly).

[0181] Phosphorus expansion is mainly divided into the first process and the second process.

[0182] In the first process, a phosphorus source and oxygen are introduced for deposition, while high temperature is used to promote phosphorus doping. The phosphorus source is introduced by nitrogen gas, which brings liquid phosphorus oxychloride from a source bottle into the furnace tube.

[0183] The process parameters of the first process include: deposition temperature of 860° C., nitrogen flow rate of 1000 sccm, oxygen flow rate of 1000 sccm, pressure of 200 torr, and time of 800 s.

[0184] In the second process, oxygen is introduced without a phosphorus source.

[0185] The process parameters of the second process include: deposition temperature of 870° C., oxygen flow rate of 2000 sccm, pressure of 400 torr, and time of 1000 s.

[0186] The thickness of the PSG layer formed in this phosphorus diffusion step is 30 nm and the doping concentration is 2×10 20 atoms / cm 3 , the square resistance is 35ohm.

[0187] S6, etching and cleaning: using chain and slot cleaning to remove the PSG layer and amorphous silicon layer on the front and side surfaces.

[0188] S7, coating: depositing an aluminum oxide layer and a first silicon nitride layer on the front surface in sequence, and depositing a second silicon nitride layer on the back surface.

[0189] S8, metallization: printing silver-aluminum paste on the front and silver paste on the back, sintering at high temperature to obtain gate lines.

[0190] Comparative Example 3

[0191] The preparation method of the solar cell of this comparative example comprises the following steps:

[0192] S1, texturing and cleaning: provide a single crystal silicon wafer and use an alkaline washing process to form a pyramid texture surface on the front side of the single crystal silicon wafer.

[0193] S2, Boron diffusion: Boron diffusion process is performed on the front side of the single crystal silicon wafer to prepare the emitter and form a PN junction.

[0194] S3, back etching: clean the PN junction plating on the back of the single crystal silicon wafer and polish the back of the single crystal silicon wafer.

[0195] S4, LPCVD: using LPCVD to deposit tunneling silicon oxide and amorphous silicon layers in sequence.

[0196] When depositing the tunneling silicon oxide layer, process parameters include: pressure of 760 Torr, temperature of 600° C., oxygen flow rate of 30,000 sccm, and time of 1,000 s.

[0197] The thickness of the formed tunnel oxide layer is 1.5 nm.

[0198] When depositing the amorphous silicon layer, the process parameters include: pressure of 0.3 torr, temperature of 600° C., SiH 4 flow rate of 1400 sccm, and time of 200 s.

[0199] The thickness of the formed amorphous silicon layer was 20 nm.

[0200] S5, phosphorus diffusion: a phosphorus diffusion process is performed on the back side of the single crystal silicon wafer to form an N-type doped polysilicon layer (n-poly).

[0201] Phosphorus expansion is mainly divided into the first process and the second process.

[0202] In the first process, a phosphorus source and oxygen are introduced for deposition, while high temperature is used to promote phosphorus doping. The phosphorus source is introduced by nitrogen gas, which brings liquid phosphorus oxychloride from a source bottle into the furnace tube.

[0203] The process parameters of the first process include: deposition temperature of 860° C., nitrogen flow rate of 1000 sccm, oxygen flow rate of 1000 sccm, pressure of 200 torr, and time of 800 s.

[0204] In the second process, oxygen is introduced without a phosphorus source.

[0205] The process parameters of the second process include: deposition temperature of 870° C., oxygen flow rate of 2000 sccm, pressure of 400 torr, and time of 1000 s.

[0206] The thickness of the PSG layer formed in this phosphorus diffusion step is 30 nm and the doping concentration is 2×10 20 atoms / cm 3 , the square resistance is 35ohm.

[0207] S6, thermal oxidation: using a tubular thermal oxidation furnace tube to grow a thermal oxide layer on the back.

[0208] The process parameters include: temperature of 1100°C and time of 8000s.

[0209] The thickness of the thermal oxide layer is 80 nm.

[0210] S8, etching and cleaning: using chain and slot cleaning to remove the PSG layer and amorphous silicon layer on the front and side surfaces.

[0211] S9, coating: depositing an aluminum oxide layer and a first silicon nitride layer on the front side in sequence, and depositing a second silicon nitride layer on the back side.

[0212] S10, metallization: printing silver-aluminum paste on the front and silver paste on the back, sintering at high temperature to obtain gate lines.

[0213] The differences between the above Examples 1-2 and Comparative Examples 1-3 are shown in Table 1.

[0214] Table 1 Differences between Examples 1-2 and Comparative Examples 1-3

[0215] The solar cells prepared in Examples 1-2 and Comparative Examples 1-3 were subjected to electrical performance tests, and the results are shown in Table 2. The test method was based on IEC TS 63202-3 Photovoltaic cells - Part 3: Measurement of current-voltage characteristics of bicial photovoltaic cells, as formulated and published by the International Electrotechnical Commission.

[0216] Table 2 Electrical properties of solar cells prepared in Examples 1-2 and Comparative Examples 1-3

[0217] As shown in the test results in Table 2, Comparative Example 1 has a thicker doped polysilicon layer than Comparative Example 2, resulting in more severe parasitic absorption and a lower short-circuit current. In contrast, despite the thinner doped polysilicon layer in Comparative Example 2, the open-circuit voltage is significantly lower than in Comparative Example 1. This is because while simply thinning the doped polysilicon layer yields a greater current gain, it also causes the silver paste on the backside to burn through the doped polysilicon layer, directly contacting the silicon substrate and leading to significant recombination, which in turn reduces the open-circuit voltage.

[0218] Compared with Comparative Example 2, Comparative Example 3 grows a thicker thermal oxide layer on the doped polysilicon layer. The dense thermal oxide layer can play a good blocking and passivation role, so while obtaining a high current gain, it can also maintain a high open circuit voltage.

[0219] In both Examples 1 and 2, a PSG layer was formed on the doped polysilicon layer and a laser doping process was performed. In terms of electrical performance, the open-circuit voltages of Examples 1 and 2 were significantly higher than those of Comparative Examples 1-3, increasing by at least 7 mV. While the PSG layer provided some protection for the doped polysilicon layer, its thinness meant that the laser still damaged the tunneling silicon oxide layer during the laser doping process, resulting in a relatively low open-circuit voltage in Example 2.

[0220] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0221] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims, and the specification may be used to interpret the content of the claims.

Claims

1. A method for preparing a solar cell, characterized in that: The following steps are involved: forming a tunneling oxide layer on a first side of a silicon substrate; forming an amorphous silicon layer on the tunnel oxide layer; The amorphous silicon layer is subjected to diffusion doping treatment, comprising: a first process, introducing a doping source and an oxygen source into the diffusion chamber, and heating the amorphous silicon layer, so that the amorphous silicon layer forms a doped polysilicon layer and a doped oxide layer located on the doped polysilicon layer; a second process, stopping introducing the doping source and keeping introducing the oxygen source to increase the thickness of the doped oxide layer; A heavily doped region is formed on the doped polysilicon layer by a laser doping process.

2. The method for preparing a solar cell according to claim 1, wherein: The preparation method meets at least one of the following characteristics (1)-(2): (1) In the first process, the process temperature is 820°C-880°C; (2) In the second process, the process temperature is 850°C-920°C.

3. The method for preparing a solar cell according to claim 1, wherein: In the second process, the thickness of the doped oxide layer is controlled to be 80nm-120nm.

4. The method for preparing a solar cell according to claim 1, wherein: The preparation method meets at least one of the following characteristics (1)-(2): (1) The thickness of the tunnel oxide layer is 0.5 nm to 2 nm; (2) The thickness of the amorphous silicon layer is 15nm-40nm.

5. The method for preparing a solar cell according to claim 1, wherein: The preparation method meets at least one of the following characteristics (1)-(3): (1) The wavelength of the light source used in the laser doping process is 350nm-700nm; (2) The width of the light spot formed by the laser doping process is 60nm-120nm; (3) The doping concentration of the heavily doped region is 2×10 20 atoms / cm 3 -2×10 21 atoms / cm 3 ; (4) The square resistance of the heavily doped region is 10 ohm-25 ohm.

6. The method for preparing a solar cell according to any one of claims 1 to 5, wherein: After the laser doping process, the preparation method further comprises the following steps: A thermal oxide layer is formed on the back side by a thermal oxidation process.

7. The method for preparing a solar cell according to claim 6, wherein: The preparation method meets at least one of the following characteristics (1)-(3): (1) The temperature of the thermal oxidation process is 1000°C-1200°C; (2) The thermal oxidation process time is 4000s-10000s; (3) The thickness of the thermal oxidation layer is 60nm-200nm.

8. The method for preparing a solar cell according to any one of claims 1 to 5, wherein: The preparation method further comprises the following steps: An emitter is formed on a second side of the silicon substrate, wherein the second side is arranged opposite to the first side.

9. The method for preparing a solar cell according to claim 8, wherein: The preparation method further comprises the following steps: preparing a first electrode in contact with the heavily doped region; and / or A second electrode is prepared in contact with the emitter.

10. A solar cell, characterized in that: It is prepared by the preparation method described in any one of claims 1 to 9.

Images