Resistive heterojunction programmable memory device

Abstract

The present invention relates to the field of memory devices. Disclosed is a resistive heterojunction programmable storage device. The memory device comprises a first electrode, a resistive heterojunction insulating dielectric layer and a second electrode which are connected in sequence; the resistive heterojunction insulating dielectric layer comprises a resistive layer and a programmable dielectric layer, and the resistive layer and the programmable dielectric layer are made of different insulating media; the first electrode and the second electrode are made of set matching materials, and the band gap of the resistive layer is smaller than the band gap of the programmable dielectric layer. The invention can achieve low-cost high-density storage.

Description

A current-blocking heterojunction programmable memory device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 10, 2023, with application number 202311008148.5 and invention name “A Current-Blocking Heterojunction Programmable Memory Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of memory devices, in particular to a current-blocking heterojunction programmable memory device. Background Art

[0003] Memory devices in the prior art include a type of 3D multi-layer stacked memory array with low cost and high storage density. For example, in patents CN101615656A and CN109545787A, a memory cell is formed by horizontal word lines (WL) and vertical bit lines (BL) composed of materials of opposite conductivity types, and a programmable insulating medium placed at the intersection of the two.

[0004] This type of 3D multi-layer stacked memory array features a WL and BL with opposite conductivity types, such as p-type and n-type highly doped polysilicon. When the programmable dielectric layer is programmed to a low-resistance state—for example, when the dielectric breakdown of an anti-fuse one-time programmable (OTP) memory device turns it into a conductive medium—the BL and WL automatically form a unidirectional diode. This arrangement offers the advantage of effectively controlling the extremely high storage density of 3D multi-layer stacked memory arrays without requiring additional space for diode components, resulting in a lower manufacturing cost.

[0005] However, in reality, any diode always has a certain reverse current. If the reverse current is large, it may be impossible to maintain a stable programming voltage, resulting in operational failure. This type of operational failure can occur under normal operation, especially when the memory array is large in scale and integration, such as 128 layers and a single layer of 1Mbit or more. The larger the memory array, the stricter the control requirements for the magnitude of the reverse current. Therefore, in order to ensure the operational stability of the memory, for the memory cells of such 3D multi-layer stacked memory arrays, a layer of semiconductor material is added between the insulating storage medium and the WL or BL as a buffer layer. For example, the dielectric layer between the unit device in patent CN109545787A can be composed of two parts: a storage insulating medium and a low-doped semiconductor. The conductivity type of the low-doped semiconductor is the same as the WL or BL it directly contacts and the doping concentration is low, generally low-doped polysilicon. The reverse current can be effectively controlled by optimizing the thickness of the buffer layer without affecting the unidirectional conduction characteristics of the device diode.

[0006] The characteristic of this method is that the thicker the buffer layer, the smaller the reverse current. However, the thickness of the buffer layer often occupies the chip's usable area. Especially when the memory cell size is further reduced to below the deep submicron to increase the storage density, the buffer layer will still occupy a considerable proportion of the memory cell's area, which limits the further improvement of the memory density. In addition, since the buffer layer generally needs to be deposited on the sidewalls of the storage hole with a high aspect ratio, if a crystalline semiconductor, such as low-doped polysilicon, is used as the buffer layer, the cost of the process implementation is very high, because the thin films prepared by the atomic layer deposition (ALD) technology with good thickness uniformity control are mostly disordered phases, and the doping concentration is difficult to control. Therefore, the existing technology often needs to compromise between device performance, chip area (storage density) and process cost.

[0007] Summary of the Invention

[0008] The purpose of the present invention is to provide a current-blocking heterojunction programmable memory device, which can realize low-cost and high-density storage.

[0009] To achieve the above object, the present invention provides the following solutions:

[0010] A current-blocking heterojunction programmable memory device, comprising: a first electrode, a current-blocking heterojunction insulating dielectric layer, and a second electrode connected in sequence;

[0011] The blocking heterojunction insulating dielectric layer includes: a blocking layer and a programmable dielectric layer;

[0012] The insulating media used in the blocking layer and the programmable dielectric layer are different; the first electrode and the second electrode are composed of set matching materials; the band gap width of the blocking layer is smaller than the band gap width of the programmable dielectric layer; no additional contact barrier is formed between the blocking layer and the first electrode or the second electrode in direct contact.

[0013] Optionally, the insulating medium used in the programmable dielectric layer is an antifuse insulating medium, a resistive non-volatile storage medium, or a phase-change non-volatile storage medium.

[0014] Optionally, the antifuse insulating medium is made of silicon oxide or aluminum oxide.

[0015] Optionally, the insulating medium used in the blocking layer includes a charge transfer insulator or an electrical insulator.

[0016] Optionally, the charge transfer insulator includes a TiO2, ZnO or HfO2 thin film.

[0017] Optionally, the electrical insulator comprises intrinsic SiC.

[0018] Optionally, the blocking layer is in a crystalline state, a polycrystalline state or a disordered state; and the blocking layer is a disordered HfO2 film, a disordered SiC film or a disordered silicon film.

[0019] Optionally, the setting supporting materials include four supporting materials;

[0020] Wherein, the first electrode is a P-type semiconductor or conductor, and the second electrode is an N-type semiconductor;

[0021] Alternatively, the first electrode is a P-type Schottky metal, and the second electrode is an N+ semiconductor or conductor;

[0022] Alternatively, the first electrode is an N+ semiconductor or conductor, and the second electrode is a P+ semiconductor;

[0023] Alternatively, the first electrode is an N-type Schottky metal, and the second electrode is a P+ semiconductor or conductor.

[0024] Optionally, the P-type Schottky metal is Au or Pt.

[0025] Optionally, the N-type Schottky metal is Al.

[0026] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0027] The present invention provides a current-blocking heterojunction programmable memory device. Due to the addition of an insulating current-blocking layer, its insulating properties significantly reduce the tunneling effect of reverse current. This allows for extremely low reverse current even with a small current-blocking layer thickness and a small chip footprint. Furthermore, there is no need for a crystalline semiconductor buffer, resulting in lower process costs. Because the current-blocking layer and the programmable dielectric layer utilize different insulating dielectrics, and the current-blocking layer has a smaller bandgap than the programmable dielectric layer, no additional contact barrier is formed between the current-blocking layer and the first or second electrode it contacts. Therefore, the addition of the current-blocking layer does not affect the current-voltage characteristics of the device during forward operation. Therefore, the present invention enables low-cost, high-density storage.

[0028] Figures in the specification

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] FIG1 is a structural diagram of a current-blocking heterojunction programmable memory device provided by an embodiment of the present invention;

[0031] FIG2 is a schematic diagram of a current-blocking heterojunction programmable memory device provided by an embodiment of the present invention;

[0032] FIG3 is a structural diagram of a first semiconductor device in the prior art provided by an embodiment of the present invention;

[0033] FIG4 is a structural diagram of a second semiconductor device in the prior art provided by an embodiment of the present invention;

[0034] FIG5 is a schematic diagram of an application circuit of a current-blocking heterojunction programmable memory device provided by an embodiment of the present invention;

[0035] FIG6 is a diagram of the energy band structure of a device provided by an embodiment of the present invention;

[0036] FIG7 is an electric field distribution diagram when an external forward voltage of 6V is provided in an embodiment of the present invention;

[0037] FIG8 is a diagram showing a comparison of the magnitude of reverse current with and without a blocking layer when the programmable dielectric layer is in a low-resistance state according to an embodiment of the present invention;

[0038] FIG9 is a diagram showing a comparison of the forward current with and without a blocking layer when the programmable dielectric layer is in a low-resistance state according to an embodiment of the present invention.

[0039] Explanation of symbols: first electrode-1; blocking heterojunction insulating dielectric layer-2; second electrode-3; blocking layer-4; programmable dielectric layer-5. DETAILED DESCRIPTION

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0041] The purpose of the present invention is to provide a current-blocking heterojunction programmable memory device, which can realize low-cost and high-density storage.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] Example 1

[0044] As shown in FIG1 , an embodiment of the present invention provides a current-blocking heterojunction programmable memory device, which includes a first electrode 1 , a current-blocking heterojunction insulating dielectric layer 2 , and a second electrode 3 connected in sequence.

[0045] The current-blocking heterojunction insulating dielectric layer 2 includes a current-blocking layer 4 and a programmable dielectric layer 5 .

[0046] The insulating media used in the blocking layer 4 and the programmable dielectric layer 5 are different; the first electrode 1 and the second electrode 3 are composed of set matching materials; the band gap width of the blocking layer 4 is smaller than the band gap width of the programmable dielectric layer 5; no additional contact resistance is formed between the blocking layer and the first electrode 1 or the second electrode 3 in direct contact, that is, no additional contact barrier is formed.

[0047] Specifically, the insulating medium used in the programmable dielectric layer 5 is a programmable non-volatile storage medium, such as an anti-fuse insulating medium, wherein the material of the anti-fuse insulating medium is silicon oxide or aluminum oxide.

[0048] The insulating medium used in the programmable dielectric layer 5 may also be a resistive non-volatile storage medium or a phase-change non-volatile storage medium.

[0049] The insulating medium used in the current blocking layer 4 is a charge transfer insulator or an electrical insulator. The charge transfer insulator is a TiO2, ZnO or HfO2 film. The electrical insulating compound includes intrinsic SiC.

[0050] The blocking layer 4 is in a crystalline state, a polycrystalline state or a disordered state.

[0051] Specifically, the bandgap of the blocking layer 4 is lower than that of the programmable dielectric layer 5, and its electron affinity matches the work function of the material of the adjacent electrode (first electrode 1 or second electrode 3), so that no additional contact barrier is formed between the two. Specifically, the material required for the blocking layer 4 can be a charge-transfer insulator, such as TiO2, ZnO, HfO2 thin film, or an electrically insulating compound, such as intrinsic SiC. The film morphology can be crystalline, polycrystalline, or disordered. For example, disordered HfO2 thin film, disordered SiC thin film, and disordered silicon thin film, with a typical thickness of 10nm to 30nm.

[0052] The blocking layer 4 can be prepared using atomic layer deposition (ALD) technology, chemical vapor deposition (CVD) technology, etc. The blocking layer 4 can be crystalline, polycrystalline, or disordered, such as disordered TiO2 film, disordered SiC film, disordered carbon, or silicon film.

[0053] Specifically, the programmable dielectric layer 5 is an anti-fuse insulating dielectric that can be programmed by dielectric breakdown.

[0054] The programmable dielectric layer 5 may also be made of a resistive non-volatile storage medium such as TaO 2 , or a phase-change non-volatile storage medium such as Ge 2 Sb 2 Te 5 or other chalcogenide compounds.

[0055] For example, if the programmable dielectric is silicon oxide with a bandgap of 9eV, the current blocking layer 4 can be made of an insulating dielectric with a bandgap of 3-7eV, such as HfO2 or ZrO2 with a bandgap of approximately 5.5eV, or TaO2 with a bandgap of approximately 4eV. The breakdown insulating dielectric for the antifuse, such as SiO2 or Al2O3, typically has a thickness of 0.5-5nm.

[0056] The programmable dielectric layer 5 is prepared by atomic layer deposition (ALD) technology, chemical vapor deposition (CVD) technology, etc.

[0057] There is no specific shape requirement for the blocking heterojunction insulating dielectric layer 2 , the first electrode 1 , and the second electrode 3 . As long as the above stacking sequence is followed, the blocking heterojunction programmable memory device provided by the present invention as shown in FIG. 2 can be obtained.

[0058] The above-mentioned blocking layer 4, due to its insulating properties, greatly reduces the tunneling effect of reverse current. Compared with the semiconductor materials in the prior art shown in Figures 3 and 4, it can still ensure extremely low reverse current while having a smaller layer thickness and occupying a smaller chip area. In addition, the present invention can further use a process cost of disordered thin films, thus achieving low-cost and high-density storage.

[0059] In one embodiment, the supporting materials are set to include four supporting materials; wherein, the first electrode 1 is a P-type semiconductor or conductor, and the second electrode 3 is an N-type semiconductor; or, the first electrode 1 is a P-type Schottky metal, and the second electrode 3 is an N+ semiconductor or conductor; or, the first electrode 1 is an N+ semiconductor or conductor, and the second electrode 3 is a P+ semiconductor; or, the first electrode 1 is an N-type Schottky metal, and the second electrode 3 is a P+ semiconductor or conductor.

[0060] Specifically, the P-type Schottky metal is Au or Pt, and the N-type Schottky metal is Al.

[0061] FIG5 is a schematic diagram of an application of a current-blocking heterojunction programmable memory device provided by the present invention. A1, A2, A3, and A4 in FIG5 are all programmable memory devices, wherein the schematic symbol of the programmable memory device can be equivalent to a capacitor symbol and a diode symbol, which is intended to indicate that the insulating medium in this memory cell and the electrode materials at both ends form a capacitor, and because the electrode materials at both ends are of different conductivity types, when the insulating dielectric layer is programmed from a high-resistance state to a low-resistance state, the entire memory cell has diode characteristics. It is worth noting that when the insulating dielectric layer is in a high-resistance state, it does not have diode characteristics.

[0062] Typically, in a three-dimensional memory device, the first electrode 1, serving as a bitline (BL), extends vertically downward in a columnar shape, connecting to the bitline decoder in the underlying circuitry. The second electrode 3, serving as a wordline (WL), extends horizontally, connecting to the wordline decoders at both ends. Alternatively, the second electrode 3, serving as a bitline (BL), extends vertically downward in a columnar shape, connecting to the bitline decoder in the underlying circuitry. The first electrode 1, serving as a wordline (WL), extends horizontally, connecting to the wordline decoders at both ends. An insulating dielectric layer is placed between the two intersecting projections, connecting them. The insulating dielectric layer is generally required to have a uniform thickness to maintain functional consistency.

[0063] The functions of this type of device are mainly in three different states, and the working conditions that need to be guaranteed are as follows:

[0064] ① Writing: The diode must be in a forward bias state, and the programming voltage applied to the programmable dielectric layer 5 must reach the dielectric strength required for the antifuse to break down. If the antifuse breaks down, the stored data changes from 0 to 1.

[0065] ② Read: The diode needs to be in a forward bias state, and the read voltage must exceed the diode threshold voltage. If the device is conducting, the reading is 1, and if it is not conducting, the reading is 0.

[0066] ③ Idle: One of the two electrodes is in a floating state.

[0067] When the crisscrossed, selected and unselected word lines and bit lines of a 3D memory work together, there is a possibility that idle memory cells may be reverse biased. Reducing the reverse current when the programmable dielectric layer 5 of the memory cell is in a low-resistance state effectively ensures the orderly operation of the entire 3D memory array. For example, in Figure 5, when only memory cell A1 is being programmed, the other cells are idle, and WL-I and BL-I are connected to the high and low levels of the programming voltage, respectively. The other electrodes, WL-II and BL-II, are floating. If memory devices A2 and A4 are already programmed to a low-resistance state at this time, if A4's diode has ideal reverse characteristics, the states of the memory cells remain unchanged. However, if A4's reverse current is large, it will cause A2 and A4 to form a path, causing the potential of the floating WL-II terminal to be pulled up, potentially causing A3 to change from its original idle state to a write state. Alternatively, if the memory devices A2, A3, and A4 are in a low-resistance state at the same time, and if the reverse current of A4 is large, a path will be formed among A2, A4, and A3, which may cause the potential of the floating BL-I terminal to be pulled up, thereby causing the programming voltage across A1 to decrease, resulting in programming failure.

[0068] To ensure the operational stability of the programmable memory device, the present invention comprises an insulating storage dielectric layer, a programmable dielectric layer 5, and a blocking layer 4. Blocking layer 4 is an insulating thin film layer with a narrower bandgap than the programmable dielectric, and its electron affinity matches the work function of the electrode material it contacts, so that no additional majority carrier transport barrier is formed between them. Because the bandgap of blocking layer 4 is narrower than that of the programmable dielectric, the electric field applied to blocking layer 4 and programmable dielectric layer 5 during programming is largely concentrated on the programmable dielectric. Therefore, the addition of blocking layer 4 has minimal impact on the programming process in operating state ①.

[0069] At the same time, the current-blocking layer 4 formed of insulating material will also reduce the forward current to a certain extent.

[0070] As can be seen from the above operating conditions, there are only two forward bias operating states: ① and ②, representing electric field-driven high-voltage programming and low-voltage data reading, respectively. In the first case, which is an electric field-driven process, there are no strict requirements for the forward current; the only requirement is to ensure that the electric field is mostly concentrated on the programmable dielectric layer 5. In the second case, after the programmable dielectric layer 5 is broken down, data can be read by appropriately increasing the read voltage and / or lowering the threshold current. Therefore, the introduction of the current blocking layer 4 does not affect normal read and write functions.

[0071] It is worth noting that the key to this method's effective reduction of reverse current by the blocking layer 4 is that, under reverse bias, it is not simply a series superposition of the reverse pn junction and the high resistance of the blocking layer 4 insulating layer itself, otherwise its impact on forward and reverse currents would be the same. Instead, because the blocking layer 4, with a larger bandgap width compared to semiconductors, is sandwiched between the two end electrodes, that is, the p- and n-type conductors (or semiconductors), it can effectively suppress the band-to-band tunneling effect of the reverse diode, thereby significantly reducing the reverse current. Therefore, ensuring that the blocking layer 4 is an insulating film layer with a narrower bandgap width than the programmable dielectric layer can significantly reduce the reverse current of the device after the programmable dielectric layer 5 breaks down, even if the thickness is relatively thin.

[0072] Furthermore, this method does not place strict requirements on the conductivity and crystallinity of the current-blocking layer 4. If amorphous thin films are further employed, process manufacturing costs can be effectively reduced. In particular, in 3D memory devices, thin films are typically deposited within deep trenches with extremely high aspect ratios. The manufacturing cost of polycrystalline thin films is very high, while that of disordered thin films is relatively low. Therefore, this method can ensure a relatively low reverse current without affecting memory read / write performance or occupying chip area, making process costs more achievable and enabling low-cost, high-density storage.

[0073] Taking one of the combinations of supporting materials as a specific embodiment, as shown in Figure 6, from left to right are: a first electrode 1, a blocking layer 4, a programmable dielectric layer 5, and a second electrode 3, wherein the first electrode 1 is an n-type semiconductor, the second electrode 3 is a p-type conductor, the blocking layer 4 is made of an insulating material with a band gap width lower than that of the programmable dielectric, and has a thickness of 18nm; the programmable dielectric layer 5 is made of silicon dioxide SiO2, a commonly used anti-fuse material, and has a thickness of 2nm.

[0074] Figure 6 shows the band structure of the device in which the various components are combined together. Figure 6 shows that the band gap width of the blocking layer 4 is lower than the band gap width of the programmable medium, and the electron affinity of the blocking layer 4 is equal to the work function of the electrode in contact with it, that is, the first electrode 1, both of which are 4.17 eV. That is, no additional carrier transport barrier is formed between the blocking layer 4 and the first electrode 1, and the conductive properties of the first electrode 1 and the second electrode 3 can be exhibited.

[0075] FIG7 is a diagram showing the electric field distribution of each component when the external forward voltage is 6V. The simulation results show that when the programmable dielectric layer 5 is in a high-resistance state, the introduction of the blocking layer 4 does not affect the high electric field required for the write state.

[0076] Figures 8 and 9 respectively show the comparison of the magnitude of the reverse current and the forward current when the programmable dielectric layer 5 is in a low-resistance state, with and without the introduction of the blocking layer 4. The simulation results show that the introduction of the blocking layer 4 has a more significant effect on reducing the reverse current in Figure 8 than the effect on reducing the forward current in Figure 9.

[0077] Furthermore, the blocking layer 4 formed of insulating material also reduces the forward current to a certain extent. Specifically, the introduction of the blocking layer 4 is intended to reduce the reverse current of the memory cell in the idle state, thereby ensuring the operational stability of the multiple memory cells in the 3D stacked arrangement. However, while reducing the reverse current, the forward current is also reduced to a certain extent (see Figure 8), which may affect other operating states. Here, we would like to add the following explanations: 1. Programming the storage medium, that is, operating state 1, in the electric field-driven mode, the programming medium is still in an insulating state, and the forward current requirement is not too high. Therefore, as long as the introduction of the blocking layer 4 does not affect the breakdown electric field in the insulating storage medium layer (see Figure 7), it will not affect the "write" operating state. 2. Reading data, that is, operating state 2, although there is a requirement for the forward current, the purpose of reading data can be achieved by appropriately increasing the read voltage and / or reducing the threshold current. Therefore, the introduction of the insulating blocking layer 4 does not affect the "read" operating state. In other words, the present invention improves the performance of operating state 3 while not affecting operating states 1 and 2.

[0078] The benefits of the present invention are:

[0079] 1. The difference from the prior art (pri-art) is that pri-art uses semiconductor materials as an intermediate layer (or buffer layer) to regulate reverse leakage current. Reducing leakage current generally requires increasing the thickness of the intermediate layer. Therefore, there is a conflict between reducing leakage current and reducing the occupied area, and a compromise needs to be considered between the two. The present invention, on the other hand, superimposes a blocking layer formed by a corresponding insulating layer material on the existing programmable dielectric layer. This can be optimized by adjusting the physical parameters of the blocking layer, such as the band gap width and dielectric constant, rather than the thickness of the insulating layer. Therefore, there is no conflict between reducing leakage current and reducing the occupied area.

[0080] 2. The typical application of the present invention can ensure extremely low PN junction reverse current, and can ensure extremely low reverse current even when the layer thickness is small and the chip area occupied is small.

[0081] 3. The process cost of disordered thin films can be further applied, so the present invention can achieve low-cost and high-density storage.

[0082] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0083] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A current-blocking heterojunction programmable memory device, characterized in that: The memory device comprises: a first electrode, a current-blocking heterojunction insulating dielectric layer, and a second electrode connected in sequence; The blocking heterojunction insulating dielectric layer comprises: a blocking layer and a programmable dielectric layer; The insulating media used by the blocking layer and the programmable dielectric layer are different; the first electrode and the second electrode are made of set matching materials; the band gap width of the blocking layer is smaller than the band gap width of the programmable dielectric layer; no additional contact barrier is formed between the blocking layer and the first electrode or the second electrode in direct contact.

2. The current-blocking heterojunction programmable memory device according to claim 1, characterized in that: The insulating medium used in the programmable dielectric layer is an anti-fuse insulating medium, a resistive non-volatile storage medium or a phase-change non-volatile storage medium.

3. The current-blocking heterojunction programmable memory device according to claim 2, characterized in that: The material of the anti-fuse insulating medium is silicon oxide or aluminum oxide.

4. The current-blocking heterojunction programmable memory device according to claim 1, characterized in that: The insulating medium used in the blocking layer includes a charge transfer insulator or an electrical insulator.

5. The current-blocking heterojunction programmable memory device according to claim 4, characterized in that: The charge transfer insulator includes TiO2, ZnO or HfO2 thin film.

6. The current-blocking heterojunction programmable memory device according to claim 4, characterized in that: The electrical insulator includes intrinsic SiC.

7. The current-blocking heterojunction programmable memory device according to claim 1, characterized in that: The blocking layer has a morphology of crystalline, polycrystalline or disordered; the blocking layer is a disordered HfO2 film, a disordered SiC film or a disordered silicon film.

8. The current-blocking heterojunction programmable memory device according to claim 1, characterized in that: The setting supporting materials include four types of supporting materials; Wherein, the first electrode is a P-type semiconductor or conductor, and the second electrode is an N-type semiconductor; Alternatively, the first electrode is a P-type Schottky metal, and the second electrode is an N+ semiconductor or conductor; Alternatively, the first electrode is an N+ semiconductor or conductor, and the second electrode is a P+ semiconductor; Alternatively, the first electrode is an N-type Schottky metal, and the second electrode is a P+ semiconductor or conductor.

9. The current-blocking heterojunction programmable memory device according to claim 8, characterized in that: The P-type Schottky metal is Au or Pt.

10. The current-blocking heterojunction programmable memory device according to claim 8, characterized in that: The N-type Schottky metal is Al.

Images