Semiconductor apparatus and manufacturing method therefor, and electronic device

Abstract

A semiconductor apparatus and a manufacturing method therefor, and an electronic device, which relate to apparatus design and manufacturing in the technical field of semiconductors. The semiconductor apparatus comprises: a plurality of storage units, wherein the plurality of storage units are distributed in a direction perpendicular to a substrate (1) and comprise a plurality of transistors and capacitors, which are distributed on different layers and are stacked in the direction perpendicular to the substrate (1); a word line (40), which penetrates through the different layers and extends in the direction perpendicular to the substrate (1), each transistor comprising a first source / drain electrode (51), a second source / drain electrode (52) and a semiconductor layer (23) surrounding a side wall of the word line (40); first insulating layers and electrically conductive layers which are alternately distributed in the direction perpendicular to the substrate (1); and at least one first hole (K1), which penetrates through the different layers. A second electrode (42) of each capacitor comprises an inner electrode provided in the first hole (K1), which is formed in a first electrode (41).

Description

Semiconductor device and manufacturing method thereof, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed on August 10, 2023, with application number 202311000832.9 and invention name “A semiconductor device, a manufacturing method thereof, and an electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0003] Semiconductor device storage can be divided into volatile memory and non-volatile memory based on application. The memory cells contained in these memories are often made smaller through structural design and process improvements. However, as the feature size of two-dimensional planar memory cells continues to shrink, the cost and difficulty of manufacturing these memories are also increasing.

[0004] The three-dimensional memory architecture can increase the density of memory cells in the vertical direction, which can solve the limitation of the density of memory cells in planar memory.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] An embodiment of the present disclosure provides a semiconductor device, comprising: a plurality of memory cells stacked perpendicular to a substrate, the plurality of memory cells comprising:

[0008] A plurality of transistors are distributed in different layers and stacked along a direction perpendicular to the substrate;

[0009] word lines, running through the different layers and extending in a direction perpendicular to the substrate;

[0010] a plurality of capacitors connected one-to-one with the plurality of transistors; the capacitors comprising a first electrode and a second electrode; the transistors comprising a first source / drain electrode, a second source / drain electrode, and a semiconductor layer surrounding the sidewalls of the word lines; the first source / drain electrode being connected to the first electrode of the corresponding capacitor;

[0011] First insulating layers and conductive layers are alternately distributed along a direction perpendicular to the substrate, each of the conductive layers comprising the first source / drain electrode, the second source / drain electrode, and the first electrode;

[0012] The first electrode region comprises at least one first hole penetrating through each of the first insulating layers and each of the conductive layers, wherein an inner wall of the first hole exposes the stacked conductive layer and the first insulating layer;

[0013] The second electrode includes an inner electrode arranged in the first hole and insulated from each first electrode. The inner electrode is distributed in the first hole and covers the area where each conductive layer is exposed on the inner wall of the first hole and the area where each first insulating layer is exposed on the inner wall of the first hole.

[0014] In some embodiments, the second pole further includes: an outer electrode, the outer sidewall of the first pole includes an end face of the first pole away from the first source / drain electrode and two side walls adjacent to the end face, and the outer electrode surrounds the end face and the two side walls of each of the first poles.

[0015] In some embodiments, the inner electrode includes a first connecting electrode filled in the first hole, and a first sub-electrode located between the first connecting electrode and the first electrode and distributed on the inner wall of the first hole.

[0016] In some embodiments, the first sub-electrodes of the capacitors are integrated ring electrodes, and the first connecting electrodes of the capacitors are integrated linear electrodes.

[0017] In some embodiments, the outer electrode includes a second sub-electrode extending along an outer sidewall of the first electrode, and a second connecting electrode located at the second sub-electrode away from the first electrode;

[0018] The plurality of second sub-electrodes of the plurality of capacitors are of an integrated structure, and the plurality of second connecting electrodes of the plurality of capacitors are of an integrated structure.

[0019] In some embodiments, the first sub-electrode and the second sub-electrode are connected only at the top of the stacked multiple memory cells to form an integrated structure, and the first connecting electrode and the second connecting electrode are connected only at the top of the stacked multiple memory cells to form an integrated structure.

[0020] In some embodiments, the semiconductor device includes multiple layers of the memory cells, each layer of the memory cells includes a memory cell array, the memory cell array includes multiple rows and columns of memory cells, the second connecting electrodes of multiple memory cells stacked in the same column and different layers are connected to form an integrated structure; the second sub-electrodes of multiple memory cells stacked in the same column and different layers are connected to form an integrated structure.

[0021] In some embodiments, the second connecting electrode of the integrated structure includes a first portion in the trench between two adjacent columns of memory cells in the row direction and a second portion extending into the trench between two adjacent memory cells in the column direction.

[0022] In some embodiments, the first electrode and the first source / drain electrode are an integral structure extending in a direction parallel to the substrate, the end face of the integral structure facing the word line is connected to the semiconductor layer, and the end face facing away from the word line is connected to the external electrode of the second electrode through a dielectric layer, and a solid structure with only the first hole is formed between the end face of the integral structure facing the word line and the end face facing away from the word line.

[0023] In some embodiments, the integrated structure formed by the first electrode of the capacitor and the first source / drain electrode extends along a first direction away from the second source / drain electrode, the area of ​​the first electrode includes a plurality of first holes, and the plurality of first holes are arranged along the first direction, and the inner electrodes in the plurality of first holes are electrically connected.

[0024] In some embodiments, on a plane parallel to the substrate, a cross-sectional shape of the first hole includes: a circle, an ellipse, or a square.

[0025] In some embodiments, the semiconductor device further includes: a second hole passing through each of the first insulating layer and the conductive layer, the word line is arranged in the second hole, the first pole, the first source / drain electrode, and the second source / drain electrode are arranged in the same layer, and the first source / drain electrode and the second source / drain electrode are disconnected at the second hole.

[0026] A method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate; a word line extending through the different layers and in a direction perpendicular to the substrate; a plurality of capacitors corresponding one-to-one to the plurality of transistors, the capacitors being connected to the corresponding transistors; the capacitors comprising a first electrode and a second electrode; the transistors comprising a first source / drain electrode, a second source / drain electrode, and a semiconductor layer surrounding the sidewalls of the word line, the first source / drain electrode being connected to the first electrode of the corresponding capacitor; the method for manufacturing the semiconductor device comprising:

[0027] forming a stack structure of alternately stacked first insulating layers and sacrificial layers on a substrate;

[0028] The stack structure is patterned to form a bit line region extending along a second direction and a plurality of memory cell regions extending along a first direction and spaced apart along the second direction; a trench extending along the first direction and penetrating the stack structure is provided between any two adjacent memory cell regions;

[0029] forming at least one first hole penetrating the stacked structure in the memory cell region and filling the first hole with a dummy electrode;

[0030] Performing lateral etching in the trench between any two adjacent memory cell regions to remove each sacrificial layer to expose a dummy electrode in a corresponding region;

[0031] Replacing the area where each removed sacrificial layer is located with a conductive layer, so that the first insulating layer and the conductive layer are alternately stacked, and the conductive layer surrounds the dummy electrode;

[0032] The dummy electrode is removed to expose the first hole, a dielectric layer of the capacitor is formed on a sidewall of the first hole, and an inner electrode of the second pole of the capacitor is formed in the first hole having the dielectric layer formed therein.

[0033] In some embodiments, a second hole is formed in the memory cell region near the bit line region, and the semiconductor layer, the gate insulating layer and the word line of the transistor are formed in the second hole;

[0034] Wherein, the first hole and the second hole are formed through a single patterning process.

[0035] In some embodiments, replacing the area where each sacrificial layer is removed with a conductive layer includes:

[0036] Depositing a conductive film, wherein the conductive film fills the area where the sacrificial layer is located and the trench;

[0037] removing the conductive film in the groove by dry etching to form the conductive layer;

[0038] Alternatively, a conductive film is deposited, wherein the conductive film fills the area where the sacrificial layer is located and covers the sidewalls and bottom wall of the trench;

[0039] The conductive film in the trench is removed by wet etching to form the conductive layer.

[0040] In some embodiments, the conductive layer includes a first electrode of the capacitor, and the method further includes: exposing an outer side wall of the first electrode, the outer side wall including an end face of the first electrode away from the bit line region and two side walls adjacent to the end face, an external electrode of the second electrode of the end face of the first electrode and the two side walls, and forming a dielectric layer arranged between the outer side wall of the first electrode and the external electrode.

[0041] In some embodiments, the method further includes forming a trench extending along the second direction and penetrating the stacked structure between two adjacent columns of the memory cell regions;

[0042] While forming the dielectric layer of the capacitor on the sidewall of the first hole, depositing the dielectric layer in the trench between the two adjacent columns of the memory cell areas through a single process;

[0043] At the same time as forming the inner electrode of the second electrode on the sidewall of the first hole, depositing the outer electrode of the second electrode in the trench between the two adjacent columns of the memory cell areas through a single process;

[0044] The inner electrode and the outer electrode are an integrated structure.

[0045] An embodiment of the present application further provides a semiconductor device, comprising:

[0046] A memory cell array stacked vertically in the substrate direction and periodically distributed;

[0047] Each memory cell region includes transistors and capacitors sequentially distributed in a first direction;

[0048] The region of the transistor includes a word line hole penetrating each memory cell;

[0049] Also included are conductive layers and first insulating layers alternately stacked;

[0050] A connected trench is included between the memory cells adjacent in the first direction and the second direction, wherein the trench exposes the outer sidewalls of the conductive layer and the first insulating layer;

[0051] The capacitor area also includes at least one first hole that penetrates each of the conductive layers and the first insulating layer, and the first hole exposes the inner side walls of the conductive layer and the first insulating layer; the conductive layer in the capacitor area is annular and adjacent conductive layers are separated by the first insulating layer.

[0052] In some embodiments, the annular conductive layer extends to the word line hole;

[0053] The invention also includes a semiconductor layer located in the word line hole, wherein the semiconductor layer is in contact with the conductive layer.

[0054] In some embodiments, the annular conductive layer is the first pole of the capacitor and further includes a dielectric layer distributed in the first hole and extending only from the topmost storage unit to the groove; and a second pole of the capacitor distributed in the first hole and extending only from the topmost storage unit to the groove.

[0055] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments, or a semiconductor device manufactured by the semiconductor device manufacturing method described in any of the above embodiments.

[0056] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0057] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0058] Summary of the Figures

[0059] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation to the technical solution.

[0060] FIG1A is a schematic plan view of a semiconductor device provided by an exemplary embodiment (a cross-sectional view of a film layer where a conductive layer is located); FIG1B is a cross-sectional view taken along the aa' direction in FIG1A; and FIG1C is a cross-sectional view taken along the bb' direction in FIG1A;

[0061] FIG2A is a schematic plan view of a substrate provided by an exemplary embodiment; FIG2B is a cross-sectional view along a direction parallel to the substrate after a stacked structure is formed provided by an exemplary embodiment;

[0062] FIG3 is a cross-sectional view of the film layer where the sacrificial layer is located along a direction parallel to the substrate after a preset pattern is formed, provided by an exemplary embodiment;

[0063] FIG4 is a cross-sectional view of the film layer where the sacrificial layer is located along a direction parallel to the substrate after forming the first hole and the second hole, provided by an exemplary embodiment;

[0064] FIG5 is a cross-sectional view of the film layer where the sacrificial layer is located along a direction parallel to the substrate after forming a dummy electrode, provided by an exemplary embodiment;

[0065] FIG6 is a cross-sectional view of a film layer where a conductive layer is located, along a direction parallel to the substrate, after the conductive layer is formed, provided by an exemplary embodiment;

[0066] FIG7 is a cross-sectional view of the film layer where the conductive layer is located along a direction parallel to the substrate after the dummy electrode in the first hole is removed, provided by an exemplary embodiment;

[0067] FIG8A is a cross-sectional view along a direction parallel to the substrate (the film layer where the conductive layer is located) after forming a dielectric layer, a second electrode, and a fifth insulating layer, according to an exemplary embodiment; FIG8B is a cross-sectional view along the aa' direction after forming a dielectric layer, a second electrode, and a fifth insulating layer, according to an exemplary embodiment;

[0068] 9A is a cross-sectional view of a film layer where a conductive layer is located after forming a second trench, provided by an exemplary embodiment, along a direction parallel to the substrate; FIG. 9B is a cross-sectional view along the bb' direction in FIG. 9A ;

[0069] FIG10A is a cross-sectional view of a film layer where a conductive layer is located after etching the conductive layer according to an exemplary embodiment, along a direction parallel to the substrate; FIG10B is a cross-sectional view along the bb' direction in FIG10A;

[0070] FIG11A is a cross-sectional view of a film layer where a conductive layer is located after a barrier layer is formed, provided by an exemplary embodiment, along a direction parallel to the substrate; FIG11B is a cross-sectional view along the bb' direction in FIG11A;

[0071] 12A is a cross-sectional view of a film layer where a conductive layer is located after forming a fourth insulating layer, provided by an exemplary embodiment, along a direction parallel to the substrate; FIG. 12B is a cross-sectional view along the bb' direction in FIG. 12A ;

[0072] FIG13A is a cross-sectional view of a film layer where a conductive layer is located after removing a dummy electrode provided by an exemplary embodiment along a direction parallel to the substrate; FIG13B is a cross-sectional view along the bb' direction in FIG13A;

[0073] FIG14A is a cross-sectional view of a film layer where a conductive layer is located after etching a first insulating layer, provided by an exemplary embodiment, along a direction parallel to the substrate; FIG14B is a cross-sectional view along the aa' direction in FIG14A; and FIG14C is a cross-sectional view along the bb' direction in FIG14A;

[0074] FIG15A is a cross-sectional view along a direction parallel to the substrate (the film layer where the conductive layer is located) after forming a semiconductor layer, a gate insulating layer, and a word line according to an exemplary embodiment; FIG15B is a cross-sectional view along the aa' direction in FIG15A; and FIG15C is a cross-sectional view along the bb' direction in FIG15A;

[0075] FIG16A is a cross-sectional view of an exemplary embodiment of an exposed semiconductor layer along a direction parallel to the substrate (the film layer where the conductive layer is located); FIG16B is a cross-sectional view along the bb' direction in FIG16A;

[0076] FIG17A is a cross-sectional view of an exemplary embodiment of an exposed semiconductor layer (a film layer where a conductive layer is located) taken along a direction parallel to the substrate; FIG17B is a cross-sectional view taken along the aa' direction in FIG17A; and FIG17C is a cross-sectional view taken along the bb' direction in FIG17A;

[0077] FIG18A is a cross-sectional view along a direction parallel to the substrate after etching a semiconductor layer (the film layer where the conductive layer is located) according to an exemplary embodiment; FIG18B is a cross-sectional view along the aa' direction in FIG18A; and FIG18C is a cross-sectional view along the bb' direction in FIG18A;

[0078] FIG19A is a cross-sectional view along a direction parallel to the substrate after lateral etching of a conductive layer provided by an exemplary embodiment (the film layer where the conductive layer is located); FIG19B is a cross-sectional view along the aa' direction in FIG19A; FIG19C is a cross-sectional view along the bb' direction in FIG19A;

[0079] FIG20A is a cross-sectional view along a direction parallel to the substrate after forming a contact layer (the film layer where the conductive layer is located) provided by an exemplary embodiment; FIG20B is a cross-sectional view along the aa' direction in FIG20A; FIG20C is a cross-sectional view along the bb' direction in FIG20A;

[0080] FIG21A is a cross-sectional view taken along a direction parallel to the substrate after etching a portion of the contact layer (the film layer where the conductive layer is located) according to an exemplary embodiment; FIG21B is a cross-sectional view taken along the aa' direction in FIG21A; and FIG21C is a cross-sectional view taken along the bb' direction in FIG21A;

[0081] FIG22A is a cross-sectional view of a film layer where a conductive layer is located after etching a first insulating layer, provided by an exemplary embodiment, along a direction parallel to the substrate; FIG22B is a cross-sectional view along the aa' direction in FIG22A; and FIG22C is a cross-sectional view along the bb' direction in FIG22A;

[0082] FIG23A is a cross-sectional view along a direction parallel to the substrate (the film layer where the conductive layer is located) after forming a semiconductor layer, a gate insulating layer, and a word line according to an exemplary embodiment; FIG23B is a cross-sectional view along the aa' direction in FIG23A; and FIG23C is a cross-sectional view along the bb' direction in FIG23A;

[0083] FIG24A is a cross-sectional view of an exemplary embodiment of an exposed semiconductor layer (the film layer where the conductive layer is located) taken along a direction parallel to the substrate; FIG24B is a cross-sectional view taken along the aa' direction in FIG24A; and FIG24C is a cross-sectional view taken along the bb' direction in FIG24A;

[0084] FIG25A is a cross-sectional view of an exemplary embodiment of an exposed semiconductor layer (the film layer where the conductive layer 12 is located) taken along a direction parallel to the substrate; FIG25B is a cross-sectional view taken along the aa' direction in FIG25A; and FIG25C is a cross-sectional view taken along the bb' direction in FIG25A;

[0085] 26A is a cross-sectional view parallel to the substrate after etching the semiconductor layer (the film layer where the conductive layer is located); FIG26B is a cross-sectional view along the aa' direction in FIG26A; and FIG26C is a cross-sectional view along the bb' direction in FIG26A.

[0086] Details

[0087] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0088] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0089] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0090] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0091] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0092] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to physical or signal connections, contact connections, or integral connections. They can be direct connections, indirect connections through intermediaries, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0093] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0094] In the present disclosure, the first source / drain electrode may be the drain electrode and the second source / drain electrode may be the source electrode, or the first source / drain electrode may be the source electrode and the second source / drain electrode may be the drain electrode. The functions of the "source electrode" and "drain electrode" may be reversed when transistors with opposite polarity are used or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0095] In this disclosure, "connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0096] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0097] The phrase "A and B disposed in the same layer" in this disclosure encompasses layers formed of the same material or different materials located on the same film layer. For example, A and B are formed by forming the same film layer from the same material and then undergoing the same patterning process or different patterning processes. A and B disposed in the same layer can be located on the same horizontal plane, but not necessarily on the same film layer, or located in different regions of the same film layer, but not necessarily on the same horizontal plane.

[0098] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0099] In the embodiment of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A.

[0100] Figure 1A is a schematic plan view of a semiconductor device according to an exemplary embodiment; Figure 1B is a cross-sectional view taken along the aa' direction in Figure 1A; and Figure 1C is a cross-sectional view taken along the bb' direction in Figure 1A. The semiconductor device may be a transistor, a memory cell including a transistor, a memory cell array including a memory cell, a 3D stacked structure including a memory cell array, or a memory device including a transistor or a memory cell array.

[0101] As shown in FIG. 1A , FIG. 1B , and FIG. 1C , an embodiment of the present disclosure provides a semiconductor device, which may include: a plurality of memory cells stacked in a direction perpendicular to a substrate 1 , wherein the plurality of memory cells may include:

[0102] Multiple transistors, corresponding one to one with the multiple memory cells, the multiple transistors are distributed in different layers and stacked along a direction perpendicular to the substrate 1. It can be understood that the multiple transistors are stacked in a vertical column in the direction perpendicular to the substrate 1 and are insulated from each other in the direction perpendicular to the substrate 1;

[0103] A word line 40 connected to the plurality of transistors, passing through the transistors of different layers and extending in a direction perpendicular to the substrate 1;

[0104] A plurality of capacitors corresponding one-to-one to the plurality of transistors, the capacitors being connected to the corresponding transistors, forming a 1T1C memory cell in some embodiments; the capacitors comprising a first electrode 41 and a second electrode 42 separated by a dielectric layer 43; the transistors comprising a first source / drain electrode 51 and a second source / drain electrode 52 separated from each other, and a semiconductor layer 23 surrounding the sidewalls of the word line 40; the first source / drain electrode 51 being electrically connected to the first electrode 41 of the corresponding capacitor;

[0105] The first insulating layer and the conductive layer are alternately distributed in a direction perpendicular to the substrate 1, and the region of the first pole 41 includes at least one first hole K1 penetrating each of the stacked first insulating layers and each of the stacked conductive layers, and the inner wall of the first hole only exposes the stacked conductive layer and the first insulating layer; wherein the conductive layer can be replaced by a sacrificial layer; the sacrificial layer before replacement and the first insulating layer are alternately stacked and distributed.

[0106] The capacitor and the transistor of each memory cell are arranged sequentially in a first direction;

[0107] The first hole may be one, two or more. In some embodiments, the first holes are two or more, and different first holes are sequentially spaced apart in the first direction.

[0108] The first electrode 41, the first source / drain electrode 51 and the second source / drain electrode 52 included in a storage unit are arranged on the conductive layer. It can be understood that the conductive layer includes the first electrode 41, the first source / drain electrode 51 and the second source / drain electrode 52 in different regions after a patterning process; the first electrode 41 and the first source / drain electrode 51 are not disconnected to form an integrated structure, and the first electrode has an opening formed by a first hole, and each first hole corresponds to an opening; in some embodiments, there is one opening on the first electrode, and the first insulating layer between the first electrode and the adjacent first electrode is annular.

[0109] In the embodiment of the present application, the stacked first electrodes have the same shape, and the stacked first insulating layers have the same shape as the first electrodes and completely overlap (their projections on the substrate completely overlap).

[0110] In some embodiments, the transistor region includes a word line hole (second hole K2) penetrating each memory cell;

[0111] Based on the above-mentioned alternating stacking of conductive layers and first insulating layers; the storage cells adjacent in the first direction and the second direction contain connected grooves, and the grooves expose the outer side walls of the conductive layer and the first insulating layer; the outer side walls of each conductive layer or each first insulating layer exposed through the grooves include an end in the first direction and two side walls in the second direction.

[0112] The capacitor region further includes at least one first hole penetrating through each of the conductive layers and the first insulating layer, wherein the first hole exposes inner sidewalls of the conductive layer and the first insulating layer; adjacent conductive layers in the capacitor region are separated by the first insulating layer.

[0113] The second electrode 42 may include an internal electrode disposed within the first hole K1 and insulated from the first electrode 41. In a plane perpendicular to the substrate 1, the internal electrode extends to the first electrode 41 of each layer of the memory cell and at least surrounds the sidewalls of the first hole K1. Alternatively, the internal electrode may fill various regions of the first hole K1. The internal electrode is distributed within the first hole K1, covering each region of the conductive layer exposed on the inner wall of the first hole K1 and each region of the first insulating layer exposed on the inner wall of the first hole K1. In some embodiments, the internal electrode filling each region of the first hole K1 may include a first sub-electrode surrounding the sidewalls of the first hole K1 and a first connecting electrode filling the first hole K1. The first connecting electrode contacts the region of the first sub-electrode facing away from the sidewalls of the first hole K1. The first sub-electrode and the first connecting electrode may be made of different materials. The first connecting electrode may be used to connect the first sub-electrode to a reference signal terminal, or the first connecting electrode may be used to connect to the external electrode of the second electrode.

[0114] It can be understood that the first hole K1 is a through-hole on a solid structure facing the substrate 1. The through-hole of the first electrode 41 exposes the inner sidewall of the first electrode 41, on which the dielectric layer 43 of the capacitor and the second electrode 42 of the capacitor are formed. The inner electrode of the second electrode 42 can be a film layer extending along the hole wall of the first hole K1. In some embodiments, the hole wall of the first hole K1 is perpendicular to the substrate 1. The inner electrode of the second electrode 42 can be an annular film layer extending perpendicular to the substrate 1, or a solid structure filling the first hole K1, or both an annular film layer and a solid structure, wherein the annular film layer and the solid structure are both made of conductive materials and in contact.

[0115] In the solution provided by this embodiment, the second electrode of the capacitor is disposed in a first hole penetrating the first electrode, which can reduce the area occupied by the capacitor, thereby reducing the area of ​​the semiconductor device and improving the density of the semiconductor device.

[0116] In some embodiments, the memory cell of the semiconductor device may further include: a second hole K2 penetrating each first insulating layer and each first source / drain electrode 51, the second hole K2 being a word line hole, and the second hole K2 may include a first sub-hole located in the first insulating layer and a second sub-hole located in the conductive layer;

[0117] The word line 40 and the multiple semiconductor layers 23 are arranged in the second hole K2, and the second sub-hole of the second hole K2 located in the conductive layer can fall into the orthographic projection of the first sub-hole of the second hole K2 located in the first insulating layer on the substrate 1; the multiple semiconductor layers 23 of the multiple transistors are arranged at intervals.

[0118] Among them, the multiple semiconductor layers 23 of the multiple transistors are arranged at intervals, which means that the multiple semiconductor layers 23 of the multiple transistors are physically disconnected, thereby eliminating the parasitic MOS tubes (which can be understood as parasitic transistors) between the transistors in adjacent layers. In the semiconductor device provided by this embodiment, since the apertures of the second hole K2 in the conductive layer and the first insulating layer are different, and the aperture of the first insulating layer is larger, the parasitic channel can be removed from the outside of the second hole K2 when manufacturing the semiconductor device. Compared with removing the parasitic channel from the inside of the second hole K2, the process is simpler and less likely to damage the channel of the transistor, thereby improving the device performance. However, the embodiments of the present disclosure are not limited to this. The orthographic projection of the first sub-hole on the substrate 1 can fall within the orthographic projection of the second sub-hole on the substrate 1, so that the parasitic channel can be removed on the inside of the second hole K2.

[0119] In some embodiments, the first hole K1 and the second hole K2 penetrate each conductive layer and the first insulating layer between the conductive layers, and the first insulating layer below the bottommost conductive layer may not penetrate.

[0120] The first pole 41 may include a top and a bottom approximately parallel to the substrate 1, and an outer sidewall between the top and the bottom. The first pole 41 extends in a direction parallel to the substrate 1 and has an end surface, and the outer sidewall includes the end surface.

[0121] In some embodiments, the surface of the outer sidewall extends in a direction perpendicular to the substrate 1. In other embodiments, the outer sidewall does not have to be perpendicular to the substrate 1, and may not be perpendicular to the substrate 1 as long as it is located between the top and the bottom.

[0122] In some embodiments, the second pole 42 in the stacked structure may only include the inner electrode, that is, only include the electrode located in the first hole K1.

[0123] In some embodiments, the second electrode 42 in the stacked structure may include, in addition to the electrode located within the first hole K1, an electrode located on the outer wall of the first electrode 41. The electrode located within the hole of the first electrode 41 and the electrode located on the outer wall together form the second electrode 42 insulated from the first electrode 41, and the second electrode 42 may be connected to a reference signal terminal.

[0124] 1A, 1B, and 1C, the second electrode 42 may further include an external electrode extending in a direction perpendicular to the substrate 1 and along the outer sidewalls of the first electrode 41 and the outer sidewalls of the first insulating layer, and insulated from the first electrode 41. The external electrode in the horizontal direction (parallel to the substrate 1) is electrically connected to the internal electrode. The outer sidewalls of the first electrode 41 include a first end surface of the first electrode 41 away from the first source / drain electrode 51 (or word line 40) and two first sidewalls adjacent to the first end surface. The first end surface and the two first sidewalls extend perpendicular to the substrate 1. The external electrode may surround the first end surface and the two first sidewalls of each first electrode 41. The outer sidewalls of the first insulating layer may include a second end surface away from the first source / drain electrode 51 (or word line 40) and two second sidewalls adjacent to the second end surface. The second end surface and the two second sidewalls extend perpendicular to the substrate 1. The external electrode may surround the second end surface and the two second sidewalls of each first insulating layer.

[0125] The external electrode can wrap around the first end face of the first electrode 41 away from the word line 40 and the two first sidewalls adjacent to the first end face and extending perpendicular to the substrate 1. That is, the second electrode 42 comprises two parts: one part is disposed within the first hole K1, and the other part is disposed on the surface of the first electrode 41, wrapping around three sidewalls of the first electrode 41 (one of which is referred to as the first end face). Compared to capacitors comprising only external electrodes, the solution provided in this embodiment allows the capacitor to include both internal and external electrodes, maximizing capacitance for a given capacitor length. Furthermore, a first insulating layer is disposed between adjacent first electrodes 41 in a direction perpendicular to the substrate 1. Therefore, the external electrode also wraps around one end face and two sidewalls adjacent to the end face of the first insulating layer, while the internal electrode is disposed within the first hole K1. In the conductive layer, the internal and external electrodes are separated by the first electrode 41 and are not connected to each other. In the first insulating layer, the internal and external electrodes are separated by the first insulating layer and are not connected to each other. That is, between adjacent first electrodes 41 in a direction perpendicular to the substrate 1, the external and internal electrodes are separated from each other. In the solution provided in this embodiment, during the manufacturing process, the first insulating layer can support the first pole 41 stacked in a direction perpendicular to the substrate 1 without the need for an additional supporting structure, thereby simplifying the process and reducing the difficulty of the process.

[0126] In some embodiments, the inner electrode may extend in a direction perpendicular to the substrate 1 to cover various areas of the inner wall of the first hole K1 .

[0127] In some embodiments, the inner electrode may fill the first hole K1 until the first hole K1 is filled.

[0128] In some embodiments, the inner electrodes of the capacitors of the memory cells along the same vertical column stacked perpendicular to the substrate 1 may be connected to form an integral structure.

[0129] In some embodiments, the external electrodes of the capacitors of the memory cells stacked in the same vertical column perpendicular to the substrate 1 can be fabricated by atomic layer deposition and connected to form an integrated structure.

[0130] In some embodiments, the inner electrode and the outer electrode may be a double-layer structure, that is, the inner electrode may include a first sub-electrode and a first connecting electrode, and the first sub-electrode is arranged between the dielectric layer 43 and the first connecting electrode; the outer electrode may include a second sub-electrode and a second connecting electrode, and the second sub-electrode is arranged between the dielectric layer 43 and the second connecting electrode. The first sub-electrode isolates the dielectric layer 43 and the first connecting electrode (that is, the first connecting electrode does not contact the dielectric layer 43), and the second sub-electrode isolates the dielectric layer 43 and the second connecting electrode (that is, the second sub-electrode does not contact the dielectric layer 43). The second sub-electrode and the second connecting electrode may be different materials, and the second connecting electrode is used to connect the second sub-electrode to the reference signal terminal, or the second connecting electrode is used to connect to the first connecting electrode. The first sub-electrode and the second sub-electrode may be metals or metal nitrides, such as TiN and other materials suitable for capacitor electrodes, and the first connecting electrode and the second connecting electrode may be conductive materials such as polysilicon with lower resistance than the second sub-electrode.

[0131] In some embodiments, the first connecting electrode fills the first hole K1, the first sub-electrode is located between the first connecting electrode and the first electrode and distributed on the inner wall of the first hole K1, and the first sub-electrode surrounds the side wall of the first hole K1, and the first connecting electrode and the first sub-electrode are in contact with the area on the side of the side wall facing away from the first hole K1.

[0132] In some embodiments, the first sub-electrode may be a ring-shaped electrode extending in a direction perpendicular to the substrate 1 , and the first connecting electrode may be a linear electrode extending in a direction perpendicular to the substrate 1 .

[0133] In some embodiments, the second sub-electrode may extend along an outer sidewall of the first electrode 41 .

[0134] In some embodiments, the integrated structure formed by connecting the first sub-electrode and the second sub-electrode of the same capacitor is referred to as a first sub-layer 421, and the integrated structure formed by connecting the first connecting electrode and the second connecting electrode of the same capacitor is referred to as a second sub-layer 422. That is, the second electrode 42 may include a first sub-layer 421 and a second sub-layer 422. The first sub-layer 421 is disposed between the second sub-layer 422 and the dielectric layer 43, isolating the second sub-layer 422 from the dielectric layer 43, with portions of the first sub-layer 421 and the second sub-layer 422 forming the inner electrode, and portions of the first sub-layer 421 and the second sub-layer 422 forming the outer electrode.

[0135] In some embodiments, the semiconductor device may include a multi-layer memory cell array distributed in a direction perpendicular to the substrate 1, and each layer of the memory cell array includes multiple rows and columns of memory cells distributed in a first direction X and a second direction Y, respectively (the columns here are horizontal columns, as distinguished from the aforementioned vertical columns. A vertical column includes a column of memory cells distributed at the same position on different layers. In the subsequent description, those not specified as vertical columns refer to horizontal columns). Among the memory cells in the same layer, a group of memory cells distributed along the first direction X is referred to as a row of memory cells, and a group of memory cells distributed along the second direction Y is referred to as a column of memory cells. The second connection electrodes of the capacitors of the multiple memory cells in the same column and stacked on different layers are connected to form an integrated structure, and the second sub-electrodes of the capacitors of the multiple memory cells in the same column and stacked on different layers are connected to form an integrated structure.

[0136] In some embodiments, the integrated second connection electrode may include a first portion within the trench between two adjacent columns of memory cells in the row direction (i.e., the first direction X) and a second portion extending into the trench between two adjacent memory cells in the column direction (i.e., the second direction Y). The second connection electrode may provide support for the semiconductor device, eliminating the need for an additional support film layer.

[0137] In some embodiments, the inner electrode and the outer electrode may be connected only at the top of the stacked memory cells (ie, the side of the stacked memory cells away from the substrate 1 ).

[0138] In some embodiments, the inner electrode and the outer electrode are connected on a side of the stacked plurality of transistors away from the substrate 1 to form a planar film layer extending parallel to the substrate 1, and the orthographic projections of the word line 40, the semiconductor layer 23, and the second source / drain electrode 52 on the substrate 1 are located outside the orthographic projection of the planar film layer on the substrate 1. In the process of manufacturing semiconductor devices, capacitors are typically fabricated first, followed by word lines, semiconductor layers, etc. After the capacitors are fabricated, the areas where the word lines, semiconductor layers, etc. are located need to be exposed to facilitate subsequent fabrication of the word lines, semiconductor layers, etc.

[0139] In some embodiments, the first sub-electrode and the second sub-electrode of the same capacitor can be connected only at the top of the stacked multiple storage cells to form an integrated structure, and the first connecting electrode and the second connecting electrode of the same capacitor can be connected only at the top of the stacked multiple storage cells to form an integrated structure.

[0140] In some embodiments, the first electrode 41 and the first source / drain electrode 51 can be connected to form an integrated structure, or the two can share a single electrode, which can be a conductive wire extending laterally in a direction parallel to the substrate 1, for example, along the first direction X. The end surface of the integrated structure facing the word line 40 is connected to the semiconductor layer 23, and the end surface facing away from the word line 40 is connected to the external electrode of the second electrode 42 through the dielectric layer 43. A solid structure having only the first hole K1 is formed between the end surface of the integrated structure facing the word line 40 and the end surface facing away from the word line 40. That is, the integrated structure is a solid structure except for the area where the first hole K1 is located. Along the direction parallel to the substrate 1, the solid structure includes two ends: one end is connected to the semiconductor layer 23, and the other end is surrounded by the external electrode 42.

[0141] In some embodiments, the first source / drain electrode 51 and the second source / drain electrode 52 can be located in the same conductive film layer and isolated from each other in a direction perpendicular to the substrate 1. This can be understood as the first source / drain electrode 51 and the second source / drain electrode 52 being patterned from the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate 1. However, the disclosed embodiments are not limited thereto; the first source / drain electrode 51 and the second source / drain electrode 52 can be located in different conductive film layers.

[0142] In some embodiments, the transistor may further include a gate electrode 26. The gate electrode 26 of transistors in different layers may be a portion of the word line 40. It is understood that before or after the word line 40 is formed, it is not necessary to separately form the gate electrode 26. After the word line 40 is formed, a portion of the word line 40 functions as the gate electrode 26.

[0143] In some embodiments, the sidewall of the second hole K2 may include a second sidewall located in the second sub-hole, where the first sidewall of the first sub-hole connects to the first sidewall. The first sidewall forms a groove relative to the second sidewall, and the groove includes a sub-sidewall extending in a direction perpendicular to the substrate 1. The semiconductor layer 23 extends continuously on the second sidewall and from the second sidewall to the sub-sidewall of the groove extending in a direction perpendicular to the substrate 1. The semiconductor layer 23 is not distributed on the sub-sidewall, so that the multiple semiconductor layers 23 are disconnected at the sub-sidewall. That is, the cross-section of the semiconductor layer 23 in the direction perpendicular to the substrate 1 may be two U-shaped structures distributed on both sides of the wordline 40, with the opening direction of the U-shaped structure facing away from the wordline 40.

[0144] In some embodiments, the semiconductor layer 23 may include a first groove 231 opening toward the first source / drain electrode 51 and a second groove 232 opening toward the second source / drain electrode 52. The first source / drain electrode 51 fills the first groove 231, and the second source / drain electrode 52 fills the second groove 232. In the solution provided by this embodiment, the semiconductor layer 23 may contact the top surface, bottom surface, and sidewalls of the first and second source / drain electrodes 51, 52. Compared to a solution in which the semiconductor layer 23 only contacts the sidewalls of the first and second source / drain electrodes 51, 52, this increases the contact area and reduces the contact resistance between the first and second source / drain electrodes 51, 52, and the semiconductor layer 23. The first groove 231 and the second groove 232 may be two separate grooves. Alternatively, when the semiconductor layer 23 forms a continuous annular groove surrounding the word line 40, the first groove 231 may be the groove formed by the region where the annular groove contacts the first source / drain electrode 51, and the second groove 232 may be the groove formed by the region where the surrounding groove contacts the second source / drain electrode 52.

[0145] In some embodiments, as shown in Figures 26A, 26B, and 26C, the semiconductor layer 23 may include a first groove 231 opening toward the first source / drain electrode 51 and a second groove 232 opening toward the second source / drain electrode 52. The first source / drain electrode 51 fills the first groove 231, and the second source / drain electrode 52 fills the second groove 232. A contact layer 6 is provided between the sidewall of the first source / drain electrode 51 facing the word line 40 and the semiconductor layer 23, and between the sidewall of the second source / drain electrode 52 facing the word line 40 and the semiconductor layer 23. A material may be selected such that the contact resistance between the contact layer 6 and the semiconductor layer 23 is lower than the contact resistance when the semiconductor layer 23 is in direct contact with the first source / drain electrode 51 and the second source / drain electrode 52, thereby reducing the contact resistance between the semiconductor layer 23 and the first source / drain electrode 51 and the second source / drain electrode 52.

[0146] In some embodiments, the semiconductor layer 23 may further include a third groove 233 and a fourth groove 234, the openings of which are oriented away from the word line 40 and the first source / drain electrode 51. The third groove 233 and the fourth groove 234 are disposed opposite each other and have openings in opposite directions. The semiconductor device may further include a barrier layer 7 filling the third groove 233 and the fourth groove 234. The third groove 233 and the fourth groove 234 may be two separate grooves. Alternatively, when the semiconductor layer 23 forms a continuous annular groove surrounding the word line 40, the barrier layer 7 may include two separate portions. The third groove 233 may be a groove formed by the region where the annular groove contacts one portion of the barrier layer 7, and the fourth groove 234 may be a groove formed by the region where the surrounding groove contacts another portion of the barrier layer 7.

[0147] In some embodiments, the barrier layer 7 may be disposed only in the third groove 233 and the fourth groove 234 .

[0148] In some embodiments, the barrier layer 7 may be connected to the first source / drain electrode 51 and the second source / drain electrode 52 .

[0149] In some embodiments, the barrier layers 7 in the third groove 233 and the fourth groove 234 of the semiconductor layer 23 of transistors filled in different layers are spaced apart from each other, that is, the barrier layers 7 in the third groove 233 and the fourth groove 234 of the semiconductor layer 23 of transistors filled in different layers are physically disconnected.

[0150] In some embodiments, the region of the first pole 41 may include a plurality of first holes K1 (i.e., a plurality of first holes K1 are provided on one first pole 41), and the plurality of first holes K1 may be arranged along the extension direction of the integrated structure formed by the first pole 41 and the first source / drain electrode 51, such as along the first direction X. However, the embodiments of the present disclosure are not limited thereto, and the plurality of first holes K1 may be arranged in other ways. A second pole 42 insulated from the first pole 41 is provided in each first hole K1, and the second pole 42 in the first hole K1 is an inner electrode. The plurality of inner electrodes in different first holes K1 are electrically connected, for example, they may be electrically connected through the top ends of the inner electrodes.

[0151] In some embodiments, on a plane parallel to the substrate 1 , the cross-sectional shape of the first hole K1 includes but is not limited to: circular, elliptical, or square.

[0152] In some embodiments, in a direction parallel to the substrate 1 , the shapes of the first hole K1 in a first cross section of the sub-hole in the conductive layer and in a second cross section of the sub-hole in the first insulating layer may be the same.

[0153] In some embodiments, the first cross section and the second cross section may have the same size. That is, the first hole can be formed by etching in one go without expanding the first hole in the first insulating layer or the conductive layer, thus simplifying the process.

[0154] In some embodiments, the transistor may further include: a gate insulating layer 24 disposed between the word line 40 and the semiconductor layer 23;

[0155] The word line 40, the gate insulating layer 24 surrounding the sidewall of the word line 40, and the plurality of semiconductor layers 23 surrounding different regions of the sidewall of the gate insulating layer 24 are sequentially distributed in the second hole K2 from the inside to the outside;

[0156] The gate insulating layers 24 of multiple transistors at different layers may be connected to form an integrated structure, but the embodiments of the present disclosure are not limited thereto, and the gate insulating layers 24 of multiple transistors at different layers may be disconnected.

[0157] In some embodiments, the aperture of the first sub-hole along the extension direction parallel to the first source / drain electrode 51 may be larger than the aperture of the first sub-hole along the extension direction perpendicular to the first source / drain electrode 51 .

[0158] As shown in Figure 1A , memory cells in the same layer form a memory cell array distributed along a first direction X and a second direction Y, respectively. Each layer may further include a bit line 30 connected to the second source / drain electrodes 52 of transistors in the same column within the layer. Figure 1A illustrates that each layer includes three rows and two columns of memory cells, but the disclosed embodiments are not limited thereto. Each layer may include memory cells in other numbers of rows and columns, for example, only one memory cell. The aa' direction may be parallel to the first direction X, and the bb' direction may be parallel to the second direction Y.

[0159] In some embodiments, the second source / drain electrodes 52 of the transistors of the memory cells in two adjacent columns may be connected to the same bit line 30 .

[0160] In some embodiments, the second source / drain electrode 52 of the transistor may be a portion of a bit line 30 connected to the second source / drain electrode 52. For example, the bit line 30 is a straight line, and a sidewall of the straight line is connected to the semiconductor layer 23. Alternatively, the bit line 30 has an integrally designed branch, and the branch is connected to the semiconductor layer 23, wherein an extension direction of the branch intersects with an extension direction of the bit line 30, such as being approximately perpendicular.

[0161] The branches may be multiple branches on one sidewall of the bit line 30 , or multiple branches on both sidewalls at the same time, and each branch may form a transistor or a memory cell.

[0162] In some embodiments, the bit lines 30 may extend along the second direction Y.

[0163] In some embodiments, the first source / drain electrode 51 may extend along a first direction X.

[0164] In some embodiments, the first electrode 41, the first source / drain electrode 51, and the second source / drain electrode 52 can be disposed on the same layer, and the first source / drain electrode 51 and the second source / drain electrode 52 can be disconnected at the second hole K2. That is, the first electrode 41, the first source / drain electrode 51, and the second source / drain electrode 52 can be formed through a single patterning process. The same-layer arrangement here can be understood as film layers formed from the same conductive layer through a patterning process. A single patterning process can at least be understood as using a single mask to simultaneously form different patterns.

[0165] The technical solution of this embodiment will be further illustrated below using the manufacturing process of the semiconductor device of this embodiment. The "patterning process" referred to in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without specific limitations here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film of a certain material formed on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, the "thin film" before patterning is referred to as a "thin film" and the "layer" after patterning is referred to as a "layer." The "layer" after patterning or photolithography contains at least one "pattern."

[0166] In an exemplary embodiment, a process for manufacturing the semiconductor device may include:

[0167] 101) A first insulating film and a sacrificial layer film are alternately deposited on a substrate 1 to form a plurality of stacked structures. Figure 2A is a schematic plan view of the substrate 1, and Figure 2B is a cross-sectional view of the stacked structure along a direction perpendicular to the substrate. As shown in Figure 2A, the substrate 1 may include a transistor region 100 and two capacitor regions 200 disposed on either side of the transistor region 100, with the plurality of stacked structures disposed on the transistor region 100 and the capacitor regions 200. As shown in Figure 2B, the stacked structure may include a stack of alternating first insulating layers 9 and sacrificial layers 11.

[0168] In some embodiments, the substrate 1 can be understood as a supporting structure, which can be a silicon substrate, or a substrate containing logic circuits or other types of circuits.

[0169] In some embodiments, the first insulating film may be a low-K dielectric layer, ie, a dielectric layer with a dielectric constant not greater than 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the multiple first insulating layers 9 may be the same or different.

[0170] In some embodiments, the sacrificial layer includes a film layer with a relatively large etching selectivity compared to the first insulating film, including but not limited to SiN (silicon nitride). In this embodiment, no conductive film is deposited during the manufacture of the stacked structure. When etching the stacked structure in the subsequent process, a smooth vertical surface can be formed more easily than etching a stacked structure formed by etching both insulating and conductive films, thereby improving control of the device structure and achieving more stable device performance.

[0171] In some embodiments, the first insulating film and the sacrificial layer film may be deposited using a chemical vapor deposition method.

[0172] The stacked structure shown in FIG. 2B includes four first insulating layers 9 and three sacrificial layers 11 , which is merely an example. In other embodiments, the stacked structure may include more or fewer first insulating layers 9 and sacrificial layers 11 that are alternately arranged.

[0173] Step 101 can also be replaced by the following solution. In some embodiments, a first insulating layer and a conductive layer are alternately deposited on a substrate. The conductive layer is used to form an electrode of a capacitor connected to a transistor and to form a bit line, etc. The step of replacing the sacrificial layer with a conductive layer after the alternating formation of the insulating layer and the sacrificial layer can be omitted.

[0174] 102) etching the plurality of stacked structures to form a predetermined pattern;

[0175] The etching the plurality of stacked structures to form a predetermined pattern may include:

[0176] Using the first mask, an active area pattern is defined, and the active area pattern is the preset pattern;

[0177] The plurality of stacked structures are etched to form a plurality of first trenches T1 penetrating the plurality of stacked structures; the plurality of first trenches T1 form a predetermined pattern of the first insulating layer 9 and the sacrificial layer 11; the predetermined pattern of the sacrificial layer 11 includes patterns of first source / drain electrodes 51 and second source / drain electrodes 52 of transistors to be formed subsequently, patterns of bit lines 30, and patterns of first electrodes 41 of capacitors; the predetermined pattern of the sacrificial layer 11 may include a plurality of first sub-portions 111 and second sub-portions 112 connected to the first sub-portions 111, the first sub-portions 111 may extend along a first direction X, and the second sub-portions 112 may extend along a second direction Y; the region where the first sub-portions 111 are located is referred to as a memory cell region, and the region where the second sub-portions 112 are located is referred to as a bit line region;

[0178] A second insulating film is deposited and polished to form a second insulating layer 13 filling the first trenches T1. The second insulating layer 13 can be flush with the topmost first insulating layer 9. As shown in Figure 3, a cross-sectional view of the film layer containing the sacrificial layer 11 after the predetermined pattern is formed is shown along a direction parallel to the substrate 1. The first direction X and the second direction Y can intersect. In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0179] In some embodiments, the second insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the first insulating layer 9 and the second insulating layer 13 may be the same or different.

[0180] 103) forming the first hole K1 and the second hole K2 simultaneously or successively;

[0181] The simultaneously forming of the first hole K1 and the second hole K2 may include:

[0182] The second mask is used to define the patterns of the first hole K1 and the second hole K2; the first hole K1 is used to form the electrode of the capacitor, and the first hole K1 is only used to distinguish the second hole K2. The number of the first holes K1 in a storage unit can be one or more.

[0183] The multiple stacked structures are etched to form a plurality of first holes K1 and a plurality of second holes K2 that penetrate the multiple stacked structures. The first holes K1 are located in the capacitor region 200, and the second holes K2 are located in the transistor region 100, as shown in Figure 4, which is a cross-sectional view of the film layer where the sacrificial layer 11 is located, along a direction parallel to the substrate 1, after the first holes K1 and the second holes K2 are formed. The first holes K1 extend in a direction perpendicular to the substrate 1, and the second holes K2 extend in a direction perpendicular to the substrate 1.

[0184] In some embodiments, the first sub-portion 111 may include a first hole K1 and a second hole K2; however, the embodiments of the present disclosure are not limited thereto. The first sub-portion 111 may include more first holes K1, for example, two first holes K1, and the two first holes K1 may be arranged along the extension direction of the first sub-portion 111 (i.e., the first direction X). However, the embodiments of the present disclosure are not limited thereto. When there are multiple first holes K1, the arrangement of the multiple first holes K1 is not limited.

[0185] In some embodiments, the cross-section of the first hole K1 in a direction parallel to the substrate 1 can be square, circular, or elliptical, etc.

[0186] In some embodiments, when there are multiple first holes K1 , the sizes and shapes of the multiple first holes K1 may be the same, or different.

[0187] In some embodiments, the first hole K1 and the second hole K2 may be formed by dry etching the plurality of stacked structures.

[0188] In this embodiment, the first hole K1 and the second hole K2 are simultaneously formed through a single patterning process, thereby reducing process steps and lowering costs. However, the embodiments of the present disclosure are not limited thereto, and the first hole K1 and the second hole K2 can be formed separately through multiple patterning processes. A single patterning process can be understood as at least using a single mask to simultaneously form the patterns of the first hole K1 and the second hole K2.

[0189] 104) forming a dummy electrode 8;

[0190] Forming the dummy electrode 8 may include depositing a dummy layer thin film on the substrate 1 forming the aforementioned structure, and grinding it flat to form the dummy electrode 8 that fills the first hole K1 and the second hole K2, as shown in FIG5 , which is a cross-sectional view of the film layer where the sacrificial layer 11 is located, along a direction parallel to the substrate 1 after the dummy electrode 8 is formed. The dummy electrode 8 can serve as a dummy word line (dummy WL) to protect the area where the word line 40 is located. The dummy electrode 8 can be flush with the topmost first insulating layer 9.

[0191] In some embodiments, the dummy layer film may be made of a material different from that of the first insulating film and the second insulating film, for example, polysilicon (poly), silicon oxycarbon ceramic (SiOC), etc.

[0192] 105) etching and removing the second insulating layer 13 to form a conductive layer 12;

[0193] The etching to remove the second insulating layer 13 and form the conductive layer 12 may include:

[0194] Using the first mask again, the second insulating layer 13 located in the plurality of first trenches T1 is removed by dry etching to expose the first insulating layer 9 and the sacrificial layer 11;

[0195] Performing wet lateral etching through the first trench T1 to remove the sacrificial layer 11;

[0196] A first conductive film is deposited on the substrate 1 forming the aforementioned structure, and is polished so that the first conductive film is flush with the topmost first insulating layer 9; the first conductive film can fill a plurality of the first trenches T1, or, incompletely fill a plurality of the first trenches T1, only covering the bottom wall and side wall of the first trench T1; the first conductive film completely replaces the sacrificial layer 11 that is laterally etched by the wet method, which can be understood as filling the space retained after the etched sacrificial layer 11, and whether the first trench T1 is filled is not necessary.

[0197] The first mask is used again to dry-etch and remove the first conductive film in the plurality of first trenches T1, leaving only the conductive layer in the space left after the sacrificial layer 11 is etched, thereby forming a conductive layer 12. As shown in FIG6 , FIG6 is a cross-sectional view of the film layer where the conductive layer 12 is located, parallel to the substrate 1, after the conductive layer in the first trench T1 is removed. The conductive layer 12 fills the area where the sacrificial layer 11 is located after forming a preset pattern, and the orthographic projections of the conductive layer 12 and the first insulating layer 9 on the substrate 1 overlap. The conductive layer 12 may include a plurality of first conductive portions 121 and a second conductive portion 122 connecting the first conductive portions 121. The first conductive portion 121 may extend along a first direction X, and the second conductive portion 122 may extend along a second direction Y. The area where the first conductive portion 121 is located is the area where the first sub-portion 111 is located, and the area where the second conductive portion 122 is located is the area where the second sub-portion 112 is located. The first conductive portion 121 may subsequently form a first source / drain electrode 51 of a transistor and a first electrode 41 of a capacitor, and the second conductive portion 122 may subsequently form a second source / drain electrode 52 of a transistor and a bit line 30 .

[0198] Alternatively, the first conductive portion 121 may subsequently form a first source / drain electrode 51 and a second source / drain electrode 52 of a transistor and a first electrode 41 of a capacitor, and the second conductive portion 122 may subsequently form a bit line 30 .

[0199] In another exemplary embodiment, when the first trench T1 is not completely filled with the first conductive film, the first conductive film in the first trench T1 may be removed by wet etching.

[0200] In some embodiments, the first conductive film may be made of the following conductive materials:

[0201] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0202] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0203] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0204] 106) forming a third insulating layer 14, and etching away the dummy electrode 8 located in the first hole K1;

[0205] The forming of the third insulating layer 14 and etching away the dummy electrode 8 located in the first hole K1 may include:

[0206] A third insulating film is deposited on the substrate 1 having the aforementioned structure and then polished to form a third insulating layer 14; the third insulating layer 14 is flush with the topmost first insulating layer 9;

[0207] Using a third mask, the capacitor region 200 is opened, and the third insulating layer 14 in the capacitor region 200 is removed by etching; that is, the third insulating layer 14 in the plurality of first trenches T1 in the capacitor region 200 is removed;

[0208] The dummy electrode 8 located in the first hole K1 is removed by wet etching, as shown in FIG7 . FIG7 is a cross-sectional view of the film layer where the conductive layer 12 is located along a direction parallel to the substrate 1 after the dummy electrode 8 in the first hole K1 is removed.

[0209] In some embodiments, the third insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0210] 107) forming a dielectric layer 43, a second electrode 42 and a fifth insulating layer 16;

[0211] Based on the above-mentioned etching to remove the third insulating layer 14 in the capacitor region 200, that is, removing the third insulating layer 14 in the plurality of first trenches T1 in the capacitor region 200, and wet etching to remove the dummy electrode 8 in the first hole K1, the formation of the dielectric layer 43, the second electrode 42, and the fifth insulating layer 16 may include:

[0212] A dielectric film and a conductor material are sequentially deposited on the substrate 1 forming the above structure, and a dielectric layer 43 and a second electrode 42 are deposited respectively; so that the semiconductor structure includes a dielectric layer distributed in the first hole K1 and extending only from the topmost memory cell to the first trench T1; and a second electrode of the capacitor distributed in the first hole K1 and extending only from the topmost memory cell to the first trench T1.

[0213] The dielectric layer 43 covers the exposed areas of the conductive layer 12, namely, the sidewalls and bottom wall of the first hole K1, as well as the end surface of the first conductive portion 121 away from the second conductive portion 122 and the two sidewalls extending perpendicular to the substrate 1 at a distance less than or equal to a preset distance from the end surface. The second electrode 42 fills the first hole K1 and the multiple first trenches T1 located in the capacitor region 200. The second electrode 42 is insulated from the first conductive portion 121 by the dielectric layer 43. The second electrode 42 wraps around the end surface of the first conductive portion 121 away from the second conductive portion 122 and the two sidewalls extending perpendicular to the substrate 1 at a distance less than or equal to a preset distance from the end surface. In other words, it wraps around the end surface of the first electrode 41 away from the second conductive portion 122 and the two sidewalls adjacent to the end surface extending perpendicular to the substrate 1.

[0214] The third mask is used again to etch away the dielectric layer 43 and the second electrode 42 located in the transistor region 100. The etching stops on the topmost first insulating layer 9, exposing the upper surface (the surface away from the substrate 1) of the dummy electrode 8 deposited in the second hole K2.

[0215] A fifth insulating film is deposited and polished to form a fifth insulating layer 16 covering the transistor region 100, as shown in Figures 8A and 8B. Figure 8A is a schematic cross-sectional view of an exemplary embodiment of the dielectric layer 43, the second electrode 42, and the fifth insulating layer 16, taken along a direction parallel to the substrate 1 (the film layer where the conductive layer 12 is located), after forming the dielectric layer 43, the second electrode 42, and the fifth insulating layer 16. Figure 8B is a schematic view taken along the aa' direction in Figure 8A. When polished, the surface of the fifth insulating layer 16 facing away from the substrate 1 is flush with the surface of the second electrode 42 facing away from the substrate 1. As shown in Figure 8A, the second electrode 42 can include an inner electrode disposed within each first hole K1 and an outer electrode wrapping around the end face and two sidewalls of the first electrode 41, with the outer electrode wrapping around the entire area of ​​the two outer sidewalls. As shown in Figure 8B, the inner and outer electrodes can be connected at the top of the semiconductor device via a planar film layer extending parallel to the substrate at the top. The planar film layer has an opening that exposes the transistor region 100.

[0216] In some embodiments, the second electrode 42 may include a first sub-layer 421 and a second sub-layer 422. After forming the dielectric layer 43, a first sub-conductive film may be deposited on the substrate 1 to form the first sub-layer 421. A second sub-conductive film may then be deposited to form the second sub-layer 422. The second sub-layer 422 fills the first hole K1 and the plurality of first trenches T1 located in the capacitor region 200. The first sub-layer 421 covers the dielectric layer 43, and the second sub-layer 422 covers the first sub-layer 421. The second sub-layer 422 is connected to the first sub-layer 421.

[0217] In some embodiments, the dielectric film and the conductor material may be deposited by atomic layer deposition (ALD).

[0218] In some embodiments, the dielectric film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, the dielectric film may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, the dielectric film may include, but is not limited to, at least one of the following high-K materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0219] In some embodiments, the first sub-conductive film includes but is not limited to at least one of the following or a combination thereof:

[0220] Metals or alloys, for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., can be metal alloys containing the aforementioned metals;

[0221] Alternatively, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0222] In some embodiments, the second sub-conductive film includes, but is not limited to, metal, metal alloy, polysilicon, silicon-doped conductive layer, metal oxide conductive layer, etc. Compared with the second sub-conductive film, the first sub-conductive film can be a film layer with better adhesion properties to enhance the adhesion between the second electrode 42 and the dielectric layer 43.

[0223] In some embodiments, the fifth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0224] 108) forming a second trench T2;

[0225] The forming of the second trench T2 may include: using a fourth mask to open the area where the second trench T2 is located, and using dry etching to etch from the top layer to the bottom layer (excluding the substrate 1) to form the second trench T2; as shown in Figures 9A and 9B, wherein Figure 9A is a cross-sectional view of the film layer where the conductive layer 12 is located after the second trench T2 is formed, along a direction parallel to the substrate 1; Figure 9B is a cross-sectional view along the bb' direction in Figure 9A.

[0226] The second trench T2 exposes the sidewall of the first conductive portion 121 near the second hole K2. The dimension of the second trench T2 along the extension direction of the first conductive portion 121 is larger than the dimension of the second hole K2 along the extension direction of the first conductive portion 121. This facilitates subsequent etching of the conductive layer 12 to expose the sidewall of the dummy electrode 8 facing the second trench T2. The second trench T2 does not expose the second conductive portion 122. The second trench T2 is located in the transistor region 100 and outside the capacitor region 200.

[0227] 109) etching the conductive layer 12;

[0228] The etching of the conductive layer 12 may include: wet-etching the conductive layer 12 laterally through the second trench T2 to expose the sidewall of the dummy electrode 8 facing the second trench T2, thereby expanding the area of ​​the second trench T2 located in the conductive layer 12; the sidewall of the dummy electrode 8 facing the second trench T2 is completely exposed, and the size of the etched area of ​​the first conductive portion 121 along the extension direction of the first conductive portion 121 is larger than the size of the second hole K2 along the extension direction of the first conductive portion 121, thereby disconnecting the first source / drain electrode 51 from the second source / drain electrode 52. As shown in Figures 10A and 10B, Figure 10A is a cross-sectional view of the film layer in which the conductive layer 12 is located after etching the conductive layer 12, along a direction parallel to the substrate 1; and Figure 10B is a cross-sectional view along the bb' direction in Figure 10A.

[0229] 110) forming a barrier layer 7;

[0230] The formation of the barrier layer 7 may include: depositing a barrier layer film on the substrate 1 forming the aforementioned structure, and grinding it to form the barrier layer 7; the barrier layer 7 covers the bottom wall and side walls of the second trench T2, and does not completely fill the second trench T2, that is, the bottom wall and the side walls are covered with a barrier layer 7 of a preset thickness, and the barrier layer 7 has an opening facing the side away from the substrate 1, as shown in Figures 11A and 11B, wherein Figure 11A is a cross-sectional view of the film layer where the conductive layer 12 is located after the barrier layer 7 is formed, along a direction parallel to the substrate 1; Figure 11B is a cross-sectional view along the bb' direction in Figure 11A.

[0231] In some embodiments, the barrier film can be a low-K dielectric layer different from the first insulating film, such as nitrogen-doped or carbon-doped silicon dioxide. A high etching selectivity is achieved between the barrier layer 7 and the dummy electrode 8, thereby protecting other film layers during the subsequent etching of the dummy electrode 8 in the second hole K2.

[0232] 111) forming a fourth insulating layer 15;

[0233] The formation of the fourth insulating layer 15 may include: depositing a fourth insulating film in the second trench T2 and grinding it flat to form a fourth insulating layer 15 filling the second trench T2, and the surface of the fourth insulating layer 15 away from the substrate 1 is flush with the surface of the topmost first insulating layer 9 away from the substrate 1, as shown in Figures 12A and 12B, wherein Figure 12A is a cross-sectional view of the film layer where the conductive layer 12 is located after the fourth insulating layer 15 is formed along a direction parallel to the substrate 1; Figure 12B is a cross-sectional view along the bb' direction in Figure 12A.

[0234] 112) removing the dummy electrode 8 located in the second hole K2;

[0235] Removing the dummy electrode 8 in the second hole K2 may include removing the dummy electrode 8 in the second hole K2 by wet etching, as shown in Figures 13A and 13B , where Figure 13A is a cross-sectional view of the film layer where the conductive layer 12 is located, parallel to the substrate 1, after the dummy electrode 8 is removed; and Figure 13B is a cross-sectional view taken along the line bb' in Figure 13A . After removing the dummy electrode 8 in the second hole K2, the semiconductor layer 23, the gate insulating layer 24, and the word line 40 are formed in the second hole K2.

[0236] 113) etching the first insulating layer 9;

[0237] The etching of the first insulating layer 9 may include: wet lateral etching of the first insulating layer 9 such that the aperture of the second sub-aperture K22 of the second aperture K2 located in the conductive layer 12 is smaller than the aperture of the first sub-aperture K21 of the second aperture K2 located in the first insulating layer 9, thereby facilitating the subsequent etching outside the second aperture K2 to remove the semiconductor layer 23 between the transistors and eliminate the parasitic transistor, as shown in Figures 14A, 14B, and 14C. Figure 14A is a cross-sectional view of the film layer where the conductive layer 12 is located, parallel to the substrate 1, after etching the first insulating layer 9, Figure 14B is a cross-sectional view along the aa' direction in Figure 14A, and Figure 14C is a cross-sectional view along the bb' direction in Figure 14A. In the bb' direction, etching of the first insulating layer 9 stops at the barrier layer 7, so that the size of the second aperture K2 along the bb' direction can be limited by the barrier layer 7, thereby achieving precise control of the second aperture K2.

[0238] In some embodiments, the first width of the first insulating layer 9 laterally etched parallel to the aa' direction can be greater than the second width of the first insulating layer 9 laterally etched parallel to the bb' direction. That is, the etching amount in the aa' direction is greater and the etching amount in the bb' direction is less. The etching amount in the aa' direction is greater. When the semiconductor layer 23 is subsequently exposed, less of the first insulating layer 9 needs to be etched, making the process more convenient. The less etching amount in the bb' direction can reduce device size and facilitate increased device density.

[0239] 114) forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40;

[0240] The forming of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 may include:

[0241] A semiconductor film, a gate insulating film, and a gate electrode film are sequentially deposited on the substrate 1 having the above structure and then polished to form a semiconductor layer 23, a gate insulating layer 24, and a word line 40, as shown in Figures 15A, 15B, and 15C. Figure 15A is a cross-sectional view parallel to the substrate 1 (the film layer where the conductive layer 12 is located) after the formation of the semiconductor layer 23, the gate insulating layer 24, and the word line 40, Figure 15B is a cross-sectional view along the aa' direction in Figure 15A, and Figure 15C is a cross-sectional view along the bb' direction in Figure 15A. The gate electrode 26 of each transistor layer is part of the word line 40.

[0242] The semiconductor layer 23 may cover the bottom wall and sidewalls of the second hole K2 . The word line 40 fills the second hole K2 . The gate insulating layer 24 is disposed between the semiconductor layer 23 and the word line 40 to insulate the semiconductor layer 23 from the word line 40 .

[0243] In some embodiments, the semiconductor film, the gate insulating film, and the gate electrode film may be deposited by ALD.

[0244] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap smaller than 2 eV, or may be a wide band gap material, such as a metal oxide material with a band gap larger than 2 eV.

[0245] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.

[0246] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0247] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0248] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0249] In exemplary embodiments of the present disclosure, the material of the gate insulating layer 24 may include one or more layers of a high-k dielectric material. In some embodiments, the gate insulating layer 24 may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, and the like. Exemplary materials include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-k materials.

[0250] In some embodiments, the gate electrode film may be one or more of the following different types of materials:

[0251] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0252] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO) and other metal oxide materials with high conductivity; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials;

[0253] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0254] 115) exposing the sidewall of the semiconductor layer 23 located in the first sub-hole K21 and connected to the barrier layer 7;

[0255] Exposing the sidewall of the semiconductor layer 23 located in the first sub-hole K21 and connected to the barrier layer 7 may include:

[0256] The fourth insulating layer 15 in the second trench T2 is dry-etched away, and a portion of the barrier layer 7 is dry-etched away, exposing the sidewalls of the semiconductor layer 23 in the first sub-hole K21 that are connected to the barrier layer 7 (after the barrier layer 7 is etched away, the exposed sidewalls of the semiconductor layer 23 are no longer connected to the barrier layer 7). The exposed sidewalls of the semiconductor layer 23 are parallel to the extension direction of the first conductive portion 121. At this point, the semiconductor layer 23 in the second sub-hole K22 is protected by the barrier layer 7, as shown in Figures 16A and 16B. Figure 16A is a cross-sectional view of the exposed semiconductor layer 23 taken along a direction parallel to the substrate 1 (the film layer where the conductive layer 12 is located), and Figure 16B is a cross-sectional view taken along the line bb' in Figure 16A. At this point, only a portion of the semiconductor layer 23 in the first sub-hole K21 is exposed, with two sidewalls remaining unexposed. In addition, only the sidewalls of the barrier layer 7 parallel to the aa' direction are retained, and the sidewalls perpendicular to the aa' direction are etched away, as shown in FIG. 16A .

[0257] 116) exposing the sidewall of the semiconductor layer 23 located in the first sub-hole K21 and connected to the first insulating layer 9;

[0258] Exposing the sidewalls of the semiconductor layer 23 located within the first sub-hole K21 and connected to the first insulating layer 9 may include wet etching the first insulating layer 9 through the second trench T2 (the fourth insulating layer 15 in the second trench T2 was removed in the previous step), thereby exposing the sidewalls of the semiconductor layer 23 located within the first sub-hole K21 and connected to the first insulating layer 9. As shown in Figures 17A, 17B, and 17C, Figure 17A is a cross-sectional view parallel to the substrate 1 (the film layer where the conductive layer 12 is located) after exposing the semiconductor layer 23, Figure 17B is a cross-sectional view along the aa' direction in Figure 17A, and Figure 17C is a cross-sectional view along the bb' direction in Figure 17A. At this point, the semiconductor layer 23 located within the first sub-hole K21 is exposed. The semiconductor layer 23 located within the second sub-hole K22 is not exposed.

[0259] 117) The semiconductor layer 23 in the first sub-hole K21 is removed by etching.

[0260] Etching and removing the semiconductor layer 23 in the first sub-hole K21 may include: removing the semiconductor layer 23 in the first sub-hole K21 by wet etching; disconnecting different semiconductor layers 23;

[0261] A sixth insulating film is deposited on the substrate 1 forming the aforementioned structure and then polished to form a sixth insulating layer 17; the sixth insulating layer 17 fills the second trench T2 and the area where the first insulating layer 9 and the semiconductor layer 23 are etched, as shown in Figures 18A, 18B and 18C, wherein Figure 18A is a cross-sectional view along a direction parallel to the substrate 1 after etching the semiconductor layer 23 (the film layer where the conductive layer 12 is located), Figure 18B is a cross-sectional view along the aa' direction in Figure 18A, and Figure 18C is a cross-sectional view along the bb' direction in Figure 18A.

[0262] In some embodiments, the sixth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0263] The manufacturing method of the semiconductor device provided in this embodiment uses an insulating layer and a sacrificial layer to stack instead of stacking an insulating layer and a conductive layer, which facilitates the etching of a multilayer structure with a high aspect ratio, reduces the process difficulty, and reduces the cost. In addition, the mask pattern or mask can be reused, which reduces the number of masks used and reduces the cost. In addition, the pattern of the capacitor and the pattern of the hole of the vertical transistor are formed at one time, avoiding multiple stacking etchings. And the capacitor includes an inner electrode and an outer electrode, which increases the capacitor area and increases the capacitance when the total length of the capacitor is constant. In addition, removing the parasitic channel from the outside of the channel is simpler than removing the parasitic channel from the inside of the channel, and is less likely to damage the channel, thereby improving the device performance.

[0264] In another exemplary embodiment, a contact layer may be provided between the semiconductor layer 23 and the first source / drain electrode 51 , the second source / drain electrode 52 to reduce contact resistance between the semiconductor layer 23 and the first source / drain electrode 51 , the second source / drain electrode 52 .

[0265] In an exemplary embodiment, a process for manufacturing the semiconductor device may include:

[0266] 201) to 212), same as steps 101) to 112);

[0267] 213) laterally etching the conductive layer 12;

[0268] The lateral etching of the conductive layer 12 may include: laterally etching the conductive layer 12 to a preset width along an extension direction parallel to the first source / drain electrode 51, so that the aperture of the second sub-hole K22 along the extension direction parallel to the first source / drain electrode 51 is enlarged (larger than the aperture of the first sub-hole K21 along the extension direction parallel to the first source / drain electrode 51), and the aperture of the second sub-hole K22 along the extension direction perpendicular to the first source / drain electrode 51 remains unchanged (consistent with the aperture of the first sub-hole K21 along the extension direction perpendicular to the first source / drain electrode 51), as shown in Figures 19A, 19B and 19C, wherein Figure 19A is a cross-sectional view along a direction parallel to the substrate 1 after the conductive layer 12 is laterally etched (the film layer where the conductive layer 12 is located), Figure 19B is a cross-sectional view along the aa' direction in Figure 19A, and Figure 19C is a cross-sectional view along the bb' direction in Figure 19A. The preset width can be set according to the width of the contact layer 6 , and the subsequent contact layer 6 is set in the area where the conductive layer 12 is etched.

[0269] 214) forming a contact layer 6;

[0270] The formation of the contact layer 6 may include: depositing a third conductive film on the substrate 1 forming the aforementioned structure to form a contact layer 6, and the contact layer 6 covers the bottom wall and side wall of the second hole K2, as shown in Figures 20A, 20B and 20C, wherein Figure 20A is a cross-sectional view along a direction parallel to the substrate 1 after the contact layer 6 is formed (the film layer where the conductive layer 12 is located), Figure 20B is a cross-sectional view along the aa' direction in Figure 20A, and Figure 20C is a cross-sectional view along the bb' direction in Figure 20A.

[0271] In some embodiments, the third conductive film may include, but is not limited to, materials such as TiN having low contact resistance with the semiconductor layer 23 .

[0272] 215) etching a portion of the contact layer 6;

[0273] The etching of a portion of the contact layer 6 may include: dry etching the contact layer 6, retaining only the contact layer 6 located on the sidewalls of the conductive layer 12, and removing the contact layer 6 located on the remaining sidewalls and bottom wall of the second hole K2, as shown in Figures 21A, 21B, and 21C. Figure 21A is a cross-sectional view along a direction parallel to the substrate 1 after etching a portion of the contact layer 6 (the film layer where the conductive layer 12 is located), Figure 21B is a cross-sectional view along the aa' direction in Figure 21A, and Figure 21C is a cross-sectional view along the bb' direction in Figure 21A. It can be seen that in the cross-sectional view in the aa' direction, the contact layer 6 exists only on the sidewalls of the first source / drain electrode 51 and the second source / drain electrode 52, and there is no contact layer 6 at other locations. In the cross-sectional view in the bb' direction, there is no contact layer 6.

[0274] 216) etching the first insulating layer 9;

[0275] The etching of the first insulating layer 9 may include: wet lateral etching of the first insulating layer 9 such that the aperture of the second sub-aperture K22 of the second aperture K2 located in the conductive layer 12 is smaller than the aperture of the first sub-aperture K21 of the second aperture K2 located in the first insulating layer 9, thereby facilitating the subsequent etching outside the second aperture K2 to remove the semiconductor layer 23 between the transistors and eliminate the parasitic transistor, as shown in Figures 22A, 22B, and 22C. Figure 22A is a cross-sectional view of the film layer where the conductive layer 12 is located, parallel to the substrate 1, after etching the first insulating layer 9, Figure 22B is a cross-sectional view along the aa' direction in Figure 22A, and Figure 22C is a cross-sectional view along the bb' direction in Figure 22A. In the bb' direction, etching of the first insulating layer 9 stops at the barrier layer 7, so that the size of the second aperture K2 along the bb' direction can be limited by the barrier layer 7, thereby achieving precise control of the second aperture K2.

[0276] In some embodiments, the first width of the first insulating layer 9 laterally etched parallel to the aa' direction can be greater than the second width of the first insulating layer 9 laterally etched parallel to the bb' direction. That is, the etching amount in the aa' direction is greater and the etching amount in the bb' direction is less. The etching amount in the aa' direction is greater. When the semiconductor layer 23 is subsequently exposed, less of the first insulating layer 9 needs to be etched, making the process more convenient. The less etching amount in the bb' direction can reduce device size and facilitate increased device density.

[0277] 217) forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40;

[0278] The forming of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 may include:

[0279] A semiconductor film, a gate insulating film, and a gate electrode film are sequentially deposited on the substrate 1 having the above structure and then polished to form a semiconductor layer 23, a gate insulating layer 24, and a word line 40, as shown in Figures 23A, 23B, and 23C. Figure 23A is a cross-sectional view parallel to the substrate 1 (the film layer where the conductive layer 12 is located) after the formation of the semiconductor layer 23, the gate insulating layer 24, and the word line 40, Figure 23B is a cross-sectional view along the aa' direction in Figure 23A, and Figure 23C is a cross-sectional view along the bb' direction in Figure 23A. The gate electrode 26 of each transistor layer is part of the word line 40.

[0280] The semiconductor layer 23 may cover the bottom wall and sidewalls of the second hole K2 . The word line 40 fills the second hole K2 . The gate insulating layer 24 is disposed between the semiconductor layer 23 and the word line 40 to insulate the semiconductor layer 23 from the word line 40 .

[0281] In some embodiments, the semiconductor film, the gate insulating film, and the gate electrode film may be deposited by ALD.

[0282] In the exemplary embodiments of the present disclosure, the materials of the semiconductor layer 23, the gate insulating layer 24, and the word line 40 can be referred to in the previous embodiment and will not be described in detail. In this embodiment, a contact layer 6 is provided between the semiconductor layer 23 and the first source / drain electrode 51, and between the semiconductor layer 23 and the second source / drain electrode 52. This reduces the contact resistance between the semiconductor layer 23 and the first source / drain electrode 51 and the second source / drain electrode 52.

[0283] 218) exposing the sidewall of the semiconductor layer 23 located in the first sub-hole K21 and connected to the barrier layer 7;

[0284] Exposing the sidewall of the semiconductor layer 23 located in the first sub-hole K21 and connected to the barrier layer 7 may include:

[0285] The fourth insulating layer 15 in the second trench T2 is removed by dry etching, and part of the blocking layer 7 is removed by dry etching to expose the side wall of the semiconductor layer 23 connected to the blocking layer 7 in the first sub-hole K21 (after the blocking layer 7 is etched away, the side wall of the exposed semiconductor layer 23 is not connected to the blocking layer 7). The side wall of the exposed semiconductor layer 23 is a side wall parallel to the extension direction of the first conductive portion 121. At this time, the semiconductor layer 23 in the second sub-hole K22 is protected by the blocking layer 7, as shown in Figures 24A, 24B, and 24C, where Figure 24A is a cross-sectional view along a direction parallel to the substrate 1 (the film layer where the conductive layer 12 is located) after the semiconductor layer 23 is exposed, Figure 24B is a cross-sectional view along the aa' direction in Figure 24A, and Figure 24C is a cross-sectional view along the bb' direction in Figure 24A. At this point, only a portion of the semiconductor layer 23 within the first sub-hole K21 is exposed, leaving two sidewalls unexposed. As shown in FIG24B , the two sidewalls of the semiconductor layer 23 within the first sub-hole 21 in the aa' direction are unexposed. Furthermore, only the sidewalls of the barrier layer 7 parallel to the aa' direction remain, while the sidewalls perpendicular to the aa' direction are etched away, as shown in FIG24A .

[0286] 219) exposing the sidewall of the semiconductor layer 23 located in the first sub-hole K21 and connected to the first insulating layer 9;

[0287] Exposing the sidewalls of the semiconductor layer 23 located in the first sub-hole K21 and connected to the first insulating layer 9 may include wet etching the first insulating layer 9 through the second trench T2 (the fourth insulating layer 15 in the second trench T2 was removed in the previous step) to expose the sidewalls of the semiconductor layer 23 located in the first sub-hole K21 and connected to the first insulating layer 9; as shown in Figures 25A, 25B, and 25C, Figure 25A is a cross-sectional view parallel to the substrate 1 (the film layer where the conductive layer 12 is located) after the semiconductor layer 23 is exposed, Figure 25B is a cross-sectional view along the aa' direction in Figure 25A, and Figure 25C is a cross-sectional view along the bb' direction in Figure 25A. At this point, the semiconductor layer 23 located in the first sub-hole K21 is completely exposed.

[0288] 220) The semiconductor layer 23 in the first sub-hole K21 is removed by etching.

[0289] The etching and removing of the semiconductor layer 23 in the first sub-hole K21 may include: removing the semiconductor layer 23 in the first sub-hole K21 by wet etching; disconnecting the semiconductor layers 23 of the memory cells in different layers;

[0290] A sixth insulating film is deposited on the substrate 1 forming the aforementioned structure and then polished to form a sixth insulating layer 17; the sixth insulating layer 17 fills the second trench T2 and the area where the first insulating layer 9 and the semiconductor layer 23 are etched, as shown in Figures 26A, 26B and 26C, wherein Figure 26A is a cross-sectional view along a direction parallel to the substrate 1 after etching the semiconductor layer 23 (the film layer where the conductive layer 12 is located), Figure 26B is a cross-sectional view along the aa' direction in Figure 26A, and Figure 26C is a cross-sectional view along the bb' direction in Figure 26A.

[0291] The solution provided in this embodiment can reduce the contact resistance between the semiconductor layer and the electrodes of the transistor by providing a contact layer between the semiconductor layer and the electrodes of the transistor (source electrode and / or drain electrode).

[0292] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate; a word line extending through the different layers and along a direction perpendicular to the substrate; a plurality of capacitors corresponding one-to-one to the plurality of transistors, the capacitors being connected to the corresponding transistors; the capacitors comprising a first electrode and a second electrode; the transistors comprising a first source / drain electrode, a second source / drain electrode, and a semiconductor layer surrounding the sidewalls of the word line, the first source / drain electrode being connected to the first electrode of the corresponding capacitor; the method for manufacturing the semiconductor device comprising:

[0293] forming a stack structure of alternately stacked first insulating layers and sacrificial layers on a substrate;

[0294] The stack structure is patterned to form a bit line region extending along a second direction and a plurality of memory cell regions extending along a first direction and spaced apart along the second direction; a trench extending along the first direction and penetrating the stack structure is provided between any two adjacent memory cell regions;

[0295] forming at least one first hole penetrating the stacked structure in the memory cell region and filling the first hole with a dummy electrode;

[0296] Performing lateral etching in the trench between any two adjacent memory cell regions to remove each sacrificial layer to expose a dummy electrode in a corresponding region;

[0297] Replacing the area where each removed sacrificial layer is located with a conductive layer, so that the first insulating layer and the conductive layer are alternately stacked, and the conductive layer surrounds the dummy electrode;

[0298] removing the dummy electrode to expose the first hole, forming a dielectric layer of the capacitor on a sidewall of the first hole, and forming an inner electrode of the second pole of the capacitor in the first hole formed with the dielectric layer;

[0299] A second hole is formed in the memory cell region near the bit line region, and the semiconductor layer, the gate insulating layer and the word line of the transistor are formed in the second hole.

[0300] The solution provided in this embodiment uses an insulating layer and a sacrificial layer to stack instead of an insulating layer and a conductive layer, which facilitates the etching of a multi-layer structure with a high aspect ratio, reduces the process difficulty, and reduces the cost. In addition, by setting a second electrode in the first hole, the area occupied by the capacitor can be reduced, thereby reducing the area of ​​the semiconductor device and improving the density of the semiconductor device.

[0301] In some embodiments, the first and second holes can be formed through a single patterning process. Compared to semiconductor devices without first holes, the solution provided by the disclosed embodiments eliminates the need for additional processing for the first holes, avoids multiple etching steps of the stacked structure, and reduces costs. However, the disclosed embodiments are not limited thereto, and the first and second holes can be formed separately through multiple patterning processes.

[0302] In some embodiments, replacing the area where each sacrificial layer is removed with a conductive layer includes:

[0303] Depositing a conductive film, wherein the conductive film fills the area where the sacrificial layer is located and the trench;

[0304] removing the conductive film in the groove by dry etching to form the conductive layer;

[0305] Alternatively, a conductive film is deposited, wherein the conductive film fills the area where the sacrificial layer is located and covers the sidewalls and bottom wall of the trench;

[0306] The conductive film in the trench is removed by wet etching to form the conductive layer.

[0307] In some embodiments, the conductive layer includes a first electrode of the capacitor, and the method further includes: exposing an outer sidewall of the first electrode, the outer sidewall including an end face of the first electrode away from the bit line region and two sidewalls adjacent to the end face, the end face and the two sidewalls both extending in a direction perpendicular to the substrate to form an outer electrode of the second electrode surrounding the end face and the two sidewalls of the first electrode, and forming a dielectric layer disposed between the outer sidewall of the first electrode and the outer electrode. The solution provided in this embodiment can include both outer and inner electrodes for the capacitor. Compared to a solution including only outer electrodes, this can increase the electrode area of ​​the capacitor and thus the capacitance, without increasing the area occupied by the capacitor.

[0308] The present disclosure also provides an electronic device comprising the semiconductor device described in any of the preceding embodiments, or a semiconductor device manufactured using the semiconductor device manufacturing method described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power bank. The storage device may include, but is not limited to, computer memory.

[0309] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: A plurality of memory cells stacked perpendicular to a substrate direction, the plurality of memory cells comprising: A plurality of transistors are distributed in different layers and stacked along a direction perpendicular to the substrate; A word line, penetrating through the different layers and extending in a direction perpendicular to the substrate; A plurality of capacitors connected to the plurality of transistors in a one-to-one correspondence; the capacitors include a first electrode and a second electrode; the transistors include a first source / drain electrode, a second source / drain electrode and a semiconductor layer surrounding the sidewall of the word line; the first source / drain electrode is connected to the first electrode of the corresponding capacitor; First insulating layers and conductive layers are alternately distributed along a direction perpendicular to the substrate, and different regions of each of the conductive layers include the first source / drain electrode, the second source / drain electrode and the first electrode; The first pole region includes at least one first hole penetrating through each of the first insulating layers and each of the conductive layers, wherein the inner wall of the first hole exposes the stacked conductive layer and the first insulating layer; The second electrode includes an inner electrode arranged in the first hole and insulated from each first electrode. The inner electrode is distributed in the first hole and covers a region where each conductive layer is exposed on the inner wall of the first hole and a region where each first insulating layer is exposed on the inner wall of the first hole.

2. The semiconductor device according to claim 1, wherein The second electrode further includes: an external electrode, the first electrode includes a first end surface away from the first source / drain electrode and two first side walls adjacent to the first end surface, and the external electrode surrounds the first end surface and the two first side walls of each of the first electrodes.

3. The semiconductor device according to claim 2, wherein: The outer electrode also surrounds the second end surface of the first insulating layer away from the first source / drain electrode and two second side walls adjacent to the second end surface; and, between adjacent first poles in a direction perpendicular to the substrate, the outer electrode and the inner electrode are spaced apart from each other.

4. The semiconductor device according to claim 2, wherein: The inner electrode includes a first connecting electrode filled in the first hole, and a first sub-electrode located between the first connecting electrode and the first electrode and distributed on the inner wall of the first hole, and the first sub-electrode surrounds the side wall of the first hole, and the first connecting electrode fills the first hole and contacts the area of ​​the first sub-electrode on the side of the side wall facing away from the first hole.

5. The semiconductor device according to claim 4, wherein: The first sub-electrodes of the capacitors are integrated ring electrodes, and the first connecting electrodes of the capacitors are integrated linear electrodes.

6. The semiconductor device according to claim 5, wherein: The external electrode comprises a second sub-electrode extending along an outer side wall of the first electrode and an outer side wall of the first insulating layer, and a second connecting electrode located at a side of the second sub-electrode away from the first electrode; The plurality of second sub-electrodes of the plurality of capacitors are of an integrated structure, and the plurality of second connecting electrodes of the plurality of capacitors are of an integrated structure; The plurality of first sub-electrodes and the plurality of second sub-electrodes are connected to form an integrated structure above the topmost storage unit; The plurality of first connection electrodes and the plurality of second connection electrodes are connected above the topmost storage unit to form an integrated structure.

7. The semiconductor device according to claim 6, wherein: The second sub-electrode and the first sub-electrode are made of metal or metal nitride, and the first connecting electrode and the second connecting electrode are made of polysilicon.

8. The semiconductor device according to claim 6, wherein: The first sub-electrode and the second sub-electrode are connected only at the top of the stacked plurality of memory cells to form an integrated structure, and the first connection electrode and the second connection electrode are connected only at the top of the stacked plurality of memory cells to form an integrated structure.

9. The semiconductor device according to claim 8, wherein: The semiconductor device includes multiple layers of memory cells, each layer of memory cells includes a memory cell array, the memory cell array includes multiple rows and columns of memory cells, the second connecting electrodes of multiple memory cells stacked in the same column and different layers are connected to form an integrated structure; the second sub-electrodes of multiple memory cells stacked in the same column and different layers are connected to form an integrated structure.

10. The semiconductor device according to claim 9, wherein The second connecting electrode of the integrated structure comprises a first portion in the trench between two adjacent columns of memory cells in the row direction and a second portion extending into the trench between two adjacent memory cells in the column direction.

11. The semiconductor device according to any one of claims 2 to 10, wherein: The first electrode and the first source / drain electrode are an integrated structure extending in a direction parallel to the substrate, the end face of the integrated structure facing the word line is connected to the semiconductor layer, and the end face away from the word line is connected to the external electrode of the second electrode through a dielectric layer, and a solid structure with only the first hole is formed between the end face of the integrated structure facing the word line and the end face away from the word line.

12. The semiconductor device according to claim 11, wherein The integrated structure formed by the first pole of the capacitor and the first source / drain electrode extends along a first direction away from the second source / drain electrode, the area of ​​the first pole includes a plurality of first holes, and the plurality of first holes are arranged along the first direction, and the inner electrodes in the plurality of first holes are electrically connected.

13. The semiconductor device according to any one of claims 1 to 10, wherein: On a plane parallel to the substrate, a cross-sectional shape of the first hole includes: a circle, an ellipse or a square.

14. The semiconductor device according to any one of claims 1 to 10, wherein: In a direction parallel to the substrate, a first cross section of a sub-hole of the first hole in the conductive layer and a second cross section of a sub-hole of the first hole in the first insulating layer have the same shape.

15. The semiconductor device according to claim 14, wherein: The first cross section and the second cross section have the same size.

16. The semiconductor device according to any one of claims 1 to 10, wherein: The semiconductor device also includes: a second hole penetrating each of the first insulating layer and the conductive layer, the word line is arranged in the second hole, the first electrode, the first source / drain electrode, and the second source / drain electrode are arranged in the same layer, and the first source / drain electrode and the second source / drain electrode are disconnected at the second hole.

17. A method for manufacturing a semiconductor device, wherein the semiconductor device comprises a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate; A word line, which runs through the different layers and extends in a direction perpendicular to the substrate; a plurality of capacitors corresponding to the plurality of transistors one by one, the capacitors being connected to the corresponding transistors; the capacitors comprising a first electrode and a second electrode; the transistor comprising a first source / drain electrode, a second source / drain electrode and a semiconductor layer surrounding the sidewall of the word line, the first source / drain electrode being connected to the first electrode of the corresponding capacitor; the manufacturing method of the semiconductor device comprising: Forming a stack structure of alternately stacked first insulating layers and sacrificial layers on a substrate; The stack structure is patterned to form a bit line region extending along a second direction and a plurality of memory cell regions extending along a first direction and spaced apart along the second direction; a groove extending along the first direction and penetrating the stack structure is provided between any two adjacent memory cell regions; forming at least one first hole penetrating the stacked structure in the memory cell region and filling a dummy electrode in the first hole, wherein the first hole is not connected to the trench; Performing lateral etching in the trench between any two adjacent storage cell areas to remove each sacrificial layer and expose the dummy electrode in the corresponding area; Replacing the area where each removed sacrificial layer is located with a conductive layer, so that the first insulating layer and the conductive layer are alternately stacked, and the conductive layer surrounds the dummy electrode; The dummy electrode in the first hole is removed to expose the conductive layer and the first insulating layer continuously distributed on the side wall of the first hole, a dielectric layer of the capacitor is formed on the side wall of the first hole, and an inner electrode of the second pole of the capacitor is formed in the first hole formed with the dielectric layer.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: A second hole is formed in the memory cell region near the bit line region, wherein the semiconductor layer, the gate insulating layer and the word line of the transistor are formed in the second hole; Wherein, the first hole and the second hole are formed by a single patterning process.

19. The method for manufacturing a semiconductor device according to claim 17, wherein: The step of replacing the area where each sacrificial layer is removed with a conductive layer comprises: Depositing a conductive film, wherein the conductive film fills the area where the sacrificial layer is located and the groove; Dry etching to remove the conductive film in the groove to form the conductive layer; Alternatively, depositing a conductive film, wherein the conductive film fills the area where the sacrificial layer is located and covers the sidewalls and bottom wall of the trench; The conductive film in the groove is removed by wet etching to form the conductive layer.

20. The method for manufacturing a semiconductor device according to claim 17, wherein: The conductive layer includes a first electrode of the capacitor, and the method further includes: exposing an outer side wall of the first electrode, the outer side wall including an end face of the first electrode away from the bit line region and two side walls adjacent to the end face, the end face and the two side walls both extending in a direction perpendicular to the substrate to form an external electrode of the second electrode surrounding the end face and the two side walls of the first electrode, and forming a dielectric layer arranged between the outer side wall of the first electrode and the external electrode.

21. The method for manufacturing a semiconductor device according to claim 17, wherein: The method further includes forming a trench extending along the second direction and penetrating the stacked structure between two adjacent columns of the memory cell regions; While forming the dielectric layer of the capacitor on the sidewall of the first hole, depositing the dielectric layer in the trench between the two adjacent columns of the memory cell regions through a single process; At the same time as forming the inner electrode of the second electrode on the sidewall of the first hole, depositing the outer electrode of the second electrode in the trench between the two adjacent columns of the memory cell areas through a single process; The inner electrode and the outer electrode are an integrated structure.

22. A semiconductor device comprising: A memory cell array stacked vertically in the substrate direction and periodically distributed; Each memory cell region includes transistors and capacitors sequentially distributed in a first direction; The region of the transistor includes a word line hole penetrating each memory cell; Also included are conductive layers and first insulating layers that are alternately stacked; A connected groove is included between adjacent memory cells along a first direction parallel to the substrate and a second direction parallel to the substrate, wherein the groove exposes the outer sidewalls of the conductive layer and the first insulating layer; The capacitor region includes at least one first hole penetrating each of the conductive layers and the first insulating layer, wherein the first hole exposes inner side walls of the conductive layer and the first insulating layer; adjacent conductive layers in the capacitor region are spaced apart by the first insulating layer.

23. The semiconductor device according to claim 22, wherein: The conductive layer extends to the word line hole; The semiconductor device further includes a semiconductor layer located in the word line hole, wherein the semiconductor layer is electrically connected to the conductive layer.

24. The semiconductor device according to claim 22, wherein: The conductive layer is the first electrode of the capacitor, and the semiconductor device also includes a dielectric layer distributed in the first hole and extending only from the topmost storage unit to the groove; and a second electrode of the capacitor distributed in the first hole and extending only from the topmost storage unit to the groove.

25. An electronic device, comprising the semiconductor device according to any one of claims 1 to 16, or comprising the semiconductor device according to any one of claims 22 to 24, or a semiconductor device manufactured according to the semiconductor device manufacturing method according to any one of claims 17 to 20.

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