Semiconductor apparatus, manufacturing method therefor and related product

Abstract

The present application relates to a semiconductor apparatus, a manufacturing method therefor and a related product. The semiconductor apparatus comprises a power device and a passive matching circuit. The power device comprises a substrate, an epitaxial layer and an element, the epitaxial layer being deposited to the substrate, the surface of the substrate facing away from the epitaxial layer being a first surface of the power device, the surface of the epitaxial layer facing away from the substrate being a second surface of the power device, and the element being located on the second surface. At least part of the passive matching circuit is located on the first surface, and the passive matching circuit located on the first surface is electrically connected to the power device. The embodiments of the present application arrange on the first surface at least part of the passive matching circuit, so as to fully use the first surface, thus improving the integration of semiconductor devices.

Description

Semiconductor device, manufacturing method thereof, and related products

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 10, 2023, with application number 202311007023.0 and application name “Semiconductor device, manufacturing method thereof, and related products”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and related products. Background Art

[0003] Electronic devices such as mobile phones, watches, headphones, computers, and smart screens are often equipped with semiconductor devices, which use a large number of passive components and circuits. To reduce the size of semiconductor devices and achieve miniaturization, passive component integration technology is often used. However, the integration level of passive matching circuits in current semiconductor devices is relatively low, resulting in the semiconductor devices occupying a large space within the electronic device, which is not conducive to device miniaturization. Therefore, it is necessary to provide a highly integrated semiconductor device.

[0004] Summary of the Invention

[0005] The present invention provides a semiconductor device, a method for manufacturing the same, and related products. These products include, but are not limited to, power amplifiers, radio frequency systems, and electronic devices. The semiconductor device of the present invention has a high degree of integration, facilitating miniaturization of semiconductor devices.

[0006] In a first aspect, embodiments of the present application provide a semiconductor device. The semiconductor device includes a power device and a passive matching circuit. The power device includes a substrate, an epitaxial layer, and a component. The epitaxial layer is deposited on the substrate. The surface of the substrate facing away from the epitaxial layer is the first surface of the power device. The surface of the epitaxial layer facing away from the substrate is the second surface of the power device. The component is located on the second surface. At least a portion of the passive matching circuit is located on the first surface. The passive matching circuit located on the first surface is electrically connected to the power device.

[0007] In some embodiments, the semiconductor device may further include a substrate, and the power device may be fixed to the substrate. It is understood that the first surface may be fixedly connected to the substrate to achieve fixing of the power device to the substrate.

[0008] The embodiments of the present application improve the integration of the semiconductor device by disposing at least a portion of the passive matching circuit on the first surface of the power device. Compared to centrally disposing the passive matching circuit on the substrate, which occupies too much substrate area, or centrally disposing the passive matching circuit on the second surface, which occupies too much second surface area, resulting in a larger semiconductor device with lower integration, the embodiments of the present application dispose at least a portion of the passive matching circuit on the first surface, which can effectively reduce the area occupied by the passive matching circuit on the substrate, or can reduce the area occupied by the passive matching circuit on the second surface, fully utilizing the first surface of the power device, improving the integration of the semiconductor device, and facilitating a reduction in the overall size of the semiconductor device, thereby achieving miniaturization of the semiconductor device.

[0009] In one possible embodiment, the passive matching circuit includes an input matching circuit and an output matching circuit, wherein the input matching circuit is used to input a radio frequency signal into the power device, and the output matching circuit is used to output a radio frequency signal from the power device. At least a portion of the input matching circuit is located on the first surface, or at least a portion of the output matching circuit is located on the first surface. It is understandable that a portion of the input matching circuit may be located on the first surface, or the entire input matching circuit may be located on the first surface, and a portion of the output matching circuit may be located on the first surface, or the entire output matching circuit may be located on the first surface. Compared to a design in which the input matching circuit and the output matching circuit are centrally arranged on the substrate and the second surface, in the embodiment of the present application, at least a portion of the input matching circuit is arranged on the first surface, or at least a portion of the output matching circuit is arranged on the first surface, thereby fully utilizing the first surface and facilitating improved integration of the semiconductor device.

[0010] In some embodiments, the input matching circuit is used to input the radio frequency signal into the power device to the maximum extent possible, and the output matching circuit is used to output the radio frequency signal from the power device to the maximum extent possible, thereby reducing the loss of the radio frequency signal.

[0011] In one possible embodiment, the passive matching circuit includes an interstage matching circuit, which is used to transmit radio frequency signals to the power device, and at least a portion of the interstage matching circuit is located on the first surface. It is understood that the interstage matching circuit can be partially located on the first surface, or the entire interstage matching circuit can be located on the first surface. Compared to the design in which the interstage matching circuit is located on the second surface, the embodiment of the present application arranges at least a portion of the interstage matching circuit on the first surface, fully utilizing the first surface of the power device and facilitating improved integration of the semiconductor device.

[0012] In some embodiments, the inter-stage matching circuit is used to maximize the transmission of radio frequency signals inside the power device, thereby reducing radio frequency signal loss.

[0013] In one possible embodiment, the power device includes a conductive member extending from the first surface to the second surface, the conductive member electrically connecting the component on the second surface with the passive matching circuit on the first surface, or, a portion of the passive matching circuit is located on the second surface, the conductive member electrically connecting the passive matching circuit on the second surface with the passive matching circuit on the first surface. The conductive member can be made of metal and has both thermal and electrical conductivity. The conductive member in the embodiment of the present application can achieve electrical connection between the circuit on the first surface and the circuit or device on the second surface without the need for additional bonding wires or other connection structures. The connection method and process are simple, and the connection path between the passive matching circuit and the device is shortened, which is conducive to improving the integration of the passive matching circuit.

[0014] In one possible embodiment, the input matching circuit and the output matching circuit are spaced apart on the first surface. There is one element, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element. The element may include a source, a drain, and a gate. In this embodiment of the present application, both the input matching circuit and the output matching circuit are disposed on the first surface, fully utilizing the space on the first surface of the power device and facilitating improved integration of the semiconductor device.

[0015] In one possible embodiment, the input matching circuit and the output matching circuit are arranged at intervals on the first surface, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence at intervals and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit. The element may include a source, a drain and a gate. The number of elements can be multiple, which is not limited in this application and can be set as needed. In the embodiment of the present application, the input matching circuit and the output matching circuit are both arranged on the first surface, making full use of the space on the first surface of the power device, which is conducive to improving the integration of the semiconductor device.

[0016] In one possible embodiment, the semiconductor device includes a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; the input matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, and the output matching circuit is located on the first surface, the number of the elements is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element; or, the input matching circuit is located on the first surface, the output matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the number of the elements is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element. In the embodiment of the present application, the input matching circuit or the output matching circuit is located on the first surface, making full use of the space on the first surface of the power device, which is conducive to improving the integration of the semiconductor device.

[0017] In one possible embodiment, the semiconductor device includes a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; the input matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, and the output matching circuit is located on the first surface, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively from the first element to the Nth element, the first element to the Nth element are arranged in sequence and spaced apart, and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit; or, the input matching circuit is located on the first surface, the output matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively from the first element to the Nth element, the first element to the Nth element are arranged in sequence and spaced apart, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit. In the embodiment of the present application, the input matching circuit or the output matching circuit is disposed on the first surface, thereby fully utilizing the space on the first surface of the power device, which is beneficial to improving the integration of the semiconductor device.

[0018] In one possible embodiment, the number of the element is one, and the input matching circuit includes a first input portion and a second input portion that are electrically connected, the first input portion being located on the first surface, the second input portion being located on the second surface, and the second input portion being electrically connected to the element; or, the number of the element is one, and the output matching circuit includes a first output portion and a second output portion that are electrically connected, the first output portion being located on the first surface, the second output portion being located on the second surface, and the second output portion being electrically connected to the element. In the embodiment of the present application, a portion of the input matching circuit (the first input portion) or a portion of the output matching circuit (the first output portion) is disposed on the first surface, fully utilizing the space on the first surface of the power device and facilitating improved integration of the semiconductor device.

[0019] In one possible embodiment, the number of elements is N, where N is an integer greater than or equal to 2, and the N elements are respectively first to Nth elements, the first to Nth elements are sequentially spaced apart, and two adjacent elements are electrically connected. The input matching circuit includes a first input portion and a second input portion that are electrically connected, the first input portion is located on the first surface, the second input portion is located on the second surface, and the second input portion is electrically connected to the first element. Alternatively, the number of elements is N, where N is an integer greater than or equal to 2, and the N elements are respectively first to Nth elements, the first to Nth elements are sequentially spaced apart, and two adjacent elements are electrically connected. The output matching circuit includes a first output portion and a second output portion, the first output portion is located on the first surface, the second output portion is located on the second surface, and the second output portion is electrically connected to the Nth element. In the embodiment of the present application, part of the input matching circuit (first input portion) or part of the output matching circuit (first output portion) is disposed on the first surface, fully utilizing the space on the first surface of the power device and facilitating improved integration of the semiconductor device.

[0020] In one possible embodiment, the semiconductor device includes a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; the number of the elements is N, N is an integer greater than or equal to 2, and the N elements are respectively a first element to an Nth element, the first elements to the Nth elements are arranged in sequence and spaced apart, and two adjacent elements are electrically connected; the input matching circuit includes a first input part, a second input part and the third input part, the first input part is located on the first surface, the second input part is located on the second surface, the second input part is electrically connected to the first element, the second input part is electrically connected to the first input part, and the third input part is located on the surface of the substrate facing the power device and is electrically connected to the The power devices are spaced apart, and the third input portion is electrically connected to the second input portion; or the number of elements is N, where N is an integer greater than or equal to 2, and the N elements are spaced apart from each other in sequence, with adjacent elements electrically connected. The output matching circuit includes a first output portion, a second output portion, and a third output portion. The first output portion is located on the first surface, the second output portion is located on the second surface, the second output portion is electrically connected to the Nth element, the second output portion is electrically connected to the first input portion, and the third output portion is located on the surface of the substrate facing the power devices and spaced apart from the power devices, and the third output portion is electrically connected to the second output portion. Placing the passive matching circuit on the substrate is simple and cost-effective. In this embodiment of the present application, a portion of the input matching circuit (the first input portion) or a portion of the output matching circuit (the first output portion) is disposed on the first surface, fully utilizing the space on the first surface of the power device and facilitating improved integration of the semiconductor device. In this embodiment of the present application, the third input portion or the third output portion is disposed on the substrate, increasing the flexibility of the semiconductor device configuration, allowing passive matching circuits to be disposed on the substrate as needed.

[0021] In one possible embodiment, the passive matching circuit includes an interstage matching circuit, which is located on the first surface and between the input matching circuit and the output matching circuit, and the interstage matching circuit electrically connects two adjacent elements; or, the passive matching circuit includes an interstage matching circuit, which is located on the second surface and between two adjacent elements, and the interstage matching circuit electrically connects two adjacent elements.

[0022] In one possible implementation, the input matching circuit includes at least one of a resistor, a capacitor, or an inductor, and the output matching circuit includes at least one of a resistor, a capacitor, or an inductor. Resistors, capacitors, or inductors, among other components, may be electrically connected to form an output matching circuit or an output matching circuit.

[0023] In a second aspect, the present application provides a method for manufacturing a semiconductor device, which is used to prepare a semiconductor device in any possible embodiment of the first aspect, including: manufacturing a power device, the power device including a substrate, an epitaxial layer and an element, the epitaxial layer being deposited on the substrate, the surface of the substrate facing away from the epitaxial layer being the first surface of the power device, the surface of the epitaxial layer facing away from the substrate being the second surface of the power device, and the element being located on the second surface; forming a passive matching circuit on the power device, at least part of the passive matching circuit being located on the first surface, and the passive matching circuit located on the first surface being electrically connected to the power device.

[0024] In some embodiments, the semiconductor device may further include a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate. It is understood that the first surface may be fixedly connected to the substrate to achieve fixing of the power device to the substrate.

[0025] The embodiments of the present application improve the integration of the semiconductor device by disposing at least a portion of the passive matching circuit on the first surface of the power device. Compared to centrally disposing the passive matching circuit on the substrate, which occupies too much substrate area, or concentrating the passive matching circuit on the second surface, which results in a larger semiconductor device with lower integration, the embodiments of the present application dispose at least a portion of the passive matching circuit on the first surface, making full use of the first surface of the power device, effectively reducing the area occupied by the passive matching circuit on the substrate, or reducing the area occupied by the passive matching circuit on the second surface, thereby improving the integration of the semiconductor device and facilitating its miniaturization.

[0026] In one possible embodiment, the steps of fabricating a power device include: depositing the epitaxial layer on the substrate; forming the component on the second surface; bonding the second surface to a carrier wafer; patterning the substrate and epitaxial layer to form a backhole, wherein the backhole extends from the first surface to the second surface; applying photoresist, patterning the photoresist, exposing and developing the backhole and remaining electroplated areas, and retaining the photoresist in the non-electroplated areas; electroplating metal in the areas not covered by the photoresist; and removing the photoresist in the non-electroplated areas. After forming the passive matching circuit on the power device, the method for fabricating a semiconductor device further includes removing the carrier wafer. Fabricating the passive matching circuit in the non-electroplated areas before removing the carrier wafer can avoid damaging the power device.

[0027] In one possible embodiment, during the patterning process of the photoresist, at least two exposure and development processes are performed, and at least two exposure and development processes partially overlap. Performing at least two exposure and development processes helps prevent photoresist residue. Having at least two exposure and development processes in different and partially overlapping areas can prevent overexposure, which can remove more photoresist and lead to metal plating in areas where metal plating is not required.

[0028] In one possible embodiment, the thickness of the photoresist on the first surface is greater than or equal to 1.2 times the thickness of the metal on the first surface. In the embodiment of the present application, by setting the thickness of the photoresist on the first surface to be greater than or equal to 1.2 times the thickness of the metal on the first surface, it is possible to avoid metal overflowing from the photoresist during metal electroplating, thereby preventing the pattern of the electroplated metal from changing.

[0029] In a third aspect, the present application provides a power amplifier, comprising the semiconductor device described in any one of the aforementioned embodiments. The power amplifier can be used to amplify the power of a radio frequency signal.

[0030] In a fourth aspect, the present application provides a radio frequency system, comprising a radio frequency chip and the power amplifier described in the third aspect, wherein the radio frequency chip is used to send the radio frequency signal to the power amplifier, and the power amplifier is used to amplify the radio frequency signal.

[0031] In a fifth aspect, the present application provides an electronic device comprising a signal output device and the radio frequency system described in the fourth aspect, wherein the signal output device is configured to transmit a signal to the radio frequency system, and the radio frequency system is configured to amplify the signal. The electronic device may be a tablet, a smart screen, a mobile phone, an electronic watch, electronic glasses, headphones, or a router. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0033] FIG1 is a schematic structural diagram of some electronic devices provided in an embodiment of the present application;

[0034] FIG2 is a schematic structural diagram of the radio frequency system shown in FIG1 ;

[0035] FIG3 is a schematic structural diagram of the power amplifier shown in FIG2 ;

[0036] FIG4 is a schematic structural diagram of a semiconductor device shown in FIG3 ;

[0037] FIG5 is a schematic diagram of a stacked structure of a power device of the semiconductor device shown in FIG4 ;

[0038] FIG6 is a schematic structural diagram of another semiconductor device shown in FIG3;

[0039] FIG7 is a schematic structural diagram of another semiconductor device shown in FIG3;

[0040] FIG8 is a schematic structural diagram of another semiconductor device shown in FIG3;

[0041] FIG9 is a schematic structural diagram of another semiconductor device shown in FIG3;

[0042] FIG10 is a flowchart of a semiconductor device fabrication process according to an embodiment of the present application;

[0043] FIG11 is a flowchart of a manufacturing process of a power device provided in an embodiment of the present application;

[0044] FIG12 is a schematic diagram of a structure after bonding an epitaxial layer to a carrier wafer according to an embodiment of the present application;

[0045] FIG13 is a schematic diagram of a structure for forming a back hole provided in an embodiment of the present application;

[0046] FIG14 is a schematic structural diagram of a deposited metal seed layer provided in an embodiment of the present application;

[0047] FIG15 is a schematic structural diagram of performing a first photolithography on a photoresist according to an embodiment of the present application;

[0048] FIG16 is a top view of a photoresist after the first photolithography step provided in an embodiment of the present application;

[0049] FIG17 is a schematic structural diagram of performing a second photolithography on a photoresist according to an embodiment of the present application;

[0050] FIG18 is a schematic diagram of a structure after metal electroplating provided in an embodiment of the present application;

[0051] FIG19 is a scanning electron microscope image of a back hole after focused ion beam cutting according to an embodiment of the present application;

[0052] FIG20 is a schematic diagram of a structure after removing the photoresist and a portion of the metal seed layer according to an embodiment of the present application;

[0053] FIG21 is a schematic structural diagram of a passive matching circuit after deposition provided in an embodiment of the present application;

[0054] FIG22 is a top view of a passive matching circuit after deposition provided in an embodiment of the present application;

[0055] FIG23 is a schematic structural diagram of a power device after debonding the power device and the carrier wafer according to an embodiment of the present application;

[0056] FIG24 is a schematic diagram of a power device obtained by two different methods provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0058] As shown in Figure 1, Figure 1 is a schematic diagram of the structure of some electronic devices 100. The electronic device 100 can be a tablet shown in (a), a smart screen shown in (b), a mobile phone shown in (c), an electronic watch shown in (d), smart glasses shown in (e), headphones shown in (f), or a router shown in (g). This embodiment of the application uses the mobile phone shown in Figure 1 (c) as an example to introduce the electronic device 100.

[0059] The electronic device 100 may include a signal output device 10 and a radio frequency system 20. The signal output device 10 sends a radio frequency signal to the radio frequency system 20. After the radio frequency signal enters the radio frequency system 20, it is amplified by the power amplifier 22 of the radio frequency system 20 and then output to an external receiving device (such as a wireless base station or a communication satellite) through a switch 24 and an antenna 23. For example, the signal output device 10 can send a voice signal to the radio frequency system 20, and the power amplifier 22 of the radio frequency system 20 amplifies the voice signal; the signal output device 10 can send an image signal to the radio frequency system 20, and the power amplifier 22 of the radio frequency system 20 amplifies the image signal; the signal output device 10 can send a video signal to the radio frequency system 20, and the power amplifier 22 of the radio frequency system 20 amplifies the video signal.

[0060] It can be understood that the electronic device 100 in Figure 1 is only schematically represented, and the position, shape, etc. of the signal output device 10 and the radio frequency system 20 can be set as needed. This application does not limit the specific structure of the electronic device 100.

[0061] As shown in Figure 2, Figure 2 is a schematic structural diagram of the RF system 20 shown in Figure 1. The RF system 20 may include a RF chip 21 and a power amplifier 22. The RF chip 21 sends a RF signal to the power amplifier 22, which is used to amplify the RF signal.

[0062] In some embodiments, the RF system 20 may further include an antenna 23, a switch 24, a low-noise amplifier 25, and a filter 26. The RF signal amplified by the power amplifier 22 is transmitted to the antenna 23, which then transmits the RF signal to a base station or a communication satellite (not shown in FIG. 2 ), thereby achieving signal transmission. Alternatively, the base station may transmit the RF signal to the antenna 23, which then transmits the RF signal to the switch 24, which in turn transmits the RF signal to the low-noise amplifier 25 and filter 26, and finally to the RF chip 21, forming an RF signal loop.

[0063] It can be understood that the radio frequency system 20 in FIG. 2 is only schematically shown, and the present application does not limit the specific structure of the radio frequency system 20 .

[0064] FIG3 is a schematic diagram of the structure of the power amplifier 22 shown in FIG2 . The power amplifier 22 may include an output load 222 and a semiconductor device 30 . A radio frequency signal is input to the semiconductor device 30 , amplified by the semiconductor device 30 , and then output to the output load 222 .

[0065] It can be understood that the power amplifier 22 in FIG3 is only schematically shown, and the embodiment of the present application does not limit the specific structure of the power amplifier 22.

[0066] As shown in Figures 4 and 5, Figure 4 is a structural schematic diagram of a semiconductor device 30 shown in Figure 3, and Figure 5 is a schematic diagram of the stacked structure of the power device 32 of the semiconductor device 30 shown in Figure 4. Figure 5 only shows the multi-layer structure of the power device 32, and does not show other structures on the power device 32.

[0067] The semiconductor device 30 may include a power device 32 and a passive matching circuit 33. The passive matching circuit 33 can better utilize the radio frequency output characteristics of the semiconductor device 30.

[0068] The power device 32 may include a substrate 321, an epitaxial layer 322, and components. The substrate 321 may be a silicon-based substrate or a substrate of other materials. The epitaxial layer 322 is deposited onto the substrate 321. The epitaxial layer 322 may include a nucleation layer 3221, a buffer layer 3222, a back barrier layer 3223, a channel layer 3224, an insertion layer 3225, a barrier layer 3226, and a capping layer 3227, which are stacked in sequence. The nucleation layer 3221 provides a foundation for the deposition of other layers. The buffer layer 3222 mitigates stress between the epitaxial layer 322 and the substrate 321. The back barrier layer 3223 improves carrier confinement and reduces leakage channels. The channel layer 3224 provides a carrier path. The insertion layer 3225 reduces carrier scattering and improves carrier mobility. The barrier layer 3226 forms a heterostructure with the channel layer 3224. The capping layer 3227 prevents oxidation.

[0069] The number of elements may be one or at least two. In the embodiment of the present application, the number of elements is two as an example, and the two elements are a first element 34 and a second element 35. The elements may include a source, a drain, and a gate.

[0070] It is understandable that the epitaxial layer 322 in FIG. 5 is merely schematically represented, and the layer structure of the epitaxial layer 322 may also be of other designs and may be specifically adjusted as needed. The embodiment of the present application does not limit the specific structure of the epitaxial layer 322 .

[0071] The surface of the substrate 321 facing away from the epitaxial layer 322 is the first surface 323 of the power device 32, and the surface of the epitaxial layer 322 facing away from the substrate 321 is the second surface 324 of the power device 32. The first element 34 and the second element 35 are located on the second surface 324.

[0072] At least a portion of the passive matching circuit 33 is disposed on the first surface 323. The passive matching circuit 33 located on the first surface 323 is electrically connected to the power device 32. It is understandable that in the semiconductor device 30, a portion of the passive matching circuit 33 can be disposed on the first surface 323, or all of the passive matching circuit 33 of the semiconductor device 30 can be disposed on the first surface 323.

[0073] In some embodiments, the semiconductor device 30 further includes a substrate 31, which may be a circuit board or a flexible circuit board. The power device 32 is fixed to the substrate 31, with the first surface 323 located between the second surface 324 and the substrate 31. The first surface 323 may contact and be fixedly connected to the substrate 31, and the power device 32 and the substrate 31 may be electrically connected.

[0074] The embodiment of the present application improves the integration of the semiconductor device 30 by disposing at least a portion of the passive matching circuit 33 on the first surface 323 of the power device 32. In the prior art, the passive matching circuit 33 is concentrated on the surface of the substrate 31, occupying too much area of ​​the substrate 31, or the passive matching circuit 33 is concentrated on the second surface 324, which increases the size of the required power device 32, resulting in a larger volume and lower integration of the semiconductor device 30. The embodiment of the present application can dispose at least a portion of the passive matching circuit 33 originally disposed on the substrate 31 or the second surface 324 on the first surface 323, making full use of the space on the first surface 323 of the power device 32, effectively reducing the area occupied by the passive matching circuit 33 on the substrate 31, or reducing the area occupied by the passive matching circuit 33 on the second surface 324, thereby improving the integration of the semiconductor device 30, and facilitating the reduction of the overall size of the semiconductor device 30, thereby achieving miniaturization of the semiconductor device 30.

[0075] In some embodiments, the passive matching circuit 33 may include an input matching circuit 331 and an output matching circuit 332. At least a portion of the input matching circuit 331 is located on the first surface 323, or at least a portion of the output matching circuit 332 is located on the first surface 323. The input matching circuit 331 is used to input the RF signal into the power device 32, and the output matching circuit 332 is used to output the RF signal from the power device 32. It is understood that part or all of the input matching circuit 331 may be located on the first surface 323, and part or all of the output matching circuit 332 may be located on the first surface 323. At least a portion of the input matching circuit 331 is located on the first surface 323, or at least a portion of the output matching circuit 332 is located on the first surface 323, or at least a portion of the input matching circuit 331 is located on the first surface 323 and at least a portion of the output matching circuit 332 is located on the first surface 323.

[0076] In some embodiments, the input matching circuit 331 is used to achieve impedance matching between the RF signal source and the first element 34, so that the RF signal is transmitted to the first element 34 to the maximum extent, and almost no signal is reflected back to the RF signal source, thereby reducing the loss of the RF signal.

[0077] Compared to the design in which the input matching circuit 331 and the output matching circuit 332 are centrally arranged on the substrate 31 and the second surface 324, in the embodiment of the present application, at least part of the input matching circuit 331 is arranged on the first surface 323, or at least part of the output matching circuit 332 is arranged on the first surface 323, thereby making full use of the first surface 323 of the power device 32 and facilitating improvement of the integration of the semiconductor device 30.

[0078] The input matching circuit 331 may include at least one of a resistor, a capacitor, or an inductor, and the output matching circuit 332 may include at least one of a resistor, a capacitor, or an inductor. Resistors, capacitors, or inductors are electrically connected to form the input matching circuit 331 or the output matching circuit 332.

[0079] In some embodiments, the passive matching circuit 33 may include an inter-stage matching circuit 333, which is used to transmit radio frequency signals to the power device. At least a portion of the inter-stage matching circuit 333 is located on the first surface 323. It is understood that the inter-stage matching circuit 333 may be partially located on the first surface 323, or the entire inter-stage matching circuit 333 may be located on the first surface 323. Compared to the design in which the inter-stage matching circuit 333 is located on the second surface 324, in the embodiment of the present application, at least a portion of the inter-stage matching circuit 333 is disposed on the first surface 323, fully utilizing the first surface 323 and facilitating improved integration of the semiconductor device 30.

[0080] In some embodiments, the inter-stage matching circuit 333 is used to perform impedance matching between the output end of the previous stage element and the input end of the subsequent stage element, so that the RF signal can be transmitted in the power device almost without reflection, thereby reducing the loss of the RF signal.

[0081] The inter-stage matching circuit 333 may include at least one of a resistor, a capacitor, or an inductor. The resistor, capacitor, or inductor components are electrically connected to each other to form the inter-stage matching circuit 333 .

[0082] In some embodiments, the power device 32 may include a conductive member extending from the first surface 323 to the second surface 324. The conductive member may be used to electrically connect the components on the second surface 324 to the passive matching circuit on the first surface 323. Alternatively, when part of the passive matching circuit is located on the second surface 324, the conductive member may be used to electrically connect the passive matching circuit on the second surface 324 to the passive matching circuit on the first surface 323. The conductive member has both thermal and electrical conductivity. The conductive member in the embodiments of the present application can electrically connect the passive matching circuit on the first surface 323 to the passive matching circuit or device on the second surface 324 without requiring additional bonding wires or other connection structures. The connection method and process are simple, and the connection path between the passive matching circuit and the device is shortened, thereby improving the integration of the semiconductor device 30.

[0083] As shown in Figure 4, in some embodiments, the input matching circuit 331 and the output matching circuit 332 are arranged at intervals on the first surface 323, and the number of elements is N, where N is an integer greater than or equal to 2, and the N elements are respectively the first element 34 to the Nth element. The first element 34 to the Nth element are arranged at intervals in sequence and any two adjacent elements are electrically connected. The input matching circuit 331 is electrically connected to the first element 34, and the Nth element is electrically connected to the output matching circuit 332.

[0084] In some embodiments, the inter-stage matching circuit 333 is located on the first surface 323 and between the input matching circuit 331 and the output matching circuit 332 . The inter-stage matching circuit 333 electrically connects two adjacent elements.

[0085] FIG4 uses an example in which two components are provided, i.e., N is equal to 2. The two components are a first component 34 and a second component 35, which are arranged in an alternating pattern. The input matching circuit 331, the inter-stage matching circuit 333, and the output matching circuit 332 are sequentially arranged in an alternating pattern on the first surface 323, fully utilizing the space on the first surface 323 of the power device 32 and facilitating improved integration of the semiconductor device 30. It is understood that if the input matching circuit 331 and the output matching circuit 332 are located on the substrate 31, they would occupy space on the substrate 31, requiring a larger design and lowering the integration of the semiconductor device 30. Alternatively, if the input matching circuit 331 and the output matching circuit 332 are located on the second surface 324, the power device 32 would require a larger design and lowering the integration of the semiconductor device 30. By disposing the input matching circuit 331, the inter-stage matching circuit 333, and the output matching circuit 332 on the first surface 323, the space on the first surface 323 of the power device 32 is fully utilized, effectively improving the integration of the semiconductor device 30.

[0086] The power device 32 may include a first conductive member 325, a second conductive member 326, a third conductive member 327, and a fourth conductive member 328. The first conductive member 325 to the fourth conductive member 328 are spaced apart and extend from the first surface 323 to the second surface 324. The first conductive member 325 to the fourth conductive member 328 may be made of metal.

[0087] It can be understood that the number of conductive parts can be one, two, three or four, etc. The embodiment of the present application takes the number of conductive parts as four as an example. For the purpose of distinction, the four conductive parts are the first conductive part 325, the second conductive part 326, the third conductive part 327 and the fourth conductive part 328.

[0088] The input matching circuit 331 and the first element 34 can be electrically connected via the first conductive member 325, the first element 34 and the inter-stage matching circuit 333 can be electrically connected via the second conductive member 326, the inter-stage matching circuit 333 and the second element 35 can be electrically connected via the third conductive member 327, and the second element 35 and the output matching circuit 332 can be electrically connected via the fourth conductive member 328. In the embodiment of the present application, the input matching circuit 331, the inter-stage matching circuit 333, and the output matching circuit 332 located on the first surface 323 are electrically connected to the first element 34 and the second element 35 located on the second surface 324 by using the existing first conductive member 325 to fourth conductive member 328 of the power device 32. No additional bonding wires or other connection structures are required, the connection method and process are simple, and the connection path is short.

[0089] In some embodiments, the number of the element may be one, and the input matching circuit 331 and the output matching circuit 332 are alternately arranged on the first surface 323 . The input matching circuit 331 is electrically connected to the element, and the output matching circuit 332 is electrically connected to the element.

[0090] FIG6 is a schematic diagram illustrating the structure of another semiconductor device 30 shown in FIG3 . The structure of the semiconductor device 30 shown in FIG6 differs from that of the semiconductor device 30 shown in FIG4 in that an inter-stage matching circuit 333 of the semiconductor device 30 shown in FIG6 is located on the second surface 324 and between two adjacent components (the first component 34 and the second component 35 ). The inter-stage matching circuit 333 electrically connects the two adjacent components (the first component 34 and the second component 35 ).

[0091] The power device 32 may include two conductive members, namely a first conductive member 325 and a second conductive member 326. The first conductive member 325 and the second conductive member 326 are spaced apart and extend from the first surface 323 to the second surface 324. The input matching circuit 331 and the first element 34 are electrically connected via the first conductive member 325, and the second element 35 and the output matching circuit 332 are electrically connected via the second conductive member 326.

[0092] In the embodiment of the present application, both the input matching circuit 331 and the output matching circuit 332 are disposed on the first surface 323, fully utilizing the space on the first surface 323 of the power device 32, thereby facilitating improved integration of the semiconductor device 30. In the embodiment of the present application, the input matching circuit 331 and the output matching circuit 332 located on the first surface 323 are electrically connected to the first element 34 and the second element 35 located on the second surface 324 by utilizing the existing first conductive member 325 and the second conductive member 326 of the power device 32. No additional bonding wires or other connection structures are required, resulting in a simple connection method and process, and a short connection path.

[0093] As shown in FIG7 , FIG7 is a schematic structural diagram of another semiconductor device 30 shown in FIG3 . In some embodiments, the input matching circuit 331 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32. The output matching circuit 332 is located on the first surface 323 . The number of elements is N, where N is an integer greater than or equal to 2. The N elements are respectively the first element 34 to the Nth element. The first element 34 to the Nth element are sequentially spaced apart and any two adjacent elements are electrically connected. The input matching circuit 331 is electrically connected to the first element 34, and the Nth element is electrically connected to the output matching circuit 332.

[0094] FIG7 takes the example of two components, i.e., N equals 2, as an example. The two components are a first component 34 and a second component 35, and the first component 34 and the second component 35 are arranged at intervals. For example, the semiconductor device 30 further includes bonding wires 36. The first component 34, the inter-stage matching circuit 333, and the second component 35 are sequentially arranged at intervals on the second surface 324, and the inter-stage matching circuit 333 electrically connects the first component 34 and the second component 35.

[0095] The output matching circuit 332 is located on the first surface 323, and the input matching circuit 331 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32. The first conductive member 325 electrically connects the output matching circuit 332 and the second element 35, and the bonding wire 36 electrically connects the input matching circuit 331 and the first element 34. In the embodiment of the present application, the output matching circuit 332 is disposed on the first surface 323, fully utilizing the space on the first surface 323 of the power device 32, which is conducive to improving the integration of the semiconductor device 30. In the embodiment of the present application, the output matching circuit 332 located on the first surface 323 and the second element 35 located on the second surface 324 are electrically connected by using the existing first conductive member 325 of the power device 32. This connection method and process are simple, and the connection path is short.

[0096] In other embodiments, the input matching circuit 331 may be located on the first surface 323, and the output matching circuit 332 may be located on the surface of the substrate 31 facing the power device 32 and spaced apart from the power device 32. The number of components is N, where N is an integer greater than or equal to 2. The N components are arranged from the first component 34 to the Nth component, and adjacent components are electrically connected. The input matching circuit 331 is electrically connected to the first component 34, and the Nth component is electrically connected to the output matching circuit 332. For example, the input matching circuit 331 is located on the first surface 323, and the output matching circuit 332 is located on the surface of the substrate 31 facing the power device 32 and spaced apart from the power device 32. A first conductive member 325 connects the input matching circuit 331 to the first component 34, and a bonding wire 36 connects the output matching circuit 332 to the second component 35. In this embodiment, the input matching circuit 331 is located on the first surface 323, fully utilizing the space on the first surface 323 of the power device 32, thereby increasing the integration density of the semiconductor device 30. In the embodiment of the present application, the input matching circuit 331 located on the first surface 323 and the first element 34 located on the second surface 324 are electrically connected by using the existing first conductive member 325 of the power device 32. The connection method and process are simple, and the connection path is short.

[0097] In other embodiments, the inter-stage matching circuit 333 may be located on the first surface 323, and the inter-stage matching circuit 333 electrically connects the first element 34 and the second element 35. In other embodiments, the inter-stage matching circuit 333 may not be provided.

[0098] In some embodiments, the input matching circuit 331 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32, the output matching circuit 332 is located on the first surface 323, there is one element, the input matching circuit 331 is electrically connected to the element, and the output matching circuit 332 is electrically connected to the element. Alternatively, the input matching circuit 331 is located on the first surface 323, the output matching circuit 332 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32, there is one element, the input matching circuit 331 is electrically connected to the element, and the output matching circuit 332 is electrically connected to the element.

[0099] As shown in FIG8 , FIG8 is a schematic structural diagram of another semiconductor device 30 shown in FIG3 . In some embodiments, the number of elements is N, where N is an integer greater than or equal to 2, and the N elements are respectively the first element 34 to the Nth element, the first element 34 to the Nth element are arranged in sequence and spaced apart, and two adjacent elements are electrically connected, the input matching circuit 331 includes a first input portion 3311 and a second input portion 3312 that are electrically connected, the first input portion 3311 is located on the first surface 323, the second input portion 3312 is located on the second surface 324, and the second input portion 3312 is electrically connected to the first element 34; or, the number of elements is N, where N is an integer greater than or equal to 2, and the N elements are respectively the first element 34 to the Nth element, the first element 34 to the Nth element are arranged in sequence and spaced apart, and two adjacent elements are electrically connected, the output matching circuit 332 includes a first output portion 3321 and a second output portion 3322, the first output portion 3321 is located on the first surface 323, the second output portion 3322 is located on the second surface 324, and the second output portion 3322 is electrically connected to the Nth element.

[0100] For example, FIG8 illustrates a case where there are two components, i.e., N is equal to 2. The two components are a first component 34 and a second component 35, which are arranged alternately. The power device 32 includes a first conductive member 325 and a second conductive member 326. The input matching circuit 331 includes a first input portion 3311 and a second input portion 3312. The first input portion 3311 is located on the first surface 323, and the second input portion 3312 is located on the second surface 324. The second input portion 3312 is electrically connected to the first component 34. The first conductive member 325 electrically connects the first input portion 3311 and the second input portion 3312. The output matching circuit 332 includes a first output portion 3321 and a second output portion 3322. The first output portion 3321 is located on the first surface 323, and the second output portion 3322 is located on the second surface 324. The second output portion 3322 is electrically connected to the second component 35. The second conductive member 326 electrically connects the first output portion 3321 and the second output portion 3322. The second input portion 3312 , the first element 34 , the inter-stage matching circuit 333 , the second element 35 and the second output portion 3322 are sequentially arranged on the second surface 324 .

[0101] In the embodiment of the present application, part of the input matching circuit (i.e., the first input part 3311) and part of the output matching circuit (i.e., the first output part 3321) are both arranged on the first surface 323, making full use of the space on the first surface 323 of the power device 32, which is beneficial to improving the integration of the semiconductor device 30.

[0102] In other embodiments, the first input part 3311 and the second input part 3312 of the input matching circuit 331 can both be located on the first surface 323, that is, the entire input matching circuit 331 is located on the first surface 323, the first output part 3321 of the output matching circuit 332 is located on the first surface 323, and the second output part 3322 is located on the second surface 324.

[0103] In other embodiments, the first input part 3311 of the input matching circuit 331 is located on the first surface 323, the second input part 3312 is located on the second surface 324, and the first output part 3321 and the second output part 3322 of the output matching circuit 332 can both be located on the first surface 323, that is, all the output matching circuits 332 are located on the first surface 323.

[0104] In other embodiments, the inter-stage matching circuit 333 may also include two parts, one part of the inter-stage matching circuit 333 may be located on the first surface 323 of the power device 32, and the other part of the inter-stage matching circuit 333 may be located on the second surface 324 of the power device 32. Alternatively, the entire inter-stage matching circuit 333 may be located on the first surface 323 and between the input matching circuit 331 and the output matching circuit 332, and the inter-stage matching circuit 333 may electrically connect two adjacent components.

[0105] It can be understood that when the input matching circuit 331, the output matching circuit 332 or the inter-stage matching circuit 333 has many devices, concentrating them in one area will occupy too much space in this area. Therefore, the input matching circuit 331, the output matching circuit 332 or the inter-stage matching circuit 333 can be divided into multiple parts, and the multiple parts can be distributed in different areas to reasonably and fully utilize the space of the semiconductor device 30 and improve the integration of the semiconductor device 30.

[0106] In some embodiments, the number of components is one, and input matching circuit 331 includes an electrically connected first input portion 3311 and a second input portion 3312. First input portion 3311 is located on first surface 323, second input portion 3312 is located on second surface 324, and second input portion 3312 is electrically connected to the component. Alternatively, the number of components is one, and output matching circuit 332 includes an electrically connected first output portion 3321 and a second output portion 3322. First output portion 3321 is located on first surface 323, second output portion 3322 is located on second surface 324, and second output portion 3322 is electrically connected to the component.

[0107] As shown in FIG9 , FIG9 is a schematic structural diagram of another semiconductor device 30 shown in FIG3 . The semiconductor device 30 shown in FIG9 differs from the semiconductor device shown in FIG8 in that, in the embodiment of the present application, the input matching circuit 331 further includes a third input portion 3313. The third input portion 3313 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32. The third input portion 3313 is electrically connected to the second input portion 3312. For example, the third input portion 3313 can be connected to the second input portion 3312 via a bonding wire. The output matching circuit 332 further includes a third output portion 3323. The third output portion 3323 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32. The third output portion 3323 is electrically connected to the second output portion 3322. For example, the third output portion 3323 can be connected to the second output portion 3322 via a bonding wire. The second input portion 3312 , the first element 34 , the inter-stage matching circuit 333 , the second element 35 and the second output portion 3322 are sequentially arranged on the second surface 324 .

[0108] Placing the passive matching circuit on the substrate 31 is simple and cost-effective. In the embodiment of the present application, the third input portion 3313 and the third output portion 3323 are disposed on the substrate 31, thereby increasing the flexibility of the semiconductor device 30 and allowing a passive matching circuit to be disposed on the substrate 31 as needed.

[0109] In other embodiments, the input matching circuit 331 may include the third input part 3313 and the output matching circuit 332 may not include the third output part 3323 , or the input matching circuit 331 may not include the third input part 3313 and the output matching circuit 332 may include the third output part 3323 .

[0110] The present application provides a method for manufacturing a semiconductor device 30, which is used to prepare any of the aforementioned semiconductor devices 30, as shown in FIG10 , which is a flowchart for manufacturing the semiconductor device 30. The method for manufacturing the semiconductor device 30 in one embodiment specifically includes the following steps:

[0111] T10. Produce a power device 32.

[0112] Referring to Figures 4 and 5, the power device 32 may include a substrate 321, an epitaxial layer 322, and components. The epitaxial layer 322 is deposited on the substrate 321. The substrate 321 may be a silicon-based substrate or a substrate of other materials. The surface of the substrate 321 facing away from the epitaxial layer 322 is the first surface 323 of the power device 32, and the surface of the epitaxial layer 322 facing away from the substrate 321 is the second surface 324 of the power device 32. The components are located on the second surface 324. The number of components may be one or at least two. In the embodiment of the present application, the number of components is two as an example, and the two components are a first component 34 and a second component 35. The components may include a source, a drain, and a gate.

[0113] T20 . Form a passive matching circuit 33 on the power device 32 , where at least a portion of the passive matching circuit 33 is located on the first surface 323 of the power device 32 .

[0114] It is understandable that in the semiconductor device 30 , part of the passive matching circuit 33 may be disposed on the first surface 323 , or all of the passive matching circuit 33 may be disposed on the first surface 323 . The passive matching circuit on the first surface 323 is electrically connected to the power device 32 .

[0115] In the embodiment of the present application, the passive matching circuit 33 originally set on the substrate 31 or at least part of the second surface 324 can be set on the first surface 323, thereby fully utilizing the space on the first surface 323 of the power device 32, effectively reducing the area occupied by the passive matching circuit 33 on the substrate 31, or reducing the area occupied by the passive matching circuit 33 on the second surface 324, thereby improving the integration of the semiconductor device 30, and facilitating reducing the overall size of the semiconductor device 30 and realizing the miniaturization of the semiconductor device 30.

[0116] In some embodiments, the passive matching circuit 33 may include an input matching circuit 331 and an output matching circuit 332, with at least a portion of the input matching circuit 331 being located on the first surface 323, or at least a portion of the output matching circuit 332 being located on the first surface 323. It is understood that the input matching circuit 331 may be located on the first surface 323, or the entire input matching circuit 331 may be located on the first surface 323, and the output matching circuit 332 may be located on the first surface 323, or the entire output matching circuit may be located on the first surface 323. At least a portion of the input matching circuit 331 may be located on the first surface 323, or at least a portion of the output matching circuit 332 may be located on the first surface 323, or at least a portion of the input matching circuit 331 may be located on the first surface 323 and at least a portion of the output matching circuit 332 may be located on the first surface 323.

[0117] Compared to the design in which the input matching circuit 331 and the output matching circuit 332 are centrally arranged on the substrate 31 and the second surface 324, in the embodiment of the present application, at least part of the input matching circuit 331 is arranged on the first surface 323, or at least part of the output matching circuit 332 is arranged on the first surface 323, thereby making full use of the first surface 323 and facilitating improvement of the integration of the semiconductor device 30.

[0118] The input matching circuit 331 may include at least one of a resistor, a capacitor, or an inductor, and the output matching circuit 332 may include at least one of a resistor, a capacitor, or an inductor. Resistors, capacitors, or inductors are electrically connected to form the input matching circuit 331 or the output matching circuit 332.

[0119] In some embodiments, the passive matching circuit 33 may include an inter-stage matching circuit 333, at least a portion of which is located on the first surface 323. It is understood that the inter-stage matching circuit 333 may be partially or entirely located on the first surface 323. Compared to the design in which the inter-stage matching circuit 333 is located on the second surface 324, in the embodiment of the present application, at least a portion of the inter-stage matching circuit 333 is located on the first surface 323, fully utilizing the first surface 323 and facilitating improved integration of the semiconductor device 30.

[0120] The inter-stage matching circuit 333 may include at least one of a resistor, a capacitor, or an inductor. The resistor, capacitor, or inductor components are electrically connected to each other to form the inter-stage matching circuit 333 .

[0121] In some embodiments, a power device 32 equipped with a passive matching circuit 33 is fixed to a substrate 31. The substrate 31 can be a circuit board or a flexible circuit board. The power device 32 is fixed to the substrate 31, with the first surface 323 located between the second surface 324 and the substrate 31. The first surface 323 can be in contact with and fixedly connected to the substrate 31. The power device 32 and the substrate 31 can be electrically connected.

[0122] As shown in FIG11 , FIG11 is a flowchart of manufacturing a power device 32 . In one embodiment, manufacturing a power device 32 specifically includes the following steps:

[0123] T101 . Deposit an epitaxial layer 322 on a substrate 321 .

[0124] Referring to FIG5 , substrate 321 can be a silicon-based substrate or a substrate of other materials. Epitaxial layer 322 can include a nucleation layer 3221, a buffer layer 3222, a back barrier layer 3223, a channel layer 3224, an insertion layer 3225, a barrier layer 3226, and a cap layer 3227, stacked in sequence. It will be appreciated that the epitaxial layer 322 in FIG5 is merely schematic, and the layer structure of epitaxial layer 322 can also be designed in other ways, which can be specifically configured as needed.

[0125] T102 , forming components on the second surface 324 .

[0126] After depositing the epitaxial layer 322, an element (not shown in FIG5 , see FIG4 and FIG12 ) may be deposited on the second surface 324. The number of elements may be one or at least two. In the embodiment of the present application, two elements are used as an example, and the two elements are a first element 34 and a second element 35. The elements may include a source 3202, a drain, and a gate.

[0127] The second surface 324 is subjected to dielectric protection. For example, a photoresist, an insulating layer, an oxide layer, etc. can be provided on the second surface 324. The dielectric protection can be used to protect the devices on the second surface 324 and prevent the devices on the second surface 324 from being damaged during subsequent processing.

[0128] T103. Bond the second surface 324 to the carrier wafer 3201.

[0129] Referring to Figure 12 , FIG12 illustrates the structure after epitaxial layer 322 is bonded to carrier wafer 3201. Carrier wafer 3201 can be made of glass, silicon carbide, or silicon. Epitaxial layer 322 can be bonded to carrier wafer 3201 using bonding adhesive 3203, firmly securing substrate 321 and epitaxial layer 322 to carrier wafer 3201. Bonding adhesive 3203 can be resin or paraffin wax, for example.

[0130] After bonding the substrate 321 and epitaxial layer 322 to the carrier 3201, the substrate 321 can be thinned. For example, mechanical grinding can be used to thin the substrate 321. After thinning, the thickness of the substrate 321 and epitaxial layer 322 can be less than or equal to 200 μm. Thinning the substrate 321 can reduce the overall thickness of the substrate 321 and epitaxial layer 322, shortening the transmission path, thereby achieving better heat dissipation and reducing ground parasitic inductance.

[0131] Due to thermal stress, the substrate 321 may crack due to stress release after thinning, causing the power device 32 to be easily damaged during subsequent processing. Therefore, the substrate 321 and the epitaxial layer 322 need to be bonded to the carrier 3201 before thinning. The carrier 3201 can prevent the substrate 321 and the epitaxial layer 322 from warping or cracking during subsequent processing.

[0132] T104 , patterning the substrate 321 and the epitaxial layer 322 to form a back hole 3204 .

[0133] Referring to FIG. 13 , FIG. 13 is a schematic diagram of the structure for forming the back hole 3204. Before etching the substrate 321 and epitaxial layer 322, the etched area needs to be patterned. A photolithography process can be used to pattern the back hole 3204. The substrate 321 and epitaxial layer 322 are etched using a photoresist mask. The etching process can be dry deep reactive ion etching, inductively coupled plasma, or a potassium hydroxide wet etching process. A combination of dry and wet etching can also be used to etch through the substrate 321 to the source electrode 3202 on the second surface 324. It is understood that the back hole 3204 extends from the first surface 323 to the second surface 324. After etching to form the back hole 3204, the photoresist mask on the second surface 324 is removed.

[0134] Refer to Figure 14, which is a schematic diagram of the structure of the deposited metal seed layer 3205. The metal seed layer 3205 is deposited on the first surface 323 and the inner wall of the back hole 3204. The provision of the metal seed layer 3205 is conducive to the subsequent electroplating of metal, and is conducive to the electroplating of thicker metals. The thickness of the metal seed layer 3205 can be 10nm to 1um, and the thickness of the metal seed layer 3205 is not limited in the embodiment of the present application. The material of the metal seed layer 3205 can be metals such as copper, gold, tungsten, nickel, tin, etc., and can also be alloy materials such as titanium tungsten and titanium gold. It can be understood that in other embodiments, the metal seed layer 3205 may not be provided.

[0135] In some embodiments, before depositing the metal seed layer 3205, an adhesion layer (not shown in FIG14 ) may be deposited on the first surface 323 and the inner wall of the back hole 3204. The adhesion layer may be used to adhere the metal seed layer 3205. The adhesion layer may be made of titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0136] T105 , coating a photoresist 3206 and patterning the photoresist 3206 .

[0137] 15 , 16 and 17 , FIG. 15 is a schematic structural diagram of the first photolithography process on the photoresist 3206 , FIG. 16 is a top view of the photoresist 3206 after the first photolithography process, and FIG. 17 is a schematic structural diagram of the second photolithography process on the photoresist 3206 .

[0138] The photoresist 3206 is patterned, and the back hole 3204 and the remaining electroplated areas are exposed and developed, while the photoresist in the non-electroplated areas is retained. It is understood that the remaining electroplated areas refer to the areas on the first surface 323 that require metal plating. In the embodiment of the present application, metal plating is subsequently required in the back hole 3204 and the areas on the first surface 323 that require metal plating. During the patterning process of the photoresist, at least two exposure and development processes are performed, and at least the areas subjected to the two exposure and development processes partially overlap.

[0139] Photoresist 3206 can be applied in a single or multiple layers by spin coating. For example, the spin coating process can be performed at a spin speed of 2500 to 5000 rpm, a pre-bake temperature of 100°C, and a pre-bake time of 2 to 4 minutes. The spin speed and baking temperature significantly affect the thickness of photoresist 3206. The specific thickness is determined by the thickness of the metal to be electroplated and is not limited in the present embodiment.

[0140] In some embodiments, the thickness of the photoresist 3206 on the first surface 323 is greater than or equal to 1.2 times the thickness of the metal on the first surface 323 (see Figure 18 for the setting of the metal on the first surface 323), which can prevent the metal from overflowing the photoresist and causing the pattern of the electroplated metal to change when electroplating the metal.

[0141] Referring to FIG. 15 , the first photolithography step is performed. The photomask 3027 is configured so that the first exposure area includes the backhole 3204 and the remaining plated areas, leaving the photoresist in the non-plated areas. Exposure is performed using a discontinuous exposure method, employing contact exposure. For example, the light source is turned on for 5.5 to 11 seconds, then turned off for a 5 to 10 second pause. This cycle repeats multiple times, and after exposure, the first development step is performed.

[0142] Using multiple exposures can thoroughly expose the thicker photoresist at the edge of the back hole 3204. When spin-coating photoresist 3206 on the first surface 323 of the power device with the back hole 3204, the glue is first dripped into the center of the first surface 323. Under the action of centrifugal force, the photoresist 3206 quickly flows to the edge of the first surface 323. However, the back hole 3204 blocks the flow of liquid photoresist 3206, making the photoresist 3206 at the edge of the back hole 3204 thicker than other areas of the first surface 323. If a continuous exposure method is used, the photoresist 3206 at the edge of the back hole 3204 is too thick and cannot be photosensitively denatured in time, making it difficult to be thoroughly exposed. However, using a discontinuous exposure method, the photoresist 3206 gradually photosensitively denatures in the thickness direction, and is ultimately thoroughly exposed and developed. In this step, the back hole 3204 area and the remaining electroplating areas are exposed and developed. As can be seen in Figure 16, the back hole 3204 is exposed.

[0143] After the first photolithography, the photoresist at the bottom and sidewalls of the back hole 3204 is difficult to be completely exposed because it is farther away from the light source than the photoresist at the first surface 323. Therefore, it is necessary to expose again to remove the photoresist at the bottom and sidewalls of the back hole 3204.

[0144] Referring to Figure 17 , a second photolithography process is performed. To prevent overexposure of the larger pattern area from the first photolithography process (overexposure would remove more photoresist, allowing metal plating in areas where metal plating is not required), the second photolithography process exposes only the backhole 3204 area. The aperture of this exposed area is generally slightly larger than that of backhole 3204 due to systematic errors in photolithography alignment. The second exposure also uses a discontinuous exposure method: the light source is turned on for 5.5 to 11 seconds, then turned off for a 5 to 10 second pause. This cycle repeats multiple times before the second development process is performed.

[0145] It is understood that after the first photolithography, the photoresist in the non-electroplating area remains after exposure and development and is not removed, and then the photolithography of the back hole 3204 is performed. If photoresist residue still remains on the bottom and sidewalls of the back hole 3204 after the second exposure and development, a third or more photolithography passes are performed to eliminate any photoresist residue on the bottom and sidewalls of the back hole 3204. Except for the first photolithography pass, the exposed areas of the remaining photolithography passes are all the areas of the back hole 3204.

[0146] It is understandable that the second photolithography shown in FIG. 17 may be performed first, and then the first photolithography shown in FIG. 15 may be performed.

[0147] T106. Electroplate metal in the areas not covered by photoresist 3206.

[0148] Referring to FIG. 18 , FIG. 18 is a schematic diagram of the structure after metal plating. After patterning the photoresist 3206, electroplating can be performed. The areas covered by the photoresist 3206 (i.e., the non-electroplating areas) cannot be electroplated with metal, while the areas not covered by the photoresist 3206 (i.e., the electroplating areas) can be electroplated with metal to form conductive members (e.g., the first conductive member 325). The material of the electroplated metal can be a metal or alloy such as copper, gold, tin, nickel, etc.

[0149] Figure 19 is a scanning electron microscope image of the back hole 3204 after focused ion beam cutting. As can be seen from Figure 19, after multiple exposures, there is no photoresist residue in the back hole 3204, the electroplated metal is well bonded to the substrate and epitaxial layer, and the electroplated metal effect is good.

[0150] 18 , the back hole 3204 is completely occupied by the plated metal. In other embodiments, the metal may be plated only on the bottom and sidewalls of the back hole 3204 , and the back hole 3204 still has a hollow space.

[0151] T107, remove photoresist 3206.

[0152] Referring to FIG. 20 , FIG. 20 illustrates the structure after removing the photoresist 3206 and partially removing the metal seed layer 3205. The photoresist 3206 in the non-electroplated areas is removed, and the metal seed layer 3205 on the first surface 323 that is not covered by the electroplated metal is etched away, thereby achieving patterning of the electroplated metal. The photoresist 3206 can be washed away with an organic solution. The metal seed layer 3205 can be etched using methods such as ion beam etching and inductively coupled plasma etching.

[0153] Since the thickness of the metal seed layer 3205 is thinner than the thickness of the electroplated metal (the thickness of the metal seed layer 3205 is generally 10nm~1um, while the electroplated metal is generally above 3um, and the thickness of the electroplated metal is generally thicker to improve the heat transfer and conductivity of the electroplated metal), when the metal seed layer 3205 is etched by the whole-surface etching method in this step, although part of the metal electroplated at the bottom of the back hole 3204 will also be etched, due to the thin thickness of the metal seed layer 3205, the damage to the metal electroplated at the bottom of the back hole 3204 is relatively small, and the metal at the bottom of the back hole 3204 still has a relatively thick thickness.

[0154] Referring to Figures 21 and 22, Figure 21 is a schematic diagram of the structure after the passive matching circuit is deposited, and Figure 22 is a top view of the structure after the passive matching circuit is deposited. The area on the first surface 323 that is not covered with metal (which can be understood as the non-electroplating area or the passive matching circuit fabrication area) can be used to fabricate passive components and passive matching circuits. The passive components can include at least one of resistors, capacitors, or inductors. The passive components are connected via interconnects to form the passive matching circuit 33.

[0155] Before removing the carrier 3201, fabricating the passive matching circuit 33 in the non-electroplating area can avoid damaging the power device. Power devices are relatively thin, and fabricating the passive matching circuit 33 on thinner power devices can easily damage the power device. The carrier 3201 can reduce damage to the power device during the fabrication process of the passive matching circuit 33.

[0156] The conductive member can realize electrical connection between the passive matching circuit on the first surface 323 and the passive matching circuit or device on the second surface 324 , shortening the connection path between the passive matching circuit and the device, and improving the integration of the semiconductor device 30 .

[0157] Referring to Figure 23, Figure 23 illustrates the structure of power device 32 after debonding the power device 32 from carrier wafer 3201. After forming the passive matching circuit on the power device, the semiconductor device fabrication method further includes debonding the power device 32 from carrier wafer 3201 to remove the carrier wafer 3201, and then performing subsequent testing, dicing, packaging, and taping processes. Debonding the power device 32 from carrier wafer 3201 can be performed by heating the bonding adhesive or dissolving the bonding adhesive in a solution.

[0158] The semiconductor device 30 formed by mounting the power device 32 provided with the passive matching circuit 33 on the substrate 31 in the embodiment of the present application has a high degree of integration and a small size.

[0159] Referring to Figures 23 and 24, Figure 24 is a schematic diagram of power devices 32 obtained using two different methods. As can be understood, Figure 24 shows a conventional power device 32 (h1) and a power device 32 according to an embodiment of the present application (h2) placed on the same plane (not shown in Figure 24) to observe the degree of warpage of the two power devices 32.

[0160] Figure 24 (h1) shows a conventional method in which the entire area of ​​the first surface 323 and the back hole 3204 are electroplated with metal and then debonded from the carrier 3201. Figure 24 (h2) shows an embodiment of the present application in which a partial area of ​​the first surface 323 and the back hole 3204 are electroplated with metal and then debonded from the carrier 3201. It can be understood that the area of ​​the deposited metal in Figure 24 (h1) is larger than the area of ​​the deposited metal in Figure 24 (h2), and the power device 32 in Figure 24 (h1) is more likely to warp or crack. It can be seen that the degree of warping of the power device 32 in Figure 24 (h2) of the embodiment of the present application is less than the degree of warping of the power device 32 in Figure 24 (h1).

[0161] In the embodiment of the present application, by disposing at least a portion of the passive matching circuit 33 on the first surface 323 of the power device 32, the space on the first surface 323 of the power device 32 is fully utilized. This effectively reduces the area occupied by the passive matching circuit 33 on the substrate 31 or the area occupied by the passive matching circuit 33 on the second surface 324, thereby improving the integration of the semiconductor device 30, reducing the overall size of the semiconductor device 30, and achieving miniaturization of the semiconductor device 30. In the embodiment of the present application, metal is plated on a portion of the first surface 323 and the back hole 3204 and debonded from the carrier 3201, thereby reducing the warping of the power device 32. In the embodiment of the present application, metal is plated in areas where metal plating is required, while photoresist is retained in areas where metal plating is not required, eliminating the need to etch the plated metal. Thus, when the metal seed layer 3205 is etched using a full-surface etching method, although the metal plated at the bottom of the back hole 3204 is also etched, the metal plated at the bottom of the back hole 3204 is less damaged due to the thin thickness of the metal seed layer 3205.

[0162] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: Including power devices and passive matching circuits; The power device comprises a substrate, an epitaxial layer and a component, wherein the epitaxial layer is deposited on the substrate, a surface of the substrate away from the epitaxial layer is a first surface of the power device, a surface of the epitaxial layer away from the substrate is a second surface of the power device, and the component is located on the second surface; At least part of the passive matching circuit is located on the first surface, and the passive matching circuit located on the first surface is electrically connected to the power device.

2. The semiconductor device as described in claim 1, wherein the passive matching circuit includes an input matching circuit and an output matching circuit, the input matching circuit is used to input the radio frequency signal into the power device, and the output matching circuit is used to output the radio frequency signal from the power device, at least part of the input matching circuit is located on the first surface, or at least part of the output matching circuit is located on the first surface.

3. The semiconductor device according to claim 1 or 2, wherein: The passive matching circuit includes an inter-stage matching circuit, which is used for transmitting radio frequency signals in the power device, and at least a part of the inter-stage matching circuit is located on the first surface.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The power device includes a conductive member, which extends from the first surface to the second surface, and the conductive member electrically connects the element on the second surface with the passive matching circuit on the first surface, or, part of the passive matching circuit is located on the second surface, and the conductive member electrically connects the passive matching circuit on the second surface with the passive matching circuit on the first surface.

5. The semiconductor device according to claim 2, wherein: The input matching circuit and the output matching circuit are arranged at intervals on the first surface, the number of the element is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element.

6. The semiconductor device according to claim 2, wherein: The input matching circuit and the output matching circuit are arranged at intervals on the first surface, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged at intervals in sequence and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit.

7. The semiconductor device according to claim 2, wherein: The semiconductor device comprises a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; The input matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the output matching circuit is located on the first surface, the number of the element is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element; Alternatively, the input matching circuit is located on the first surface, the output matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the number of the elements is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element.

8. The semiconductor device according to claim 2, wherein: The semiconductor device comprises a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; The input matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the output matching circuit is located on the first surface, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are sequentially spaced apart and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit; Or, the input matching circuit is located on the first surface, the output matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence and spaced apart and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit.

9. The semiconductor device according to claim 2, wherein: The number of the element is one, the input matching circuit comprises a first input part and a second input part which are electrically connected, the first input part is located on the first surface, the second input part is located on the second surface, and the second input part is electrically connected to the element; Or, the number of the element is one, the output matching circuit includes a first output part and a second output part that are electrically connected, the first output part is located on the first surface, the second output part is located on the second surface, and the second output part is electrically connected to the element.

10. The semiconductor device according to claim 2, wherein: The number of the elements is N, where N is an integer greater than or equal to 2, and the N elements are respectively a first element to an Nth element, the first element to the Nth element are sequentially arranged at intervals and two adjacent elements are electrically connected, the input matching circuit comprises a first input part and a second input part that are electrically connected, the first input part is located on the first surface, the second input part is located on the second surface, and the second input part is electrically connected to the first element; Or, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence and spaced apart, and two adjacent elements are electrically connected, the output matching circuit includes a first output part and a second output part, the first output part is located on the first surface, the second output part is located on the second surface, and the second output part is electrically connected to the Nth element.

11. The semiconductor device according to claim 2, wherein: The semiconductor device comprises a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; The number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are sequentially arranged at intervals and two adjacent elements are electrically connected, the input matching circuit comprises a first input part, a second input part and the third input part, the first input part is located on the first surface, the second input part is located on the second surface, the second input part is electrically connected to the first element, the second input part is electrically connected to the first input part, the third input part is located on the surface of the substrate facing the power device and is spaced from the power device, and the third input part is electrically connected to the second input part; Or, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence and spaced apart and two adjacent elements are electrically connected, the output matching circuit includes a first output part, a second output part and a third output part, the first output part is located on the first surface, the second output part is located on the second surface, the second output part is electrically connected to the Nth element, the second output part is electrically connected to the first input part, the third output part is located on the surface of the substrate facing the power device and is spaced apart from the power device, and the third output part is electrically connected to the second output part.

12. The semiconductor device according to claim 6, 8, 10 or 11, wherein: The passive matching circuit includes an inter-stage matching circuit, the inter-stage matching circuit is located on the first surface and between the input matching circuit and the output matching circuit, and the inter-stage matching circuit electrically connects two adjacent elements; Alternatively, the passive matching circuit includes an inter-stage matching circuit, the inter-stage matching circuit is located on the second surface and between two adjacent elements, and the inter-stage matching circuit electrically connects the two adjacent elements.

13. The semiconductor device according to any one of claims 2 to 12, characterized in that: The input matching circuit includes at least one of a resistor, a capacitor or an inductor, and the output matching circuit includes at least one of a resistor, a capacitor or an inductor.

14. A method for manufacturing a semiconductor device, used for preparing the semiconductor device according to any one of claims 1 to 13, characterized in that: include: Manufacturing a power device, the power device comprising a substrate, an epitaxial layer and a component, the epitaxial layer being deposited on the substrate, the surface of the substrate facing away from the epitaxial layer being the first surface of the power device, the surface of the epitaxial layer facing away from the substrate being the second surface of the power device, and the component being located on the second surface; A passive matching circuit is formed on the power device, at least a portion of the passive matching circuit is located on the first surface, and the passive matching circuit located on the first surface is electrically connected to the power device.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The steps of manufacturing the power device include: depositing the epitaxial layer on the substrate; forming the element on the second surface; bonding the second surface to a slide; Performing patterning on the substrate and the epitaxial layer to form a back hole, wherein the back hole extends from the first surface to the second surface; Coating a photoresist, patterning the photoresist, exposing and developing the back hole and the remaining electroplating areas, and retaining the photoresist in the non-electroplating area; Electroplating metal in areas not covered by the photoresist; removing the photoresist in the non-plating area; After forming the passive matching circuit on the power device, the method for manufacturing the semiconductor device further includes: removing the carrier.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: During the process of patterning the photoresist, at least two exposure and development processes are performed, and at least two exposure and development process regions partially overlap.

17. The method for manufacturing a semiconductor device according to claim 15, wherein: The thickness of the photoresist on the first surface is greater than or equal to 1.2 times the thickness of the metal on the first surface.

18. A power amplifier, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 13.

19. A radio frequency system, characterized in that: It comprises a radio frequency chip and a power amplifier as claimed in claim 18, wherein the radio frequency chip is used to send the radio frequency signal to the power amplifier, and the power amplifier is used to amplify the radio frequency signal.

20. An electronic device, characterized in that: It comprises a signal output device and the radio frequency system as claimed in claim 19, wherein the signal output device is used to send a signal to the radio frequency system, and the radio frequency system is used to amplify the signal.

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