Method for producing an optoelectronic semiconductor component, and optoelectronic semiconductor component

Abstract

Proposed is a method for producing an optoelectronic semiconductor component (10), comprising: applying (S100) a passivation layer (100) over a surface (101) of a semiconductor layer stack (112) that comprises a first semiconductor layer (110) of a first conductivity type, an active zone (115) and a second semiconductor layer (120) of a second conductivity type, such that the passivation layer (100) is arranged adjacent to the first semiconductor layer (110). The method furthermore comprises: structuring (S110) the passivation layer (100), whereby openings (102) are formed in the passivation layer (100), which extend to the first semiconductor layer (110); applying (S120) a metallisation layer (105) over the passivation layer (100), the metallisation layer (105) being in contact with the first semiconductor layer (110) in the region of the openings (102); and structuring (S130) the metallisation layer (105) by ion beam etching, whereby first contact elements (107) are formed in contact with the first semiconductor layer (110).

Description

[0001] METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND OPTOELECTRONIC SEMICONDUCTOR COMPONENT

[0002] DESCRIPTION

[0003] Light-emitting diodes (LEDs) that emit in the red or infrared wavelength range are typically based on an As or P-type compound semiconductor material system. In general, processes are being sought to improve the electrical contacting of LEDs.

[0004] The present invention is based on the object of providing an improved method for producing an optoelectronic semiconductor component and an improved semiconductor component.

[0005] According to embodiments, the problem is solved by the subject matter of the independent patent claims. Further developments are defined in the dependent patent claims.

[0006] According to embodiments, a method for producing an optoelectronic semiconductor component comprises applying a passivation layer over a surface of a semiconductor layer stack comprising a first semiconductor layer of a first conductivity type, an active zone and a second semiconductor layer of a second conductivity type, such that the passivation layer is arranged adjacent to the first semiconductor layer.The method further comprises structuring the passivation layer, whereby openings are formed in the passivation layer which extend to the first semiconductor layer, applying a metallization layer over the passivation layer, wherein in the region of the openings the metallization layer is in contact with the first semiconductor layer, and structuring the metallization layer by ion beam etching, whereby first contact elements are formed in contact with the first semiconductor layer.

[0007] For example, by forming the openings in the passivation layer, a part of the first semiconductor layer can be exposed.

[0008] For example, the metallization layer can be applied by sputtering. According to further embodiments, the metallization layer can be applied by vapor deposition.

[0009] For example, the passivation layer may be insulating. The passivation layer may further contain one or more conductive layers.

[0010] According to embodiments, the passivation layer may contain a sacrificial layer that is selectively etchable relative to an adjacent region of the passivation layer. The method may further comprise removing the sacrificial layer after patterning the metallization layer. The sacrificial layer may, for example, be arranged on the side of the passivation layer facing away from the semiconductor layer stack.

[0011] For example, the metallization layer may contain a precious metal, such as gold.

[0012] According to embodiments, the first and second semiconductor layers and the active zone may contain As compound semiconductor materials. According to further embodiments, the first and second semiconductor layers and the active zone may contain P compound semiconductor materials.

[0013] The method may further include forming second contact elements for contacting the second semiconductor layer before applying the passivation layer.

[0014] Further embodiments relate to an optoelectronic semiconductor component that can be produced by the method described above. For example, the passivation layer can be arranged above the surface of the semiconductor layer stack.

[0015] The accompanying drawings provide an understanding of embodiments of the invention. The drawings illustrate embodiments and, together with the description, serve to explain the same. Further embodiments and many of the intended advantages will be apparent from the following detailed description. The elements and structures shown in the drawings are not necessarily to scale. Like reference numerals refer to like or corresponding elements and structures.

[0016] Figs. 1A to 1E illustrate a cross-sectional view of a workpiece when carrying out a method according to embodiments.

[0017] Fig. 1 F shows a cross-sectional view of a workpiece to illustrate a process variant.

[0018] Fig. 2 shows a cross-sectional view of an optoelectronic semiconductor device. Fig. 3 summarizes a method according to embodiments.

[0019] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which specific embodiments are shown for purposes of illustration. In this context, directional terminology such as "top," "bottom," "front," "back," "over," "on," "in front of," "behind," "fore," "rear," etc., refers to the orientation of the figures just described. Since the components of the embodiments can be positioned in different orientations, the directional terminology is for the purpose of explanation only and is in no way limiting.

[0020] The description of the embodiments is not limiting, as other embodiments exist and structural or logical changes may be made without departing from the scope defined by the claims. In particular, elements of embodiments described below may be combined with elements of other described embodiments, unless the context indicates otherwise.

[0021] The terms "wafer" or "semiconductor substrate" used in the following description can encompass any semiconductor-based structure having a semiconductor surface. Wafer and structure are to be understood as including doped and undoped semiconductors, epitaxial semiconductor layers, optionally supported by a base support, and other semiconductor structures. For example, a layer of a first semiconductor material can be grown on a growth substrate of a second semiconductor material, for example a GaAs substrate, a GaN substrate or a Si substrate, or of an insulating

[0022] material, for example on a sapphire substrate.

[0023] Depending on the intended use, the semiconductor can be based on a direct or an indirect semiconductor material. Examples of semiconductor materials particularly suitable for generating electromagnetic radiation include, in particular, nitride semiconductor compounds, which can be used to generate ultraviolet, blue or longer-wavelength light, for example, such as GaN, InGaN, AlN, AlGaN, AlGaInN, AlGaInBN, phosphide semiconductor compounds, which can be used to generate green or longer-wavelength light, for example, such as GaAsP, AlGaInP, GaP, AlGaP, and arsenide semiconductor materials such as GaAs, AlGaAs, InGaAs, AlInGaAs, which can be used to generate red or longer-wavelength light, for example, or other semiconductor materials such as SiC, ZnSe, ZnO, Ga2Oa, diamond, hexagonal BN and combinations of the materials mentioned. The stoichiometric ratio of compound semiconductor materials can vary.Other examples of semiconductor materials may include silicon, silicon-germanium, and germanium.

[0024] In the context of the present application, for example, P- or As-semiconductor materials in particular can be used.

[0025] The term "substrate" generally includes insulating, conductive or semiconductor substrates.

[0026] The term "vertical," as used in this description, is intended to describe an orientation that is substantially perpendicular to the first surface of a substrate or semiconductor body. The vertical direction can, for example, correspond to a growth direction during the growth of layers.

[0027] The terms "lateral" and "horizontal," as used in this description, are intended to describe an orientation or alignment that is substantially parallel to a first surface of a substrate or semiconductor body. This may, for example, be the surface of a wafer or a chip (die).

[0028] The horizontal direction can, for example, lie in a plane perpendicular to a growth direction during the growth of layers.

[0029] In the context of this description, the term "electrically connected" means a low-resistance electrical connection between the connected elements. The electrically connected elements do not necessarily have to be directly connected to one another. Additional elements may be arranged between electrically connected elements.

[0030] The term "electrically connected" also includes tunnel contacts between the connected elements.

[0031] Fig. 1A shows an example of a workpiece 15 before carrying out the method according to embodiments. The workpiece 15 has, for example, a semiconductor layer stack 112 comprising a first semiconductor layer 110 of a first conductivity type, for example n-type, an active zone for generating electromagnetic radiation, and a second semiconductor layer 120 of a second conductivity type, for example p-type. Of course, each of the first and second semiconductor layers 110, 120 can comprise a plurality of sub-layers, for example with different compositions, different doping levels, etc.

[0032] The active zone can, for example, have a pn junction, a double heterostructure, a single quantum well (SQW), or a multi-quantum well (MQW) structure for radiation generation. The term "quantum well structure" has no significance with regard to the dimensionality of the quantization. It thus encompasses, among other things, quantum wells, quantum wires, and quantum dots, as well as any combination of these layers.

[0033] For example, the first and second semiconductor layers and the active zone 115 contain As compound semiconductor materials. According to further embodiments, the first and second semiconductor layers 110, 120 and the active zone can contain semiconductor layers of the P compound semiconductor material system. Furthermore, compound semiconductor materials containing both As and P compounds are conceivable. Accordingly, the resulting optoelectronic semiconductor component can emit electromagnetic radiation in a red or infrared wavelength range. For example, an emission wavelength can be greater than 600 nm.

[0034] Typically, the first semiconductor layer 110, the active zone 115 and the second semiconductor layer 120 are grown in this order on a suitable growth substrate. As a result, a surface of the second semiconductor layer 120 may be exposed or not covered. The exposed surface of the second semiconductor layer can then be processed, for example to produce second contact elements 108 in electrical contact with the second semiconductor layer 120 or to produce mirror coatings. The second contact elements 108 are no longer shown in detail in the subsequent figures. A rebonding process then takes place, as a result of which a carrier 125 is bonded over the resulting surface. Subsequently, the growth substrate is removed so that a surface 101 of the first semiconductor layer 110 is exposed or not covered.Furthermore, a surface 101 of the first semiconductor layer 110 may be roughened to improve light extraction.

[0035] As shown in Fig. 1B, a passivation layer 100 is subsequently applied over the surface 101 of the first semiconductor layer 110. The passivation layer 100 has a low absorption capacity in the range of the emission wavelength. The passivation layer 100 may comprise several different layers. For example, the passivation layer 100 may contain silicon nitride or another dielectric material. According to further embodiments, the passivation layer 100 may also contain conductive material. A layer thickness of the passivation layer 100 may be less than 100 nm, for example approximately 30 nm.

[0036] As shown in Fig. 1C, openings 102 are then formed in the passivation layer 100. This can be done, for example, by wet-chemical etching in a suitable etchant, for example dilute hydrofluoric acid. In this way, regions of the surface 101 are exposed in the region of the openings 102. The openings 102 typically have a feature size of a few pm. For example, the feature size can be less than 10 pm. For example, the openings 102 can have a shape through which contact fingers can be formed. The contact fingers can then extend, for example in the form of conductor tracks, over the entire surface of the finished semiconductor component in order to distribute the current evenly in the finished semiconductor component. Subsequently, as shown in Fig. 1D, a metallization layer 105 is applied. For example, a layer thickness of the metallization layer 105 can be more than 1 pm.For example, the layer thickness may be in a range of 2 pm or less. The metallization layer 105 may contain one or more arbitrary materials, for example, precious metals or alloys, for example, precious metal alloys. The metallization layer 105 may comprise a plurality of individual layers, for example, made of different metals. The metallization layer 105 may be applied by any method, such as sputtering or vapor deposition.

[0037] Subsequently, as illustrated in Fig. IE, the metallization layer 105 is structured to form first contact elements 107, for example using a suitable etching mask (not shown), for example a photolithographically produced resist mask.

[0038] The structuring of the metallization layer 105 can be carried out, for example, by ion beam etching. In an ion beam etching process, the layer to be structured is irradiated with noble gas ions, for example, Ar ions, whereby the metallization layer 105 is removed in unmasked areas. The etching process is carried out, for example, with endpoint detection, so that the etching process is stopped in time when the passivation layer 100 is reached. As a result, first contact elements are formed in contact with the first semiconductor layer.

[0039] According to a method variant, which is illustrated in Fig. 1F, the passivation layer 100 can have a sacrificial layer 103 as the uppermost layer. The sacrificial layer 103 can, for example, be removed after etching selectively with respect to an adjacent region of the passivation layer 100, for example the underlying remaining passivation layer 100 and the first contact elements 107. The sacrificial layer 103 can thus be used as a stop layer for the etching process. Furthermore, a homogeneous thickness of the passivation layer 100 can be achieved in the semiconductor component. In this way, problems can be eliminated if the etching process does not stop completely homogeneously across the wafer or if there is shading or trench formation directly around the structures or first contact elements 107.

[0040] The process can be performed, for example, at the wafer level. After the first contact elements have been produced, the wafers can be separated into individual semiconductor components.

[0041] Fig. 2 shows a cross-sectional view of an optoelectronic semiconductor component 10 that can be produced by the described method. The optoelectronic semiconductor component has a first semiconductor layer 110 of a first conductivity type, for example n-conducting, an active zone 115 for generating or receiving radiation, and a second semiconductor layer 120 of a second conductivity type, for example p-type. A first contact element 107 is formed directly adjacent to the first semiconductor layer 110 in the region of the surface 101. A second contact element 108 is formed in the region of a surface of the second semiconductor layer 120. If a suitable voltage is applied between the first and second contact elements 107, 108, electromagnetic radiation 20 is emitted via the surface 101 of the first semiconductor layer 110.For example, the first contact element 107 may consist of a region of a metallization layer that directly adjoins the first semiconductor layer 110. For example, the passivation layer 100 may be arranged above the first semiconductor layer 110 between the first contact elements 107. The passivation layer 100 may be arranged above the main surface 101 of the semiconductor layer stack 112. In this way, the main surface 101 can be tightly encapsulated and protected against environmental influences. According to further embodiments, a part of the passivation layer 100 may be arranged between the first contact element 107 and the first semiconductor layer 110.

[0042] Fig. 3 summarizes a method according to embodiments. A method for producing an optoelectronic semiconductor component comprises applying (S 100 ) a passivation layer 100 over a surface 101 of a semiconductor layer stack 112 comprising a first semiconductor layer 110 of a first conductivity type, an active zone 115 and a second semiconductor layer 120 of a second conductivity type, such that the passivation layer 100 is arranged adjacent to the first semiconductor layer 110.The method further comprises structuring (S 110) the passivation layer 100, whereby openings 102 are formed in the passivation layer 100, which openings extend to the first semiconductor layer 110, applying (S 120) a metallization layer 105 over the passivation layer 100, wherein in the region of the openings 102 the metallization layer 105 is in contact with the first semiconductor layer 110, and structuring (S 130) the metallization layer 105 by ion beam etching, whereby first contact elements 107 are formed in contact with the first semiconductor layer 110.

[0043] As has been described, a method for directly structuring the first contact element 107 is described. Because the direct ion beam etching process can be carried out over a large area, the method can be implemented industrially. The presence of the passivation layer 100 can protect the semiconductor material from damage caused by ion bombardment. As a result, good crystal quality can be maintained. Because the first contact elements 107 can be directly structured, much denser materials, which have been applied by sputtering, for example, can be structured compared to a conventional lift-off process. Furthermore, the structuring method enables new degrees of freedom. Direct structuring can, for example, achieve other structural geometries, for example finer dimensions in the lateral dimensions.Because other paint systems are used, the profile of the metal structures in the cross section can also be adjusted differently than with the inverse structuring by a lift-off process.

[0044] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that the specific embodiments shown and described may be replaced by a variety of alternative and / or equivalent designs without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is limited only by the claims and their equivalents. LIST OF REFERENCE SYMBOLS

[0045] 10 optoelectronic semiconductor component

[0046] 15 Workpiece 20 electromagnetic radiation

[0047] 100 passivation layer

[0048] 101 Surface

[0049] 102 Opening

[0050] 103 Sacrificial layer 105 Metallization layer

[0051] 107 first contact element

[0052] 108 second contact element

[0053] 110 first semiconductor layer

[0054] 112 Semiconductor layer stack 115 active zone

[0055] 120 second semiconductor layer

[0056] 125 carriers

Claims

CLAIMS 1. A method for producing an optoelectronic semiconductor component (10) comprising: Applying (S100) a passivation layer (100) over a surface (101) of a semiconductor layer stack (112) comprising a first semiconductor layer (110) of a first conductivity type, an active zone (115) and a second semiconductor layer (120) of a second conductivity type, such that the passivation layer (100) is arranged adjacent to the first semiconductor layer (110), structuring (S110) the passivation layer (100), whereby openings (102) are formed in the passivation layer (100) which extend to the first semiconductor layer (110); Applying (S120) a metallization layer (105) over the passivation layer (100), wherein in the region of the openings (102) the metallization layer (105) is in contact with the first semiconductor layer (110); and structuring (S130) the metallization layer (105) by ion beam etching, whereby first contact elements (107) are formed in contact with the first semiconductor layer (110).

2. The method according to claim 1, wherein the metallization layer (105) is applied by sputtering.

3. The method according to claim 1, wherein the metallization layer (105) is applied by vapor deposition.

4. Method according to one of the preceding claims, wherein the passivation layer (100) is insulating.

5. Method according to one of claims 1 to 3, wherein the Passivation layer (100) contains a conductive layer.

6. The method according to any one of the preceding claims, wherein the passivation layer (100) includes a sacrificial layer (103) that is selectively etchable relative to an adjacent region of the passivation layer (100), and the method further includes removing the sacrificial layer (103) after patterning the metallization layer (105).

7. Method according to one of the preceding claims, wherein the metallization layer (105) contains a noble metal.

8. The method according to any one of the preceding claims, wherein the first and second semiconductor layers (110, 120) and the active zone (115) contain As compound semiconductor materials.

9. The method according to any one of the preceding claims, wherein the first and second semiconductor layers (110, 120) and the active zone (115) contain P-compound semiconductor materials.

10. The method according to any one of the preceding claims, further comprising forming second contact elements (108) for contacting the second semiconductor layer (120) before applying the passivation layer (100).

11. Optoelectronic semiconductor component (10) which can be produced by the method according to one of the preceding claims.

12. Optoelectronic semiconductor component (10) according to claim 11, wherein the passivation layer (100) is formed over the upper surface (101) of the semiconductor layer stack (112).

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