Semiconductor device

Abstract

Provided is a semiconductor device having a high operation speed. The present invention has an oxide semiconductor, first and second insulators, and first to third conductors. The oxide semiconductor is disposed on a substrate. The first conductor and the second conductor are disposed on the oxide semiconductor. The first insulator is disposed on the first conductor and the second conductor and has an opening that overlaps a region between the first conductor and the second conductor. The second insulator is disposed within the opening so as to overlap the oxide semiconductor. The third conductor is disposed on the second insulator within the opening. The height of the oxide semiconductor is greater than the width of the oxide semiconductor in a cross-sectional view in the channel width direction. In top view, there are two or more regions in which the oxide semiconductor and the third conductor overlap.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor layer. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, etc. A CPU is an aggregate of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0010] Another object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated.Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity.Another object of one embodiment of the present invention is to provide a memory device with high operation speed.Another object of one embodiment of the present invention is to provide a memory device with low power consumption.Another object of one embodiment of the present invention is to provide a novel memory device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a semiconductor device including an oxide semiconductor, first and second insulators, and first to third conductors, in which the oxide semiconductor is disposed over a substrate, the first conductor and the second conductor are disposed over the oxide semiconductor, the first insulator is disposed over the first conductor and the second conductor and has an opening overlapping with a region between the first conductor and the second conductor, the second insulator is disposed in the opening overlapping with the oxide semiconductor, and the third conductor is disposed on the second insulator in the opening, the height of the oxide semiconductor is longer than the width of the oxide semiconductor in a cross-sectional view in a channel width direction, and the semiconductor device has two or more regions where the oxide semiconductor and the third conductor overlap in a top view.

[0013] One embodiment of the present invention is a semiconductor device including an oxide semiconductor, first to third insulators, and first to third conductors. The oxide semiconductor is disposed over a substrate. The first conductor and the second conductor are disposed over the oxide semiconductor. The first insulator is disposed over the first conductor and the second conductor and has an opening overlapping with a region between the first conductor and the second conductor. The second insulator is disposed in the opening and overlapping with the oxide semiconductor. The third conductor is disposed in the opening on the second insulator. The third insulator is disposed under the oxide semiconductor and overlaps with the oxide semiconductor in a top view. The thickness of the third insulator is thicker than the thickness of the second insulator. The height of the oxide semiconductor is greater than the width of the oxide semiconductor in a cross-sectional view in a channel width direction. The semiconductor device has two or more regions where the oxide semiconductor and the third conductor overlap in a top view.

[0014] In the above, the lower surface of the third conductor preferably has a portion located lower than the lower surface of the oxide semiconductor.

[0015] In the above, the oxide semiconductor preferably has a circumferential shape with both ends coinciding with each other when viewed from above.

[0016] In the above, it is preferable that, when viewed from above, a side surface of the opening of the first insulator coincides or substantially coincides with a side surface of the first conductor and a side surface of the second conductor.

[0017] In the above, it is preferable that the width of the oxide semiconductor be 5 nm to 50 nm in cross section in the channel width direction, and that the height of the oxide semiconductor be 2 to 10 times the width of the oxide semiconductor in cross section in the channel width direction.

[0018] In the above, it is preferable that the oxide semiconductor contains indium, is formed perpendicular or approximately perpendicular to the surface of the substrate, and when a cross-section of the oxide semiconductor is observed using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are confirmed.

[0019] In the above, it is preferable that the oxide semiconductor contains indium, is formed perpendicular or substantially perpendicular to a surface of the substrate, has a first region, a second region in contact with the first region, and a third region in contact with the second region, and that, in cross-sectional observation of the oxide semiconductor using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are confirmed in each of the first region, the second region, and the third region.

[0020] In the above, it is preferable that the second region contains zinc, the second region has crystals, and the c-axes of the crystals are approximately parallel to a normal to the side surfaces of the oxide semiconductor.

[0021] In the above, it is preferable that the indium content in the first region is higher than the indium content in the second region, and the indium content in the third region is higher than the indium content in the second region.

[0022] One embodiment of the present invention includes first and second oxide semiconductors, first to third insulators, and first to fourth conductors, in which the first oxide semiconductor and the second oxide semiconductor are disposed over a substrate, the first conductor is disposed over the first oxide semiconductor, the second conductor is disposed over the first oxide semiconductor and the second oxide semiconductor, the first insulator is disposed over the first conductor and the second conductor, and the first insulator has a first opening and a second opening, the first opening overlaps with a region between the first conductor and the second conductor and reaches the first oxide semiconductor, and the second opening is formed through a second oxide semiconductor. the second insulator is disposed in the first opening, overlapping the first oxide semiconductor; the third conductor is disposed in the first opening on the second insulator; the third insulator is disposed in the second opening, overlapping the second conductor; and the fourth conductor is disposed in the second opening on the third insulator; the height of the first oxide semiconductor is greater than the width of the first oxide semiconductor in a cross-sectional view in the channel width direction; and the semiconductor device has two or more regions where the first oxide semiconductor and the third conductor overlap in a top view.

[0023] In the above, it is preferable that the height of the second oxide semiconductor be greater than the width of the second oxide semiconductor when viewed cross-sectionally in the channel width direction, and that the second oxide semiconductor have two or more regions where the second oxide semiconductor and the fourth conductor overlap when viewed from above.

[0024] One embodiment of the present invention includes a first oxide semiconductor, first to third insulators, and first to fourth conductors. The first oxide semiconductor is disposed over a substrate. The first conductor and the second conductor are disposed over the first oxide semiconductor. The first insulator is disposed over the first conductor and the second conductor. The first opening and the second opening overlap with a region between the first conductor and the second conductor and reach the first oxide semiconductor. The second opening overlaps with the first oxide semiconductor and reaches the second conductor. a third conductor is disposed in the first opening on the second insulator, the third insulator is disposed in the second opening on the second conductor, and the fourth conductor is disposed in the second opening on the third insulator; the height of the first oxide semiconductor is greater than the width of the first oxide semiconductor in a cross-sectional view in the channel width direction; and the semiconductor device has two or more regions where the first oxide semiconductor and the third conductor overlap and two or more regions where the first oxide semiconductor and the fourth conductor overlap in a top view.

[0025] In the above, it is preferable that the semiconductor device includes a first layer and a second layer over the first layer, the first layer includes a first transistor having silicon in a channel formation region, the second layer includes a second transistor and a capacitor, the first transistor is electrically connected to the second transistor and the capacitor, the second transistor includes a first oxide semiconductor, first to third conductors, and a second insulator, and the capacitor includes the second conductor, a fourth conductor, and a third insulator.

[0026] In the above, the first transistor is preferably a fin transistor. Also, in the above, the first transistor preferably has a portion overlapping with the second transistor.

[0027] According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to another embodiment of the present invention, a highly reliable semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to another embodiment of the present invention, a novel semiconductor device can be provided. According to another embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to another embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0028] According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a memory device with a large storage capacity can be provided. According to one embodiment of the present invention, a memory device with a high operating speed can be provided. According to one embodiment of the present invention, a memory device with low power consumption can be provided. According to one embodiment of the present invention, a novel memory device can be provided.

[0029] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0030] FIG. 1A is a plan view illustrating an example of a semiconductor device. FIGS. 1B to 1D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 3A to 3C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views illustrating an example of a part of a semiconductor device. FIGS. 5A and 5B are plan views illustrating an example of a part of a semiconductor device. FIGS. 6A to 6C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 8A to 8D are cross-sectional views illustrating an example of a method for manufacturing an oxide semiconductor. FIGS. 9A to 9D are cross-sectional views illustrating an example of an oxide semiconductor. FIG. 10A is a plan view illustrating an example of a semiconductor device. FIGS. 10B to 10D are cross-sectional views illustrating an example of a semiconductor device. FIG. 11 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 12A is a plan view illustrating an example of a semiconductor device. FIGS. 12B to 12D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 14A to 14C are cross-sectional views illustrating an example of a semiconductor device. 15A and 15B are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 16B to 16D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 17A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 17B to 17D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 18A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 18B to 18D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 19A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 19B to 19D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 20A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 20B to 20D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 21A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 21B to 21D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 22A is a plan view showing an example of a method for manufacturing a semiconductor device. 22B to 22D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.FIG. 23A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 23B to 23D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 24A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 24B to 24D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 25A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 25B to 25D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIGS. 26A and 26B are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIGS. 27A and 27B are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 28 is a block diagram illustrating a structural example of a semiconductor device. FIGS. 29A to 29H are diagrams illustrating an example of a circuit structure of a memory cell. FIGS. 30A and 30B are perspective views illustrating a structural example of a semiconductor device. FIG. 31 is a block diagram illustrating a CPU. FIG. 32 is a block diagram illustrating a CPU. FIGS. 33A and 33B are perspective views of a semiconductor device. FIGS. 34A and 34B are perspective views of a semiconductor device. Fig. 35A and Fig. 35B are diagrams explaining the hierarchy of memory devices in a semiconductor device. Fig. 36A and Fig. 36B are diagrams showing an example of electronic equipment, and Fig. 36C to Fig. 36E are diagrams showing an example of a mainframe computer. Fig. 37 is a diagram showing an example of space equipment. Fig. 38 is a diagram showing an example of a storage system applicable to a data center.

[0031] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0032] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0033] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0034] In order to make the invention easier to understand, particularly in plan views (also called "top views") and perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0035] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0036] The terms "film" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be interchangeable with the term "conductive film." Or, for example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0037] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0038] The openings include, for example, grooves, slits, etc. Furthermore, the area in which the openings are formed may be referred to as an opening portion.

[0039] Although the drawings used in this embodiment mode show the case where the sidewall of the insulator in the opening portion is perpendicular or approximately perpendicular to the substrate surface or the surface where the insulator is formed, the sidewall may have a tapered shape.

[0040] In this specification, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, but may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0041] In this specification, "having the same or approximately the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in the manufacturing process of a memory device, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process have a configuration in which the heights from the reference surface are equal. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "having the same or approximately the same height." For example, in the case of a structure having two layers (here, a first layer and a second layer) with different heights relative to a reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "having the same or approximately the same height."

[0042] In this specification, "side edges that coincide or approximately coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "side edges that coincide or approximately coincide" is also used.

[0043] Embodiment 1 In this embodiment, a semiconductor device including an oxide semiconductor layer and a method for manufacturing the semiconductor device will be described with reference to FIGS.

[0044] <Configuration Example of Semiconductor Device> A configuration example of a semiconductor device will be described with reference to Fig. 1 to Fig. 15. Fig. 1A to Fig. 1D are plan views and cross-sectional views of a semiconductor device including a transistor 200 over a substrate (not shown).

[0045] FIG. 1A is a plan view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1C is a cross-sectional view of a portion indicated by the dashed-dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by the dashed-dotted line A5-A6 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. The dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of FIG. 1A, some elements are omitted and shown transparently for clarity. 2A shows an enlarged view of the vicinity of the conductor 260 in Fig. 1D. Also, Fig. 2B shows an enlarged view of the vicinity of the oxide semiconductor 230 in Fig. 1B. Also, Fig. 6A shows an enlarged view of the vicinity of the oxide semiconductor 230 in Fig. 1C.

[0046] The semiconductor device according to this embodiment includes an insulator 216 on a substrate (not shown), an insulator 221 on the insulator 216, an insulator 222 on the insulator 221, an oxide semiconductor 230 on the insulator 222, conductors 242a and 242b on the oxide semiconductor 230 and the insulator 222, an insulator 250 on the oxide semiconductor 230, and a conductor 260 (conductors 260a and 260b) on the insulator 250. Note that hereinafter, the conductors 242a and 242b may be collectively referred to as conductors 242.

[0047] An insulator 275 is provided over the conductor 242, and an insulator 280 is provided over the insulator 275. The insulator 250 and the conductor 260 are disposed inside openings provided in the insulator 280 and the insulator 275. The openings reach the oxide semiconductor 230, and the insulator 250 is in contact with the oxide semiconductor 230 in the openings. An insulator 282 is provided over the insulator 280 and the conductor 260. An insulator 283 is provided over the insulator 282. An insulator 215 is provided under the insulator 216.

[0048] An insulator 241a is provided in contact with the inner wall of an opening of the insulator 280 or the like, and a conductor 240a is provided in contact with the side surface of the insulator 241a. The lower surface of the conductor 240a is in contact with the upper surface of the conductor 242a. An insulator 241b is provided in contact with the inner wall of an opening of the insulator 280 or the like, and a conductor 240b is provided in contact with the side surface of the insulator 241b. The lower surface of the conductor 240b is in contact with the upper surface of the conductor 242b. Note that hereinafter, the conductors 240a and 240b may be collectively referred to as the conductor 240. The insulators 241a and 241b may be collectively referred to as the insulator 241.

[0049] The oxide semiconductor 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region that functions as a first gate insulator of the transistor 200.

[0050] The conductor 242a has a region that functions as one of the source electrode and the drain electrode of the transistor 200. The conductor 240a functions as a plug connected to the conductor 242a. The conductor 242b has a region that functions as the other of the source electrode and the drain electrode of the transistor 200. The conductor 240b functions as a plug connected to the conductor 242b.

[0051] The oxide semiconductor 230 is formed on and in contact with the insulator 222. As shown in Figures 2B and 6A, the oxide semiconductor 230 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction. Therefore, the oxide semiconductor 230 can also be said to have a fin-like shape.

[0052] Here, the aspect ratio of the oxide semiconductor 230 in a cross-sectional view in the channel width direction refers to the ratio of the length L of the oxide semiconductor 230 in the A1-A2 direction (which can also be referred to as the width L of the oxide semiconductor 230) to the length H of the oxide semiconductor 230 in a direction perpendicular to a surface on which the oxide semiconductor 230 is formed (for example, the insulator 222) (which can also be referred to as the height H of the oxide semiconductor 230). The aspect ratio of the oxide semiconductor 230 is preferably as large as possible within a range in which the oxide semiconductor 230 does not collapse during the manufacturing process of the transistor 200. In the transistor 200, the height H of the oxide semiconductor 230 is at least longer than the width L of the oxide semiconductor 230. The height H of the oxide semiconductor 230 can be greater than 1 time and less than 400 times, preferably from 2 times to 100 times, more preferably from 5 times to 40 times, and even more preferably from 10 times to 20 times the width L of the oxide semiconductor 230. For example, the height H may be from 2 times to 10 times the width L. For example, the width L can be 5 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 10 nm or more and 30 nm or less. Also, for example, the height H can be 50 nm or more and 2000 nm or less, preferably 100 nm or more and 1000 nm or less. Also, for example, the height H may be 50 nm or more and 100 nm or less.

[0053] 2B , in a cross-sectional view in the channel width direction, the angle θ between the side surface of the oxide semiconductor 230 and the top surface of the insulator 222 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0054] The insulator 250, the conductor 260, and the conductor 242 are provided to cover the oxide semiconductor 230 having such a high aspect ratio. In the transistor 200, as shown in FIG. 2B , parts of the insulator 250 and the conductor 260 are provided so as to sandwich the oxide semiconductor 230 in two. As a result, in a cross-sectional view in the channel width direction, the oxide semiconductor 230 and the conductor 260 are provided facing each other with the insulator 250 sandwiched between the top, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230. That is, the top, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230 each function as a channel formation region. Therefore, the channel width of the transistor 200 is larger by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230 than when the oxide semiconductor 230 is formed in a planar shape.

[0055] The increased channel width as described above can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, in the above structure, by providing the oxide semiconductor 230, the channel width can be increased without increasing the area occupied by the transistor 200. This enables miniaturization or high integration of the semiconductor device. Furthermore, the memory capacity of a memory device using the semiconductor device can be increased. Furthermore, with the above structure, the area where the conductor 260 and the oxide semiconductor 230 face each other is increased, so that the transistor 200 can be made normally off by controlling the threshold voltage.

[0056] 2B and other figures, the upper portion of the oxide semiconductor 230 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulator 250 and the conductor 242 near the upper portion of the oxide semiconductor 230. While FIGS. 2B and 6A and other figures illustrate a symmetrical structure in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the oxide semiconductor 230, the present invention is not limited to this. For example, an asymmetrical structure may also be obtained in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the oxide semiconductor 230.

[0057] Because the oxide semiconductor 230 has a high aspect ratio, it is preferably formed in the shape of a sidewall on the side surface of a pillar (the insulator 223 described later). Therefore, the oxide semiconductor 230 is preferably formed by an ALD method, which has good coverage. When the oxide semiconductor 230 has a stacked structure, it is preferable to form at least one layer, preferably a layer in contact with the pillar, by the ALD method.

[0058] Since the oxide semiconductor 230 is formed in a sidewall shape in contact with the pillar, the top surface shape of the oxide semiconductor 230 has a circumferential shape (which can also be called a frame shape, annular shape, doughnut shape, or closed curve shape) with both ends coinciding, as shown in FIG. 1A . The oxide semiconductor 230 can also be said to have a shape with an opening in the center. Note that in FIG. 1A , the top surface shape of the oxide semiconductor 230 is line-symmetrical about A1-A2, but the present invention is not limited to this. For example, the top surface shape of the oxide semiconductor 230 may be asymmetrical.

[0059] The structure shown in FIG. 1A has two pillars arranged in the A1-A2 direction, and a circumferential oxide semiconductor 230 formed in contact with the side surface of each pillar. As shown in FIG. 1A , the oxide semiconductor 230 preferably overlaps with the conductor 260 at two or more locations in a top view. That is, the oxide semiconductor 230 has two or more regions where the oxide semiconductor 230 and the conductor 260 overlap. With this structure, as shown in FIG. 1B , a plurality of fin-shaped oxide semiconductors 230 are formed in a cross-sectional view in the channel width direction. Each of the plurality of fin-shaped oxide semiconductors 230 functions as a channel formation region. That is, the transistor 200 functions as a multi-channel transistor. Therefore, the channel width of the transistor 200 can be further increased.

[0060] Although the above description has been given of a configuration in which two circumferential oxide semiconductors 230 are provided, the present invention is not limited to this. For example, a configuration in which one or three or more circumferential oxide semiconductors 230 are provided may be used. Furthermore, the circumferential oxide semiconductors 230 may be joined to form an oxide semiconductor 230 having a shape with multiple openings. For example, as shown in FIG. 5A , an oxide semiconductor 230 having a shape in which three openings are arranged in the A1-A2 direction in a top view may be used. In this case, three pillars may be formed adjacent to each other at a short distance, and the oxide semiconductor 230 may be formed between the pillars. Furthermore, as shown in FIG. 5B , an oxide semiconductor 230 having a lattice shape in a top view may be used. In this case, lattice-shaped trenches may be formed in the pillars, and the oxide semiconductor 230 may be formed to fill the trenches. The number of oxide semiconductors 230 is not limited to two, and a configuration in which one or three or more oxide semiconductors 230 are provided may also be used. In this way, it is preferable that the oxide semiconductor 230 has a structure including a plurality of portions extending in the channel width direction (A1-A2 direction) and a plurality of portions extending in the channel length direction (A5-A6 direction), which can prevent the oxide semiconductor 230 from collapsing during the manufacturing process of the transistor when the oxide semiconductor 230 has a high aspect ratio.

[0061] [Oxide Semiconductor Layer] Here, an oxide semiconductor layer that can be used for the oxide semiconductor 230 will be described. The oxide semiconductor layer contains a metal oxide.

[0062] When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids.

[0063] By using a crystalline metal oxide for an oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure.

[0064] The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention has a plurality of microcrystals. Furthermore, no clear grain boundary is observed between the plurality of microcrystals. The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention preferably has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when observed from the orientation direction.

[0065] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a crystal structure different from either a single-crystal structure or a polycrystalline structure. In particular, the oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure.

[0066] The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected in the a-b plane without any clear grain boundaries. When a cross section of an oxide semiconductor layer having the CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having the CAAC structure can also be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. The bright spots are arranged, for example, in a direction parallel to the surface on which the oxide semiconductor layer is formed.

[0067] In addition, a structure in which metal atoms in each of the multiple microcrystals are arranged in layers parallel or approximately parallel to the surface on which the metal atoms are formed, and the layers in which the metal atoms are arranged are stacked in a direction perpendicular or approximately perpendicular to the surface on which the metal atoms are formed, is sometimes referred to as a CAAC structure. If the microcrystals have such a configuration, the crystal structure of the microcrystals is not limited to a hexagonal system. For example, some of the multiple microcrystals may have a crystal structure other than a hexagonal system (e.g., a cubic system crystal structure).

[0068] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the metal is formed. In the CAAC structure, metal atoms are arranged in layers parallel or approximately parallel to the surface on which the metal is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the metal is formed.

[0069] A polycrystalline structure has crystal grain boundaries. Furthermore, when a heat treatment is performed after forming an oxide semiconductor layer with a polycrystalline structure, tiny gaps (also referred to as nanocracks or microcracks) or tiny spaces (also referred to as nanospaces or microspaces) can be formed between crystalline portions. When tiny gaps or tiny spaces are formed in the oxide semiconductor layer, the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In contrast, in the CAAC structure, crystal grain boundaries are not clearly observed in the a-b plane, so a highly reliable semiconductor device can be realized. Furthermore, because there are fewer crystal grain boundaries, the energy barrier against carrier conduction in the transistor channel is small, and an improvement in on-current is expected. Furthermore, it is expected that an increase in the electrical resistance of a semiconductor layer of a transistor using an oxide semiconductor layer can be suppressed or the initial characteristics (particularly on-state current) of the transistor can be improved, making the transistor suitable for high-speed operation.

[0070] A metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0071] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0072] When an oxide semiconductor layer having a CAAC structure is subjected to electron diffraction, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed or a normal vector of the surface of the oxide semiconductor layer.

[0073] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0074] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0075] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the layer has crystallinity. Furthermore, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0076] A method for creating a Voronoi diagram will now be described. First, image analysis of a TEM image involves performing FFT processing, filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal regions enclosed by the lines connecting the Voronoi points are defined as Voronoi regions. In this way, a Voronoi diagram can be created.

[0077] As an example of the observation range of the TEM in creating a Voronoi diagram, a rectangular region of 50 nm in length and 50 nm in width can be observed, but the observation range is not limited to this.

[0078] Furthermore, when the distribution of the orientation of the hexagonal lattice is analyzed using lattice points extracted by image analysis of a planar TEM image, the difference in the orientation of the hexagonal lattice at the boundary between two structures with different hexagonal lattice orientations is small, and the boundary is observed to be blurred, and it appears that the two structures are connected in a manner that makes them intertwine. In other words, no clear boundary is observed in the CAAC structure.

[0079] The orientation of the hexagonal lattice can be calculated by calculating the orientation of a hexagon formed by the six lattice points closest to each lattice point.

[0080] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not limited. The oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0081] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain element M. Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain element M. Note that element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, tin, yttrium, and aluminum, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0082] The main component in a metal oxide refers to a metal element whose proportion relative to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more, or 1 atomic % or more.

[0083] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed. The metal atoms are observed as bright spots in the TEM image. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Furthermore, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0084] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum. Examples of usable metal oxides include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as a metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as a metal oxide according to one embodiment of the present invention.

[0085] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0086] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0087] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0088] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0089] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, and hydrogen.

[0090] [Method for Forming Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide using two types of film formation methods.

[0091] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a metal oxide having a CAAC structure is deposited. At this time, a sputtering method can be used as a deposition method, thereby forming a metal oxide having high crystallinity. Alternatively, a pulsed laser deposition (PLD) method or another deposition method may be used.

[0092] Here, when a metal oxide is formed using the above-described film formation method (hereinafter referred to as the first film formation method), a mixed layer may be formed at the interface between the metal oxide and the surface on which the metal oxide is to be formed. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide. By first forming a metal oxide as a first layer on the surface on which the metal oxide is to be formed using a film formation method (hereinafter referred to as the second film formation method) that causes less damage than the sputtering method, PLD method, etc., which are described as the first film formation method, and then providing a metal oxide formed using the first film formation method as a second layer, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface on which the metal oxide is to be formed can be suppressed. Furthermore, impurities contained in the surface on which the metal oxide is to be formed can be suppressed from being mixed into the second layer. These factors can further enhance the crystallinity of the second layer.

[0093] Atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to sputtering. Examples of the second film formation method include molecular beam epitaxy (MBE) and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed.The wet method is also one of the film formation methods that causes little damage to the surface on which the film is formed.An example of a wet method is a spray coating method.

[0094] A third layer can be further formed on the second layer, for example, by the second film formation method.

[0095] After the oxide semiconductor layer is formed, heat treatment is preferably performed.

[0096] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of upper and lower oxide semiconductor layers (the first layer and the third layer) can be increased by using the second layer (i.e., the CAAC) having high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor layer. In other words, the second layer serves as a nucleus or seed to cause solid-phase growth of a metal oxide in the upper and lower oxide semiconductor layers, thereby forming oxide semiconductor layers with high crystallinity. An oxide semiconductor layer formed by such a film formation method, specifically, an oxide semiconductor layer having a CAAC structure, can be referred to as an axial growth CAAC (AG CAAC).

[0097] Even when a method that easily forms a metal oxide with high crystallinity is not used as a method for forming the first layer and the third layer, the crystallinity of the first layer and the third layer can be increased by using the method for forming an oxide semiconductor layer of one embodiment of the present invention. Furthermore, heat treatment has a function of assisting in increasing the crystallinity of the first layer and the third layer.

[0098] An example of a method for manufacturing the oxide semiconductor 30 will be described below with reference to FIGS. 8A to 8D.

[0099] First, a layer 29 is formed. The layer 29 corresponds to an insulating film or a conductive film included in the semiconductor device. For example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film can be used as the layer 29. Alternatively, for example, a conductive film that functions as an electrode of the semiconductor device can be used as the layer 29. The layer 29 does not need to be crystalline. In other words, the layer 29 may have an amorphous structure. Furthermore, when the layer 29 is crystalline, it may have a crystal structure that has low lattice matching with the metal oxide included in the oxide semiconductor 30.

[0100] Next, an oxide semiconductor 30a is formed on the layer 29 (FIG. 8A).

[0101] In a manufacturing method of one embodiment of the present invention, the oxide semiconductor 30b is formed by a sputtering method, as described later. When a metal oxide film is formed by a sputtering method, a mixed layer (also called alloying) of components of the metal oxide film to be formed and components of a layer on which the film is to be formed may be formed due to sputtering particles emitted from a target or the like, or energy imparted to the substrate by the sputtering particles or the like. There is a concern that alloying may inhibit crystallization of the oxide semiconductor layer thereover. Furthermore, when alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. There is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor.

[0102] Therefore, before forming the oxide semiconductor 30b, the oxide semiconductor 30a is formed in advance using a film formation method that causes minimal damage to the surface on which the oxide semiconductor 30b is to be formed. This suppresses alloying of the components contained in the oxide semiconductor 30 with the components contained in the layer 29, and makes it possible to reduce the thickness of the alloyed region or to make the alloyed region thin enough that it is not observable. Here, the oxide semiconductor 30a is formed using the ALD method.

[0103] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0104] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Because the ALD method can deposit atoms layer by layer, it has the following advantages: it is possible to form an ultrathin film; it is possible to form a film on a surface with a high aspect ratio or large steps; it is possible to form a film with few defects such as pinholes; it is possible to form a film with excellent coverage; and it is possible to form a film at a low temperature. By using the ALD method as a film formation method for the oxide semiconductor 30a and the oxide semiconductor 30c (described later), the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio.

[0105] Furthermore, the PEALD method may be preferable because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods.

[0106] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor 30a by ALD will be described.

[0107] First, a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed onto the surface of layer 29. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer in which indium and oxygen are combined.

[0108] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the layer of indium and oxygen. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer of element M and oxygen.

[0109] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the layer in which element M and oxygen are bonded. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0110] By repeating the above-described method, an In-M-Zn oxide can be formed as the oxide semiconductor 30a on the layer 29 by the ALD method.

[0111] The substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the substrate heating temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0112] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the chamber, and then discharge excess precursor, reaction products, etc. from the chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the chamber, and then discharge excess reactant, reaction products, etc. from the chamber.

[0113] Furthermore, in the present specification and elsewhere, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

[0114] When the oxide semiconductor 30a is formed using the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed.

[0115] Next, an In-M-Zn oxide is formed as an oxide semiconductor 30b on the oxide semiconductor 30a by sputtering (FIG. 8B). The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure.

[0116] When the oxide semiconductor 30b is formed by sputtering, a mixed layer 31 is formed on or near the surface of the oxide semiconductor 30a. During the formation of the oxide semiconductor 30b, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 31. In a subsequent heat treatment step, the mixed layer 31 or the minute crystalline regions formed in the mixed layer 31 may act as nuclei, causing at least a portion of the oxide semiconductor 30a to crystallize.

[0117] Sputtering methods include RF sputtering, which uses a high-frequency power supply as a sputtering power supply; DC sputtering, which uses a direct-current power supply; and pulsed DC sputtering, which changes the voltage applied to an electrode in a pulsed manner. DC sputtering can be suitably used to form a metal conductive film and can improve productivity due to its high film formation rate. Pulsed DC sputtering can be suitably used to form a metal conductive film and a semiconductor film. RF sputtering can be suitably used to form an insulating film. Compounds such as oxides, nitrides, and carbides can be formed by reactive sputtering using a reactive gas. The metal oxide used for the oxide semiconductor layer of one embodiment of the present invention can be formed by a method appropriately selected from these methods depending on the conductivity of the sputtering target and the like.

[0118] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0119] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0120] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0121] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease by up to about 50% compared to the sputtering target.

[0122] In forming the oxide semiconductor 30b by sputtering, it is preferable to heat the substrate. In forming the metal oxide, increasing the substrate temperature (stage temperature) during metal oxide formation may result in the formation of a metal oxide with high crystallinity. In forming the oxide semiconductor 30b by sputtering, the substrate heating temperature is preferably 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0123] Next, the oxide semiconductor 30c is formed on the oxide semiconductor 30b (FIG. 8C). Here, the oxide semiconductor 30c is formed by the ALD method. For the formation of the oxide semiconductor 30c by the ALD method, the method for forming the oxide semiconductor 30a can be referred to.

[0124] When an oxide semiconductor 30c having a lower crystallinity than the CAAC structure is formed on an oxide semiconductor 30b having a CAAC structure by using an ALD method, the oxide semiconductor 30c may grow epitaxially around the oxide semiconductor 30b as a nucleus. Therefore, when the oxide semiconductor 30c is formed, the oxide semiconductor 30c may have a region having the CAAC structure. Furthermore, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 30c.

[0125] The oxide semiconductor 30c can be used, for example, as a layer in contact with a gate insulating layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0126] Furthermore, by forming the oxide semiconductor 30c using the ALD method, damage to the oxide semiconductor 30b is reduced, and the oxide semiconductor 30 as a whole can have high crystallinity.

[0127] By using the ALD method, which has high coverage, as a method for forming the oxide semiconductors 30a and 30c, the oxide semiconductor layer as a whole can have coverage. Furthermore, by forming the oxide semiconductor 30b with high crystallinity using a sputtering method, the crystallinity of the upper and lower oxide semiconductor layers (the oxide semiconductors 30a and 30c) can be improved by epitaxial growth from the oxide semiconductor 30b. This allows the crystallinity of the oxide semiconductor 30 to be improved throughout the entire layer. Therefore, the oxide semiconductor 30 can have both high coverage and high crystallinity.

[0128] Next, a heat treatment step may be carried out.

[0129] The heat treatment temperature may be, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the heat treatment temperature may be 400° C.±25° C. (375° C. to 425° C.). The treatment time may be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When a rapid thermal annealing (RTA) apparatus is used, the treatment time may be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level gaps in the crystal portions of the CAAC structure of the oxide semiconductor 30b with the oxide semiconductor 30c (in other words, the crystal molecules formed by the ALD method).

[0130] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0131] The heat treatment step may enhance the crystallinity of the region having the CAAC structure in the oxide semiconductor 30c. Furthermore, if the region is formed only below the oxide semiconductor 30c after the ALD deposition, the heat treatment step may cause the region to expand upward ( FIG. 8D ). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 30c.

[0132] Furthermore, the heat treatment process may further repair the oxide semiconductor 30b by the oxide semiconductor 30c (in other words, the crystal molecules formed by the ALD method) filling gaps in the atomic-level crystal portions of the CAAC structure of the oxide semiconductor 30b.

[0133] Furthermore, it is preferable that at least a portion of the oxide semiconductor 30a is converted into CAAC by this heat treatment ( FIG. 8D ). It is expected that the CAAC conversion is facilitated by the mixed layer 31 formed in the oxide semiconductor 30a during the deposition of the oxide semiconductor 30b, which acts as a nucleus or seed. It is preferable that the region in the oxide semiconductor 30a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 29.

[0134] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 30a, the CAAC can be formed up to the vicinity of the layer 29 regardless of the material or crystallinity of the layer 29. For example, even if the layer 29 has an amorphous structure, the oxide semiconductor 30a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0135] After the oxide semiconductor 30c is formed, a microwave treatment may be performed.

[0136] Here, microwave processing refers to processing using a device with a power source that generates high-density plasma using microwaves, for example. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave processing can also be called microwave-excited high-density plasma processing.

[0137] It is preferable to reduce the impurity concentration in the oxide semiconductor 30 by performing microwave treatment in an atmosphere containing oxygen. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave treatment may be performed on an insulating film, more specifically, a silicon oxide film, located near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave treatment may increase the crystallinity of the oxide semiconductor layer.

[0138] The microwave treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or more and 1000 Pa or less, and more preferably being 300 Pa or more and 700 Pa or less. The microwave plasma treatment is preferably carried out with the substrate heated. The substrate temperature is preferably set to a range from room temperature (e.g., 25°C) to 500°C or less, preferably from 100°C to 500°C or less, more preferably from 200°C to 500°C or less, even more preferably from 300°C to 500°C or less, and even more preferably from 400°C to 500°C or less. For example, the temperature can be set to a range from 400°C to 450°C or less.

[0139] Alternatively, after the microwave treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0140] The microwave treatment can be performed using, for example, oxygen gas and argon gas. By performing the microwave treatment in an atmosphere containing oxygen, the oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the oxide semiconductor layer. By the action of plasma, microwaves, or the like, defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer (hereinafter referred to as V Ｏ By splitting V (sometimes referred to as H) into oxygen vacancies and hydrogen, the hydrogen impurities can be removed from the oxide semiconductor layer. ＯH can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave treatment. Furthermore, oxygen radicals generated by the oxygen plasma can be supplied to oxygen vacancies formed in the oxide semiconductor layer, thereby further reducing the oxygen vacancies in the oxide semiconductor layer.

[0141] Oxygen to be implanted into the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). Note that the oxygen to be implanted into the oxide semiconductor layer may be in one or more of the above forms, and is particularly preferably an oxygen radical.

[0142] In this manner, the impurities in the oxide semiconductor layer can be reduced. When crystal growth is performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0143] Note that one or both of the heat treatment and the microwave treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0144] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0145] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0146] In the oxide semiconductor 30, it is preferable that a region having a CAAC structure is widely present throughout the entire layer including the oxide semiconductor 30a and the oxide semiconductor 30c. FIG. 9A shows the crystallization of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c. The crystals in the region having the CAAC structure in the oxide semiconductor 30a are connected to the crystals in the region having the CAAC structure in the oxide semiconductor 30b. The crystals in the region having the CAAC structure in the oxide semiconductor 30c are connected to the crystals in the region having the CAAC structure in the oxide semiconductor 30b. The oxide semiconductor 30 can sometimes be expressed as a single layer with no clearly observed interface. The oxide semiconductor 30 can sometimes be expressed as a single layer.

[0147] The regions having the CAAC structure in the oxide semiconductors 30a, 30b, and 30c can be observed as bright spots aligned parallel to the surface on which they are formed, for example, in cross-sectional observation using a high-resolution TEM. Furthermore, it is preferable that the c-axes of the CAAC structures in the oxide semiconductors 30a, 30b, and 30c are each substantially parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0148] Furthermore, there are cases where a portion of the oxide semiconductor 30a or the oxide semiconductor 30c is not crystallized. The example shown in Fig. 9B shows a state in which the vicinity of the interface with the layer 29 in the oxide semiconductor 30a is not crystallized. Fig. 9C shows a state in which the vicinity of the surface in the oxide semiconductor 30c is not crystallized. Fig. 9D shows a state in which the vicinity of the interface with the layer 29 in the oxide semiconductor 30a and the vicinity of the surface of the oxide semiconductor 30c are not crystallized.

[0149] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor 30, the boundaries between the stacked oxide semiconductors 30a, 30b, and 30c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0150] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 30b and the crystals of the oxide semiconductor 30a or the oxide semiconductor 30c is small. This allows the oxide semiconductor 30a or the oxide semiconductor 30c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 30b. In this case, for example, when a cross section of the oxide semiconductor 30 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor 30a or the oxide semiconductor 30c.

[0151] As long as the lattice mismatch between the crystal of the oxide semiconductor 30b and the crystal of the oxide semiconductor 30a or the oxide semiconductor 30c is small, the crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c is not particularly limited. The crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0152] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0153] When the oxide semiconductor 30 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor 30 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. Furthermore, in transistors used in smaller semiconductor devices, the film thickness of the oxide semiconductor 30 is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, and further preferably 5 nm to 12 nm.

[0154] The oxide semiconductor 30b preferably has a thickness of, for example, 200 nm or less. When the oxide semiconductor 30b has a layer shape, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0155] Alternatively, if the oxide semiconductor 30b can function as a crystal nucleus, the oxide semiconductor 30b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor 30b exist discretely.

[0156] The oxide semiconductor 30a and the oxide semiconductor 30c each have a thickness of, for example, 1 nm to 50 nm, preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 2 nm to 20 nm.

[0157] The thickness of the region where the component contained in the oxide semiconductor 30 and the component contained in the layer 29 are alloyed is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Figures 8A and 8B show an example in which no alloy region is formed between the layer 29 and the oxide semiconductor 30a.

[0158] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0159] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 30a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 30a contains In) that is the main component of the oxide semiconductor 30a but is not the main component of the layer that will become the surface (here, layer 29) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 30a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 30a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0160] Furthermore, for example, when a silicon oxide layer is used as the layer 29 and an SIMS analysis is performed on the oxide semiconductor 30 formed on the layer 29, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 29 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 0.5 nm and the interface is defined as thickness t_s. The thickness t_s is preferably 3 nm or less, and more preferably 2 nm or less.

[0161] By reducing the alloyed region, it is possible to form the CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor 30 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably more than 0 nm and 2 nm, more preferably 1 nm or more and 2 nm, inclusive.

[0162] The oxide semiconductor 30a has a region located, for example, at a distance of 0 to 3 nm from the top surface of the layer 29. The oxide semiconductor 30c is located, for example, at a distance of 0 to 3 nm from the top surface of the oxide semiconductor 30b. The oxide semiconductors 30a, 30b, and 30c have, for example, approximately the same thickness. Alternatively, the oxide semiconductors 30a, 30b, and 30c may have different thicknesses.

[0163] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0164] The CAAC structure of an oxide semiconductor layer can sometimes be evaluated from a map showing crystal orientation. For example, in a region having the CAAC structure, it is observed that crystals are c-axis oriented.

[0165] A map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing a fast Fourier transform (FFT) on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the crystal axis direction of each region. Specifically, for example, two spots of high intensity are observed in the FFT pattern of a region having layered crystal portions. The crystal axis direction of the region can be obtained from the angle of the line segment connecting the two spots. The FFT pattern reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0166] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing the crystal orientation.

[0167] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by performing TEM observation of a cross section or a plan view of the oxide semiconductor layer and using the map showing the crystal orientation described above. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0168] Furthermore, when performing analysis using a cross-sectional TEM image, the observation range of the cross-sectional TEM image can be, for example, a region with a width of 100 nm in the horizontal direction, with the direction perpendicular to the surface to be formed being the vertical direction. However, the observation range is not limited to this.

[0169] In the oxide semiconductor layer of one embodiment of the present invention, when the c-axis orientation rate is calculated as the percentage of regions whose orientation is within 20° of the c-axis, the c-axis orientation rate is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0170] The c-axis orientation rates of the region where the oxide semiconductor 30a is formed, the region where the oxide semiconductor 30b is formed, and the region where the oxide semiconductor 30c is formed are denoted by Rc1, Rc2, and Rc3, respectively. Here, the c-axis orientation rate is calculated as, for example, the percentage of regions where the difference from the c-axis is within 20°. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. It is preferable that Rc3 / Rc1 be greater than 1. It is also preferable that Rc2 / Rc1 be greater than 1.

[0171] [Composition of Oxide Semiconductor Layer] The oxide semiconductor 30a preferably has a different composition from the oxide semiconductor 30b. The oxide semiconductor 30c preferably has a different composition from the oxide semiconductor 30b. The oxide semiconductor 30a may have the same composition as the oxide semiconductor 30c. Alternatively, the oxide semiconductor 30a and the oxide semiconductor 30c may have different compositions.

[0172] The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 30b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor 30b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 30b preferably contains, in addition to zinc, the element M. By containing the element M in the oxide semiconductor 30b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Specifically, the oxide semiconductor 30b may be a metal oxide having an In:M:Zn=1:1:1 atomic ratio or a composition thereof, an In:M:Zn=1:1:1.2 atomic ratio or a composition thereof, an In:M:Zn=1:1:0.5 atomic ratio or a composition thereof, an In:M:Zn=1:1:2 atomic ratio or a composition thereof, an In:M:Zn=4:2:3 atomic ratio or a composition thereof, an In:M:Zn=1:3:2 atomic ratio or a composition thereof, or an In:M:Zn=1:3:4 atomic ratio or a composition thereof. Note that a composition thereof includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, tin, yttrium, and aluminum as the element M.

[0173] The oxide semiconductor 30b may not contain the element M. For example, it may be an In-Zn oxide. Specifically, it may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. Furthermore, it may have a composition containing a trace amount of the element M. For example, it may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, it may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0174] The oxide semiconductor 30a and the oxide semiconductor 30c can be metal oxides having a high proportion of In. It is particularly preferable that the oxide semiconductor 30a and the oxide semiconductor 30c be metal oxides having a higher proportion of In than the oxide semiconductor 30b. For example, the ALD method can be used to form the oxide semiconductor 30a and the oxide semiconductor 30c. It is particularly preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, it is possible to increase the on-current and improve the frequency characteristics when the oxide semiconductor layer is used in a transistor.

[0175] An oxide semiconductor with a high In content tends to be polycrystalline. Using a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. In the oxide semiconductor layer of one embodiment of the present invention, the crystal orientation of the oxide semiconductor 30b can be reflected in the oxide semiconductors 30a and 30c with a high In content. Therefore, even when a metal oxide with a high In content is used for the oxide semiconductors 30a and 30c, polycrystallization can be suppressed.

[0176] Alternatively, the oxide semiconductors 30a and 30c may not contain the element M. For example, they may be In-Zn oxides. Specifically, they may have a composition with an atomic ratio of In:Zn=1:1 or a ratio therebetween, an atomic ratio of In:Zn=2:1 or a ratio therebetween, or an atomic ratio of In:Zn=4:1 or a ratio therebetween. Alternatively, indium oxide may be used. Furthermore, the oxide semiconductors 30a and 30c may contain a trace amount of the element M. Specifically, they may have a composition with an atomic ratio of In:Ga:Zn=4:0.1:1 or a ratio therebetween, an atomic ratio of In:Ga:Zn=2:0.1:1 or a ratio therebetween, an atomic ratio of In:Sn:Zn=4:0.1:1 or a ratio therebetween, or an atomic ratio of In:Sn:Zn=2:0.1:1 or a ratio therebetween.

[0177] Alternatively, metal oxides with a high Ga content may be used for the oxide semiconductors 30a and 30c. For example, metal oxides with a higher Ga content than the oxide semiconductor 30b may be used for the oxide semiconductors 30a and 30c. For example, metal oxides with an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, metal oxides with an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or metal oxides with an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout are preferably used for the oxide semiconductors 30a and 30c, respectively. Increasing the Ga content may result in the band gaps of the oxide semiconductors 30a and 30c being larger than those of the oxide semiconductor 30b. As a result, the oxide semiconductor 30b is sandwiched between the oxide semiconductors 30a and 30c, which have larger band gaps, allowing the oxide semiconductor 30b to function primarily as a current path (channel). Furthermore, the trap levels at and near the interface of the oxide semiconductor 30b can be reduced. This allows a buried channel transistor in which the channel is located away from the insulating layer interface, thereby increasing the field-effect mobility. Furthermore, the influence of interface states that may be formed on the back channel side can be reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation), and improving the reliability of the transistor.

[0178] Alternatively, one of the oxide semiconductors 30a and 30c may be a metal oxide having a higher proportion of In than the oxide semiconductor 30b, and the other may be a metal oxide having a higher proportion of Ga than the oxide semiconductor 30b.

[0179] The oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c may each have a plurality of layers each having the above-described composition stacked together. For example, the oxide semiconductor 30c may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0180] The oxide semiconductor 30a and the oxide semiconductor 30c may be made of a metal oxide having the same composition as the oxide semiconductor 30b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0181] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 30a and 30c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs with the oxide semiconductor 30b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 30a and 30c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductors 30a and 30c and the oxide semiconductor 30b.

[0182] The composition of the metal oxide used in the oxide semiconductor 30 can be analyzed by, for example, EDX, X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0183] [Impurities in Oxide Semiconductor] The influence of each impurity in an oxide semiconductor will be described below. The impurities contained in an oxide semiconductor can be quantified using XPS, SIMS, EDX, ICP-MS, ICP-AES, or the like.

[0184] It is preferable that the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer have fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or metal elements than the source and drain regions. Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H may be formed, and electrons that serve as carriers may be generated. Therefore, when oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor tends to have normally-on characteristics. Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0185] Therefore, reducing the impurity concentration in an oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in an oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 1 atomic % or less than 0.1 atomic % may be referred to as an impurity.

[0186] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10１８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0187] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0188] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0189] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0190] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0191] The average thickness of the oxide semiconductor 30 in the channel formation region is preferably 30 nm or less, more preferably 15 nm or less, and even more preferably 10 nm or less.

[0192] The oxide semiconductor 30a is an oxide semiconductor layer formed on a surface to be formed. The thickness of the oxide semiconductor 30a is preferably 0.5 nm or more and 3 nm or less.

[0193] In addition, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide semiconductor 230 is observed, it may be possible to see that metal atoms of the metal oxide are arranged in a layered manner in a region having a CAAC structure. In this case, for example, the metal atoms are arranged in a direction perpendicular or approximately perpendicular to the substrate surface.

[0194] The metal atoms arranged in a layered manner in the region having the CAAC structure can be observed as bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. Therefore, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide semiconductor 230 is observed, it may be possible to confirm that the bright spots are arranged in a direction perpendicular or substantially perpendicular to the substrate surface.

[0195] The oxide semiconductor 30, which is an AG CAAC, can be used as the oxide semiconductor 230 of the transistor 200. For example, as shown in FIG. 2B , the oxide semiconductor 230 can have a structure including an oxide semiconductor 230a, an oxide semiconductor 230b in contact with the oxide semiconductor 230a, and an oxide semiconductor 230c in contact with the oxide semiconductor 230b. Here, the oxide semiconductor 230a corresponds to the oxide semiconductor 30a, the oxide semiconductor 230b corresponds to the oxide semiconductor 30b, and the oxide semiconductor 230c corresponds to the oxide semiconductor 30c.

[0196] Here, the pillar (the insulator 223 described later) corresponds to the layer 29. That is, the surface on which the oxide semiconductor 230 is formed is the pillar, and the pillar is removed in the transistor 200. During the manufacturing process, one side surface of the oxide semiconductor 230a is in contact with the pillar and the other side surface of the oxide semiconductor 230b. After the pillar is removed, one side surface of the oxide semiconductor 230a is in contact with the insulator 250. One side surface of the oxide semiconductor 230b is in contact with the oxide semiconductor 230a and the other side surface of the oxide semiconductor 230c. One side surface of the oxide semiconductor 230c is in contact with the oxide semiconductor 230b and the other side surface of the oxide semiconductor 230c is in contact with the oxide semiconductor 230b and the insulator 250. Here, since the side surfaces of the pillars are formed perpendicular or approximately perpendicular to the substrate surface (which can also be referred to as the surface of the insulator 222), the side surfaces of the oxide semiconductors 230 (oxide semiconductors 230a to 230c) are also perpendicular or approximately perpendicular to the substrate surface.

[0197] As described above, in the cross section of the oxide semiconductor 230 (the oxide semiconductors 230a to 230c) observed using the TEM image, it is confirmed that metal atoms are arranged in layers parallel to or substantially parallel to the formation surface. In other words, in the cross section of the oxide semiconductor 230 (the oxide semiconductors 230a to 230c) observed using the TEM image, it is confirmed that metal atoms are arranged in layers perpendicular to or substantially perpendicular to the substrate surface. It can also be said that the c-axis of the axial growth CAAC is substantially parallel to the normal direction to the side surface of the oxide semiconductor 230.

[0198] In this manner, by using the oxide semiconductor 230, which is AG CAAC, for the channel formation region of the transistor 200, a transistor with favorable on-state current, field-effect mobility, S value, frequency characteristics, and reliability can be provided.

[0199] Furthermore, when the oxide semiconductor 230 has a three-layer structure of oxide semiconductors 230a to 230c as described above, the oxide semiconductor 230 is formed in the order of oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c, centered on the region where the pillars were formed. Therefore, as shown in FIG. 4A , in a cross-sectional view in the channel width direction, the oxide semiconductor 230c, oxide semiconductor 230b, oxide semiconductor 230a, oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c are arranged symmetrically in this order. That is, to make the oxide semiconductor 230 have a bilaterally symmetric structure in a cross-sectional view, it is preferable that the oxide semiconductors 230a and 230c have approximately the same composition. It is also preferable that the oxide semiconductors 230a and 230c have approximately the same film thickness. 2B is equal to or greater than 80° and less than 90°, that is, when the side surface of the oxide semiconductor 230 is slightly tilted, the tilt of the oxide semiconductor 230 is arranged symmetrically as shown in Fig. 4B. When the oxide semiconductor 230 is formed with a tilt, the upper part of the oxide semiconductor 230 may be thinner than the lower part of the oxide semiconductor 230, as shown in Fig. 4B.

[0200] A channel formation region and a source region and a drain region sandwiching the channel formation region in the transistor 200 are formed in the oxide semiconductor 230. At least part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0201] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0202] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0203] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0204] Note that when the carrier concentration of the oxide semiconductor 230 is reduced, the impurity concentration in the oxide semiconductor 230 is reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0205] To stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region in the oxide semiconductor 230. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide semiconductor 230 refer to, for example, elements other than the main components constituting the oxide semiconductor 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0206] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide semiconductor 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in a region closer to the channel formation region.

[0207] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, impurities, oxygen vacancies, and V Ｏ It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and the channel formation region be i-type (intrinsic) or substantially i-type.

[0208] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and VＯ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0209] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce the V Ｏ It is preferable to prevent the amount of H from being reduced excessively. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0210] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, and suppress reduction in the hydrogen concentration in the source and drain regions.

[0211] The insulator 250 in contact with the channel formation region of the oxide semiconductor 230 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0212] 2A , the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. In this case, the insulator 250a and the insulator 250c preferably have a function of capturing hydrogen or fixing hydrogen.

[0213] Examples of insulators that have the function of capturing or fixing hydrogen include metal oxides with an amorphous structure. For the insulators 250a and 250c, it is preferable to use, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides with an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0214] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulators 250a and 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulators 250a and 250c makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0215] For the insulators 250a and 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0216] In this embodiment, an aluminum oxide film is used as the insulator 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulator 250a in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 and the like can be more effectively captured and fixed.

[0217] In this embodiment, hafnium oxide is used as the insulator 250c. By providing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0218] Next, it is preferable to use a thermally stable insulator such as silicon oxide or silicon oxynitride for the insulator 250b. Note that in this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0219] The silicon oxide film used as the insulator 250b is preferably formed using a PEALD method.

[0220] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 250a, the insulator 250d, the insulator 250c, and the insulator 275.

[0221] In this specification and the like, a barrier insulator refers to an insulator with barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulator with barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulator. Furthermore, for example, an insulator with barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0222] Examples of the oxygen barrier insulator include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, 250d, and 275 each preferably have a single-layer structure or a stacked-layer structure of the above-mentioned oxygen barrier insulators.

[0223] The insulator 250a preferably has a barrier property against oxygen. The insulator 250a is preferably at least less permeable to oxygen than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. The insulator 250a has a barrier property against oxygen, which can prevent the side surfaces of the conductor 242a and the conductor 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0224] The insulator 250a is provided in contact with the top surface and side surface of the oxide semiconductor 230 and the top surface of the insulator 222. The insulator 250a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the oxide semiconductor 230 during heat treatment or the like. Thus, oxygen vacancies can be reduced in the oxide semiconductor 230.

[0225] Furthermore, the insulator 250a prevents excessive oxygen from being supplied from the insulator 280 to the oxide semiconductor 230, and enables an appropriate amount of oxygen to be supplied to the oxide semiconductor 230. Therefore, excessive oxidation of the source and drain regions can be suppressed, which can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0226] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and can therefore be suitably used as the insulator 250a.

[0227] The insulator 250d also preferably has a barrier property against oxygen. The insulator 250d is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260 and between the insulator 280 and the conductor 260. With this structure, oxygen contained in the channel formation region of the oxide semiconductor 230 can be prevented from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor 230. Furthermore, oxygen contained in the oxide semiconductor 230 and oxygen contained in the insulator 280 can be prevented from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250d is preferably at least less permeable to oxygen than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0228] The insulator 250d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide semiconductor 230.

[0229] The insulator 275 also preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a and between the insulator 280 and the conductor 242b. The insulator 275 is provided in contact with the side surface of the conductor 242, the side surface of the oxide semiconductor 230, and the top surface of the insulator 222. This structure can prevent oxygen contained in the insulator 280 from diffusing into the conductor 242. Therefore, an increase in resistivity due to oxidation of the conductor 242 caused by the oxygen contained in the insulator 280 can be prevented. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, silicon nitride is preferably used as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0230] A barrier insulator against hydrogen is preferably provided near each of the source and drain regions in order to suppress a decrease in the hydrogen concentrations in the source and drain regions of the oxide semiconductor 230. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, the insulator 275.

[0231] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0232] By providing the insulator 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making it possible to make the source and drain regions n-type.

[0233] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve frequency characteristics. Specifically, the cutoff frequency can be improved.

[0234] The insulators 250a to 250d function as part of the gate insulator. The insulators 250a to 250d, together with the conductor 260, are provided in the opening formed in the insulator 280. To miniaturize the transistor 200, the thicknesses of the insulators 250a to 250d are preferably small. The thicknesses of the insulators 250a to 250d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulators 250a to 250d may have a region with the above thickness at least in part.

[0235] Furthermore, the thickness of the silicon oxide film used as the insulator 250b is preferably 0.7 nm or more and 3 nm or less.

[0236] To thin the film thicknesses of the insulators 250a to 250d as described above, it is preferable to deposit the insulators by an ALD method. Furthermore, to provide the insulators 250a to 250d in openings in the insulator 280 and the like, it is preferable to deposit the insulators by an ALD method. Examples of ALD methods include thermal ALD (thermal ALD), which uses only thermal energy to cause a reaction between a precursor and a reactant, and plasma-enhanced ALD (PEALD), which uses a plasma-excited reactant. The PEALD method may be preferable because it uses plasma, which enables film deposition at a lower temperature.

[0237] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, the formation of films at low temperatures, etc. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the openings formed in the insulator 280 and the side ends of the conductors 242a and 242b, etc., with a thin film thickness as described above.

[0238] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using SIMS, XPS, or Auger Electron Spectroscopy (AES).

[0239] Although the above description has been given of a structure in which the insulator 250 has a four-layer structure of the insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can have a structure including at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0240] For example, as shown in Fig. 3A, the insulator 250 may have a three-layer structure. In this case, it is preferable that the insulator 250 has a layered structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In other words, this is the same as the structure shown in Fig. 2A except that the insulator 250d is removed.

[0241] It is preferable to use the ALD process two or more times in forming the insulator 250. For example, the insulator 250 preferably has a stacked structure of multiple insulating films, and two or more of the multiple insulating films are preferably formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulator 250. Furthermore, it is possible to increase productivity by continuously forming two or more different films, for example, two or more insulating films, using the ALD process.

[0242] In addition to the above structure, it is preferable to have a structure that suppresses hydrogen from being mixed into the transistor 200 or the like. For example, it is preferable to provide an insulator that has a function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor 200 or the like. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 283, the insulator 282, the insulator 222, or the insulator 221. Furthermore, the insulator 215 provided under the transistor 200 may have a structure similar to either or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom.

[0243] It is preferable that one or more of the insulators 283, 282, 222, and 221 function as barrier insulators that suppress diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, one or more of the insulators 283, 282, 222, and 221 suppress diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0244] The insulators 283, 282, 222, and 221 each preferably have an insulator that functions to suppress the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulators 283 and 221 are preferably made of silicon nitride, which has a high hydrogen barrier property. Furthermore, for example, the insulator 282 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. Furthermore, for example, the insulator 222 is preferably made of hafnium oxide, which is a high-dielectric-constant (high-k) material and has a high ability to capture or fix hydrogen.

[0245] At least one of the insulators 221 and 222 can have a stacked structure of silicon oxide or silicon oxynitride in addition to the above-described materials. For example, the insulator 221 can have a stacked structure of silicon nitride and silicon oxide. For example, the insulator 222 can have a stacked structure of hafnium oxide and silicon oxide.

[0246] With this structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged above the insulator 283 to the transistor 200 and the like. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged below the insulator 221 to the transistor 200 and the like. Furthermore, hydrogen contained in the insulator 280, the insulator 250, and the like can be captured and fixed to the insulator 282 or the insulator 222. Furthermore, the provision of the insulators 282 and 283 can prevent oxygen contained in the insulator 280 and the like from diffusing upward from the transistor 200 and the like. Furthermore, the provision of the insulators 222 and 221 can prevent oxygen contained in the oxide semiconductor 230 and the like from diffusing downward from the transistor 200 and the like. Thus, by surrounding the transistor 200 from above and below with insulators that have a function of preventing the diffusion of impurities such as water and hydrogen and oxygen, the diffusion of excess oxygen and hydrogen into the oxide semiconductor can be reduced. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0247] Furthermore, it is preferable to use silicon nitride or the like, which has a higher hydrogen barrier property, for the insulators 275 and 250d. It is also preferable to use aluminum oxide or the like, which has a high ability to capture or fix hydrogen, for the insulator 250a. It is also preferable to use hafnium oxide or the like, which has a high ability to capture or fix hydrogen, for the insulator 250c.

[0248] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as the conductors 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 are conductors that contain at least metal and nitrogen.

[0249] The conductor 242a and the conductor 242b are disposed apart from each other and are provided in contact with the oxide semiconductor 230. As shown in FIG. 6A and other figures, the conductor 242 is provided so as to cover the oxide semiconductor 230, which has a high aspect ratio. Furthermore, the conductor 242a (the conductor 242b) preferably has a structure in which it is in contact with two or more fin-shaped oxide semiconductors 230 in a cross-sectional view, as shown in FIG. 1C .

[0250] Here, as shown in FIG. 6A , near the source or drain of the transistor 200, the conductor 242a is provided so as to be folded in half with the oxide semiconductor 230 sandwiched therebetween. As a result, in a cross-sectional view in the channel width direction, the conductor 242a is in contact with the oxide semiconductor 230 at the top, the side surface on the A3 side, and the side surface on the A4 side of the oxide semiconductor 230. Therefore, compared to when the oxide semiconductor 230 is formed in a planar shape, the contact area between the conductor 242a and the oxide semiconductor 230 is increased by the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230. Furthermore, by using a structure in which multiple fin-shaped oxide semiconductors 230 are in contact with the conductor 242a as shown in FIG. 1C , the contact area can be further increased. Note that while FIGS. 6A and 1C show the vicinity of the conductor 242a, the same applies to the conductor 242b. That is, similar to the contact area between the conductor 242a and the oxide semiconductor 230 described above, the contact area between the conductor 242b and the oxide semiconductor 230 is increased.

[0251] By increasing the contact area between the conductor 242 and the oxide semiconductor 230 as described above, the on-state current, frequency characteristics, and the like of the transistor 200 can be improved without increasing the area occupied by the transistor 200. As a result, a semiconductor device with high operating speed can be provided. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, as a result, miniaturization or high integration of the semiconductor device can be achieved. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0252] The conductor 242a and the conductor 242b are preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion because they are in contact with the oxide semiconductor 230. This can suppress a decrease in the conductivity of the conductor 242a and the conductor 242b. Furthermore, it can suppress the extraction of oxygen from the oxide semiconductor 230, which can cause excessive oxygen vacancies to be formed. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the conductor 242a and the conductor 242b, because this can reduce the hydrogen concentration in the oxide semiconductor 230.

[0253] As the conductor 242, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen.

[0254] Note that hydrogen contained in the oxide semiconductor 230 or the like might diffuse to the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used for the conductor 242a and the conductor 242b, hydrogen contained in the oxide semiconductor 230 or the like is likely to diffuse to the conductor 242a or the conductor 242b, and the diffused hydrogen might bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide semiconductor 230 or the like might be absorbed by the conductor 242a or the conductor 242b.

[0255] To prevent a decrease in the conductivity of the conductor 242a and the conductor 242b, a crystalline oxide such as CAAC-OS can be used as the oxide semiconductor 230. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. The use of CAAC-OS can prevent the conductor 242a or the conductor 242b from extracting oxygen from the oxide semiconductor 230. Furthermore, a decrease in the conductivity of the conductor 242a and the conductor 242b can be prevented.

[0256] 3B , the conductor 242a and the conductor 242b may have a two-layer structure. The conductor 242a may be a stacked film of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b may be a stacked film of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, the layers in contact with the oxide semiconductor 230 (the conductors 242a1 and 242b1) are preferably made of the above-mentioned conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion. This can suppress a decrease in the conductivity of the conductor 242a and the conductor 242b. Furthermore, it can suppress the extraction of oxygen from the oxide semiconductor 230, which can result in the formation of an excessive amount of oxygen vacancies. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the layers in contact with the oxide semiconductor 230 (the conductor 242a1 and the conductor 242b1) because the hydrogen concentration in the oxide semiconductor 230 can be reduced.

[0257] Furthermore, the conductors 242a2 and 242b2 preferably have higher conductivity than the conductors 242a1 and 242b1. For example, the film thicknesses of the conductors 242a2 and 242b2 are preferably larger than the film thicknesses of the conductors 242a1 and 242b1. Conductors that can be used for the conductor 260b described below may be used for the conductors 242a2 and 242b2. The above structure can reduce the resistance of the conductors 242a2 and 242b2. This increases the on-state current of the transistor 200, thereby improving the operating speed of the semiconductor device according to this embodiment.

[0258] For example, tantalum nitride or titanium nitride can be used as the conductors 242a1 and 242b1, and tungsten can be used as the conductors 242a2 and 242b2.

[0259] Furthermore, as shown in FIG. 3C , in a cross-sectional view of the transistor 200 in the channel length direction, the conductor 242a1 and the conductor 242b1 may be configured to protrude more than the conductor 242a2 and the conductor 242b2, respectively. The protruding portions of the conductor 242a1 and the conductor 242b1 are covered with an insulator 250. Here, the distance between the conductor 242a1 and the conductor 242b1 is smaller than the distance between the conductor 242a2 and the conductor 242b2. This configuration makes it possible to further shorten the distance between the source and the drain, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. In this way, miniaturization of the semiconductor device can provide a semiconductor device with improved operating speed.

[0260] 1B and 1D , the conductor 260 is disposed in an opening formed in the insulator 280 and the insulator 275. The conductor 260 is disposed in the opening so as to cover the top surface of the insulator 222, the side surface of the oxide semiconductor 230, and the top surface of the oxide semiconductor 230 via the insulator 250. The top surface of the conductor 260 is disposed so as to be flush or approximately flush with the height of the uppermost portion of the insulator 250 and the top surface of the insulator 280.

[0261] In the opening in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may have a tapered shape. By making the sidewall tapered, the coverage of the insulator 250 and the like provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.

[0262] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction, as shown in Figures 1A and 1B. With this configuration, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0263] A part of the conductor 260 is provided so as to be folded in half with the fin-shaped oxide semiconductor 230 sandwiched therebetween. As a result, as shown in FIG. 2B , in a cross-sectional view in the channel width direction, the oxide semiconductor 230 and the conductor 260 are provided to face each other with the insulator 250 sandwiched between them at the upper part, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230. In other words, the upper part, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230 each function as a channel formation region. Therefore, compared to when the oxide semiconductor 230 has a planar shape, the channel width of the transistor 200 is increased by the amount of the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230.

[0264] In Figure 1D and other figures, the conductor 260 is shown as having a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0265] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0266] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 280, etc. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0267] The conductor 260b is preferably made of a highly conductive material. For example, the conductor 260b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0268] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill an opening formed in the insulator 280 or the like. Here, the side surface of the insulator 280 in the opening coincides with or substantially coincides with the side surface of the conductor 242a and the side surface of the conductor 242b. Therefore, the conductor 260 can be arranged to overlap the region between the conductor 242a and the conductor 242b without alignment.

[0269] The insulators 216 and 280 preferably have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0270] For example, it is preferable that the insulators 216 and 280 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0271] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0272] Furthermore, the top surfaces of the insulators 216 and 280 may each be flattened.

[0273] It is preferable that the concentration of impurities such as water and hydrogen be reduced in the insulator 280. For example, it is preferable that the insulator 280 have an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0274] Conductor 240a and conductor 240b are formed in openings of insulators 275, 280, 282, and 283, respectively. The lower surface of conductor 240a contacts the upper surface of conductor 242a, and the lower surface of conductor 240b contacts the upper surface of conductor 242b. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 283 are approximately the same.

[0275] The conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240 may also have a layered structure in which a first conductor is provided in contact with the side surface of the insulator 241 and a second conductor is provided further inside. In this case, the above-mentioned conductive material can be used as the second conductor. Here, the first conductor corresponds to the conductor 240a1 shown in FIG. 6A, and the second conductor corresponds to the conductor 240a2 shown in FIG. 6A.

[0276] Furthermore, when the conductor 240 has a layered structure, the first conductor disposed near the insulators 283, 282, 280, and 275 is preferably made of a conductive material that has a function of suppressing permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, the conductive material that has a function of suppressing permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulator 283 can be prevented from entering the oxide semiconductor 230 through the conductors 240a and 240b.

[0277] The insulators 241a and 241b are formed in contact with the inner walls of the openings of the insulators 275, 280, 282, and 283, respectively. The inner side surface of the insulator 241a contacts the conductor 240a, and the inner side surface of the insulator 241b contacts the conductor 240b.

[0278] The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. Providing the insulator 241 can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide semiconductor 230 through the conductor 240a and the conductor 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

[0279] When the insulator 241 has a layered structure as shown in Figure 1D, it is preferable that the first insulator in contact with the inner wall of the opening, such as insulator 280, and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0280] For example, the first insulator may be aluminum oxide formed by thermal ALD, and the second insulator may be silicon nitride formed by PEALD. This configuration can suppress oxidation of the conductor 240 and further reduce hydrogen contamination of the conductor 240.

[0281] Although the above describes a configuration in which the insulator 241 has a two-layer stacked structure, the present invention is not limited to this. For example, the insulator 241 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, although the above describes a configuration in which the conductor 240 has a two-layer stacked structure, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers.

[0282] For example, as shown in FIG. 6A , a structure may be used in which the conductor 240a covers the oxide semiconductor 230 and the conductor 242a that is folded in half with the oxide semiconductor 230 sandwiched therebetween. As a result, in a cross-sectional view in the channel width direction, the conductor 240a contacts the conductor 242a at the top, the side surface on the A3 side, and the side surface on the A4 side of the oxide semiconductor 230. Therefore, compared to when the oxide semiconductor 230 is formed in a planar shape, the contact area between the conductor 240a and the conductor 242a is increased by the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230. Furthermore, as shown in FIG. 1C , a structure in which the conductor 240a covers multiple fin-shaped oxide semiconductors 230 can further increase the contact area between the conductor 240a and the conductor 242a. Note that while FIGS. 6A and 1C show the vicinity of the conductor 240a and the conductor 242a, the same applies to the conductor 240b and the conductor 242b. That is, similar to the above-described conductor 240a and conductor 242a, the contact area between conductor 240b and conductor 242b is large.

[0283] As described above, by increasing the contact area between the conductor 240 and the conductor 242, the contact resistance between the conductor 240 and the conductor 242 can be reduced. This allows the on-state current, frequency characteristics, and the like of the transistor 200 to be improved without significantly increasing the area occupied by the transistor 200. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0284] Note that in the above description, as shown in FIG. 1A , the shape of the opening through which the conductor 240 and the insulator 241 are provided is rectangular in top view; however, this is not limiting. For example, the opening may be circular, approximately circular (e.g., elliptical), polygonal (e.g., rectangular), or polygonal (e.g., rectangular) with rounded corners, in top view. As shown in FIG. 1C , the opening is formed to overlap with multiple fin-shaped oxide semiconductors 230; however, this is not limiting and the opening may be formed to overlap at least the conductor 242 a or the conductor 242 b. For example, as shown in FIG. 6B , a part of the opening (which can also be referred to as a part of the conductor 240) may overlap with the oxide semiconductor 230, and another part of the opening (which can also be referred to as another part of the conductor 240) may not overlap with the oxide semiconductor 230. By configuring the opening so that a part of the conductor 240 overlaps with the oxide semiconductor 230, the margin for arranging the conductor 240 can be increased. Alternatively, for example, as shown in FIG. 6C , the opening and the conductor 240 can be provided in a region that does not overlap with the oxide semiconductor 230 .

[0285] 1D , 6B, and 6C , the conductor 240a and the conductor 240b are arranged symmetrically with respect to the conductor 260, but the present invention is not limited to this. For example, as shown in FIG. 7A , in a cross-sectional view in the channel length direction, the conductor 240a may be arranged so that part of the conductor 240a overlaps with the oxide semiconductor 230 and the conductor 240b does not overlap with the oxide semiconductor 230. For example, as shown in FIG. 7B , in a cross-sectional view in the channel length direction, the conductor 240a may be arranged so that part of the conductor 240a overlaps with the oxide semiconductor 230 and the conductor 240b does not overlap with the oxide semiconductor 230.

[0286] 10A to 10D , the semiconductor device of this embodiment may have a structure in which an insulator 224 is provided under the oxide semiconductor 230. The top surface of the insulator 224 has the same shape as that of the oxide semiconductor 230, and the insulator 224 overlaps with the oxide semiconductor 230 in top view. The bottom surface of the insulator 224 is in contact with the insulator 222, the side surfaces of the insulator 224 are in contact with the insulator 250 and the conductor 242, and the top surface of the insulator 224 is in contact with the bottom surface of the oxide semiconductor 230. The insulator 224 may be formed using an insulating material that can be used for the insulator 250b. For example, silicon oxide can be used as the insulator 224. Since FIGS. 10A to 10D correspond to FIGS. 1A to 1D , the above description can be referred to for detailed configurations.

[0287] 11 , it is preferable that the thickness t2 of the insulator 250 in the openings of the insulator 280 and the insulator 275 be thinner than the thickness t1 of the insulator 224. With this configuration, the bottom surface of the conductor 260 (conductor 260a) located in the opening can be positioned lower than the bottom surface of the oxide semiconductor 230 by the difference (t1−t2) between the thickness t1 and the thickness t2.

[0288] By disposing the bottom surface of the conductor 260 below the bottom surface of the oxide semiconductor 230, a gate electric field can be applied sufficiently from the top end to the bottom end of the oxide semiconductor 230. In other words, the entire oxide semiconductor 230 is electrically surrounded by the electric field of the conductor 260 in the opening of the insulator 280 or the like, and can function as a channel formation region. This configuration prevents the bottom end of the oxide semiconductor 230 from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, it is possible to suppress characteristic defects, such as normally-on transistor behavior, that are caused by the parasitic channel. In other words, the electrical characteristics of the transistor 200 can be improved.

[0289] Furthermore, as described above, the oxide semiconductor 230 functions as a channel formation region from the top end to the bottom end, whereby the channel width can be increased, which can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200.

[0290] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is arranged so as to surround at least two sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to provide a transistor in which the short channel effect is less likely to occur.

[0291] Note that the S-channel structure electrically surrounds the channel formation region, and therefore, can be said to be substantially equivalent to a gate all around (GAA) structure or a lateral gate all around (LGAA) structure. By forming the transistor 200 in the S-channel structure, the GAA structure, or the LGAA structure, a channel formation region formed at or near the interface between the oxide semiconductor 230 and a gate insulator can be formed in the entire bulk of the oxide semiconductor 230. Therefore, the current density flowing through the transistor can be increased, which is expected to result in an increase in the on-state current or the field-effect mobility of the transistor. In one embodiment of the present invention, the oxide semiconductor 230 has a CAAC structure and a fin-like structure. With this structure, a current path flowing to the source and drain of the transistor can be parallel to the a-b plane of the crystal axis. In other words, an oxide semiconductor having a CAAC structure and a fin-like structure has a conduction path equivalent to that of a two-dimensional semiconductor material, and by using such an oxide semiconductor, a device having two-dimensional conduction can be fabricated.

[0292] 12A to 12D , the semiconductor device of this embodiment may have a structure in which a conductor 205 is provided under an insulator 221. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200. The insulators 222 and 221 each have a region that functions as a second gate insulator of the transistor 200. Here, FIGS. 12A to 12D correspond to FIGS. 1A to 1D , and therefore the above description can be referred to for detailed configurations.

[0293] In the transistor 200, the conductor 205 is arranged to overlap with the oxide semiconductor 230 and the conductor 260. Here, the conductor 205 is preferably provided to be embedded in an opening formed in the insulator 216. Furthermore, the conductor 205 is preferably provided to extend in the channel width direction as shown in FIGS. 12A and 12B . With such a structure, the conductor 205 functions as a wiring when a plurality of transistors are provided.

[0294] 12B and 12D, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to fill the recess of the conductor 205a formed along the opening. Here, the height of the upper surface of the conductor 205 coincides with or approximately coincides with the height of the upper surface of the insulator 216.

[0295] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0296] By using a conductive material that can reduce hydrogen diffusion for the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide semiconductor 230 via the insulator 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0297] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0298] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0299] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match the electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore, diffusion of the impurities into the oxide semiconductor 230 can be suppressed.

[0300] Although the above describes a layered structure of conductor 205a and conductor 205b, the present invention is not limited to this, and conductor 205 may have a single-layer structure or a layered structure of three or more layers. For example, when conductor 205 has a three-layer layered structure, the layered structure of conductor 205a and conductor 205b may further include a conductor made of the same material as conductor 205a provided on conductor 205b. In this case, the conductor may be formed so that the top surface of conductor 205b is lower than the top of conductor 205a, and the conductor fills the recess formed by conductor 205a and conductor 205b.

[0301] 13A, the transistor 200, the capacitor 460, and the transistor 310 formed on a silicon substrate can be used to function as a 2T (transistor) 1C (capacitor) memory cell. As shown in Fig. 13A, a layer including the transistor 200 and the capacitor 460 can be provided over a layer including the transistor 310. Fig. 14A shows a cross-sectional view of the transistor 200 in the channel width direction, Fig. 14B shows a cross-sectional view of the capacitor 460 in the channel width direction, and Fig. 14C shows a cross-sectional view of the transistor 310 in the channel width direction.

[0302] The transistor 310 is provided over a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that includes part of the substrate 311, and low-resistance regions 314a and 314b that function as source and drain regions. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single-crystal silicon substrate.

[0303] As shown in FIG. 14C , the transistor 310 has a semiconductor region 313 (a part of the substrate 311) where a channel is formed, which has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. An insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0304] Note that the transistor 310 illustrated in FIG. 13A is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0305] A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0306] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. A conductor 328 or the like is embedded in the insulators 320 and 322. A conductor 330 or the like is embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0307] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0308] The transistor 200 and the capacitor 460 are provided over the insulator 326. Here, the transistor 200 shown in FIG. 3C is used as the transistor 200. The structures of the transistor 200 and the layer in which the transistor 200 is formed are the same as those described above and are indicated by the same hatching patterns and symbols. For detailed structures, refer to the above description. Note that an insulator 285 is formed over the insulator 283, and a conductor 413 electrically connected to the conductor 240a is formed over the insulator 285. The insulator 285 can be formed using an insulating material that can be used for the insulator 216. The conductor 413 can be formed using a conductive material that can be used for the conductor 242.

[0309] The capacitor 460 includes an oxide semiconductor 452, a conductor 242b1 over the oxide semiconductor 452, an insulator 454 over the conductor 242b1, and a conductor 456 over the insulator 454. As shown in FIGS. 13A , 14A , and 14B , the oxide semiconductor 452 has a structure similar to that of the oxide semiconductor 230 and can be formed in the same process. The conductor 242b1 is also used in the transistor 200. The insulator 454 has a structure similar to that of the insulator 250 and can be formed in the same process. The conductor 456 has a structure similar to that of the conductor 260 and can be formed in the same process. Note that the conductors 456 and 260 can be extended to function as wirings.

[0310] Here, the capacitor 460 includes a conductor 242b1 functioning as a first electrode, a conductor 456 functioning as a second electrode, and an insulator 454 functioning as a dielectric. That is, the capacitor 460 forms a metal-insulator-metal (MIM) capacitor.

[0311] The capacitor 460 has a structure similar to that of the transistor 200 and can be formed in the same layer as the transistor 200 in parallel. Therefore, the insulator 454 and the conductor 456 are provided in openings formed in the insulator 280 and the insulator 275. However, the capacitor 460 differs from the transistor 200 in that the conductor 242b1 overlaps with the conductor 456 and the insulator 454. Therefore, the opening reaches the conductor 242b1, and the insulator 454 contacts the top surface of the conductor 242b1 in the opening.

[0312] 14B , the oxide semiconductor 452 of the capacitor 460 has a structure with a high aspect ratio, similar to the oxide semiconductor 230. Therefore, a plurality of oxide semiconductors 230 can be provided. Therefore, similar to the oxide semiconductor 230, the height of the oxide semiconductor 452 is larger than the width of the oxide semiconductor 452 in a cross-sectional view in the channel width direction. Furthermore, similar to the oxide semiconductor 230, the oxide semiconductor 452 has two or more regions where the oxide semiconductor 452 and the conductor 456 overlap with each other in a top view. Therefore, the area where the conductor 242b1, the insulator 454, and the conductor 456, which are provided along the top surface and side surface of the oxide semiconductor 452, face each other can be increased. As a result, the capacitance can be increased without significantly increasing the area occupied by the capacitor 460.

[0313] Furthermore, it is preferable to provide a conductor 458 in openings formed in the insulators 215, 216, 221, and 222. The conductor 458 can have a structure similar to that of the conductor 240, for example. The upper surface of the conductor 458 is in contact with the lower surface of the conductor 242b1 and can be electrically connected to the conductor 330. Note that while only one conductor 458 is shown in FIG. 13A , this is not limiting, and two or more conductors may be used to electrically connect the conductor 242b1 and the conductor 330. Furthermore, a configuration in which a portion of the conductor 242b1 is embedded in the openings formed in the insulators 215, 216, 221, and 222 may be used.

[0314] With the above structure, one of the source and drain of the transistor 200, one electrode of the capacitor 460, and the gate of the transistor 310 are electrically connected to form a 2T1C memory cell. Note that a 1T1C memory cell can also be formed by using a structure without the transistor 310. Furthermore, a 2T0C memory cell can also be formed by using a structure without the capacitor 460.

[0315] Here, the transistor 310 is preferably provided so as to overlap with at least one of the transistor 200 and the capacitor 460. For example, the transistor 310 can overlap with the transistor 200. With such a structure, the area occupied by the memory cell can be reduced.

[0316] 13A illustrates a structure in which the transistor 200 and the capacitor 460 include the oxide semiconductor 230 and the oxide semiconductor 452, respectively, but the present invention is not limited to this. For example, as illustrated in FIG. 13B , a structure insulator 250, a conductor 260, an insulator 454, and a conductor 456 may be formed over the oxide semiconductor 230. That is, the transistor 200 and the capacitor 460 may share the oxide semiconductor 230. This eliminates the need to separately pattern the oxide semiconductor 230 for the transistor 200 and the capacitor 460, thereby reducing the area occupied by the transistor 200 and the capacitor 460.

[0317] Although the structure shown in FIG. 13A illustrates a configuration in which the transistor 310 is formed on a silicon substrate, the present invention is not limited to this. For example, as shown in FIG. 15A , two transistors (hereinafter referred to as transistors 200a and 200b) having the same structure as the above-described transistor 200 may be provided. Here, the transistors 200a and 200b are formed in the same layer and arranged so that their channel length directions intersect with each other. Note that the transistors 200a and 200b have the same structure as the transistor 200, and therefore the components are indicated by the same hatched patterns and symbols. For detailed structure, please refer to the above description.

[0318] 15A , the capacitor 400 is provided over the insulator 285. The capacitor 400 includes a conductor 410 over the insulator 285, an insulator 430 over the conductor 410, and a conductor 420 over the insulator 430. The conductor 240b, the insulator 241b, the conductor 240c, and the insulator 241c are provided in contact with the bottom surface of the conductor 410. The conductor 240c and the insulator 241c are formed so as to be embedded in the openings of the insulators 282, 283, and 285, and have the same structure as the conductor 240b and the insulator 241c. The bottom surface of the conductor 240c is in contact with the top surface of the conductor 260 of the transistor 200b. With this structure, one of the source and drain of the transistor 200a, one electrode of the capacitor 400, and the gate of the transistor 200b are electrically connected to each other.

[0319] The capacitor 400 includes a conductor 410 functioning as a first electrode, a conductor 420 functioning as a second electrode, and an insulator 430 functioning as a dielectric. That is, the capacitor 400 forms an MIM capacitor.

[0320] The conductor 410 and the conductor 420 may be made of a conductive material that can be used for the conductor 260. For example, tungsten can be used for the conductor 410 and the conductor 420. Here, by using a structure in which the conductor 420 covers the conductor 410, the side surface of the conductor 410 can function as the capacitor 400. This allows the capacitance of the capacitor 400 to be increased. The conductor 413 can be formed simultaneously with the conductor 410.

[0321] Although the conductors 410, 413, and 420 each have a single-layer structure, they are not limited to this structure and may have a stacked structure of two or more layers. For example, a stacked structure of a conductor having barrier properties and a conductor with high conductivity may be used. For example, a stacked structure of titanium nitride and tungsten on titanium nitride may be used.

[0322] The insulator 430 of the capacitor 400 is preferably made of a high-dielectric-constant (high-k) material. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Using such high-k materials makes it possible to thicken the insulator 430 to suppress leakage current and ensure sufficient capacitance of the capacitor 400. Furthermore, since the insulator 430 is formed to cover the conductor 410, it is preferable to form the insulator 430 using a film formation method with good coverage, such as an ALD method or a CVD method.

[0323] The insulator 430 may also have a layered structure. It is preferable to use a layered structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-dielectric-constant (high-k) material. Materials with a high dielectric strength (materials with a low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added. The insulator 430 may have a layered structure of aluminum oxide, a high-dielectric-constant (high-k) material, and silicon oxide with a high dielectric strength on the aluminum oxide.

[0324] For example, the insulator 430 can be an insulator stacked in this order: zirconium oxide, aluminum oxide, and zirconium oxide. For example, the insulator 430 can be an insulator stacked in this order: zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide. For example, the insulator 430 can be an insulator stacked in this order: hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide. By stacking insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown of the capacitor 400 can be suppressed.

[0325] Furthermore, a material that can have ferroelectricity may be used as the insulator 430. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of zirconium atoms to the number of element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close to 1:1. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0326] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0327] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0328] Although the above description has been given with reference to metal oxides and metal nitrides, the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, may also be used.

[0329] Furthermore, the material capable of exhibiting ferroelectricity may be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the insulator 430 may have a layered structure of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, not only materials that exhibit ferroelectricity are referred to as ferroelectrics, but also as materials capable of exhibiting ferroelectricity.

[0330] 15A, the shape of the capacitor 400 is a planar type, but the shape of the capacitor 400 in the memory device described in this embodiment is not limited to this. For example, the shape of the capacitor 400 may be a cylinder or a pillar.

[0331] An insulator 487 is provided to cover the capacitor 400, and an insulator 488 is provided to cover the insulator 487. The insulator 487 is preferably an insulator that has a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulator 487. The insulator 488 is preferably an insulator that has a function of suppressing diffusion of hydrogen. For example, silicon nitride, which has a higher hydrogen barrier property, may be used for the insulator 488.

[0332] 15A illustrates a structure in which the transistors 200a and 200b are provided in the same layer, but the present invention is not limited to this. For example, as illustrated in FIG. 15B, a structure may be adopted in which a layer 401a including the transistor 200a is stacked on a layer 401b including the transistor 200b. Note that the layers 401a and 401b have the same structure as the layers from the insulator 215 to the insulator 285 illustrated in FIG. 15A.

[0333] 15B, the conductor 240c and the insulator 241c can be formed in the openings provided in the insulators 282 to 285 of the layer 401b and the insulators 215 to 285 of the layer 401a. With such a structure, the conductor 410 of the capacitor 400 and the conductor 260 of the transistor 200b can be electrically connected. Note that the conductor 410 and the conductor 260 of the transistor 200b do not need to be connected only by the conductor 240c. Two or more conductors may be used to electrically connect the conductor 410 and the conductor 260 of the transistor 200b.

[0334] Here, the transistor 200b is preferably provided so as to overlap with at least one of the transistor 200a and the capacitor 400. For example, the oxide semiconductor 230 of the transistor 200b is preferably provided so as to overlap with at least one of the oxide semiconductor 230 of the transistor 200a and the conductor 410 of the capacitor 400. With such a structure, the area occupied by the memory cell can be reduced.

[0335] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for the semiconductor device will be described below. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0336] <<Substrate>> Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include semiconductor substrates having an insulator region within the semiconductor substrate, such as SOI (Silicon-On-Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides, substrates having metal oxides, substrates in which a conductor or semiconductor is provided on an insulator substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductor substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0337] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0338] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, materials can be selected depending on the function of the insulator.

[0339] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0340] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0341] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0342] The insulator functioning as the gate insulator preferably has a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 can be compensated for.

[0343] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. Examples of the conductor include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Alternatively, a semiconductor with high conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0344] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0345] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0346] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive materials containing the metal element and nitrogen described above may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0347] 1A to 1D , an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

[0348] A in each figure shows a plan view. B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. D in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. Note that some elements are omitted from the plan view A in each figure for clarity.

[0349] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0350] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0351] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0352] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0353] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0354] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0355] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0356] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0357] First, a substrate (not shown) is prepared, and an insulator 215 is formed on the substrate (see FIGS. 16A to 16D ). As described above, the insulator 215 can be formed using an insulator similar to one or more of the insulators 282 and 283. The insulator 215 can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. Sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, is preferable because it can reduce the hydrogen concentration in the insulator 215.

[0358] Next, the insulator 216 is deposited over the insulator 215. The insulator 216 is preferably deposited by a sputtering method. The hydrogen concentration in the insulator 216 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. However, the deposition of the insulator 216 is not limited to a sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate. In this embodiment, silicon oxide is deposited as the insulator 216 by a sputtering method.

[0359] The insulators 215 and 216 are preferably successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 215 and 216 to be formed with reduced hydrogen content and reduces the amount of hydrogen mixed into the films between film formation steps.

[0360] 12A to 12D can be formed by forming an opening in the insulator 216 that reaches the insulator 215 and forming the conductor 205 in the opening. The conductor 205 can be formed by depositing a conductive film that can be used for the conductor 205 so as to fill the opening and removing part of the conductive film by CMP treatment.

[0361] Next, an insulator 221 is formed on the insulator 216 (see FIGS. 16A to 16D).

[0362] The insulator 221 may be any of the above insulators that have barrier properties against oxygen, hydrogen, and water. The insulator 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon nitride is formed as the insulator 221 by a PEALD method.

[0363] Next, an insulator 222 is formed on the insulator 221 (see FIGS. 16A to 16D).

[0364] The insulator 222 can be formed as an insulator containing one or both of an oxide of aluminum and hafnium. As the insulator containing one or both of an oxide of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of an oxide of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. When the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in structures provided around the transistor are prevented from diffusing into the transistor through the insulator 222, and thus oxygen vacancies in the oxide semiconductor 230 can be suppressed.

[0365] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, hafnium oxide is formed as the insulator 222 by a thermal ALD method.

[0366] In this embodiment, silicon nitride is deposited as the insulator 221 by a PEALD method, and hafnium oxide is deposited as the insulator 222 by a thermal ALD method. By using silicon nitride, which has a function of suppressing hydrogen diffusion, for the insulator 221 in this manner, diffusion of hydrogen from a lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide, which has a function of capturing or fixing hydrogen, for the insulator 222, hydrogen contained in the oxide semiconductor 230 can be captured or fixed to the insulator 222. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0367] Next, an insulating film is formed over the insulator 222 and etched to form the insulator 223 (see FIGS. 16A to 16D ). The insulator 223 functions as a template for forming the oxide semiconductor 230. The insulator 223 may be, for example, the insulator that can be used for the insulator 216.

[0368] The insulator 223 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a silicon oxide film is formed as the insulator 223 by a sputtering method.

[0369] The insulator 223 can be processed into an island shape by lithography. For this processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. In this embodiment, as shown in FIGS. 16A to 16C , two columnar insulators 223 are formed and arranged in the A1-A2 direction.

[0370] 16B and 16C , the side surface of the insulator 223 may be configured to be perpendicular or approximately perpendicular to the top surface of the insulator 222. With such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors.

[0371] Next, an oxide semiconductor film 230f that will become the oxide semiconductor 230 is formed to cover the insulator 223 (see FIGS. 17A to 17D ). The oxide semiconductor film 230f is a metal oxide film that will become the oxide semiconductor 230 in a later step, and the above-described metal oxide film can be used. The oxide semiconductor film 230f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0372] Since the oxide semiconductor film 230f is formed along the insulator 223, it is preferable that the oxide semiconductor film 230f has good coverage. Therefore, it is preferable that the oxide semiconductor film 230f be formed by an ALD method or the like, which has good coverage. Furthermore, since it is preferable that the oxide semiconductor 230 has a high aspect ratio, it is preferable that the oxide semiconductor film 230f have a thin film thickness. Therefore, it is preferable that the oxide semiconductor film 230f be formed by an ALD method, which allows for adjustment of the film thickness to a thin film thickness. By forming the oxide semiconductor film 230f in this manner, the oxide semiconductor film 230f is formed in contact with the top surface and side surface of the insulator 223.

[0373] Here, the oxide semiconductor film 230f is preferably formed by the same method as that for forming the oxide semiconductor 30 described above.

[0374] For example, when the oxide semiconductor 230 has a three-layer structure including oxide semiconductors 230a to 230c as shown in FIG. 2B and other figures, films to be the oxide semiconductors 230a to 230c can be deposited by ALD, and a film to be the oxide semiconductor 230b can be deposited by sputtering. Specifically, the film to be the oxide semiconductor 230a can be deposited to have an atomic ratio of In:Zn=2:1 or a composition therebetween. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230a. The film to be the oxide semiconductor 230b can be deposited using an oxide target having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition therebetween. The film to be the oxide semiconductor 230c can be deposited to have an atomic ratio of In:Zn=2:1 or a composition therebetween. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230c.

[0375] Next, heat treatment is preferably performed within a temperature range in which the oxide semiconductor film 230f does not become polycrystallized. The heat treatment of the oxide semiconductor film 230f may be performed by the same method as the heat treatment of the oxide semiconductor 30 described above.

[0376] For example, the heat treatment can be carried out at a flow rate ratio of nitrogen gas to oxygen gas of 4:1 at a temperature of 450° C. for one hour.

[0377] By forming the oxide semiconductor 230 using the above method and then performing heat treatment, the oxide semiconductor 230 can be made into an axial growth CAAC. As a result, the on-state current, the S value, the field-effect mobility, the frequency characteristics, and the like of the transistor 200 can be improved, and a semiconductor device with favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0378] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0379] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film 230f and the like as much as possible. Note that highly purified gas can also be used in the heat treatment before and after this step.

[0380] Furthermore, the heat treatment using oxygen gas as described above can reduce impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f. Reducing the impurities in the film in this manner can improve the crystallinity of the oxide semiconductor film 230f, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor film 230f, reducing in-plane variations in the crystalline regions in the oxide semiconductor film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0381] Furthermore, by performing heat treatment, oxygen can be supplied to the oxide semiconductor film 230f, and oxygen vacancies in the oxide semiconductor film 230f can be reduced, thereby improving the reliability of the transistor 200.

[0382] Furthermore, by the heat treatment, hydrogen in the oxide semiconductor film 230f moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the oxide semiconductor film 230f diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentration in the oxide semiconductor film 230f decreases. Note that by providing the insulator 221 in contact with the lower surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.

[0383] In particular, the oxide semiconductor film 230f (later the oxide semiconductor 230) functions as a channel formation region of the transistor 200. The transistor 200 formed using the oxide semiconductor film 230f in which the hydrogen concentration is reduced is preferable because it has good reliability.

[0384] Next, a portion of the oxide semiconductor film 230f is removed by anisotropic etching, and the insulator 223 is then removed (see FIGS. 18A to 18D ). The oxide semiconductor film 230f is etched mainly in a portion parallel to the substrate surface, and a sidewall-shaped oxide semiconductor 230 is formed in contact with the side surface of the insulator 223. While FIGS. 18B and 18C show a structure in which curved shapes are formed on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the oxide semiconductor 230, this is not limiting. A curved shape may also be formed only on the side of the oxide semiconductor 230 that is not in contact with the insulator 223. When removing a portion of the oxide semiconductor film 230f by anisotropic etching, an insulator serving as a hard mask may be provided in the portion. Suitable insulating films for the oxide semiconductor film 230f include silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide.

[0385] Anisotropic etching can form the oxide semiconductor 230 with a high aspect ratio. By using the oxide semiconductor 230, the channel width of the transistor 200 can be increased without increasing the occupation area, thereby improving the on-state current and frequency characteristics of the transistor 200. Furthermore, the contact area between the oxide semiconductor 230 and the conductors 242a and 242b can be increased without increasing the occupation area, thereby improving the on-state current and frequency characteristics of the transistor 200.

[0386] 18A to 18C , by forming the oxide semiconductor film 230f in contact with the side surfaces of the insulators 223 and forming the oxide semiconductor 230 in a sidewall shape, the oxide semiconductors 230 can be formed simultaneously. By forming the oxide semiconductors 230 in this manner, the distance between the oxide semiconductors 230 can be set in accordance with the size and shape of the insulators 223. Therefore, the distance between the oxide semiconductors 230 can be reduced, the area occupied by the transistor 200 can be reduced, and the semiconductor device can be highly integrated.

[0387] 18A , the oxide semiconductor 230 has a circumferential top surface shape with both ends aligned. The oxide semiconductor 230 can also be said to have an opening in the center. When the oxide semiconductor 230 has a three-layer structure including the oxide semiconductors 230a to 230c as described above, the circumferential oxide semiconductor 230 is formed in the order of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c, with the region where the insulator 223 was formed at the center. Therefore, as shown in FIG. 4A , in a cross-sectional view in the channel width direction, the oxide semiconductor 230c, the oxide semiconductor 230b, the oxide semiconductor 230a, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are arranged symmetrically in this order.

[0388] Although the above description has been given of a configuration in which two circumferential oxide semiconductors 230 are provided, the present invention is not limited to this. For example, one or three or more circumferential oxide semiconductors 230 may be provided. Furthermore, the circumferential oxide semiconductors 230 may be joined to form an oxide semiconductor 230 having a shape with multiple openings. For example, as shown in FIG. 5A , the oxide semiconductor 230 may have a shape in which three openings are arranged in the A1-A2 direction in top view. In this case, three insulators 223 may be formed adjacent to each other at a short distance in the process shown in FIG. 16 . Furthermore, as shown in FIG. 5B , the oxide semiconductor 230 may have a lattice shape in top view. In this case, lattice-shaped trenches may be formed in the insulator 223 in the process shown in FIG. 16 .

[0389] 18A , the oxide semiconductor 230 has a circumferential structure in top view, but etching may be further performed to remove part of the oxide semiconductor 230. For example, in the structure shown in FIG. 18A , part of the oxide semiconductor 230 may be removed to form a rectangular shape extending in the A5-A6 direction in top view.

[0390] The anisotropic etching of the oxide semiconductor film 230f is preferably performed by dry etching.

[0391] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, the etching gas may contain C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ gas, or BBr ３Gases such as fluorine-containing gases can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, gases containing hydrocarbon gas or hydrogen gas but not containing halogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0392] A capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used as the dry etching apparatus. A capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, a high-frequency voltage of the same frequency may be applied to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to the parallel-plate electrodes. Such a CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. In a DF-CCP etching apparatus, a high-frequency voltage of a different frequency may be applied to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus. The etching apparatus can be appropriately configured according to the object to be etched. In the above-mentioned dry etching apparatus, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, thereby enabling highly anisotropic etching.

[0393] Note that a dry etching method or a wet etching method can be used to remove the insulator 223. For example, the insulator 223 can be removed by a wet etching method.

[0394] Furthermore, by using a material that is difficult to etch, such as hafnium oxide, for the insulator 222, the insulator 222 can function as an etching stopper in the etching process of the oxide semiconductor film 230f and the insulator 223.

[0395] 17 and 18 show the configuration in which two insulators 223 and two oxide semiconductors 230 are provided for the transistor 200, but the present invention is not limited thereto. As shown in FIG. 26A , two transistors (transistor 200_1 and transistor 200_2) may each be provided with two insulators 223 and two oxide semiconductors 230. As shown in FIG. 26B , insulators 223 with different widths may be provided, and three fin-shaped oxide semiconductors 230 may be provided for each of the transistors 200_1 and 200_2 in the cross-sectional view along the A1-A2 direction. In this case, part of the oxide semiconductor 230 is removed so that the top surface shape is linearly elongated in the A5-A6 direction, and the oxide semiconductor 230 of the transistor 200_1 and the oxide semiconductor 230 of the transistor 200_2 are separated.

[0396] Although FIG. 18 illustrates a structure in which the insulator 223 is removed, the present invention is not limited to this. For example, as illustrated in FIG. 27A , a structure in which part of the insulator 223 remains may be used. Here, the insulator 223 remains in a region where the conductor 240 will be provided in a later step. For example, when removing the insulator 223 in the above step, a mask may be formed by lithography in the region where the conductor 240 will be provided, so that the insulator 223 remains in that region. As illustrated in FIG. 27A , the insulator 223 is formed so as to be embedded inside the circumferential oxide semiconductor 230. As illustrated in FIG. 27B , in the transistor 200, the conductor 242a (conductor 242b) and the conductor 240a (conductor 240b) are formed to cover the oxide semiconductor 230 and the insulator 223. Here, the conductor 242a (conductor 242b) is in contact with the side surface and top surface of the oxide semiconductor 230 and the top surface of the insulator 223.

[0397] Next, a conductive film 242f is formed over the insulator 222 and the oxide semiconductor 230 (see FIGS. 19A to 19D). The conductive film 242f may be formed using a conductor corresponding to the conductors 242a and 242b.

[0398] The conductive film 242f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, tantalum nitride can be formed as the conductive film 242f by a sputtering method. Alternatively, as shown in FIG. 3B and other drawings, a stacked structure of tantalum nitride and tungsten on the tantalum nitride may be used. By forming the conductive film 242f to cover the oxide semiconductor 230, the contact area between the oxide semiconductor 230 and the conductors 242a and 242b can be increased without increasing the occupation area. This can improve the on-state current and frequency characteristics of the transistor 200.

[0399] Next, the conductive film 242f is processed into an island shape by lithography to form a conductor 242A (see FIGS. 20A to 20D). At this time, the conductor 242A is preferably formed to cover the oxide semiconductor 230. Furthermore, the insulator 222 is exposed in a region that does not overlap with the conductor 242A.

[0400] For the above processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. Note that the above description can be referred to for the conditions for the dry etching method and the dry etching apparatus.

[0401] The side surface of the conductor 242A may be configured to be perpendicular or approximately perpendicular to the upper surface of the insulator 222. By using such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors.

[0402] However, the present invention is not limited to the above, and the side surfaces of the oxide semiconductor 230 and the conductor 242A may be tapered. The taper angle of the side surfaces of the oxide semiconductor 230 and the conductor 242A may be, for example, greater than or equal to 60° and less than 90°. Tapering the side surfaces in this manner improves coverage with the insulator 275 and the like in subsequent steps, and reduces defects such as voids.

[0403] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left behind using a developer to form a resist mask. Next, an etching process is performed through the resist mask, allowing a conductor, semiconductor, or insulator to be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be required.

[0404] The resist mask that is no longer needed after processing can be removed by performing a dry etching treatment such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), a wet etching treatment, a dry etching treatment followed by a wet etching treatment, or a wet etching treatment followed by a dry etching treatment.

[0405] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as a hard mask material is formed on the conductive film 242f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 242f and the like may be performed after removing the resist mask or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242f. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0406] Alternatively, a spin-on-carbon (SOC) film and a spin-on-glass (SOG) film may be formed between the workpiece and the resist mask. Using the SOC film and the SOG film as masks can improve the durability of the mask pattern. For example, a lithography method can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0407] Next, an insulator 275 is formed to cover the conductor 242A, and an insulator 280 is further formed over the insulator 275 (see FIGS. 21A to 21D). The insulators 275 and 280 may be any of the insulators described above.

[0408] Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222 .

[0409] As the insulator 280, it is preferable to form an insulator with a flat upper surface by forming an insulating film to be the insulator 280 and performing CMP treatment on the insulating film. Note that it is also possible to form a silicon nitride film on the insulator 280 by, for example, a sputtering method and perform CMP treatment on the silicon nitride until it reaches the insulator 280.

[0410] The insulators 275 and 280 can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0411] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film by a PEALD method as the insulator 275. Alternatively, it is preferable to form an aluminum oxide film by a sputtering method and then form a silicon nitride film thereon by a PEALD method as the insulator 275. By using the above structure for the insulator 275, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0412] In this manner, the oxide semiconductor 230 and the conductor 242A can be covered with the insulator 275, which has a function of suppressing oxygen diffusion. This can suppress oxygen from diffusing directly from the insulator 280 or the like into the oxide semiconductor 230 and the conductor 242A in a later step.

[0413] The insulator 280 is preferably formed using silicon oxide by a sputtering method. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. The hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 and the like can be removed, and the moisture and hydrogen concentrations in the oxide semiconductor 230 can be further reduced. The heat treatment can be performed under the above-described heat treatment conditions.

[0414] Next, the conductor 242A, the insulator 275, and the insulator 280 are processed by lithography to form openings that reach the oxide semiconductor 230 and the insulator 222 (see FIGS. 22A to 22D ). Here, the conductor 242A is divided, and the conductors 242a and 242b are formed. The openings are formed in regions that overlap with the oxide semiconductor 230.

[0415] The lithography method can be any of the above-mentioned methods, as appropriate. In order to finely process the openings in the insulator 280, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0416] The above processing is preferably performed using a dry etching method. Dry etching is suitable for forming openings with high aspect ratios because it allows anisotropic etching. The above description can be referred to for the conditions of the dry etching method and the dry etching apparatus.

[0417] 3C , it is preferable to form the conductor 242a1 and the conductor 242b1 by performing an etching process after forming the conductor 242a2 and the conductor 242b2. With this structure, the transistor 200 and the capacitor 460 shown in FIGS. 13A and 13B can be manufactured in parallel. In this case, when the conductor 242A of the transistor 200 is etched to form the conductor 242a1 and the conductor 242b1, the capacitor 460 can be configured such that the oxide semiconductor 452 is covered with the conductor 242b1 without undergoing the etching process. This allows the capacitor 460, including the conductor 242b1, the insulator 454, and the conductor 456, to be manufactured in parallel with the transistor 200.

[0418] Note that after processing the conductor 242A, ashing treatment using oxygen plasma may be performed. By performing such oxygen plasma treatment, impurities generated during the etching treatment and diffused into the oxide semiconductor 230 and the like can be removed. Examples of such impurities include those originating from components contained in the workpiece of the etching treatment and components contained in the gas used in the etching treatment. Examples include chlorine, fluorine, tantalum, silicon, and hafnium. In particular, when chlorine gas is used in processing the conductor 242A as shown in the etching treatment, the oxide semiconductor 230 is exposed to an atmosphere containing chlorine gas. Therefore, it is preferable to remove chlorine attached to the oxide semiconductor 230. Removing the impurities attached to the oxide semiconductor 230 in this manner can improve the electrical characteristics and reliability of the transistor.

[0419] Furthermore, a cleaning treatment may be performed to remove impurities and the like attached to the surface of the oxide semiconductor 230 during the etching process. Examples of the cleaning method include wet cleaning using a cleaning solution or the like (also referred to as wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment. The above cleaning methods may be combined as appropriate. Note that the cleaning treatment may deepen the grooves in some cases.

[0420] Wet cleaning may be performed using an aqueous solution in which one or more of oxalic acid, phosphoric acid, and hydrofluoric acid are diluted with carbonated water or pure water. Wet cleaning may also be performed using an aqueous solution in which ammonia water is diluted with carbonated water or pure water. Wet cleaning may also be performed using pure water or carbonated water. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0421] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution are adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0422] Note that the ultrasonic cleaning is preferably performed at a frequency of 200 kHz or higher, more preferably 900 kHz or higher, because damage to the oxide semiconductor 230 and the like can be reduced by using such a frequency.

[0423] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0424] In this embodiment, wet cleaning is performed using diluted ammonia water as the cleaning treatment. By performing the cleaning treatment, impurities attached to the surface of the oxide semiconductor 230 or diffused into the oxide semiconductor 230 can be removed. Furthermore, the crystallinity of the oxide semiconductor 230 can be improved.

[0425] It is preferable to perform heat treatment after the etching or cleaning. The temperature of the heat treatment is 100° C. to 650° C., preferably 250° C. to 600° C., more preferably 300° C. to 550° C., and still more preferably 350° C. to 400° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment is preferably performed in an atmosphere containing oxygen. For example, the heat treatment is preferably performed at 350° C. for 1 hour with a flow ratio of nitrogen gas to oxygen gas of 4:1. This allows oxygen to be supplied to the oxide semiconductor 230, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the oxide semiconductor 230. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide semiconductor 230, converting the hydrogen into H ２ As a result, hydrogen remaining in the oxide semiconductor 230 is recombined with the oxygen vacancies to form V Ｏ The formation of H can be suppressed. Therefore, the electrical characteristics of the transistor including the oxide semiconductor 230 can be improved, and the reliability can be improved. Furthermore, variation in the electrical characteristics of a plurality of transistors formed over the same substrate can be suppressed. Note that the heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be successively performed in a nitrogen atmosphere without exposure to the air. Furthermore, the heat treatment can also serve as the heat treatment described in Embodiment 1. Therefore, the heat treatment may cause a crystalline region of the oxide semiconductor 230 to grow.

[0426] Note that when heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide semiconductor 230, the sheet resistance of a region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b may decrease. Also, the carrier concentration may increase. Therefore, the resistance of the region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b can be reduced in a self-aligned manner.

[0427] Next, an insulating film 250A to be the insulator 250 is formed so as to fill the openings formed in the insulator 280 and the like (see FIGS. 23A to 23D ). Here, the insulating film 250A is in contact with the insulator 280, the insulator 275, the conductor 242a, the conductor 242b, the insulator 222, and the oxide semiconductor 230.

[0428] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulating film 250A is preferably formed using an ALD method. Like the insulator 250 described above, the insulating film 250A is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, the insulating film 250A must be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the opening, allowing the insulating film 250A to be formed with good coverage on the opening.

[0429] When the insulating film 250A is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using HCl, HCl, or the like as an oxidizing agent, hydrogen diffusing into the oxide semiconductor 230 can be reduced.

[0430] The insulator 250 can have a layered structure as shown in FIG. 2 and the like. For example, as shown in FIG. 2A, the insulator 250 can have a layered structure of insulators 250a to 250d. In this case, aluminum oxide can be deposited as the insulator 250a by a thermal ALD method, silicon oxide can be deposited as the insulator 250b by a PEALD method, hafnium oxide can be deposited as the insulator 250c by a thermal ALD method, and silicon nitride can be deposited as the insulator 250d by a PEALD method.

[0431] Furthermore, after the insulating film 250A or any of the insulators constituting the insulating film 250A is formed, it is preferable to perform microwave treatment in an atmosphere containing oxygen. Here, the microwave treatment refers to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. In this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0432] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. The use of high-density plasma can generate high-density oxygen radicals. Furthermore, the power of the power supply that applies microwaves to the microwave treatment device is preferably 1000 W to 10,000 W, more preferably 2000 W to 5,000 W. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the oxide semiconductor 230.

[0433] The microwave treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

[0434] Furthermore, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%.２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less. By performing microwave treatment in an atmosphere containing oxygen in this manner, the carrier concentration in the oxide semiconductor 230 can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration in the oxide semiconductor 230 can be prevented.

[0435] By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to a region between the conductor 242 a and the conductor 242 b of the oxide semiconductor 230. The action of the plasma, microwaves, or the like can reduce the V Ｏ The H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Here, when using the structure shown in FIG. 2A or the like, it is preferable to use an insulating film (such as aluminum oxide) that has the function of capturing or fixing hydrogen as the insulator 250a. With such a structure, hydrogen generated by microwave treatment can be captured or fixed in the insulating film 250A. In this way, V included in the channel formation region can be removed. Ｏ As a result, oxygen vacancies in the channel formation region and V Ｏ By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0436] The oxygen implanted into the channel formation region can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also called O radicals). The oxygen implanted into the channel formation region may take one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0437] Furthermore, the microwave treatment can also remove impurities such as carbon from the oxide semiconductor 230. Removal of carbon, which is an impurity in the oxide semiconductor 230, can improve the crystallinity of the oxide semiconductor 230. As a result, the oxide semiconductor 230 can be made into a CAAC-OS. In particular, when the oxide semiconductor 230 is formed by an ALD method, carbon contained in a precursor might be taken into the oxide semiconductor 230; therefore, it is preferable to remove carbon by microwave treatment.

[0438] Meanwhile, the oxide semiconductor 230 has a region overlapping with either the conductor 242a or the conductor 242b. The region can function as a source region or a drain region. Here, the conductor 242a and the conductor 242b preferably function as a shielding film against the action of microwaves, high frequency waves such as RF, oxygen plasma, and the like when microwave treatment is performed in an oxygen-containing atmosphere. Therefore, the conductor 242a and the conductor 242b preferably have a function of shielding electromagnetic waves of 300 MHz to 300 GHz, for example, 2.4 GHz to 2.5 GHz.

[0439] The conductors 242a and 242b shield the oxide semiconductor 230 from microwaves, high-frequency waves such as RF, oxygen plasma, and the like, and therefore these effects do not reach a region of the oxide semiconductor 230 that overlaps with either the conductor 242a or the conductor 242b. As a result, V Ｏ Since the amount of H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0440] In this manner, oxygen vacancies and V Ｏ By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions that function as source or drain regions can be suppressed, and the conductivity (low resistance region state) before the microwave treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0441] Furthermore, by performing microwave treatment to modify the film quality of the insulator 250, diffusion of hydrogen, water, impurities, and the like can be suppressed. Therefore, in a post-process such as deposition of a conductive film to be the conductor 260 or a post-treatment such as heat treatment, diffusion of hydrogen, water, impurities, and the like through the insulator 250 into the oxide semiconductor 230 and the like can be suppressed. In this way, improving the film quality of the insulator 250 can improve the reliability of the transistor.

[0442] When the insulator 250 has a stacked structure of insulators 250a to 250d, microwave treatment is preferably performed after the formation of the insulator 250b. Furthermore, microwave treatment may be performed again after the formation of the insulator 250c. In this manner, microwave treatment in an atmosphere containing oxygen may be performed multiple times (at least twice or more). The microwave treatment may also serve as the heat treatment described in Embodiment 1. Therefore, the microwave treatment may cause a crystalline region of the oxide semiconductor 230 to grow.

[0443] After the microwave treatment, heat treatment may be performed while the reduced pressure state is maintained. By performing such treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be efficiently removed. Alternatively, the step of performing heat treatment while the reduced pressure state is maintained after the microwave treatment may be repeated multiple times. By repeatedly performing the heat treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be more efficiently removed. Note that the heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The heat treatment described above can also serve as the heat treatment described in Embodiment 1. Therefore, the heat treatment may cause growth of a crystalline region in the oxide semiconductor 230.

[0444] Next, a conductive film 260A to be the conductor 260a and a conductive film 260B to be the conductor 260b are sequentially formed (see FIGS. 24A to 24D ). The conductive films 260A and 260B can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. In this embodiment, titanium nitride is formed as the conductive film 260A by a CVD method, and tungsten is formed as the conductive film 260B by a CVD method. Note that the conductive films 260A and 260B may be formed while heating the substrate. Heating the substrate can also serve as the heat treatment described in Embodiment 1. Therefore, the substrate heating may cause a crystalline region of the oxide semiconductor 230 to grow.

[0445] Next, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed. That is, the portions of the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the openings are removed. As a result, the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b) are formed in the openings (see FIGS. 25A to 25D).

[0446] As a result, the insulator 250 is provided in the opening in contact with the insulator 280, the insulator 275, the conductor 242a, the conductor 242b, the oxide semiconductor 230, and the insulator 222. The conductor 260 is arranged to fill the opening with the insulator 250 interposed therebetween. In this manner, the transistor 200 is formed.

[0447] Next, the insulator 282 is formed over the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 1A to 1D). The insulator 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably formed by a sputtering method. Alternatively, the insulator 282 may be formed by forming a first layer by an ALD method and then forming a second layer thereon by a sputtering method.

[0448] Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere by a sputtering method, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. At this time, the insulator 282 is preferably deposited while heating the substrate. Depositing the insulator 282 in this manner allows a suitable amount of oxygen to be supplied from the insulator 280 to the oxide semiconductor 230 through the insulator 250. Furthermore, providing the insulator 250a in the insulator 250 can prevent excessive oxygen from being supplied into the insulator 250 and causing excessive oxidation of the conductors 242a and 242b near the insulator 250.

[0449] The aluminum oxide film is formed using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen implanted into the insulator 280 can be controlled by the magnitude of the bias power applied to the substrate by the sputtering method. For example, the smaller the bias power, the less oxygen is implanted into the insulator 280, and the more likely the oxygen amount is to saturate even if the insulator 282 is thin. Furthermore, the greater the bias power, the more oxygen is implanted into the insulator 280. By reducing the RF power, the amount of oxygen implanted into the insulator 280 can be suppressed. Note that when applying a substrate bias using an RF power supply, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0450] Furthermore, by forming a second layer by sputtering on top of the first layer formed by ALD, the upper end of the insulator 250 and the upper surface of the conductor 260 can be protected from the impact of ion collisions caused by sputtering film formation.

[0451] Alternatively, heat treatment may be performed before the formation of the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed and the moisture and hydrogen concentrations in the insulator 280 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0452] Next, the insulator 283 is formed over the insulator 282 (see FIGS. 1A to 1D). The insulator 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. The hydrogen concentration in the insulator 283 can be reduced by using a sputtering method, which does not require the use of molecules containing hydrogen in the deposition gas. In this embodiment, silicon nitride is formed as the insulator 283 by a sputtering method.

[0453] Here, it is preferable to successively deposit the insulators 282 and 283 without exposing them to the air environment. Depositing the insulators 282 and 283 without exposing them to the air environment can prevent impurities or moisture from the air environment from adhering to the insulators 282 and 283, and can keep the interface or the vicinity of the interface between the insulators 282 and 283 clean.

[0454] In this embodiment, a silicon nitride film is formed as the insulator 283, and an aluminum oxide film is formed as the insulator 282. By using silicon nitride, which has a function of suppressing hydrogen diffusion, for the insulator 283, diffusion of hydrogen from the upper layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide, which has a function of capturing or fixing hydrogen, for the insulator 282, hydrogen contained in the insulator 280 or the like can be captured or fixed to the insulator 282. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0455] Next, openings reaching the conductor 242a and the conductor 242b are formed in the insulators 275, 280, 282, and 283 (see FIGS. 1A to 1D ). The openings may be formed by lithography. The openings are preferably formed by processing the workpiece using dry etching. Dry etching is suitable for forming openings with a high aspect ratio because it allows anisotropic etching. When performing anisotropic etching, reactive ion etching, for example, is preferably performed. The conditions for the dry etching method and the dry etching apparatus can be described above. While the shape of the opening in FIG. 1A is rectangular in top view, the shape is not limited thereto. For example, the opening may be circular, approximately circular such as elliptical, polygonal such as rectangular, or polygonal such as rectangular with rounded corners in top view.

[0456] Next, after the openings are formed, heat treatment may be performed. The temperature for the heat treatment can be 100° C. or higher and 600° C. or lower, preferably 250° C. or higher and 550° C. or lower, more preferably 350° C. or higher and 450° C. or lower. Note that the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. Furthermore, the heat treatment is preferably performed in an atmosphere containing neither an oxidizing gas nor oxygen gas because the conductors 242a and 242b are exposed. For example, the heat treatment is preferably performed in a nitrogen gas atmosphere at 400° C. for one hour. Note that the heat treatment may be performed under reduced pressure. By the heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250. This can reduce oxygen vacancies in the channel formation region of the oxide semiconductor 230. The heat treatment can also serve as the heat treatment described in Embodiment 1. Therefore, the heat treatment may cause a crystalline region of the oxide semiconductor 230 to grow.

[0457] Here, because the side surface of the insulator 280 is exposed through the opening, the heat treatment can outwardly diffuse oxygen contained in the insulator 280, thereby controlling the amount of oxygen contained in the insulator 280. Meanwhile, because the insulators 282 and 283, which have a barrier property against oxygen, are provided on the insulator 280, oxygen does not outwardly diffuse from the upper surface of the insulator 280. This can prevent excessive outward diffusion of oxygen from the insulator 280 and the formation of oxygen vacancies in the insulator 280. Furthermore, the oxide semiconductor 230, the conductor 242a, and the conductor 242b are covered with the insulator 275. This can prevent excessive oxygen from directly diffusing from the insulator 280 to the oxide semiconductor 230, the conductor 242a, and the conductor 242b during the heat treatment.

[0458] In this manner, the amount of oxygen in the insulator 280 can be more suitably adjusted, and an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. This reduces oxygen vacancies in the oxide semiconductor 230 and prevents excessive oxygen from being supplied to the oxide semiconductor 230. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. Furthermore, the step of exposing the side surfaces of the insulator 280 can also serve as the step of forming openings into which the conductors 240a and 240b are to be embedded, which simplifies the manufacturing process of the semiconductor device.

[0459] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241a in the opening that reaches the conductor 242a, and the insulator 241b in the opening that reaches the conductor 242b (see FIGS. 1A to 1D). The insulating film that will become the insulator 241 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that will become the insulator 241, it is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to form a silicon nitride film using a PEALD method. Silicon nitride is preferable because it has high blocking properties against hydrogen.

[0460] Furthermore, dry etching, for example, may be used to anisotropically etch the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductors 240a and 240b. Note that this anisotropic etching may form recesses in parts of the upper surfaces of the conductors 242a and 242b.

[0461] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that will become the conductor 240a and the conductor 240b is preferably a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 240a and the conductor 240b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0462] Next, CMP processing is performed to remove portions of the conductive film that will become the conductors 240a and 240b, thereby exposing the upper surface of the insulator 283. As a result, the conductive film remains only in the openings, thereby forming the conductors 240a and 240b with flat upper surfaces (see FIGS. 1A to 1D). Note that the CMP processing may remove portions of the upper surface of the insulator 283.

[0463] As described above, by providing the conductor 240a in contact with the conductor 242a, the conductor 240a functioning as one of the source and drain of the transistor 200 can be electrically connected to a wiring. Furthermore, by providing the conductor 240b in contact with the conductor 242b, the conductor 240b functioning as the other of the source and drain of the transistor 200 can be electrically connected to a wiring.

[0464] Note that a conductive film functioning as a wiring or a conductive film functioning as a plug can be formed over the conductor 240a and the conductor 240b.

[0465] In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

[0466] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0467] Embodiment 2 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0468] Fig. 28 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 28 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 28 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0469] The transistor described as an example in Embodiment 1 can be applied to the memory cell 950. By using the transistor, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0470] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0471] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0472] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0473] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0474] The voltage generating circuit 928 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a voltage.

[0475] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0476] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0477] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0478] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ 28, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0479] 29A to 29H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0480] 29C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0481] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0482] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0483] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and connecting the wiring WBL to the first terminal of the capacitance element CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitance element CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitance element CB and the potential of the gate of the transistor M3.

[0484] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0485] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in Figure 29D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0486] 29E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 29F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0487] Note that it is preferable to use the OS transistor described in Embodiment 1 for at least the transistor M2. For example, the transistor 200, the transistor 310, and the capacitor 460 shown in FIG. 13A or 13B can be used for the transistor M2, the transistor M3, and the capacitor CB of the memory cell 953 and the memory cell 954. In particular, it is preferable to use the OS transistor described in Embodiment 1 for the transistor M2 and the transistor M3. For example, the transistor 200a, the transistor 200b, and the capacitor 400 shown in FIG. 15A or 15B can be used for the transistor M2, the transistor M3, and the capacitor CB of the memory cell 953 and the memory cell 954. By using the OS transistor described in Embodiment 1, the operating speed of the memory device can be improved. Furthermore, the area occupied by the memory cell can be reduced.

[0488] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0489] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0490] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0491] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0492] 29G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitative element CC.

[0493] The first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, the second terminal of the transistor M4 is connected to the wiring BIL, and the gate of the transistor M4 is connected to the wiring WOL. The second terminal of the capacitor CC is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RWL.

[0494] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0495] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and connecting the wiring BIL to the first terminal of the capacitor CC. Specifically, when the transistor M4 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0496] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0497] Note that at least the transistor M4 is preferably the OS transistor described in Embodiment 1. By using the OS transistor described in Embodiment 1, the area occupied by the memory cell can be reduced.

[0498] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0499] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0500] 29A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0501] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0502] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0503] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0504] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and connecting the wiring BIL and the first terminal of the capacitor CA.

[0505] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 950 may have the configuration of a memory cell 952 as shown in FIG. 29B. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0506] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0507] Note that the OS transistor described in Embodiment 1 is preferably used as the transistor M1. For example, the transistor 200 and the capacitor 460 shown in FIG. 13A or 13B can be used as the transistor M1 and the capacitor CA of the memory cell 951. For example, the transistor 200a and the capacitor 400 shown in FIG. 15A or 15B can be used as the transistor M1 and the capacitor CA of the memory cell 951. By using the OS transistor described in Embodiment 1, the operation speed of the memory device can be improved. Furthermore, the area occupied by the memory cell can be reduced. Furthermore, the OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, thereby reducing the frequency of refreshing the memory cell. Alternatively, refreshing the memory cell can be eliminated. Furthermore, the extremely low leakage current allows the memory cells 951 and 952 to hold multilevel data or analog data.

[0508] 29H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 29H is a memory cell of an SRAM capable of backing up data.

[0509] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0510] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0511] A second terminal of the transistor MS1 is electrically connected to the wiring VDL. A second terminal of the transistor MS2 is electrically connected to the wiring VDL. A second terminal of the transistor MS3 is electrically connected to the wiring GNDL. A second terminal of the transistor MS4 is electrically connected to the wiring GNDL.

[0512] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0513] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0514] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.

[0515] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0516] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0517] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is conductive, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Furthermore, because the transistors M9 and M10 are conductive, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Subsequently, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0518] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL, so that the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. Also, the potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. In the wirings BIL and BILB, the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1 change from the precharged potentials, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0519] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, thereby reducing the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated. Furthermore, by using the OS transistors described in Embodiment 1 as the transistors M7 to M10, the operating speed of the memory device can be improved. Furthermore, the area occupied by the memory cells can be reduced.

[0520] Note that Si transistors may be used as the transistors MS1 to MS4.

[0521] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 30A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 30B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0522] In the above-described memory array 920, a plurality of memory arrays 920[1] to 920[m] can be stacked. The memory arrays 920[1] to 920[m] included in the memory array 920 can be arranged in the vertical direction of the substrate surface on which the driver circuit 910 is provided, thereby improving the memory density of the memory cells 951. Furthermore, the memory array 920 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The semiconductor device 900 can reduce the manufacturing cost of the memory array 920.

[0523] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0524] 31 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 31 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0525] The arithmetic device 960 shown in FIG. 31 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0526] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0527] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0528] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0529] The arithmetic device 960 shown in FIG. 31 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 31 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0530] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0531] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates an address for a register 996 and reads or writes data from or to the register 996 depending on the state of the arithmetic unit 960.

[0532] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0533] In the arithmetic unit 960 shown in FIG. 31 , a register controller 997 selects a holding operation in a register 996 in accordance with an instruction from the ALU 991. That is, it selects whether data is to be held by a flip-flop or by a capacitive element in the memory cell of the register 996. If holding data by a flip-flop is selected, power is supplied to the memory cell in the register 996. If holding data in a capacitive element is selected, data is rewritten to the capacitive element, and the supply of power to the memory cell in the register 996 can be stopped.

[0534] FIG. 32 shows an example in which a substrate 990 is provided with not only the arithmetic unit 960 but also a storage device 962, an interface circuit 964, an input / output unit 966, and the like.

[0535] The memory device 962 can be used as a cache lower in level than the cache 999, or as a main memory. The memory device 962 is connected to a cache interface 989 in the arithmetic device 960 via an interface circuit 964. The memory device 962 is also connected to a main memory provided on a separate chip via the interface circuit 964 and an input / output unit 966.

[0536] The semiconductor device 900 having the memory array 920 can be applied to the memory device 962 .

[0537] Various interface circuits and bus lines are provided in the interface circuit 964. The interface circuit 964 may also include a power supply circuit, a clock generation circuit, and the like.

[0538] The interface circuit 964 may include, for example, an I2C (Inter Integrated Circuit), an SPI (Serial Peripheral Interface), or a GPIO (General Purpose Input / Output).

[0539] The input / output portion 966 has an input portion to which a signal, a potential, etc. is input from the outside, and an output portion to which a signal is output to the outside. The input / output portion 966 is provided with a plurality of connection terminals, which are connected to a substrate different from the substrate 990 by connection wiring. The input / output portion 966 may also be provided with a buffer circuit, a protection circuit, etc.

[0540] Methods for connecting the substrate 990 to another substrate include wire bonding using gold or copper wiring, flip-chip bonding using bumps, and direct bonding (hybrid bonding) using a direct bonding technique such as Cu-Cu bonding. Alternatively, a bonding method without using a substrate may be used in which two or more layers are bonded together with insulating films and then through-electrodes are formed to connect electrodes provided on each layer. In particular, using direct bonding or a method using through-electrodes is preferable because it allows the pitch of the connection electrodes to be extremely narrow, making it possible to arrange a large number of connection electrodes at high density and increasing the amount of data transmitted between layers.

[0541] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 33A and 33B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 33B.

[0542] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0543] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, the two substrates are bonded together, and the two substrates are electrically connected using a through-via or a conductive film bonding technique (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce the manufacturing cost.

[0544] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0545] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0546] 33B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0547] Although the number of memory arrays functioning as caches is three in this example, it may be one or two, or four or more.

[0548] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0549] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0550] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0551] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 34A shows a perspective view of a semiconductor device 970B.

[0552] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 34A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0553] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0554] Also, multiple memory arrays may be stacked. Figure 34B shows a perspective view of a semiconductor device 970C.

[0555] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity...

Claims

a first oxide semiconductor, first and second insulators, and first to third conductors; the first oxide semiconductor is disposed on a substrate; the first conductor and the second conductor are disposed on the first oxide semiconductor; the first insulator is disposed on the first conductor and the second conductor and has an opening overlapping a region between the first conductor and the second conductor; the second insulator is disposed in the opening and overlies the first oxide semiconductor; the third conductor is disposed in the opening and on the second insulator; In a cross-sectional view in a channel width direction, a height of the first oxide semiconductor is longer than a width of the first oxide semiconductor, the first oxide semiconductor and the third conductor overlap each other in two or more regions when viewed from above; Semiconductor device. 　 In claim 1, When viewed from above, the first oxide semiconductor has a circumferential shape with both ends coinciding with each other. Semiconductor device. 　 In claim 1, When viewed from above, a side surface of the opening of the first insulator coincides or substantially coincides with a side surface of the first conductor and a side surface of the second conductor. Semiconductor device. 　 In claim 1, When viewed in a cross section in a channel width direction, the first oxide semiconductor has a width of 5 nm to 50 nm, In a cross-sectional view in a channel width direction, a height of the first oxide semiconductor is two times or more and ten times or less than a width of the first oxide semiconductor. Semiconductor device. 　 a first oxide semiconductor, first to third insulators, and first to third conductors; the first oxide semiconductor is disposed on a substrate; the first conductor and the second conductor are disposed on the first oxide semiconductor; the first insulator is disposed on the first conductor and the second conductor and has an opening overlapping a region between the first conductor and the second conductor; the second insulator is disposed in the opening and overlies the first oxide semiconductor; the third conductor is disposed in the opening and on the second insulator; the third insulator is disposed under the first oxide semiconductor and overlaps with the first oxide semiconductor in a top view; The third insulator has a thickness greater than that of the second insulator, In a cross-sectional view in a channel width direction, a height of the first oxide semiconductor is longer than a width of the first oxide semiconductor, the first oxide semiconductor and the third conductor overlap each other in two or more regions when viewed from above; Semiconductor device. 　 In claim 5, When viewed from above, the first oxide semiconductor has a circumferential shape with both ends coinciding with each other. Semiconductor device. 　 In claim 5, When viewed from above, a side surface of the opening of the first insulator coincides or substantially coincides with a side surface of the first conductor and a side surface of the second conductor. Semiconductor device. 　 In claim 5, When viewed in a cross section in a channel width direction, the first oxide semiconductor has a width of 5 nm to 50 nm, In a cross-sectional view in a channel width direction, a height of the first oxide semiconductor is two times or more and ten times or less than a width of the first oxide semiconductor. Semiconductor device. 　 In claim 5, a lower surface of the third conductor has a portion located lower than a lower surface of the first oxide semiconductor; Semiconductor device. 　 a first oxide semiconductor layer, a second oxide semiconductor layer, a first insulator layer, a third insulator layer, and a fourth conductor layer; the first oxide semiconductor and the second oxide semiconductor are disposed on a substrate; the first conductor is disposed on the first oxide semiconductor; the second conductor is disposed on the first oxide semiconductor and on the second oxide semiconductor; the first insulator is disposed on the first conductor and the second conductor and has a first opening and a second opening; the first opening overlaps a region between the first conductor and the second conductor and reaches the first oxide semiconductor; the second opening overlaps with the second oxide semiconductor and reaches the second conductor; the second insulator is disposed in the first opening and overlaps the first oxide semiconductor; the third conductor is disposed in the first opening and on the second insulator; the third insulator is disposed in the second opening overlying the second conductor; the fourth conductor is disposed in the second opening and on the third insulator; In a cross-sectional view in a channel width direction, a height of the first oxide semiconductor is longer than a width of the first oxide semiconductor, the first oxide semiconductor and the third conductor overlap each other in two or more regions when viewed from above; Semiconductor device. 　 In claim 10, In a cross-sectional view in a channel width direction, a height of the second oxide semiconductor is longer than a width of the second oxide semiconductor, the second oxide semiconductor and the fourth conductor overlap each other in two or more regions when viewed from above. Semiconductor device. 　 In claim 10, a first layer and a second layer on the first layer, the first layer includes a first transistor having silicon in a channel formation region; the second layer includes a second transistor and a capacitance element; the first transistor is electrically connected to the second transistor and the capacitive element; the second transistor includes the first oxide semiconductor, the first to third conductors, and the second insulator; the capacitive element includes the second conductor, the fourth conductor, and the third insulator. Semiconductor device. 　 a first oxide semiconductor, first to third insulators, and first to fourth conductors; the first oxide semiconductor is disposed on a substrate; the first conductor and the second conductor are disposed on the first oxide semiconductor; the first insulator is disposed on the first conductor and the second conductor and has a first opening and a second opening; the first opening overlaps a region between the first conductor and the second conductor and reaches the first oxide semiconductor; the second opening overlaps with the first oxide semiconductor and reaches the second conductor; the second insulator is disposed in the first opening and overlaps the first oxide semiconductor; the third conductor is disposed in the first opening and on the second insulator; the third insulator is disposed in the second opening overlying the second conductor; the fourth conductor is disposed in the second opening and on the third insulator; In a cross-sectional view in a channel width direction, a height of the first oxide semiconductor is longer than a width of the first oxide semiconductor, when viewed from above, there are two or more regions where the first oxide semiconductor and the third conductor overlap, and there are two or more regions where the first oxide semiconductor and the fourth conductor overlap. Semiconductor device. 　 In claim 13, a first layer and a second layer on the first layer, the first layer includes a first transistor having silicon in a channel formation region; the second layer includes a second transistor and a capacitance element; the first transistor is electrically connected to the second transistor and the capacitive element; the second transistor includes the first oxide semiconductor, the first to third conductors, and the second insulator; the capacitive element includes the second conductor, the fourth conductor, and the third insulator. Semiconductor device. 　 In any one of claims 1 to 14, the first oxide semiconductor contains indium; the first oxide semiconductor is formed perpendicular or substantially perpendicular to a surface of the substrate; In a cross-sectional observation of the first oxide semiconductor using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to a surface of the substrate are confirmed. Semiconductor device. 　 In any one of claims 1 to 14, the first oxide semiconductor contains indium; the first oxide semiconductor is formed perpendicular or substantially perpendicular to a surface of the substrate; the first oxide semiconductor has a first region, a second region in contact with the first region, and a third region in contact with the second region; In a cross-sectional observation of the first oxide semiconductor using a transmission electron microscope, bright points arranged in layers in a direction perpendicular to a surface of the substrate are confirmed in each of the first region, the second region, and the third region. Semiconductor device. 　 In claim 16, the second region comprises zinc; the second region has crystals; a c-axis of the crystal is approximately parallel to a normal direction of a side surface of the first oxide semiconductor. Semiconductor device. 　 In claim 16, a content of indium in the first region is higher than a content of indium in the second region; The indium content in the third region is higher than the indium content in the second region. Semiconductor device.

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