Semiconductor device

Abstract

Provided is a semiconductor device having a novel configuration. The present invention is provided with a first transistor, a capacitor, and a second transistor. The first transistor has a silicon layer having a channel formation region. The capacitor has a first electrode and a second electrode. The second transistor has an oxide semiconductor layer having a channel formation region. The first electrode is electrically connected to a first gate electrode of the first transistor. The second electrode is electrically connected to the source electrode or the drain electrode of the second transistor. The first electrode is provided along a side surface and the bottom section of a first opening section provided in a first insulating layer on the first gate electrode. The oxide semiconductor layer is provided along a side surface and the bottom section of a second opening section provided in a second insulating layer on the second electrode. In a plan view, the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer have overlapping regions.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device or the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, efforts to combat global warming have become increasingly important. Energy consumption continues to increase, and carbon dioxide emissions, one of the causes of global warming, have yet to be reduced. Simply reducing energy consumption may actually result in a loss of convenience. To reduce energy consumption without sacrificing convenience, low-power consumption technologies for electronic devices are becoming extremely important.

[0004] As a technology for reducing power consumption that can be applied to electronic devices, for example, a signal processing circuit that retains data using a transistor including an oxide semiconductor (also referred to as an OS transistor) is known (see, for example, Patent Document 1). The signal processing circuit described in Patent Document 1 utilizes the characteristics of an OS transistor, which flows very little current in an off state, for data retention, thereby enabling nondestructive read and low-voltage operation (writing and reading) and also having very high rewrite endurance. Therefore, it is possible to reduce the power consumption of electronic devices that include the signal processing circuit.

[0005] JP 2013-179642 A

[0006] In the signal processing circuit described in Patent Document 1, data is retained by turning off an OS transistor connected to the gate of a transistor having silicon (Si transistor). The element size of Si transistors is being reduced. Similarly, to reduce the element size of OS transistors, a drive voltage must be reduced. Therefore, there is a demand for an element structure that allows a transistor to flow very little current in an off state while still having a low drive voltage.

[0007] In the case of Patent Document 1, a charge corresponding to data is stored in a capacitor connected to the gate of a Si transistor. However, connecting a capacitor with a large storage capacity to the gate of a Si transistor increases the circuit area. Furthermore, connecting both the capacitor and the gate of the Si transistor and the source or drain of the OS transistor to the gate of the Si transistor increases the number of openings, resulting in an increase in the circuit area.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device having a novel structure. Another object of one embodiment of the present invention is to provide a semiconductor device that is excellent in terms of reduced power consumption, improved operating speed, miniaturization, or improved storage capacity.

[0009] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and / or other problems.

[0010] One embodiment of the present invention is a semiconductor device including a first transistor, a capacitor, and a second transistor. The first transistor has a silicon layer having a channel formation region. The capacitor has a first electrode and a second electrode. The second transistor has an oxide semiconductor layer having a channel formation region. The first electrode is electrically connected to a first gate electrode of the first transistor. The second electrode is electrically connected to one of a source electrode and a drain electrode of the second transistor. The first electrode is provided along a side surface and a bottom of a first opening provided in a first insulating layer over the first gate electrode. The oxide semiconductor layer is provided along a side surface and a bottom of a second opening provided in a second insulating layer over the second electrode. The first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer have overlapping regions.

[0011] In one embodiment of the present invention, the semiconductor device preferably has the other of the source electrode and the drain electrode of the second transistor provided over the first electrode with a second insulating layer interposed therebetween.

[0012] In one embodiment of the present invention, the semiconductor device preferably has a silicon layer provided over a substrate including single crystal silicon, and the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer overlap with each other in a direction perpendicular to a surface of the substrate.

[0013] In one embodiment of the present invention, the semiconductor device preferably includes a second gate electrode, and the second gate electrode has a region overlapping with the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer in a direction perpendicular to a surface of the substrate.

[0014] In one aspect of the present invention, the semiconductor device preferably has a capacitor provided in an upper layer above the first transistor, a second transistor provided in an upper layer above the capacitor, and the first transistor, the capacitor, and the second transistor have overlapping regions.

[0015] In one aspect of the present invention, the semiconductor device is preferably such that the first electrode is directly connected to the gate electrode of the first transistor.

[0016] In one embodiment of the present invention, the semiconductor device preferably includes an oxide semiconductor layer containing at least In.

[0017] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0018] One embodiment of the present invention can provide a novel semiconductor device or the like. Alternatively, one embodiment of the present invention can provide a semiconductor device that is excellent in terms of reduced power consumption, increased operating speed, miniaturization, or increased storage capacity.

[0019] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

[0020] FIG. 1A is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 1B is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 2 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. FIGS. 3A and 3B are plan views illustrating configuration examples of a semiconductor device, and FIG. 3C is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. FIGS. 4A and 4B are schematic cross-sectional views illustrating a configuration example of a semiconductor device. FIG. 5A is a schematic cross-sectional view illustrating a configuration example of a semiconductor device, and FIG. 5B is a circuit diagram illustrating a configuration example of a semiconductor device. FIGS. 6A and 6B are schematic cross-sectional views illustrating a configuration example of a semiconductor device. FIG. 7A is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 7B is a timing chart illustrating a configuration example of a semiconductor device. FIG. 8 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 9A is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 9B is a schematic diagram illustrating a configuration example of a semiconductor device. FIGS. 10A to 10D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 11A to 11D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. 12A and 12B are diagrams showing an example of an electronic component. FIGS. 13A to 13D are diagrams explaining an example of an electronic component. FIGS. 14A and 14B are diagrams showing an example of an electronic device. FIGS. 15A to 15C are diagrams showing an example of an electronic device. FIG. 16 is a diagram showing an example of a mainframe computer.

[0021] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0022] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0023] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0024] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0025] Furthermore, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "_R", or "_W" may be added to the symbol.

[0026] A semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. The semiconductor device is a device that utilizes semiconductor characteristics, and is a circuit including a semiconductor element (such as a transistor, a diode, or a photodiode) or a device having the circuit.

[0027] 1A is a circuit diagram of a semiconductor device 10 according to one embodiment of the present invention. The semiconductor device 10 includes a transistor MT, a transistor VT, and a capacitor C1. FIG. 1B is a cross-sectional view illustrating the arrangement of each component of the semiconductor device 10 shown in FIG. 1A. FIG. 1B illustrates an element layer 20 and an element layer 30.

[0028] In the drawings described below, arrows indicating the X, Y, and Z directions may be used. The X, Y, and Z directions are perpendicular to each other. In this specification, one of the X, Y, or Z directions may be referred to as the "first direction." One of the other two directions may be referred to as the "second direction." The remaining direction may be referred to as the "third direction." Note that the surface on which a conductive layer, an insulating layer, or the like is formed corresponds to the XY plane. The Z direction corresponds to the direction perpendicular to the aforementioned surface.

[0029] The transistor MT has a silicon layer having a channel formation region. A transistor having a silicon layer having a channel formation region is sometimes called a Si transistor. The element layer 20 shown in FIG. 1B is a layer including transistors having silicon layers.

[0030] The silicon layer uses silicon with high crystallinity, such as single crystal silicon or polycrystalline silicon. Highly crystalline silicon allows Si transistors to achieve high field-effect mobility, enabling faster operation. Therefore, the semiconductor device 10 can operate at high speeds in response to data backup and recovery operations of memory circuits, such as latch circuits or flip-flop circuits, provided in the same layer as the Si transistors.

[0031] 1A and 1B illustrate electrodes GE, SD1, SD2, BSD, TSD, TGE, CE1, and CE2. Electrode BSD also functions as electrode CE1. In FIGS. 1A and 1B, it is illustrated as electrode BSD (electrode CE1). Electrode GE is connected to electrode CE2. In FIG. 1A, it is illustrated as electrode GE (electrode CE2). As shown in FIG. 1B, electrodes GE and CE2 may be separate electrodes. In FIG. 1B, electrodes GE and CE2 are connected via conductive layers 328 and 330.

[0032] The electrode GE functions as the gate of the transistor MT. The electrode SD1 functions as either the source or the drain of the transistor MT. The electrode SD2 functions as the other of the source or the drain of the transistor MT. The electrode CE1 functions as one electrode of the capacitor C1. The electrode CE2 functions as the other electrode of the capacitor C1. The electrode TGE functions as the gate of the transistor VT. The electrode TSD functions as either the source or the drain of the transistor VT. The electrode BSD functions as the other of the source or the drain of the transistor VT.

[0033] The capacitor C1 is formed by the electrode BSD (electrode CE1) and the electrode CE2 facing each other via an insulating layer. The capacitor C1 is formed in an opening in the insulating layer. In other words, the capacitor C1 can be a trench-type capacitor. This allows for an increased capacitor electrode area per unit area. The capacitor C1 also allows the electrode CE2 and the electrode GE connected to the electrode CE2 to be electrically floating. This allows for fluctuations in the potential of the electrodes CE2 and GE in response to fluctuations in the potential of the electrode BSD. While the electrode BSD is described as also serving as the electrode CE1, it can also be a separate electrode. Alternatively, the electrodes CE1 and CE2 can be formed from multiple conductive layers.

[0034] The transistor VT includes an oxide semiconductor layer having a channel formation region. A transistor including an oxide semiconductor layer having a channel formation region is sometimes called an OS transistor. The element layer 30 shown in FIG. 1B includes the transistor VT including the oxide semiconductor layer and a capacitor C1. The element layer 30 can be stacked over the element layer 20.

[0035] Examples of metal oxides that can be used for the oxide semiconductor layer of an OS transistor include indium oxide (In oxide), gallium oxide (Ga oxide), and zinc oxide (Zn oxide). The metal oxide used for an OS transistor can be an In—Zn oxide. The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0036] An OS transistor has an extremely low off-state current. In the semiconductor device 10, the transistor VT is turned on to set the potential of the electrode BSD to a potential (data potential) corresponding to the potential of the electrode TSD, and the transistor VT is turned off to allow charge corresponding to the data potential to be held in the semiconductor device 10 for a long time. In this specification, setting the potential of the electrode BSD to a potential corresponding to the potential of the electrode TSD is also referred to as writing data to the semiconductor device 10. In this specification, holding the potential of the electrode BSD with the transistor VT turned off is also referred to as holding data.

[0037] Furthermore, OS transistors have better electrical characteristics than Si transistors in high-temperature environments. Specifically, OS transistors have a large ratio of on-state current to off-state current even at high temperatures of 125° C. to 150° C., and therefore can perform favorable switching operations. In addition, OS transistors have excellent heat resistance.

[0038] In the semiconductor device 10, data is written by charging and discharging the capacitor C1, so in principle there is no limit to the number of times it can be rewritten and it consumes low energy. Furthermore, the semiconductor device 10 does not consume power to retain data. Therefore, the semiconductor device 10 can function as a low-power memory that can retain data for a long period of time.

[0039] The electrodes GE and CE2 are in an electrically floating state. Therefore, when data is written to the semiconductor device 10, a change in the potential of the electrode BSD causes a change in potential due to capacitive coupling between the electrodes at both ends of the capacitor C1. Specifically, the potential of the electrodes GE and CE2 can also be changed in response to the change in the potential of the electrode BSD. In other words, the gate of the transistor MT can be set to a potential corresponding to the written data. Therefore, the transistor MT can pass a current corresponding to the potential of the electrode BSD, which holds a charge corresponding to the data. Because the transistor MT is a Si transistor, it can achieve high field-effect mobility and can pass a large current between the electrodes SD1 and SD2.

[0040] In this specification, flowing a current between the electrode SD1 and the electrode SD2 by flowing a current corresponding to the potential of the gate of the transistor MT is also referred to as “reading data.” When reading data in the semiconductor device 10, the electrode SD1 can be set to, for example, voltage VDD (high-level power supply voltage, also referred to as H-level potential, or H-level) and the electrode SD2 can be set to, for example, voltage VSS (low-level power supply voltage), thereby allowing a current corresponding to the potential of the gate of the transistor MT to flow.

[0041] The transistor VT is a vertical transistor in which the electrode TSD and the electrode BSD are located at different heights. In the vertical transistor, a current flows in the height direction (Z direction) in the channel formation region of the oxide semiconductor layer. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the above-described vertical transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, a vertical channel transistor, or a vertical transistor.

[0042] In a vertical transistor, the source region, the channel formation region, and the drain region can be at least partially overlapped in a planar view, compared to a horizontal transistor (also called a planar structure or a planar type) in which the electrodes SD1 and SD2 are located at the same height as the transistor MT. Therefore, the vertical transistor can reduce the occupied area (also called a footprint). Furthermore, the structure allows the channel length to be reduced and the channel width to be increased, so the on-resistance can be reduced (the on-current can be increased).

[0043] 1A and 1B, the transistor VT is a vertical transistor. A vertical transistor can have a shorter channel length and a wider channel width than a horizontal transistor. Therefore, even when the OS transistor is miniaturized to the same extent as a Si transistor, the driving voltage can be reduced. Therefore, a semiconductor device having an element structure with a low driving voltage can be obtained, even though the transistor has an extremely small current flowing in an off state.

[0044] 1A and 1B, the capacitor C1 has a trench structure, and one of its electrodes is connected to the gate of the transistor MT. In a capacitor with a trench structure, the capacitor electrodes are disposed in the openings as shown in FIG. 1B, which allows the capacitor to have a large storage capacitance per unit area. Furthermore, in the semiconductor device 10 shown in FIGS. 1A and 1B, data is read by capacitive coupling that utilizes the electrically floating state of the gate of the transistor MT. This allows the circuit area to be reduced without increasing the number of openings, such as the connection between the capacitor and the gate of the Si transistor, or the connection between the source or drain of the OS transistor and the gate of the Si transistor.

[0045] An example of the configuration of a transistor MT included in the semiconductor device 10 shown in Figures 1A and 1B will be described using Figure 2. The transistor MT shown in Figure 2 is provided on a substrate 311 and includes a conductive layer 316 functioning as a gate electrode, an insulating layer 315, a semiconductor region 313 formed of a part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions.

[0046] The transistor MT may be either a p-channel transistor or an n-channel transistor. For example, the transistor MT may be a p-channel transistor, and the transistor VT may be an n-channel transistor. This configuration allows for a complementary circuit configuration (also called a complementary metal oxide semiconductor (CMOS)).

[0047] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0048] The transistor MT shown in FIG. 2 is an example, and the structure is not limited to this example. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0049] A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between the element layer 20 and the element layer 30. On the transistor MT, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film. A conductive layer 328, etc. is embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330, etc. is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wiring.

[0050] The capacitor C1 and the transistor VT included in the element layer 30 on the element layer 20 shown in FIG. 2 will be described with reference to FIGS. 3A to 5B.

[0051] 3A is a plan view showing an example of the configuration of the capacitor C1 and transistor VT and their periphery included in the element layer 30. FIG. 3B is a plan view in which some of the components shown in FIG. 3A are omitted. FIG. 3C is a cross-sectional view taken along the dashed dotted line A1-A2 shown in FIG. 3A. Note that some of the components of the transistor VT, such as the insulating layer 250, are omitted in FIG. 3A. Also, some of the components, such as the insulating layer, are omitted in the subsequent plan views of transistors.

[0052] In FIG. 3C, insulating layers 322, 324, and 326 having conductive layers 328, 330 as shown in FIG. 2 are disposed, with insulating layer 180 disposed on insulating layer 326, insulating layer 280 disposed on insulating layer 180, and insulating layer 285 disposed on insulating layer 280.

[0053] An opening 601 is provided in a region of the insulating layer 180 that overlaps with the conductive layer 330. The conductive layer 115 is provided so as to be in contact with the bottom and side surfaces of the opening 601. That is, the conductive layer 115 has a region in contact with the top surface of the conductive layer 330 and a region in contact with the side surface of the insulating layer 180 in the opening 601. Note that in FIG. 3C , the conductive layer 115 has a region in contact with the top surface of the insulating layer 180.

[0054] An insulating layer 116 is provided over the insulating layer 180 and the conductive layer 115. A conductive layer 220 is provided over the insulating layer 116. The conductive layer 220 is provided so as to fill the opening 601.

[0055] The capacitor C1 includes a conductive layer 115, a conductive layer 220, and an insulating layer 116.

[0056] In the capacitor C1, the conductive layer 115 functions as one of a pair of electrodes, the conductive layer 220 functions as the other of the pair of electrodes, and the insulating layer 116 functions as a dielectric sandwiched between the pair of electrodes.

[0057] The transistor VT is provided above the capacitor C1. The transistor VT includes a conductive layer 220, a conductive layer 240, a semiconductor layer 270, an insulating layer 250, and a conductive layer 260.

[0058] In the transistor VT, the conductive layer 260 functions as a gate electrode, and the insulating layer 250 functions as a gate insulating film. The conductive layer 220 and the conductive layer 240 function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 220 also functions as the other of the pair of electrodes of the capacitor C1.

[0059] The entire region of the semiconductor layer 270 that faces the gate electrode via the gate insulating film between the source electrode and the drain electrode functions as a channel formation region. The region of the semiconductor layer 270 that contacts the source electrode functions as a source region, and the region that contacts the drain electrode functions as a drain region.

[0060] The insulating layer 280 can function as an interlayer insulating layer. The interlayer insulating layer here can be an interlayer film for separating the source electrode and the gate electrode of the transistor VT.

[0061] The conductive layer 240 is provided on the insulating layer 280. The insulating layer 280 has an opening 602 that reaches the conductive layer 220. The conductive layer 240 has an opening 603 that reaches the opening 602. That is, the opening 603 has a region that overlaps with the opening 602.

[0062] 3A shows conductive layers 220, 240, 260, openings 602, and 603 as components of the transistor VT. Here, FIG. 3B shows a configuration example in which the conductive layer 260 is omitted from the components shown in FIG. 3A. That is, FIG. 3B shows conductive layers 220, 240, openings 602, and openings 603.

[0063] 3A and 3B show an example in which the openings 602 and 603 each have a circular shape in a plan view. By forming the openings 602 and 603 in a circular shape, the processing accuracy during the formation of the openings 602 and 603 can be improved, and the openings 602 and 603 can be formed in a very small size. This allows for miniaturization or high integration of OS transistors and capacitors. Note that in this specification and the like, "circular" is not limited to a perfect circle. For example, the planar shapes of the openings 602 and 603 may be elliptical or may include curves. Alternatively, the openings 602 and 603 may be polygonal or may have rounded corners.

[0064] The description of the shapes of the openings 602 and 603 can also be applied to the opening 601 .

[0065] The conductive layer 240 is preferably not provided inside the opening 602. In other words, the conductive layer 240 is preferably not in contact with the side surface of the insulating layer 280 on the opening 602 side. With this structure, the opening 603 and the opening 602 can be formed at the same time, thereby simplifying the process.

[0066] 3C shows an example in which the bottom edge of the conductive layer 240 in the opening 603 coincides with or roughly coincides with the top edge of the insulating layer 280 in the opening 602. In this specification and the like, the bottom surface of the conductive layer 240 refers to the surface on the insulating layer 280 side. The top surface of the insulating layer 280 refers to the surface on the conductive layer 240 side.

[0067] Incidentally, "the edges are aligned or approximately aligned" can also be said to mean that the edges are aligned or approximately aligned. When the edges are aligned or approximately aligned, and when the planar shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, it is also said that the edges are approximately aligned or the planar shapes are approximately aligned.

[0068] Hereinafter, an opening including openings 602 and 603 may be referred to as opening 290. That is, opening 290 reaching conductive layer 220 is provided in insulating layer 280 and conductive layer 240. Opening 602 is a part of opening 290, and opening 603 is another part of opening 290.

[0069] At least a portion of the semiconductor layer 270 is disposed in the opening 290. In the opening 290, the semiconductor layer 270 has a region in contact with a side surface of the conductive layer 240, a region in contact with a side surface of the insulating layer 280, and a region in contact with the top surface of the conductive layer 220. The semiconductor layer 270 has a region in contact with the top surface of the conductive layer 240.

[0070] At least a portion of the insulating layer 250 is disposed in the opening 290. The insulating layer 250 is provided on the semiconductor layer 270 and the insulating layer 280. The insulating layer 250 has a region in contact with the top surface of the semiconductor layer 270, a region in contact with the side surface of the semiconductor layer 270, a region in contact with the side surface of the conductive layer 240, and a region in contact with the top surface of the insulating layer 280.

[0071] The conductive layer 260 is provided on the insulating layer 250, and has a region in contact with the upper surface of the insulating layer 250. The conductive layer 260 is provided so as to fill the opening 290. The conductive layer 260 is provided so as to fill a recess in the insulating layer 250 that reflects the shape of the opening 290. The conductive layer 260 has a region that overlaps with the semiconductor layer 270, with the insulating layer 250 interposed therebetween.

[0072] 3C shows an example in which the conductive layer 260 has a region overlapping with the conductive layer 240 with the insulating layer 250 and the semiconductor layer 270 interposed therebetween, but the present invention is not limited to this. For example, the conductive layer 260 may be provided so as not to overlap with the conductive layer 240. With such a structure, parasitic capacitance occurring between the conductive layer 260 and the conductive layer 240 can be reduced. Therefore, the operating speed of the semiconductor device can be improved.

[0073] The transistor VT is configured such that the direction of the channel length is not substantially parallel to the substrate (not shown) but is along the sidewall of an opening 602 provided in the insulating layer 280. In other words, the transistor VT is a vertical transistor.

[0074] In a vertical transistor, the source region, the channel formation region, and the drain region can at least partially overlap each other in a plan view, which allows the area occupied by the vertical transistor (also referred to as a footprint) to be reduced.Furthermore, the vertical transistor has a structure that allows the channel length to be reduced and the channel width to be increased, which allows the on-resistance to be reduced (the on-current to be increased).

[0075] Furthermore, in the vertical transistor of one embodiment of the present invention, the gate electrode of the Si transistor can at least partially overlap with the electrodes on both ends of the capacitor C1. That is, the conductive layer 316 of the transistor MT, the conductive layers 115 and 220 constituting the capacitor C1, and the semiconductor layer 270 of the transistor VT can have overlapping regions in a plan view. In this vertical transistor, the Si transistor and the capacitor C1 can be connected to each other with a small occupying area.

[0076] FIG. 3A shows an example in which the conductive layer 240 extends in a direction perpendicular to the conductive layers 330 and 260 .

[0077] 4A shows an enlarged view of the semiconductor layer 270 and its vicinity in FIG. 3C. Also, FIG. 4B shows a cross-sectional view in the XY plane including the conductive layer 240.

[0078] As shown in FIG. 4A, the semiconductor layer 270 has a region 270i, and regions 270na and 270nb that are provided so as to sandwich the region 270i.

[0079] Region 270na is a region of the semiconductor layer 270 that contacts the conductive layer 220. Region 270nb is a region of the semiconductor layer 270 that contacts the conductive layer 240. Regions 270na and 270nb each function as a source region or a drain region of the transistor VT. As shown in FIG. 4B , the conductive layer 240 contacts the entire periphery of the semiconductor layer 270. Therefore, the source region or the drain region of the transistor VT can be formed around the entire periphery of a portion of the semiconductor layer 270 that is formed in the same layer as the conductive layer 240.

[0080] The region 270i is a region sandwiched between the regions 270na and 270nb in the semiconductor layer 270. The region 270i functions as a channel formation region of the transistor VT. That is, the channel formation region of the transistor VT is formed in a part of the semiconductor layer 270 located in a region between the conductive layer 220 and the conductive layer 240. It can also be said that the channel formation region of the transistor VT is located in a region of the semiconductor layer 270 that is in contact with the insulating layer 280 or in a region in the vicinity thereof.

[0081] The channel length of the transistor VT is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor VT is determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 4A, the channel length L of the transistor VT is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the edge of the region where the semiconductor layer 270 and the conductive layer 220 contact each other and the edge of the region where the semiconductor layer 270 and the conductive layer 240 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 602 side in a cross-sectional view.

[0082] In a planar transistor, the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor VT can be made into an extremely fine structure below the exposure limit of photolithography (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor VT, thereby improving the frequency characteristics. Therefore, a semiconductor device with high operating speed can be provided.

[0083] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. This reduces the area occupied by the transistor VT compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for a higher integration of the semiconductor device.

[0084] Furthermore, in the XY plane including the channel formation region of the semiconductor layer 270, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are arranged concentrically, as in FIG. 4B . Therefore, the side surface of the centrally located conductive layer 260 faces the side surface of the semiconductor layer 270 via the insulating layer 250. That is, in a top view, the entire periphery of the semiconductor layer 270 forms the channel formation region. In this case, for example, the channel width of the transistor VT is determined by the outer periphery length of the semiconductor layer 270. In other words, it can be said that the channel width of the transistor VT is determined by the maximum width of the opening 602. In FIGS. 4A and 4B, the maximum width D of the opening 602 is indicated by a double-headed, dashed arrow. In FIG. 4B, the channel width W of the transistor VT is indicated by a double-headed, dashed arrow. By increasing the maximum width D of the opening 602, the channel width per unit area can be increased, thereby increasing the on-current.

[0085] When the opening 602 is formed using lithography, the maximum width D of the opening 602 is set by the exposure limit of photolithography. The maximum width D of the opening 602 is also set by the film thicknesses of the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 provided in the opening 602. The maximum width D of the opening 602 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 602 is circular in top view, the maximum width D of the opening 602 corresponds to the diameter of the opening 602, and the channel width W can be calculated as "D × π".

[0086] The maximum width D of the opening 602 may be calculated appropriately according to the shape of the opening 602 in a planar view. For example, if the opening 602 is rectangular in a planar view, the maximum width of the opening 602 may be the length of the diagonal of the rectangle. Alternatively, for example, if the opening 602 is elliptical, polygonal, or polygonal with rounded corners in a planar view, the maximum width of the opening 602 may be the diameter of the smallest circle (also referred to as the minimum encompassing circle) that encompasses the shape of the opening 602 in a planar view.

[0087] In the semiconductor device of one embodiment of the present invention, the channel length L of the transistor VT is preferably smaller than at least the channel width W of the transistor VT. The channel length L of the transistor VT of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor VT. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0088] Furthermore, by forming the opening 602 so as to have a substantially circular shape in top view, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the semiconductor layer 270 substantially uniform, allowing a gate electric field to be applied to the semiconductor layer 270 substantially uniformly.

[0089] 4A and other drawings, the opening 602 is provided so that the side surface of the opening 602 is perpendicular to the upper surface of the conductive layer 220, but the present invention is not limited to this. For example, the side surface of the opening 602 may be tapered.

[0090] In this specification and the like, the term "tapered shape" refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface. For example, it is preferable that the structure has a region in which the angle between the inclined side surface and the substrate surface (also referred to as the taper angle) is less than 90°.

[0091] 3C , a portion of insulating layer 250 is located outside opening 603, i.e., on insulating layer 280. In this case, insulating layer 250 preferably covers the side edges of conductive layer 240. This can prevent conductive layer 260 and conductive layer 240 from shorting out.

[0092] The semiconductor layer 270 can be formed using a single layer or a stacked layer of an oxide semiconductor.

[0093] The semiconductor layer 270 preferably has layered crystals that are approximately parallel to the side surface of the insulating layer 280 in the opening 602. With this configuration, the layered crystals of the semiconductor layer 270 are formed approximately parallel to the channel length direction of the transistor VT, thereby increasing the on-state current of the transistor.

[0094] When the semiconductor layer 270 and the conductive layer 220 come into contact with each other, a metal compound or oxygen vacancy is formed, and the resistance of a region 270na of the semiconductor layer 270 decreases. When the semiconductor layer 270 comes into contact with the conductive layer 220, the resistance of the semiconductor layer 270 and the conductive layer 220 decreases, thereby reducing the contact resistance between the semiconductor layer 270 and the conductive layer 220. Similarly, when the semiconductor layer 270 and the conductive layer 240 come into contact with each other, the resistance of a region 270nb of the semiconductor layer 270 decreases. Therefore, the contact resistance between the semiconductor layer 270 and the conductive layer 240 can be reduced.

[0095] The conductive layer 240 can have a stacked structure of a first conductive layer and a second conductive layer over the first conductive layer. In this case, the first conductive layer can be formed using a conductive material with high conductivity, and the second conductive layer can be formed using a conductive material containing oxygen. When an oxide semiconductor is used for the semiconductor layer 270, the contact resistance between the second conductive layer of the conductive layer 240 and the semiconductor layer 270 can be reduced by using a conductive material containing oxygen for the second conductive layer of the conductive layer 240 that is in contact with the semiconductor layer 270, and a decrease in the on-state current of the transistor VT due to the contact resistance can be suppressed. For example, tungsten can be used for the first conductive layer of the conductive layer 240, and indium tin oxide containing silicon can be used for the second conductive layer of the conductive layer 240.

[0096] The conductive layer 220 has a recessed portion at a position overlapping with the opening 602. The semiconductor layer 270 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220. Note that the recessed portion of the conductive layer 220 may be regarded as part of the opening 290.

[0097] By providing a recess in the conductive layer 220 at a position overlapping with the opening 602, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be lower than the height of the top surface of the conductive layer 220 in contact with the insulating layer 280, with the top surface of the insulating layer 326 as the reference, compared to when the recess is not provided. Here, the height of each surface can be determined with the surface on which the transistor is formed as the reference. Here, the top surface of the insulating layer 326 is used as the reference. The surface used as the reference is not particularly limited, and may be, for example, the top surface of a substrate on which a memory cell or a transistor is provided as the reference.

[0098] This increases the contact area between the conductive layer 220 and the semiconductor layer 270, thereby reducing the contact resistance between the conductive layer 220 and the semiconductor layer 270. This suppresses a decrease in the on-state current of the transistor VT due to the contact resistance between the conductive layer 220 and the semiconductor layer 270. Furthermore, a gate electric field is more easily applied to the channel formation region of the semiconductor layer 270, improving the electrical characteristics of the transistor VT. Furthermore, a gate electric field is more easily applied to the region of the semiconductor layer 270 that is in contact with the conductive layer 220, improving the on-state current of the transistor VT. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor VT can be improved.

[0099] A conductive material containing oxygen is preferably used for the conductive layer 220. When an oxide semiconductor is used for the semiconductor layer 270, the use of a conductive material containing oxygen for the conductive layer 220 can reduce contact resistance between the semiconductor layer 270 and the conductive layer 220.

[0100] Alternatively, the conductive layer 220 may have a structure in which tungsten is stacked under a conductive material containing oxygen. By providing tungsten in this manner, the conductivity of the conductive layer 220 can be improved.

[0101] The insulating layers 280 and 285 preferably have a low dielectric constant because they function as interlayer films. By using a material with a low dielectric constant as the interlayer film, the capacitance value of parasitic capacitance generated between wirings can be reduced.

[0102] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 270.

[0103] An insulator containing excess oxygen is preferably used for the insulating layer 280. By performing heat treatment on the insulating layer 280 containing excess oxygen, oxygen is supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 270, and oxygen vacancies and V ＯIt is possible to reduce H. This makes it possible to stabilize the electrical characteristics of the transistor VT and improve reliability.

[0104] Note that a transistor that can be used in the present invention is not limited to the transistor VT shown in Figure 3C. For example, a transistor VT_BG having a structure shown in Figure 5A may be used. The transistor VT_BG shown in Figure 5A differs from the transistor VT shown in Figure 3C in that a conductive layer 215 and an insulating layer 225 are provided.

[0105] 5A, a conductive layer 215 is provided on an insulating layer 280. An insulating layer 281 is disposed on the insulating layer 280 and the conductive layer 215. A conductive layer 240 is provided on the insulating layer 281.

[0106] An opening 604 reaching the conductive layer 220 is provided in the insulating layer 280, the conductive layer 215, the insulating layer 281, and the conductive layer 240. The opening 604 includes an opening in the insulating layer 280, an opening in the conductive layer 215, an opening in the insulating layer 281, and an opening in the conductive layer 240. The sidewalls of the opening 604 include the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 215, the side surfaces of the insulating layer 281, and the side surfaces of the conductive layer 240.

[0107] Each of the insulating layer 225, the semiconductor layer 270, the insulating layer 250, and the conductive layer 220 is provided so that at least a portion thereof is located in the opening 604. Specifically, the insulating layer 225 is provided so as to cover a portion of the bottom and the sidewall of the opening 290, the semiconductor layer 270 is provided so as to cover another portion of the bottom of the opening 290 and the insulating layer 225, and the insulating layer 250 is provided so as to cover the semiconductor layer 270. Then, the conductive layer 260 is provided so as to fill a recess in the insulating layer 250 that reflects the shape of the opening 604.

[0108] Insulating layer 225 contacts part of the top surface of conductive layer 220 , the side surfaces of insulating layer 280 , conductive layer 215 , insulating layer 281 , and conductive layer 240 in opening 604 .

[0109] In the transistor VT_BG shown in FIG. 5A, the semiconductor layer 270 functions as a semiconductor layer, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating film, the conductive layer 215 functions as a second gate electrode, the insulating layer 225 functions as a second gate insulating film, and the conductive layer 220 and the conductive layer 240 function as a source electrode or a drain electrode, respectively.

[0110] The potential applied to the conductive layer 215 is changed independently of the potential applied to the conductive layer 260, and the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 215, the V ｔｈ Therefore, when a negative potential is applied to the conductive layer 215, the drain current when the potential applied to the conductive layer 260 is 0 V can be made smaller than when a negative potential is not applied. Note that the conductive layer 260 may function as a second gate electrode, and the conductive layer 215 may function as a first gate electrode.

[0111] Alternatively, the conductive layer 215 may be connected to the conductive layer 260. Connecting the conductive layer 215 and the conductive layer 260 and applying the same potential to them makes it possible to increase the on-current, reduce variations in initial characteristics, suppress deterioration of electrical characteristics in a negative GBT (Gate Bias-Temperature) stress test, and suppress fluctuations in the on-current rise voltage at different drain voltages.

[0112] As described above, the transistor VT_BG shown in Fig. 5A has the first gate electrode and the second gate electrode, which can improve the electrical characteristics of the transistor VT of the semiconductor device 10. Fig. 5B shows a circuit diagram in which the configuration of the transistor VT_BG is applied to Fig. 1A. The semiconductor device 10A shown in Fig. 5B can be a transistor VT_BG having an electrode BGL that functions as the second gate electrode.

[0113] 6A is a schematic cross-sectional view showing an example of the configuration of a semiconductor device different from semiconductor device 10. Semiconductor device 10B shown in FIG. 6A corresponds to a configuration in which conductive layers 328 and 330 and the insulating layer having conductive layers 328 and 330 are omitted. This configuration allows the distance between the wirings of capacitor C1 and transistor MT to be shortened. Therefore, the parasitic capacitance of the gate electrode of transistor MT is significantly reduced, thereby reducing power consumption and signal delay.

[0114] FIG. 6B is a cross-sectional view showing a configuration example of a semiconductor device different from the semiconductor device 10. The semiconductor device 10C shown in FIG. 6B includes, in addition to the conductive layer 328 and the conductive layer 330, a wiring layer 40 for connecting the electrode GE of the transistor MT and the electrode CE1 of the capacitor C1. The wiring layer 40 includes an electrode LE for connecting the elements of the element layer 20 and the elements of the element layer 30. This configuration allows the wiring distance between the capacitor C1 and the transistor MT to be increased. Therefore, the distance between the transistor VT and the transistor MT can be increased, preventing electrical interference between the transistors. Furthermore, using the electrode LE as a wiring layer improves the flexibility of circuit design.

[0115] The following describes constituent materials that can be used in semiconductor devices.

[0116] Substrates that can be used in semiconductor devices include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include an insulating substrate with a conductor or semiconductor provided thereon, a semiconductor substrate with a conductor or insulator provided thereon, and a conductive substrate with a semiconductor or insulator provided thereon. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, or the like.

[0117] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0118] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the capacitance value of the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the insulator's function. Note that materials with a low dielectric constant also have high dielectric strength.

[0119] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0120] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0121] Furthermore, a transistor using an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0122] An insulating layer, such as a gate insulating film, that is in contact with a semiconductor layer or that is provided near the semiconductor layer preferably has a region containing excess oxygen. For example, by providing an insulating layer having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0123] Examples of insulators having a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0124] Examples of insulators having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0125] An insulator having a barrier property against oxygen and an insulator having a barrier property against hydrogen can be said to be an insulator having a barrier property against one or both of oxygen and hydrogen.

[0126] Furthermore, examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. These oxides preferably have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. While these metal oxides preferably have an amorphous structure, they may also have crystalline regions formed in some parts.

[0127] In this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). The function of capturing or fixing (also referred to as gettering) a corresponding substance can be rephrased as barrier properties. When hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "barrier property against oxygen" refers to at least one of oxygen atoms, oxygen molecules, etc., which are difficult to diffuse.

[0128] The conductor preferably includes a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the aforementioned metal element or an alloy combining the aforementioned metal elements. As the alloy containing the aforementioned metal element, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. may be used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0129] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and elsewhere, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0130] Furthermore, conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0131] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0132] When an oxide semiconductor is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0133] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the oxide semiconductor in which a channel is formed. Alternatively, the above-mentioned conductive materials containing the metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator may be captured.

[0134] The semiconductor material that can be used for the semiconductor layer is not limited to an oxide semiconductor. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor layer. For example, it is preferable to use a semiconductor of a single element, a compound semiconductor, or a layered material (also called an atomic layer material or a two-dimensional material) as the semiconductor material.

[0135] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0136] Examples of semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0137] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure.

[0138] Layered materials include graphene, silicene, boron carbonitride, and chalcogenides. Boron carbonitride, a layered material, has carbon atoms, nitrogen atoms, and boron atoms arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0139] For example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-mentioned transition metal chalcogenide to a semiconductor layer, a semiconductor device with a large on-current can be provided.

[0140] In a semiconductor device according to one embodiment of the present invention, an OS transistor is a vertical transistor. A vertical transistor can have a shorter channel length and a wider channel width than a horizontal transistor. Therefore, even when the OS transistor is miniaturized to the same extent as a Si transistor, the driving voltage can be reduced. Therefore, a semiconductor device having an element structure with a low driving voltage can be obtained, even though the OS transistor has an extremely low current flowing in an off state.

[0141] In addition, in the structure of the semiconductor device according to one embodiment of the present invention, the capacitor has a trench structure, and one of the electrodes is connected to the gate of the Si transistor. In a capacitor with a trench structure, the capacitor electrode is disposed in an opening, so that the capacitor can have a large storage capacitance per unit area. Furthermore, in the structure of the semiconductor device according to one embodiment of the present invention, data is read by capacitive coupling utilizing the electrically floating state of the gate of the Si transistor. Therefore, the circuit area can be reduced without increasing the number of openings, such as a connection between the capacitor and the gate of the Si transistor, or a connection between one of the source or drain of the OS transistor and the gate of the Si transistor.

[0142] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0143] Embodiment Mode 2 In this embodiment mode, a configuration example of a signal processing circuit including the semiconductor device described in Embodiment Mode 1 will be described.

[0144] 7A shows a block diagram of a signal processing circuit 100 having a semiconductor device 10. FIG. 7B is a timing chart for explaining the operation of the signal processing circuit 100.

[0145] 7A includes a memory circuit 101, a semiconductor device 10, an inverter circuit 111, a switch circuit 112, and an inverter circuit 113. The inverter circuit 111 includes a p-channel transistor 111P and an n-channel transistor 111N. The memory circuit 101 retains data only while a power supply voltage is being supplied. The semiconductor device 10 includes the transistor MT, capacitor C1, and transistor VT described in Embodiment 1.

[0146] The signal processing circuit 100 may further include other circuit elements such as diodes, resistors, and inductors as necessary.

[0147] 7A, a control signal S1 is input to the gate of the transistor VT. A control signal S2 different from the control signal S1 is input to the inverter circuit 111. A control signal S3 different from the control signals S1 and S2 is input to the switch circuit 112. A voltage V2 is also applied to the inverter circuit 111. The output signal of the inverter circuit 111 is applied to the switch circuit 112 via the inverter circuit 113. A voltage V1 is applied to the transistor MT of the semiconductor device 10. The voltage V2 is, for example, the voltage VDD. The voltage V1 is, for example, the voltage VSS or the ground potential GND.

[0148] 7A, a voltage corresponding to the potential difference between voltages V1 and V2 is supplied to the memory circuit 101 as the power supply voltage of the signal processing circuit 100. During a period in which the power supply voltage is not supplied to the memory circuit 101, the potential difference between voltages V1 and V2 can be (substantially) eliminated. For example, both voltages V1 and V2 can be set to voltage VSS.

[0149] One of the source and drain of the transistor VT is connected to the terminal D of the memory circuit 101. ＩＮ Connected to terminal D ＩＮThe data potential of data dataX held in the memory circuit 101 is output to node M1. The data potential of data dataX can be held at node M1, i.e., one electrode of capacitor C1, by controlling the conductive or non-conductive state of transistor VT in response to control signal S1. The potentials of the other electrode of capacitor C1 and the gate electrode of transistor M1 are electrically floating, and therefore have a potential corresponding to fluctuations in the data potential of data dataX. The potentials of the other electrode of capacitor C1 and the gate electrode of transistor M1 are initially at voltage V1 due to leakage current through the gate insulating film. Therefore, the potentials of the other electrode of capacitor C1 and the gate electrode of transistor M1 can be set to the data potential of data dataX.

[0150] When the potential of the gate electrode of the transistor M1 becomes the data potential of the data dataX, the supply of the power supply voltage to the inverter circuit 111 can be controlled.

[0151] When transistor MT is in a conductive state due to the data potential of data dataX, inverter circuit 111 functions to provide an inverted signal of control signal S2 to node M2. For example, when control signal S2 is at an H level, transistor 111P is in a non-conductive state, and transistor 111N and transistor MT are in a conductive state, so node M2 ​​is at voltage V1, i.e., at an L level. Also, for example, when control signal S2 is at an L level, transistor 111P and transistor MT are in a conductive state, and transistor 111N is in a non-conductive state, so node M2 ​​is at voltage V2, i.e., at an H level.

[0152] When transistor MT is in a non-conductive state due to the data potential of data dataX, node M2 ​​is at the H level or in an undefined state. For example, when control signal S2 is at the H level, transistor 111P is in a non-conductive state, and transistor 111N and transistor MT are in a non-conductive state, so node M2 ​​is in an undefined state. As a result, node M2 ​​maintains its previous state. Also, for example, when control signal S2 is at the L level, transistor 111P is in a conductive state, and transistor 111N and transistor MT are in a non-conductive state, so node M2 ​​is at voltage V2, i.e., the H level.

[0153] The potential of the node M2 ​​is applied to one terminal of the switch circuit 112 via the inverter circuit 113. In the switch circuit 112, a control signal S3 controls whether the one terminal and the other terminal of the switch circuit 112 are in a conductive state or a non-conductive state. The other terminal of the switch circuit 112 is connected to the terminal D of the memory circuit 101. ＯＵＴ Connected to terminal D ＯＵＴ is given a data potential having the same logic as the data dataX held at the node M1 of the semiconductor device 10.

[0154] The memory circuit 101 is a memory circuit configured using Si transistors. The memory circuit 101 is a memory element capable of storing 1 bit of data. The memory circuit 101 functions as, for example, a flip-flop circuit or latch circuit included in a register or cache in a processor. The flip-flop circuit or latch circuit can operate at high speed using a clock signal or the like. On the other hand, it is difficult for the flip-flop circuit or latch circuit to retain data during a period when no power supply voltage is supplied. Furthermore, the flip-flop circuit or latch circuit requires a large amount of power to retain data during a period when data is not updated. By configuring the memory circuit 101 to save data to a semiconductor device during a period when data is updated infrequently and then restore the data, a period can be set during which the supply of power supply voltage to the memory circuit 101 is stopped, thereby reducing power consumption.

[0155] The signal processing circuit 100 having the memory circuit 101 includes, in its category, a central processing unit (CPU), a microprocessor, an image processing circuit, a digital signal processor (DSP), a large scale integrated circuit (LSI) such as a field programmable gate array (FPGA), and the like.

[0156] The switch circuit 112 can be configured using a transistor. The transistor may be an n-channel transistor or a p-channel transistor. Alternatively, an n-channel transistor and a p-channel transistor may be used in combination. For example, the switch circuit 112 can be an analog switch.

[0157] The above is a description of the configuration of the signal processing circuit 100. Next, a description will be given of a method for driving the signal processing circuit 100 shown in Fig. 7A. In the signal processing circuit 100, after the supply of the power supply voltage is started, the supply of the power supply voltage is stopped in order to reduce power consumption during data retention, and then the power supply voltage is supplied again. The driving method can be as follows.

[0158] The timing chart of Figure 7B illustrates signals and potentials in the signal processing circuit 100 shown in Figure 7A. In Figure 7B, 101 represents data stored in the memory circuit 101, S1 represents the potential of the control signal S1, S2 represents the potential of the control signal S2, S3 represents the potential of the control signal S3, V1 represents voltage V1, and V2 represents voltage V2. When the potential difference V between voltages V1 and V2 is 0, this corresponds to the case where no power supply voltage is supplied. M1 represents the potential of node M1, and M2 represents the potential of node M2.

[0159] 7A, the transistors VT and MT are n-channel transistors. That is, when the control signal S1 is at a high level, the transistor VT is turned on, and when the control signal S1 is at a low level, the transistor VT is turned off. Also, the example shows a case where the voltage V1 is set to the voltage VSS, and the voltage V2 is switched between the voltage VDD and the voltage VSS.

[0160] The operation of the period T01 in FIG. 7B will be described. During the period T01, the power supply voltage is supplied to the signal processing circuit 100. Here, the voltage V2 is VDD. While the power supply voltage is supplied to the signal processing circuit 100, the memory circuit 101 holds data (denoted as dataX in FIG. 7B). At this time, the control signal S3 is set to an L level, and a non-conduction state is established between one terminal and the other terminal of the switch circuit 112. Note that during the period T02, the control signal S2 may be at an H level or an L level (denoted as A in FIG. 7B). Furthermore, the state of the transistor VT (conductive state or non-conductive state) may be either. That is, the control signal S1 may be at an H level or an L level (denoted as A in FIG. 7B). During the period T01, the node M1 may have any potential (denoted as A in FIG. 7B). During the period T01, the node M2 ​​may have any potential (denoted as A in FIG. 7B). The operation during the period T01 is referred to as normal operation.

[0161] The operation of period T02 in FIG. 7B will be described. Before the supply of power supply voltage to the signal processing circuit 100 is stopped, the control signal S1 is set to H level to turn on the transistor VT. Thus, a data potential corresponding to the data (dataX) stored in the memory circuit 101 is input to the capacitor C1 via the transistor VT. As the potential of one electrode of the capacitor C1 fluctuates, the potential of the gate of the transistor MT also fluctuates. The signal input to the gate of the transistor MT is held by the capacitor C1. Thus, the potential of the node M1 becomes a signal potential (denoted as VX in FIG. 7B) corresponding to the data stored in the memory circuit 101. Thereafter, the control signal S1 is set to L level to turn off the transistor VT. Thus, the data potential corresponding to the data stored in the memory circuit 101 is held in the semiconductor device 10. Even during period T02, the control signal S3 maintains a non-conductive state between one terminal and the other terminal of the switch circuit 112. Note that during period T02, the control signal S2 may be at H level or L level (denoted as A in FIG. 7B). During period T02, the node M2 ​​may be at any potential (denoted as A in FIG. 7B). The operation during period T02 is referred to as the operation before the supply of power supply voltage is stopped.

[0162] The operation of the period T03 in FIG. 7B will be described. After the operation before the power supply voltage supply is stopped, the supply of power supply voltage to the signal processing circuit 100 is stopped at the beginning of the period T03. The voltage V2 becomes VSS. When the supply of power supply voltage is stopped, the data (dataX) held in the memory circuit 101 is erased. However, even after the supply of power supply voltage to the signal processing circuit 100 is stopped, the signal potential (VX) corresponding to the data (dataX) held in the memory circuit 101 is held at the node M1 by the capacitor C1. The transistor VT is an OS transistor. The transistor VT can be an enhancement-type (normally-off) n-channel transistor that flows very little current (off-state current) when it is off. By configuring the transistor VT so that a ground potential (0 V) continues to be input to the gate of the transistor VT when the supply of power supply voltage to the signal processing circuit 100 is stopped, the transistor VT can be maintained in a non-conductive state even after the supply of power supply voltage to the signal processing circuit 100 is stopped. As a result, the potential held by the capacitor C1 (potential VX of node M2) can be maintained for a long period of time. In this way, the signal processing circuit 100 holds data (dataX) even after the supply of power supply voltage is stopped. Period T03 corresponds to the period during which the supply of power supply voltage to the signal processing circuit 100 is stopped.

[0163] The operation during period T04 in FIG. 7B will be described. To resume the supply of power supply voltage to the signal processing circuit 100, voltage V2 is set to VDD. Also, control signal S2 is set to L level. At this time, control signal S1 is at L level, and transistor VT remains non-conductive. Also, control signal S3 is at L level, and there is non-conduction between one terminal and the other terminal of switch circuit 112. In this way, voltage V2 when power supply voltage is being supplied, i.e., VDD, is input to inverter circuit 111. Therefore, in inverter circuit 111, transistor 111P is set to a conductive state, and the potential of node M2 ​​can be set to a constant potential (e.g., VDD) (hereinafter referred to as a precharge operation).

[0164] After the precharge operation, in period T05, the control signal S2 is set to H level. At this time, the control signal S1 remains at L level, the transistor VT remains non-conductive, and the control signal S3 is at L level, so that one terminal and the other terminal of the switch circuit 112 are non-conductive.

[0165] The conductive or non-conductive state of transistor MT is selected according to the signal held in capacitor C1 (potential VX at node M2), and whether or not an L-level potential is supplied to inverter circuit 111 is determined. When transistor MT is conductive and transistor 111N in inverter circuit 111 is also conductive, voltage V1 (e.g., VSS) is input to node M2. As a result, node M2 ​​becomes L-level. On the other hand, when transistor MT is non-conductive and transistor 111N in inverter circuit 111 is also conductive, an L-level potential is not supplied to node M2, and the potential of node M2 ​​remains at a constant potential (e.g., VDD) determined by the precharge operation.

[0166] Thus, the potential of node M2 ​​becomes VDD or VSS depending on whether transistor MT is conductive or non-conductive. For example, when the signal held in the memory circuit 101 is "1" and corresponds to an H-level potential (VDD), the potential of node M2 ​​becomes an L-level potential (VSS) corresponding to a signal "0." On the other hand, when the signal held in the memory circuit 101 is "0" and corresponds to an L-level potential (VSS), the potential of node M2 ​​becomes an H-level potential (VDD) corresponding to a signal "1." In other words, an inverted signal of the data (dataX) stored in the memory circuit 101 is held in node M2. In FIG. 7B, this potential is denoted as VXb. That is, a signal corresponding to the data (dataX) input from the memory circuit 101 during period T02 is converted to the potential (VXb) of node M2.

[0167] After that, in period T06, the control signal S3 is set to H level, thereby establishing electrical continuity between one terminal and the other terminal of the switch circuit 112. At this time, the control signal S2 remains at H level. Also, the control signal S1 remains at L level, and the transistor VT remains non-conductive. Then, the potential (VXb) of the node M2 ​​is converted into an inverted signal via the inverter circuit 113, and this inverted signal can be input to the memory circuit 101. In other words, the potential (VXb) of the node M2 ​​can have the logic of the inverted data (dataX). In this way, the memory circuit 101 can again hold the data (dataX) that it held before the supply of power supply voltage to the signal processing circuit 100 was stopped.

[0168] Furthermore, the potential of the node M2 ​​is set to a constant potential (VDD in FIG. 7B) by the precharge operation in the period T04, and then becomes a potential VXb corresponding to the data (dataX) in the period T05. Because the precharge operation is performed, the time until the potential of the node M2 ​​is set to a predetermined potential VXb can be shortened. In this way, the time until the memory circuit 101 retains the original data after the supply of the power supply voltage is resumed can be shortened.

[0169] This completes the description of the method for driving the signal processing circuit 100. In the above-described driving method, while the power supply voltage is not supplied to the signal processing circuit 100, the data stored in the storage circuit 101, which corresponds to a volatile memory, can be held by the capacitor C1 provided in the semiconductor device 10.

[0170] In the structure of the semiconductor device 10 according to one embodiment of the present invention, the OS transistor is a vertical transistor. A vertical transistor can have a shorter channel length and a wider channel width than a horizontal transistor. Therefore, even when the OS transistor is miniaturized to the same extent as a Si transistor, the driving voltage can be reduced. Therefore, a semiconductor device having an element structure with a low driving voltage can be obtained, even though the OS transistor is a transistor with an extremely low current flowing in an off state.

[0171] Additionally, in the semiconductor device 10 according to one embodiment of the present invention, the capacitor has a trench structure, and one of the electrodes is connected to the gate of the Si transistor. In a trench capacitor, the capacitor electrode is disposed in an opening, which allows the capacitor to have a large storage capacitance per unit area. Furthermore, in the semiconductor device according to one embodiment of the present invention, data is read by capacitive coupling utilizing the electrically floating state of the gate of the Si transistor. This allows the circuit area to be reduced without increasing the number of openings, such as the connection between the capacitor and the gate of the Si transistor, or the connection between one of the source or drain of the OS transistor and the gate of the Si transistor.

[0172] In the semiconductor device 10, the signal held by the capacitor C1 is input to the gate of the transistor MT. Therefore, after the supply of power supply voltage to the signal processing circuit 100 is resumed, the state (conductive state or non-conductive state) of the transistor MT is determined according to the signal held by the capacitor C1, and can be read out from the semiconductor device 10. Therefore, even if the potential corresponding to the signal held in the capacitor C1 fluctuates slightly, the original signal can be accurately read out.

[0173] By using such a signal processing circuit 100 in a storage device such as a register or cache memory of a processor, it is possible to prevent data loss in the storage device due to a power supply voltage interruption. Furthermore, after the supply of power supply voltage is resumed, the state before the power supply interruption can be restored in a short time. Therefore, it is possible to provide a signal processing circuit that can reduce power consumption by interrupting power supply to the entire signal processing circuit or one or more logic circuits that constitute the signal processing circuit, even for a short time.

[0174] When the components of the signal processing circuit 100 shown in FIG. 7A are divided into the element layer 20 and the element layer 30 shown in the first embodiment, they can be expressed as shown in FIG.

[0175] 8, the components provided in the element layer 20 are illustrated as an inverter circuit 111, an inverter circuit 113, a switch circuit 112, a memory circuit 101, and a transistor MT. Also in Fig. 8, the components provided in the element layer 30 are illustrated as a capacitor C1 and a transistor VT. The element layer 20 and the element layer 30 can be stacked in the Z direction as illustrated in Fig. 1B etc.

[0176] In the configuration of the signal processing circuit 100 of one embodiment of the present invention, the capacitor C1 and the transistor MT are arranged in an element layer 30 that is above an element layer 20 such as the memory circuit 101. Therefore, the distance between the capacitor C1 and the transistor MT and the wiring between the transistor MT and the wiring between the capacitor C1 and the transistor MT can be shortened. As a result, the parasitic capacitance of the gate electrode of the transistor MT is significantly reduced, thereby reducing power consumption and signal delay.

[0177] 9A shows a configuration example different from the element layer 20 and the element layer 30 described in FIG. 9A, the inverter circuit 111, the inverter circuit 113, the switch circuit 112, the memory circuit 101, and the transistor MT in the element layer 20 are illustrated as a circuit section 120. The capacitor C1 and the transistor MT in the element layer 30 are illustrated as a circuit section 130.

[0178] 9A , one electrode of capacitor C1 is connected to a terminal that applies voltage V1. One of the source or drain of transistor VT is connected to the gate of transistor MT. The connection between one of the source or drain of transistor VT and the gate of transistor MT is made at connection portion 150A provided between element layer 20 and element layer 30. The connection between one electrode of capacitor C1 and the terminal that applies voltage V1 is made at connection portion 150B provided between element layer 20 and element layer 30.

[0179] 9B is a schematic diagram illustrating the positional relationship between the connection portion 150A and the connection portion 150B shown in FIG. 9A. The circuit portion 120 provided in the element layer 20 has an area that overlaps with the circuit portion 130 provided in the element layer 30. The connection portion 150 can be provided in the area where the circuit portion 120 and the circuit portion 130 overlap. On the other hand, the connection portion 150B is preferably provided in an area where the circuit portion 120 and the circuit portion 130 are not provided.

[0180] 9A and 9B , the connection portions for connecting the capacitor C1 to the transistor VT and the transistor VT to the transistor MT can be arranged separately in the region where the circuit portions 120 and 130 are provided and in the region outside the region where the circuit portions 120 and 130 are provided. Therefore, even in a configuration in which a capacitor is connected to the gate of a Si transistor and a source or drain of an OS transistor is connected to the gate of a Si transistor, the circuit area can be reduced without increasing the number of openings for providing a connection portion between the element layer 20 and the element layer 30.

[0181] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0182] Embodiment 3 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0183] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0184] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0185] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0186] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0187] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0188] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0189] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0190] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0191] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0192] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0193] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0194] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0195] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0196] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using at least two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed using at least two kinds of film formation methods may be referred to as a hybrid OS.

[0197] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by a first deposition method and then forming a metal oxide as a second layer on the first layer by a second deposition method. In this case, it is preferable to use a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed compared to the second deposition method as the first deposition method. By using a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed as the first deposition method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer, thereby increasing the crystallinity of the oxide semiconductor layer.

[0198] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). Examples of wet methods include spray coating. Compared to the sputtering method described below, the ALD and CVD methods are suitable as the first film formation method because they can suppress damage to the surface to be formed.

[0199] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0200] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling ultrathin film formation, film formation on high aspect ratio structures or surfaces with large steps, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable in some cases because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs a high substrate temperature during film formation and / or an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0201] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0202] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0203] Examples of the second film formation method include sputtering, pulsed laser deposition (PLD), etc. Metal oxides formed using the second film formation method tend to have a CAAC structure.

[0204] Note that the first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0205] Furthermore, a third layer can be further formed on the second layer. Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0206] For example, the oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide as a first layer by a first deposition method, forming a metal oxide as a second layer by a second deposition method, and forming a metal oxide as a third layer by the first deposition method. Specifically, an ALD method can be used as the first deposition method, and a sputtering method can be used as the second deposition method. The ALD method has better coverage than the sputtering method, and the use of the ALD method as the deposition method for the first layer and the third layer can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0207] [Method for Manufacturing Oxide Semiconductor Layer] The oxide semiconductor 230, which is an oxide semiconductor layer, can be manufactured by, for example, forming an oxide semiconductor 230a over the layer 229, which is a surface to be formed, by an ALD method, forming an oxide semiconductor 230b on the oxide semiconductor 230a by a sputtering method, and forming an oxide semiconductor 230c on the oxide semiconductor 230b by an ALD method. After the oxide semiconductor 230 is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor 230. The heat treatment here is not limited to heat treatment. For example, heat applied during the manufacturing process may be used.

[0208] The oxide semiconductor 230 can be used for the semiconductor layer 270 or the like. The layer 229 corresponds to the insulating layer 280 or the like described in the above embodiment.

[0209] The layer 229 does not need to be crystalline. When the layer 229 is crystalline, the layer 229 may have a crystal structure with low lattice matching with a metal oxide included in the oxide semiconductor 230.

[0210] An example of a method for manufacturing the oxide semiconductor 230 will be described with reference to FIGS. 10A to 11D.

[0211] When a metal oxide film is formed by sputtering, alloying of components contained in the metal oxide film with components contained in the layer on which the film is formed may occur due to damage caused by sputtered particles on the surface on which the film is formed or by energy imparted to the substrate by the sputtered particles, etc. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying of components contained in the metal oxide film with components contained in the layer on which the film is formed.

[0212] Therefore, first, an oxide semiconductor 230a is formed on the layer 229 by ALD (FIG. 10A), and then an oxide semiconductor 230b is formed on the oxide semiconductor 230a by sputtering (FIG. 10B).

[0213] In the method for forming the oxide semiconductor layer of one embodiment of the present invention, the oxide semiconductor 230a is formed between the oxide semiconductor 230b and the layer 229 by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is formed. This prevents alloying of components contained in the oxide semiconductor 230 and components contained in the layer 229, thereby enabling the crystallinity of the oxide semiconductor 230 to be further improved.

[0214] By using the above structure, the thickness of the alloyed region can be reduced, or the thickness can be reduced to such an extent that the alloyed region is not observable. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that FIGS. 10A and 10B show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor 230a.

[0215] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0216] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 230a being the depth direction. Next, in the profile of quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 230a contains In) that is the main component of the oxide semiconductor 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 230a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0217] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0218] For example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the oxide semiconductor 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0219] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0220] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor 230 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably between more than 0 nm and 2 nm, more preferably between 1 nm and 2 nm.

[0221] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of the oxide semiconductor 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0222] When the oxide semiconductor 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 10A , the oxide semiconductor 230a may have a region having lower crystallinity than the oxide semiconductor 230b.

[0223] The oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure.

[0224] When the oxide semiconductor 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, sputtering particles or energy imparted to the substrate by the sputtering particles or the like during the formation of the oxide semiconductor 230b may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, causing at least a part of the oxide semiconductor 230a to crystallize.

[0225] In the formation of the oxide semiconductor 230b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, a metal oxide with high crystallinity can be formed in some cases.

[0226] Next, the oxide semiconductor 230c is formed on the oxide semiconductor 230b by ALD (FIG. 10C). The formation of the oxide semiconductor 230c by ALD can be performed by referring to the method for forming the oxide semiconductor 230a.

[0227] When the oxide semiconductor 230c is formed on the oxide semiconductor 230b having the CAAC structure by the ALD method, the oxide semiconductor 230c may grow epitaxially around the oxide semiconductor 230b as a nucleus. Therefore, when the oxide semiconductor 230c is formed, the oxide semiconductor 230c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 230c.

[0228] Next, a heat treatment step may be performed. This heat treatment step may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c. Furthermore, if the region is formed only below the oxide semiconductor 230c after film formation by the ALD method, this heat treatment step may cause the region to expand upward ( FIG. 10D ). That is, this heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 230c.

[0229] Furthermore, it is preferable that at least a portion of the oxide semiconductor 230a is converted into CAAC by the heat treatment ( FIG. 10D ). It is expected that the CAAC is easily generated because the mixed layer 231 formed in the oxide semiconductor 230a during the formation of the oxide semiconductor 230b serves as a nucleus or seed. It is preferable that the region in the oxide semiconductor 230a that is converted into CAAC is wide, and it is preferable that the CAAC is converted into CAAC up to the vicinity of the layer 229.

[0230] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 230a, the CAAC can be formed up to the vicinity of the layer 229 regardless of the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor 230a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0231] 10A to 10D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIGS. 10A to 10D can be regarded as conceptual diagrams illustrating a film formation model of a metal oxide film according to one embodiment of the present invention. As shown in FIGS. 10A to 10D , the oxide semiconductors 230a and 230c each have high crystallinity using the oxide semiconductor 230b, which has high crystallinity, as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor 230a may be increased by heat treatment during the formation of the oxide semiconductor 230b or after the formation of the oxide semiconductor 230c. The crystallinity of the oxide semiconductor 230c may be increased by heat treatment during the formation of the oxide semiconductor 230c or after the formation of the oxide semiconductor 230c. The heat treatment has an assisting effect of increasing the crystallinity.

[0232] As described above, in the method for forming a metal oxide film of one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the oxide semiconductor 230a and the oxide semiconductor 230c here) can be increased by using the oxide semiconductor 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown by solid-phase growth using the oxide semiconductor 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, i.e., a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC). Note that although FIGS. 11A to 11D illustrate a structure including the oxide semiconductors 230a, 230b, and 230c, the present invention is not limited thereto. For example, an AG CAAC film can also be formed in a structure including the oxide semiconductors 230a and 230b.

[0233] In the oxide semiconductor 230, it is preferable that a region having a CAAC structure is widely present throughout the entire layer. Fig. 11A shows the oxide semiconductors 230a, 230b, and 230c each being crystallized. At this time, the boundary between the oxide semiconductors 230a and 230b may not be observed. Also, the boundary between the oxide semiconductors 230b and 230c may not be observed. The oxide semiconductor 230 may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor 230 may be expressed as a single layer.

[0234] Furthermore, there are cases where a portion of the oxide semiconductor 230a or the oxide semiconductor 230c is not crystallized. The example shown in Fig. 11B illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a is not crystallized. Fig. 11C illustrates a state in which the vicinity of the surface in the oxide semiconductor 230c is not crystallized. Fig. 11D illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a and the vicinity of the surface of the oxide semiconductor 230c are not crystallized.

[0235] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0236] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor 230, the boundaries between the stacked films of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0237] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the oxide semiconductors 230a and 230c, crystals that reflect the crystal orientation of the oxide semiconductor 230b are formed, thereby suppressing polycrystallization.

[0238] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 230b and the crystals of the oxide semiconductor 230a or the oxide semiconductor 230c is small. This allows the oxide semiconductor 230a or the oxide semiconductor 230c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 230b. In this case, for example, when a cross section of the oxide semiconductor 230 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the oxide semiconductor 230a or the oxide semiconductor 230c.

[0239] The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c is not particularly limited as long as the lattice mismatch between the crystal of the oxide semiconductor 230b and the crystal of the oxide semiconductor 230a or the oxide semiconductor 230c is small. The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0240] [Composition of Oxide Semiconductor Layer] As described above, the oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed by, for example, a sputtering method. The oxide semiconductor 230b preferably contains, for example, zinc. The inclusion of zinc results in a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 230b preferably contains the element M in addition to zinc. The inclusion of the element M in the oxide semiconductor 230b can, for example, prevent oxygen vacancies from being formed in the metal oxide. Therefore, the reliability of a transistor using the oxide semiconductor layer can be improved. Specifically, the oxide semiconductor 230b may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, or an atomic ratio of In:M:Zn = 1:3:4 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0241] The oxide semiconductor 230b may not contain the element M. For example, it may be an In—Zn oxide. Specifically, it may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. Furthermore, it may have a composition containing a trace amount of the element M. For example, it may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, it may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0242] The oxide semiconductor 230a and the oxide semiconductor 230c can be metal oxides having a high proportion of In. The oxide semiconductor 230a and the oxide semiconductor 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-state current and frequency characteristics can be increased.

[0243] Alternatively, the oxide semiconductors 230a and 230c may not contain the element M. For example, they may be In-Zn oxides. Specifically, they may have a composition of In:Zn=1:1 (atomic ratio) or a composition therearound, a composition of In:Zn=2:1 (atomic ratio) or a composition therearound, or a composition of In:Zn=4:1 (atomic ratio) or a composition therearound. Alternatively, indium oxide may be used. The oxide semiconductors 230a and 230c may contain a trace amount of the element M. Specifically, the composition may be In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition close thereto, In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, or In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition close thereto.

[0244] Note that increasing the zinc composition of the oxide semiconductor can improve the crystallinity of the oxide semiconductor. It is particularly preferable that the oxide semiconductor 230a contains zinc. For example, when the oxide semiconductor 230a is formed by an ALD method and the oxide semiconductor 230b is formed by a sputtering method, zinc contained in the oxide semiconductor 230a may diffuse into the oxide semiconductor 230b. Note that this diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the oxide semiconductor 230a to the oxide semiconductor 230b is expected to improve the crystallinity. Alternatively, the diffusion of zinc from the oxide semiconductor 230a to the oxide semiconductor 230b is expected to promote the lateral growth of crystal parts having c-axis orientation, thereby accelerating the formation of CAAC.

[0245] The oxide semiconductors 230a and 230c can be metal oxides containing a higher proportion of In than the oxide semiconductor 230b.

[0246] Alternatively, for example, metal oxides having a higher Ga content than the oxide semiconductor 230b may be used for the oxide semiconductors 230a and 230c. For example, the oxide semiconductors 230a and 230c may be metal oxides having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereabout, metal oxides having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout, or metal oxides having an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereabout. Increasing the Ga content may result in the band gaps of the oxide semiconductors 230a and 230c being larger than those of the oxide semiconductor 230b. As a result, the oxide semiconductor 230b is sandwiched between the oxide semiconductors 230a and 230c, which have larger band gaps, and the oxide semiconductor 230b mainly functions as a current path (channel). The oxide semiconductor 230b is sandwiched between the oxide semiconductor 230a and the oxide semiconductor 230c, whereby trap states at the interface of the oxide semiconductor 230b and in the vicinity thereof can be reduced, thereby realizing a buried channel transistor in which the channel is located away from the insulating layer interface, and thereby increasing the field-effect mobility.

[0247] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 230a and 230c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the oxide semiconductor 230b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor 230a and the oxide semiconductor 230c and the oxide semiconductor 230b.

[0248] In particular, even when the oxide semiconductor 230 a and the oxide semiconductor 230 c have a high In content, the oxide semiconductor layer can have suitable crystallinity for a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0249] The oxide semiconductor 230a and the oxide semiconductor 230c may have different compositions.

[0250] The oxide semiconductor 230a and the oxide semiconductor 230c may be made of a metal oxide having the same composition as the oxide semiconductor 230b.

[0251] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0252] The composition of the metal oxide used in the oxide semiconductor 230 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0253] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0254] The crystal orientation can be obtained from a Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on a TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0255] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0256] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0257] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be a circle with a diameter of 1.0 nm, for example. Note that the region where FFT is performed is not limited to a circle.

[0258] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0259] The c-axis orientation rates of the region where the oxide semiconductor 230a is formed, the region where the oxide semiconductor 230b is formed, and the region where the oxide semiconductor 230c is formed are denoted by Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0260] After the oxide semiconductor 230 is formed, the boundaries between the oxide semiconductors 230a, 230b, and 230c may not be clearly observed.

[0261] The oxide semiconductor 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, starting from the top of the layer 229. Each region has a layer shape.

[0262] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rates of the second region and the third region are each 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0263] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor 230 .

[0264] Alternatively, the layer thickness in each region may be approximately the same, for example.

[0265] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0266] In this embodiment, electronic components, electronic devices, and large scale computers that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, and large scale computers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0267] [Electronic Component] FIG. 12A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 709 is mounted. The electronic component 709 shown in FIG. 12A has a semiconductor device 710 inside a mold 711. FIG. 12A omits some parts in order to show the interior of the electronic component 709. The electronic component 709 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714. The electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0268] The semiconductor device 710 also includes a layer 715 having an arithmetic core and a layer 716 having a memory. The layer 716 having the memory is configured by stacking multiple memory cell arrays. The stacked configuration of the layer 715 having the arithmetic core and the layer 716 having the memory can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the layer 715 having the arithmetic core and the layer 716 having the memory as a monolithic stack, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0269] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0270] Furthermore, it is preferable that the memory cell arrays included in the memory-containing layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used in the memory-containing layer 716, it is more difficult to achieve a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0271] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0272] 12B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0273] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0274] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0275] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0276] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0277] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0278] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0279] Electrodes 733 may be provided on the bottom of the package substrate 732 in order to mount the electronic component 730 on another substrate. FIG. 12B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0280] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0281] 13A to 13D are diagrams illustrating configuration examples different from the electronic components 709 and 730 described above in Fig. 12A and 12B. Electronic components 730A to 730D illustrated in Fig. 13A to 13D have a configuration in which a layer 715 having an arithmetic core and a layer 716 having a memory are provided in a mold 711 on an interposer 731 provided with the above-described electrodes 733.

[0282] In the configuration of electronic component 730A shown in FIG. 13A , layer 715 having processor cores is provided on interposer 731 and connected to electrode pads (not shown) via wires 714. Layer 716 having memory formed on layer 715 having processor cores has the monolithic stack configuration described above. In the monolithic stack configuration, layer 716 having memory and layer 715 having processor cores are electrically connected. Therefore, wires 714 between interposer 731 and layer 715 having processor cores can also serve as wiring between each layer having memory 716 and interposer 731, thereby reducing the number of wires.

[0283] While the configuration example of FIG. 13A illustrates a single monolithic stacked structure, a monolithic stacked electronic component may be stacked with other electronic components. For example, as shown in FIG. 13B , a monolithic stacked electronic component 730B may be stacked with a layer 716A having memory and a layer 715A having an arithmetic core, and a layer 716B having memory and a layer 715B having an arithmetic core. The monolithic stacked electronic component stacked with other electronic components is fixed to a resin sheet 744 by an adhesive layer 743. This configuration allows for stacking multiple memory cell arrays with different circuit configurations. Having different circuit configurations allows for a semiconductor device with different memory bandwidths and memory access latencies, making it suitable for use in a hierarchical structure such as a cache memory.

[0284] The configuration example of FIG. 13A can also be stacked with other electronic components. For example, as shown in FIG. 13C , electronic component 730C can be formed by stacking the above-described electronic component 730A with an electronic component in which a layer 715C having an operational core such as a processor is provided in mold 711 between interposers 731A and 731B. The respective circuit layers can be connected via conductors such as electrodes 733. This configuration can increase the speed of the interface between the processor and memory. Furthermore, a gap (space) can be provided between the mold including the layer 715C having the operational core and the electronic component 730A, thereby making it difficult for heat generated in the layer 715C having the operational core to be transmitted to electronic component 730A.

[0285] 13C , a memory layer having an OS transistor may be provided on a layer 715C having an arithmetic core such as a processor. For example, as shown in FIG. 13D , a memory layer 716C may be provided on a layer 715C having an arithmetic core, and stacked on an electronic component 730A, as in electronic component 730D. This configuration enables the high-speed operation of the interface between a so-called on-chip memory configuration in which memory is formed directly on a processor and a semiconductor device configuration having stacked memory layers.

[0286] [Electronic Device] Fig. 14A is an external view showing an example of a portable electronic device. Fig. 14B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0287] In the portable electronic device 595, the electronic component 709 can be provided on the printed circuit board 596. The portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by the speaker 597, the camera 598, the microphone 599, etc. using the electronic component 709. The portable electronic device 595 can also be used in systems that perform voice guidance, image search, etc.

[0288] The electronic component 709 performs arithmetic processing of the obtained image data using a neural network or the like, thereby enabling processing such as increasing the image resolution, reducing image noise, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0289] 15A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, and the like. The housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, the video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated and function as an operation unit. The electronic component 709 can be incorporated into chips or the like provided on the substrates of the housings 1102 and 1103.

[0290] 15B shows a stick-shaped electronic device 1120 of a USB connection type. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The electronic component 709 can be incorporated into the controller chip 1126 of the board 1124, etc.

[0291] 15C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the electronic component 709 described above.

[0292] [Mainframe] The electronic component 709 can be used in a system 3000 including a mainframe that communicates with the electronic device, instead of being built into the electronic device. In this case, the electronic device and the mainframe constitute a computing system. Fig. 16 shows an example of the configuration of the system 3000.

[0293] The system 3000 is configured by an electronic device 3001 and a mainframe computer 3002. Communication between the electronic device 3001 and the mainframe computer 3002 can be performed via an internet line 3003.

[0294] The mainframe 3002 has a plurality of racks 3004. A plurality of circuit boards 3005 are provided on the racks, and the electronic components 709 described in the above embodiment can be mounted on the circuit boards 3005. This forms a neural network in the mainframe 3002. The mainframe 3002 can then perform neural network calculations using data input from the electronic device 3001 via the Internet line 3003. The results of calculations by the mainframe 3002 can be transmitted to the electronic device 3001 via the Internet line 3003 as necessary. This reduces the calculation load on the electronic device 3001.

[0295] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0296] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes will be given regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0297] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0298] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0299] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0300] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0301] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0302] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0303] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0304] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0305] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0306] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0307] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0308] In this specification, the channel length of a planar transistor refers to, for example, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap in a plan view of the transistor, or a distance between a source and a drain in a region where a channel is formed.

[0309] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0310] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0311] In this specification, "A and B are connected" refers to an electrical connection between A and B. Here, "A and B are electrically connected" refers to a connection in which an electrical signal can be transmitted between A and B when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between A and B. Note that "A and B are electrically connected" also includes a case in which A and B are directly connected. Here, "A and B are directly connected" refers to a connection in which an electrical signal can be transmitted between A and B via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection refers to a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0312] BGL: electrode, BSD: electrode, GE: electrode, LE: electrode, MT: transistor, TGE: electrode, TSD: electrode, VDD: voltage, VT: transistor, 10: semiconductor device, 20: element layer, 30: element layer, 100: signal processing circuit,

Claims

A first transistor; A capacitor; a second transistor; the first transistor has a silicon layer having a channel formation region; the capacitor has a first electrode and a second electrode; the second transistor includes an oxide semiconductor layer having a channel formation region, the first electrode is electrically connected to a first gate electrode of the first transistor; the second electrode is electrically connected to one of a source electrode or a drain electrode of the second transistor; the first electrode is provided along a side surface and a bottom surface of a first opening provided in a first insulating layer on the first gate electrode; the oxide semiconductor layer is provided along a side surface and a bottom surface of a second opening provided in a second insulating layer on the second electrode; the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer have overlapping regions; Semiconductor device. 　 In claim 1, the other of the source electrode and the drain electrode of the second transistor is provided above the first electrode via the second insulating layer; Semiconductor device. 　 In claim 1, The silicon layer is provided on a substrate having single crystal silicon; the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer have an overlapping region in a direction perpendicular to a surface of the substrate; Semiconductor device. 　 In claim 3, the second transistor has a second gate electrode; the second gate electrode has a region overlapping with the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer in a direction perpendicular to a surface of the substrate; Semiconductor device. 　 In claim 1, the capacitor is provided in an upper layer of the first transistor, the second transistor is provided in an upper layer of the capacitor, the first transistor, the capacitor, and the second transistor have overlapping regions. Semiconductor device. 　 In claim 1, the first electrode is directly connected to a gate electrode of the first transistor; Semiconductor device. 　 In claim 1, The oxide semiconductor layer contains at least In. Semiconductor device.

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