Method for manufacturing semiconductor device

Abstract

This method for manufacturing a semiconductor device comprises: a step for forming a SiC layer on a single crystal SiC layer of a substrate having a polycrystalline SiC substrate, which has a first surface and a second surface, and a single crystal SiC layer, which is provided on the second surface; a step for forming a first insulating film and a second insulating film on the SiC layer, the first insulating film and second insulating film being spaced a third width apart in a first direction parallel to the second surface; a step for removing a first portion, which extends in a second direction parallel to the second surface and crossing the first direction, and a second portion, which is provided on the first portion and extends in the second direction, of the SiC layer below the space between the first insulating film and the second insulating film, thereby forming a second groove which has a second width narrower than the third width in the first direction, extends in the second direction, and cuts the single crystal SiC layer and the SiC layer, and in which the polycrystalline SiC substrate is exposed at the bottom; and a step for forming, through dicing, a first groove which is provided below the second groove, has a first width narrower than the second width in the first direction, extends in the second direction, and cuts the polycrystalline SiC substrate.

Description

Semiconductor device manufacturing method

[0001] FIELD An embodiment of the present invention relates to a method for manufacturing a semiconductor device.

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has approximately three times the band gap, ten times the breakdown field strength, and three times the thermal conductivity. Therefore, the use of SiC can realize semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] Japanese Patent Application Laid-Open No. 2017-034255

[0004] The problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device with improved yield.

[0005] A method for manufacturing a semiconductor device according to an embodiment includes the steps of: forming a SiC layer on the single-crystal SiC layer of a polycrystalline SiC substrate having a first surface and a second surface; and forming, on the SiC layer, first and second insulating films spaced apart from each other by a third width in a first direction parallel to the second surface; and forming, below the first and second insulating films, a first portion of the single-crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction. and a second portion of the SiC layer provided on the first portion and extending in the second direction, thereby forming a second groove having a second width in the first direction narrower than the third width, extending in the second direction, cutting the single-crystal SiC layer and the SiC layer, and exposing the polycrystalline SiC substrate at its bottom; and a dicing process to form a first groove provided below the second groove, having a first width in the first direction narrower than the second width, extending in the second direction, and cutting the polycrystalline SiC substrate.

[0006] According to the present invention, it is possible to provide a method for manufacturing a semiconductor device with improved yield.

[0007] 1. A schematic cross-sectional view of a substrate of the first embodiment. 2. A schematic cross-sectional view showing a manufacturing process of a semiconductor device of the first embodiment. 3. A schematic cross-sectional view showing a manufacturing process of a semiconductor device of the first embodiment. 4. A schematic cross-sectional view showing a manufacturing process of a semiconductor device of the first embodiment. 5. A schematic cross-sectional view showing a manufacturing process of a semiconductor device of the first embodiment. 6. A schematic cross-sectional view showing a manufacturing process of a semiconductor device of the first embodiment. 7. A schematic cross-sectional view showing a manufacturing process of a semiconductor device of the first embodiment. 8. A schematic cross-sectional view showing a manufacturing process of a semiconductor device of the first embodiment. 9. A flowchart showing a manufacturing process of a semiconductor device of the first embodiment. 10. A schematic cross-sectional view showing a manufacturing process of a semiconductor device of the second embodiment. 11. A schematic cross-sectional view showing a manufacturing process of a semiconductor device of the second embodiment. 12. A schematic cross-sectional view showing a manufacturing process of a semiconductor device of the second embodiment. 13. A flowchart showing a manufacturing process of a semiconductor device of the second embodiment. 14. A schematic diagram of a predetermined layer of the third embodiment. 15. A schematic diagram of a predetermined layer of a comparative embodiment of the third embodiment. 16. A schematic diagram of a predetermined layer of a comparative embodiment of the third embodiment.

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same components will be denoted by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0009] In the following description, n ＋ , n, n － and p ＋ , p, p － When the notations are used, these notations represent the relative levels of impurity concentration in each conductivity type. ＋ has a relatively higher n-type impurity concentration than n, － indicates that the n-type impurity concentration is relatively lower than that of n. ＋ has a relatively higher p-type impurity concentration than p － indicates that the p-type impurity concentration is relatively lower than that of p. ＋ type, n － The type is simply n-type, p ＋ type, p － The type may also be simply referred to as p-type.

[0010] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained, for example, by SCM (Scanning Capacitance Microscopy). The distance, such as the depth of the impurity region, can be determined, for example, by SIMS. The distance, such as the width and depth of the impurity region, can also be determined, for example, from an SCM image.

[0011] Hereinafter, the first conductivity type will be referred to as n-type, and the second conductivity type will be referred to as p-type.

[0012] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing will be described as "up" and the downward direction of the drawing will be described as "down." In this specification, the concepts of "up" and "down" do not necessarily refer to the direction of gravity.

[0013] (First embodiment) a first insulating film and a second insulating film spaced apart from each other by a third width in a first direction parallel to the second surface; a second insulating film and a first portion of the single-crystal SiC layer below the first insulating film and extending in a second direction parallel to the second surface and intersecting the first direction; and a second portion of the SiC layer below the first insulating film and extending in the second direction, the second portion being located on the first insulating film and extending in the second direction, thereby forming a second groove having a second width in the first direction narrower than the third width and extending in the second direction, cutting the single-crystal SiC layer and the SiC layer; and a first groove, by dicing, located below the second groove, having a first width in the first direction narrower than the second width and extending in the second direction, cutting the polycrystalline SiC substrate.

[0014] 1 to 8 are schematic cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment, and Fig. 9 is a flowchart showing the manufacturing process of the semiconductor device of this embodiment.

[0015] The semiconductor device 100 of this embodiment is a semiconductor chip. The semiconductor device 100 of this embodiment is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, the semiconductor device 100 is not limited to this and may be, for example, a PIN diode or the like.

[0016] First, a substrate 4 as shown in FIG. 1 is prepared.

[0017] The substrate 4 includes a polycrystalline SiC substrate 2 and a single-crystal SiC layer 6 .

[0018] The polycrystalline SiC substrate 2 has a first surface 1 and a second surface 3. The second surface 3 is provided on the opposite side of the first surface 1.

[0019] Here, the X direction, the Y direction perpendicular to the X direction, and the Z direction perpendicular to the X and Y directions are defined. The first surface 1 and the second surface 3 are arranged parallel to the XY plane. The X direction is an example of a first direction. The Y direction is an example of a second direction. The -X direction is an example of a third direction.

[0020] The thickness of the polycrystalline SiC substrate 2 in the Z direction is, for example, about 350 μm.

[0021] The single-crystal SiC layer 6 is provided on the second surface 3 of the polycrystalline SiC substrate 2. The thickness of the single-crystal SiC layer 6 in the Z direction is, for example, not less than 0.4 μm and not more than 0.7 μm.

[0022] The substrate 4 is, for example, a substrate in which a single-crystal SiC layer 6 is bonded to a polycrystalline SiC substrate 2 .

[0023] Voids (vacancies) V may be formed between the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6. The voids (vacancies) V are thought to be formed, for example, when the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6 are not properly bonded together. In Fig. 2 and subsequent figures, the voids (vacancies) V between the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6 are not shown.

[0024] Next, a SiC layer 10 is formed on the single-crystal SiC layer 6 by epitaxial growth using, for example, a CVD (Chemical Vapor Deposition) method (S102 in FIGS. 2 and 9). The SiC layer 10 is an epitaxial SiC layer. Note that, as shown in FIG. 2, a portion of the SiC layer 10 may be formed directly on the polycrystalline SiC substrate 2.

[0025] Next, the device structure of the semiconductor device 100 is formed on the SiC layer 10. For example, conductive films 20, 22, 24, and 26 are formed. For example, if the semiconductor device 100 is a MOSFET, the conductive films 20, 22, 24, and 26 are source electrodes of the MOSFET. The conductive films 20, 22, 24, and 26 contain a conductive material such as Al (aluminum), Au (gold), Ag (silver), or Cu (copper).

[0026] Next, insulating films 30 and 40 are formed on the SiC layer 10 such that the conductive film 20 is provided between the insulating films 30 and 40. Furthermore, insulating films 32 and 42 are formed on the SiC layer 10 such that the conductive film 22 is provided between the insulating films 32 and 42. Furthermore, insulating films 34 and 44 are formed on the SiC layer 10 such that the conductive film 24 is provided between the insulating films 34 and 44. Furthermore, insulating films 36 and 46 are formed on the SiC layer 10 such that the conductive film 26 is provided between the insulating films 36 and 46. The insulating films 30, 32, 34, 36, 40, 42, 44, and 46 are, for example, interlayer insulating films of the semiconductor device 100. The insulating films 30, 32, 34, 36, 40, 42, 44, and 46 include, for example, an insulating material such as polyimide (S104 in FIGS. 3 and 9 ).

[0027] 7 , which will be described later, one semiconductor device 100 includes, for example, a conductive film 20, an insulating film 30, and an insulating film 40. Also, for example, one semiconductor device 100 includes a conductive film 22, an insulating film 32, and an insulating film 42. Also, for example, one semiconductor device 100 includes a conductive film 24, an insulating film 34, and an insulating film 44. Also, for example, one semiconductor device 100 includes a conductive film 26, an insulating film 36, and an insulating film 46.

[0028] The insulating film 40 (an example of a first insulating film) and the insulating film 32 (an example of a second insulating film) are spaced apart from each other by a third width in the X direction. The spaced apart portion between the insulating film 40 and the insulating film 32 is a dicing line 52. The insulating film 42 (an example of a first insulating film) and the insulating film 34 (an example of a second insulating film) are spaced apart from each other by the third width in the X direction. The spaced apart portion between the insulating film 42 and the insulating film 34 is a dicing line 54. The insulating film 44 (an example of a first insulating film) and the insulating film 36 (an example of a second insulating film) are spaced apart from each other by the third width in the X direction. The spaced apart portion between the insulating film 44 and the insulating film 36 is a dicing line 56. A dicing line 50 is provided on the −X direction side of the insulating film 30. A dicing line 58 is provided on the +X direction side of the insulating film 46. The third width is illustrated as "W3" in FIG. 8 , which will be described later.

[0029] Dicing lines 50, 52, 54, 56, and 58 are portions that will be diced using, for example, a blade in a later step. Dicing lines 50, 52, 54, 56, and 58 each extend in the Y direction.

[0030] Similarly, dicing lines (not shown) extending in the X direction may be provided.

[0031] Next, a photomask (mask) 60, such as a photoresist, is formed on polycrystalline SiC substrate 2, SiC layer 10, conductive film 20, conductive film 22, conductive film 24, conductive film 26, insulating film 30, insulating film 32, insulating film 34, insulating film 36, insulating film 40, insulating film 42, insulating film 44, and insulating film 46 (FIG. 4). Note that photomask 60 in the areas of dicing line 52, dicing line 54, dicing line 56, and dicing line 58 has openings parallel to the Y direction.

[0032] Next, using a photomask (mask) 60, portions of the single-crystal SiC layer 6 extending in the Y direction and portions of the SiC layer 10 extending in the Y direction below between the insulating film 40 and the insulating film 32 are removed along the dicing lines 52. The removed portions of the single-crystal SiC layer 6 extending in the Y direction are the first portions 5 of the single-crystal SiC layer 6 shown in FIG. 8 . The removed portions of the SiC layer 10 extending in the Y direction are the second portions 7 of the SiC layer 10 shown in FIG. 8 . This forms second grooves 72 that cut the single-crystal SiC layer 6 and the SiC layer 10 ( S106 in FIGS. 5 and 9 ). The width of the second grooves 72 is a second width. The second width is narrower than the third width. The second width is illustrated as "W2" in FIG. 8 .

[0033] Similarly, a second groove 74 is formed along the dicing line 54 below the gap between the insulating film 42 and the insulating film 34. A second groove 76 is formed along the dicing line 56 below the gap between the insulating film 44 and the insulating film 36. A second groove 78 is formed along the dicing line 58. A second groove 70 is also formed.

[0034] Here, the second grooves 70, 72, 74, 76, and 78 are formed by, for example, SF ６ This is performed by reactive ion etching (RIE) using a fluorine-based gas such as sulfur hexafluoride (SF). ６ The fluorine-based gases such as those mentioned above may be diluted with Ar (argon) or the like.

[0035] Here, it is preferable that polycrystalline SiC substrate 2 is exposed at the bottoms of second groove 70 , second groove 72 , second groove 74 , second groove 76 and second groove 78 .

[0036] The second grooves 70, 72, 74, 76, and 78 may be formed by plasma dicing, wet etching, chemical dry etching (CDE), or the like.

[0037] Next, the photomask 60 is removed (FIG. 6).

[0038] Next, a first groove 82 is formed by dicing using, for example, a blade B. The first groove 82 is provided below the second groove 72, has a first width narrower than the second width in the X direction, extends in the Y direction, and cuts the polycrystalline SiC substrate 2. Similarly, the first groove 80 is formed below the second groove 70. Similarly, the first groove 84 is formed below the second groove 74. Note that first grooves (not shown) are also formed below the second grooves 76 and 78 (S108 in FIGS. 7 and 9). Note that the first groove 82 may be formed by laser dicing or plasma dicing. The first width is illustrated as "W1" in FIG. 8.

[0039] Here, the first surface 1 of the polycrystalline SiC substrate 2 is attached to, for example, a dicing tape S.

[0040] The respective portions separated by the first grooves are peeled off from the dicing tape S to obtain the semiconductor device 100 of this embodiment.

[0041] FIG. 8 is an enlarged schematic cross-sectional view of the first groove 82 and the second groove 72.

[0042] The width of the first groove 82 in the X direction is a first width W1. The width of the second groove 72 in the X direction is a second width W2. In the X direction, the insulating film 40 and the insulating film 32 are spaced apart by a third width W3.

[0043] The second width W2 is preferably larger than the first width W1 by a width W1b in the X direction and a width W1a in the -X direction. Here, the width W1b and the width W1a are preferably each 10 μm or more and 25 μm or less. Therefore, the second width W2 is preferably larger than the first width W1 by a width W1b in the X direction and a width W1a in the -X direction.

[0044] The third width W3 is preferably larger than the second width W2 by a width W2b in the X direction and a width W2a in the −X direction. Here, the widths W2a and W2b are preferably 5 μm or more and 10 μm or less, respectively. Therefore, the third width W3 is preferably larger than the second width W2 by 5 μm or more and 10 μm or less in both the X direction and the −X direction.

[0045] Next, the effects of this embodiment will be described.

[0046] It is difficult to manufacture a high-quality single-crystal SiC substrate. Therefore, it is conceivable to manufacture a bonded substrate by thermally delaminating a SiC single-crystal base material onto a polycrystalline SiC substrate 2 to form a thin plate, and then bonding a single-crystal SiC layer to the polycrystalline SiC substrate 2.

[0047] However, there is a problem in that voids (vacancies) are formed between the polycrystalline SiC substrate 2 and the single-crystal SiC layer 6 .

[0048] When such a bonded substrate is diced, there is a problem that chipping or peeling occurs in the single crystal SiC layer.

[0049] In areas where voids (vacancies) are formed between the polycrystalline SiC substrate 2 and the single-crystal SiC layer, for example, the single-crystal SiC layer is floating above the polycrystalline SiC substrate 2. Furthermore, in areas where voids (vacancies) are formed between the polycrystalline SiC substrate 2 and the single-crystal SiC layer, the single-crystal SiC layer and the polycrystalline SiC substrate 2 are partially bonded over a very small area. When cutting such void areas, the single-crystal SiC layer, which is relatively thinner than the polycrystalline SiC substrate 2, is peeled off due to contact with the blade or frictional force, resulting in chipping or peeling. Such chipping or peeling can cause deterioration in the electrical characteristics and reliability of the semiconductor device. Similar chipping and peeling can also occur when laser dicing or plasma dicing is performed.

[0050] Furthermore, such a bonded substrate may have a laminated substrate structure with different crystal structures, which can cause a problem of substrate warpage due to a difference in stress between the polycrystalline SiC substrate 2 and the single-crystal SiC layer, or distortion at the bonding interface between the polycrystalline SiC substrate 2 and the single-crystal SiC layer.

[0051] Therefore, the method for manufacturing a semiconductor device according to the present embodiment includes the steps of: forming a SiC layer on the single-crystal SiC layer of the substrate having a polycrystalline SiC substrate having a first surface and a second surface; forming a first insulating film and a second insulating film spaced apart from each other by a third width in a first direction parallel to the second surface on the SiC layer; removing, below the first insulating film and the second insulating film, a first portion of the single-crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, thereby forming a second groove having a second width in the first direction narrower than the third width and extending in the second direction, cutting the single-crystal SiC layer and the SiC layer; and forming, by dicing, a first groove provided below the second groove, having a first width in the first direction narrower than the second width, extending in the second direction, and cutting the polycrystalline SiC substrate.

[0052] According to the semiconductor device manufacturing method of this embodiment, before dicing, second grooves are formed to cut the single crystal SiC layer 6 and the SiC layer 10. This makes it possible to suppress chipping and peeling of the single crystal SiC layer 6 and the SiC layer 10, which occurs when the first grooves are formed by dicing. Therefore, according to the semiconductor device manufacturing method of this embodiment, it is possible to provide a semiconductor device manufacturing method with improved yield.

[0053] Furthermore, since the single crystal SiC layer and the SiC layer are divided into small areas during the manufacturing process, the above-mentioned substrate warpage can be suppressed.

[0054] The second width W2 is preferably 10 μm or more and 25 μm or less in both the X and −X directions than the first width W1. The widths W1a and W1b (FIG. 8) are preferably larger than the kerf deviation width, which is caused by a combination of factors such as the mechanical precision of the dicing device, the specifications of the blade B (blade thickness and strength), and the cutting speed of the dicing device. This kerf deviation width is approximately 10 μm in both the X and −X directions. Therefore, the second width W2 is preferably 10 μm or more larger than the first width W1 in both the X and −X directions. On the other hand, if the difference between the second width W2 and the first width W1 in the X and −X directions is greater than 25 μm, the number of semiconductor chips that can be obtained is reduced, which is undesirable.

[0055] The third width W3 is preferably 5 μm or more and 10 μm or less in both the X direction and the −X direction than the second width W2. During dry etching, the SiC layer below the insulating film may be etched back and the insulating film may protrude like an overhang. To prevent this, the third width W3 is preferably 5 μm or more larger than the second width W2 in both the X direction and the −X direction. On the other hand, it is sufficient for the third width W3 to be 10 μm larger than the second width W2.

[0056] It is preferable that the polycrystalline SiC substrate 2 is exposed at the bottom of the second groove 70, the second groove 72, the second groove 74, the second groove 76, and the second groove 78. In other words, it is preferable that a part of the second groove is formed so as to extend into the polycrystalline SiC substrate 2.

[0057] For example, a case where the first groove is formed by dicing using a blade will be described. When the blade comes into contact with the void V and the polycrystalline SiC substrate 2 is further cut, the polycrystalline SiC substrate 2 may not be cut smoothly. For example, it is presumed that this is because the gas in the void V applies some kind of unintended pressure to the surrounding polycrystalline SiC substrate 2, single-crystal SiC layer 6, and SiC layer 10. If a portion of the second groove is formed so as to penetrate into the polycrystalline SiC substrate 2, it is possible to reliably avoid contact between the blade and the SiC layer 10, single-crystal SiC layer 6, and void V during dicing to form the first groove.

[0058] According to the method for manufacturing a semiconductor device of this embodiment, it is possible to provide a method for manufacturing a semiconductor device with improved yield.

[0059] Second Embodiment A method for manufacturing a semiconductor device according to the present embodiment includes the steps of: forming a SiC layer on the single-crystal SiC layer of a substrate having a polycrystalline SiC substrate having a second surface; and forming, on the SiC layer, third and fourth insulating films each containing an oxide and spaced apart from each other by a second width in a first direction parallel to the second surface; and forming, below the third and fourth insulating films, a first portion of the single-crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction; and forming, on the first portion of the single-crystal SiC layer and below the second direction, a second portion of the SiC layer extending in the second direction and disposed on the first portion. and forming a second groove having a second width in the first direction, extending in the second direction, and cutting the single-crystal SiC layer and the SiC layer by removing the third insulating film and the fourth insulating film; forming a first insulating film and a second insulating film on the SiC layer, the first insulating film and the second insulating film being spaced apart in the first direction by a third width larger than the second width and sandwiching the second groove; and forming a first groove by dicing, the first groove being provided below the second groove, having a first width in the first direction narrower than the second width, extending in the second direction, and cutting the polycrystalline SiC substrate.

[0060] Here, the description of the contents that overlap with the first embodiment will be omitted.

[0061] 10 to 13 are schematic cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment, and Fig. 14 is a flowchart showing the manufacturing process of the semiconductor device of this embodiment.

[0062] As in the first embodiment, the SiC layer 10 is formed on the single-crystal SiC layer 6 by epitaxial growth using, for example, a CVD (Chemical Vapor Deposition) method (S202 in FIG. 14).

[0063] Next, an insulating film 62 containing an oxide, an insulating film 63 containing an oxide (an example of a third insulating film), an insulating film 64 containing an oxide (an example of a fourth insulating film), an insulating film 65 containing an oxide, an insulating film 66 containing an oxide, and an insulating film 67 containing an oxide are formed on the SiC layer 10. The insulating films 62 and 63 are spaced apart from each other by a second width in the X direction. The insulating films 63 and 64 are spaced apart from each other by a second width in the X direction. The insulating films 64 and 65 are spaced apart from each other by a second width in the X direction. The insulating films 65 and 66 are spaced apart from each other by a second width in the X direction. The insulating films 66 and 67 are spaced apart from each other by the second width in the X direction (S204 in FIGS. 10 and 14 ).

[0064] The spaced apart portion between insulating films 62 and 63 is a dicing line 50. The spaced apart portion between insulating films 63 and 64 is a dicing line 52. The spaced apart portion between insulating films 64 and 65 is a dicing line 54. The spaced apart portion between insulating films 65 and 66 is a dicing line 56. The spaced apart portion between insulating films 66 and 67 is a dicing line 58.

[0065] Next, using insulating films 62, 63, 64, 65, 66, and 67 as masks, second grooves 70 are formed in dicing line 50, second grooves 72 in dicing line 52, second grooves 74 in dicing line 54, second grooves 76 in dicing line 56, and second grooves 78 in dicing line 58 (S206 in Figures 11 and 14).

[0066] Here, the insulating films 62, 63, 64, 65, 66, and 67 contain, for example, an oxide. The insulating films 62, 63, 64, 65, 66, and 67 contain, for example, silicon oxide.

[0067] Next, the insulating films 62, 63, 64, 65, 66 and 67 are removed (S208 of S14).

[0068] Next, the device structure of the semiconductor device 100 is formed on the SiC layer 10. For example, conductive films 20, 22, 24, and 26 are formed. Next, insulating films 30 and 40 are formed on the SiC layer 10 such that the conductive film 20 is provided between the insulating films 30 and 40. Furthermore, insulating films 32 and 42 are formed on the SiC layer 10 such that the conductive film 22 is provided between the insulating films 32 and 42. Furthermore, insulating films 34 and 44 are formed on the SiC layer 10 such that the conductive film 24 is provided between the insulating films 34 and 44. Furthermore, insulating films 36 and 46 are formed on the SiC layer 10 such that the conductive film 26 is provided between the insulating films 36 and 46.

[0069] Here, the insulating film 40 (an example of a first insulating film) and the insulating film 32 (an example of a second insulating film) are spaced apart from each other by a third width in the X direction. The insulating film 42 (an example of a first insulating film) and the insulating film 34 (an example of a second insulating film) are spaced apart from each other by the third width in the X direction. The insulating film 44 (an example of a first insulating film) and the insulating film 36 (an example of a second insulating film) are spaced apart from each other by the third width in the X direction (S210 in FIGS. 12 and 14 ).

[0070] Next, a first groove 82 is formed by dicing using, for example, a blade B. The first groove 82 is provided below the second groove 72, has a first width narrower than the second width in the X direction, extends in the Y direction, and cuts the polycrystalline SiC substrate 2. Similarly, a first groove 80 is formed below the second groove 70. Similarly, a first groove 84 is formed below the second groove 74. Note that first grooves (not shown) are also formed below the second grooves 76 and 78 (S212 in FIGS. 13 and 14 ).

[0071] Here, the first surface 1 of the polycrystalline SiC substrate 2 is attached to, for example, a dicing tape S.

[0072] The respective portions separated by the first grooves are peeled off from the dicing tape S to obtain the semiconductor device 100 of this embodiment.

[0073] For example, there may be a case where it is required to ensure the resistance of a photomask during dry etching because the SiC layer 10 is thick. In such a case, a manufacturing method using the insulating films 62, 63, 64, 65, 66, and 67 as masks, as in the manufacturing method of the semiconductor device of this embodiment, is suitable.

[0074] According to the method for manufacturing a semiconductor device of this embodiment, it is possible to provide a method for manufacturing a semiconductor device with improved yield.

[0075] Third Embodiment The method for manufacturing a semiconductor device according to this embodiment differs from the methods for manufacturing a semiconductor device according to the first and second embodiments in that, in the step of forming the second trench, a predetermined layer is formed in the second trench, the predetermined layer having a third portion that is a part of the first portion, and a fourth portion that is provided on the third portion and is a part of the second portion. Here, a description of the content that overlaps with the first and second embodiments will be omitted.

[0076] 15A and 15B are schematic top views showing the manufacturing process of the semiconductor device of this embodiment. The schematic cross-sectional view shown in FIG. 6 corresponds to, for example, the cross-section AA' in FIG.

[0077] 16A-B are schematic diagrams of the predetermined layer 102 of this embodiment. Fig. 16A is a schematic top view of the predetermined layer 102 of this embodiment. Fig. 16B is a schematic cross-sectional view of the predetermined layer 102 of this embodiment taken along the line BB' of Fig. 16A.

[0078] In the process of forming second grooves 70, 72, 74, 76, and 78, a predetermined layer 102 is formed in each of the second grooves. Here, in the process of forming the second grooves, the portion of the single-crystal SiC layer 6 extending in the Y direction that is removed is the first portion 5 of the single-crystal SiC layer 6 ( FIG. 8 ). In the process of forming the second grooves, the portion of the SiC layer 10 extending in the Y direction that is removed is the second portion 7 of the SiC layer 10 ( FIG. 8 ). The predetermined layer 102 includes a third portion 9 that is a portion of the first portion 5 that is not removed but remains in the second grooves, and a fourth portion 11 that is a portion of the second portion that is not removed but remains in the second grooves. The fourth portion 11 is provided on the third portion 9.

[0079] In addition, when a portion of the second groove 70, the second groove 72, the second groove 74, the second groove 76, and the second groove 78 are each formed in the polycrystalline SiC substrate 2, a portion of the polycrystalline SiC substrate 2 around the specified layer 102 is also removed.

[0080] 16A , the shape of the predetermined layer 102 when viewed from above is a cross shape. However, the shape of the predetermined layer 102 when viewed from above is not limited to a cross shape. For example, the shape of the predetermined layer 102 when viewed from above may be a rectangle.

[0081] In the dicing device, a camera photographs the pattern arranged on the dicing line and performs an alignment operation (alignment) of the substrate 4. The predetermined layer 102 is used as a reference (alignment mark) for aligning the substrate 4.

[0082] Figure 17 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device of a comparative embodiment of this embodiment. Figures 18A-B are schematic views of a predetermined layer 1002 of a comparative embodiment of this embodiment. Figure 18A is a schematic top view of the predetermined layer 1002 of the comparative embodiment. Figure 18B is a schematic cross-sectional view of the predetermined layer 1002 of the comparative embodiment at the AA' cross section of Figure 18A.

[0083] The predetermined layer 1002 has a metal layer 1004 provided on the single-crystal SiC layer 6 and the SiC layer 10. Here, the metal layer 1004 contains a metal material such as Al (aluminum). The metal layer 1004 corresponds to, for example, the conductive film 20 shown in the first and second embodiments. The single-crystal SiC layer 6 and the SiC layer 10 around the metal layer 1004 are not removed by dry etching or the like.

[0084] The metal layer 1004 of the comparative example contains a conductive material such as Al, similar to the conductive film 20. In this case, the surface may become rough or the shape may change due to the influence of manufacturing processes after formation, such as sintering heat treatment, the developer used in photolithography, or the chemicals used to strip the photoresist. If the surface roughness causes diffuse reflection of light or the shape differs from the predetermined shape, there is a problem of reduced alignment accuracy.

[0085] In the method for manufacturing a semiconductor device according to this embodiment, a predetermined layer 102 including a single-crystal SiC layer 6 and a portion of the SiC layer 10 is formed. Therefore, the number of manufacturing steps can be reduced compared to when a predetermined layer 1002 including a metal layer is formed, as in the comparative example. Furthermore, since the predetermined layer 102 is formed from SiC, it is less susceptible to the effects of process steps compared to a predetermined layer 1002 including a metal material. Therefore, the alignment of the substrate 4 can be performed more effectively.

[0086] According to the method for manufacturing a semiconductor device of this embodiment, it is possible to provide a method for manufacturing a semiconductor device with improved yield.

[0087] Although several embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0088] The above embodiments can be summarized as the following technical proposals: (Technical proposal 1) A substrate including a polycrystalline SiC substrate having a first surface and a second surface, and a single-crystal SiC layer provided on the second surface, forming a SiC layer on the single-crystal SiC layer, forming a first insulating film and a second insulating film on the SiC layer, the first insulating film and the second insulating film being spaced apart from each other by a third width in a first direction parallel to the second surface, and removing, below the first insulating film and the second insulating film, a first portion of the single-crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, to cut the single-crystal SiC layer and the SiC layer, thereby forming a second groove having a second width narrower than the third width in the first direction and extending in the second direction, with the polycrystalline SiC substrate exposed at the bottom. forming, by dicing, a first groove that is provided below the second groove, has a first width that is narrower than the second width in the first direction, extends in the second direction, and cuts the polycrystalline SiC substrate.(Technical Solution 2) A process for forming a SiC layer on the single crystal SiC layer of a substrate having a polycrystalline SiC substrate having a first surface and a second surface, and a single crystal SiC layer provided on the second surface; A process for forming a third insulating film and a fourth insulating film containing an oxide on the SiC layer, the third insulating film and the fourth insulating film being spaced apart from each other by a second width in a first direction parallel to the second surface; A process for forming a second groove having the second width in the first direction and extending in the second direction, cutting the single crystal SiC layer and the SiC layer, by removing a first portion of the single crystal SiC layer that is parallel to the second surface and extends in a second direction that intersects the first direction, and a second portion of the SiC layer that is provided on the first portion and extends in the second direction, below the third insulating film and the fourth insulating film; A process for removing the third insulating film and the fourth insulating film; A process for forming a first insulating film and a second insulating film on the SiC layer that are spaced apart from each other by a third width that is greater than the second width in the first direction, the second groove being provided on either side of the second groove, forming, by dicing, a first groove provided below the second groove, the first groove having a first width narrower than the second width in the first direction, extending in the second direction, and cutting the polycrystalline SiC substrate. (Technical Proposal 3) The method for manufacturing a semiconductor device according to Technical Proposal 1 or Technical Proposal 2, wherein the second width is greater than the first width by 10 μm or more and 25 μm or less in both the first direction and a third direction opposite to the first direction. (Technical Proposal 4) The method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 3, wherein the third width is greater than the second width by 5 μm or more and 10 μm or less in both the first direction and a third direction opposite to the first direction. (Technical Proposal 5) The method for manufacturing a semiconductor device according to any one of Technical Proposals 1, 3, or 4, wherein the second groove is formed by dry etching using photoresist provided on the first insulating film and the second insulating film as a mask. (Technical proposal 6) A method for manufacturing a semiconductor device described in any one of Technical proposals 1 to 5, wherein in the step of forming the second groove, a predetermined layer is formed in the second groove, the predetermined layer having: a third portion that is part of the first portion; and a fourth portion that is provided on the third portion and is part of the second portion.

[0089] REFERENCE SIGNS LIST 1 First surface 2 Polycrystalline SiC substrate 3 Second surface 4 Substrate 6 Single crystal SiC layer 7 Third portion 10 SiC layer 11 Fourth portion 20 Conductive film 22 Conductive film 24 Conductive film 26 Conductive film 30 Insulating film 32 Insulating film 34 Insulating film 36 Insulating film 40 Insulating film 42 Insulating film 44 Insulating film 46 Insulating film 50 Dicing line 52 Dicing line 54 Dicing line 56 Dicing line 58 Dicing line 60 Photomask 62 Insulating film 63 Insulating film 64 Insulating film 65 Insulating film 66 Insulating film 67 Insulating film 70 Second groove 72 Second groove 74 Second groove 76 Second groove 78 Second groove 80 First groove 82 First groove 84 First groove 100 Semiconductor device 102 Predetermined layer 1002: Predetermined layer B: Blade S: Dicing tape V: Void W1: First width W2: Second width W3: Third width

Claims

1. A method for manufacturing a substrate comprising: a polycrystalline SiC substrate having a first surface and a second surface; and a single crystal SiC layer provided on the second surface, the steps of: forming a SiC layer on the single crystal SiC layer of the substrate; forming a first insulating film and a second insulating film on the SiC layer, the first insulating film and the second insulating film being spaced apart from each other by a third width in a first direction parallel to the second surface; and removing a first portion of the single crystal SiC layer below the first insulating film and the second insulating film, the first portion extending in a second direction parallel to the second surface and intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, to form a second groove having a second width narrower than the third width in the first direction, extending in the second direction, and cutting the single crystal SiC layer and the SiC layer, the second groove having a bottom at which the polycrystalline SiC substrate is exposed. forming, by dicing, a first groove provided below the second groove, having a first width narrower than the second width in the first direction, extending in the second direction, and cutting the polycrystalline SiC substrate.

2. A method for manufacturing a polycrystalline SiC substrate having a first surface and a second surface, and a single crystal SiC layer provided on the second surface, comprising the steps of: forming a SiC layer on the single crystal SiC layer of the substrate; forming a third insulating film and a fourth insulating film containing an oxide on the SiC layer, the third insulating film and the fourth insulating film being spaced apart from each other by a second width in a first direction parallel to the second surface; removing a first portion of the single crystal SiC layer extending in a second direction parallel to the second surface and intersecting the first direction, and a second portion of the SiC layer provided on the first portion and extending in the second direction, to form a second groove having the second width in the first direction and extending in the second direction, cutting the single crystal SiC layer and the SiC layer; removing the third insulating film and the fourth insulating film; and forming a first insulating film and a second insulating film on the SiC layer, the first insulating film and the second insulating film being spaced apart from each other by a third width greater than the second width in the first direction, the second groove being provided on either side of the first insulating film. forming, by dicing, a first groove provided below the second groove, having a first width narrower than the second width in the first direction, extending in the second direction, and cutting the polycrystalline SiC substrate.

3. A method for manufacturing a semiconductor device according to claim 1 or 2, wherein the second width is greater than the first width by 10 μm or more and 25 μm or less in both the first direction and a third direction opposite to the first direction.

4. A method for manufacturing a semiconductor device according to claim 1 or 2, wherein the third width is greater than the second width by 5 μm or more and 10 μm or less in both the first direction and in a third direction opposite to the first direction.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the second groove is formed by dry etching using a photoresist provided on the first insulating film and the second insulating film as a mask.

6. A method for manufacturing a semiconductor device as claimed in claim 1 or claim 2, wherein in the step of forming the second groove, a predetermined layer is formed in the second groove, the predetermined layer having: a third portion which is part of the first portion; and a fourth portion which is provided on the third portion and is part of the second portion.

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