Semiconductor device

Abstract

A semiconductor device according to the present invention includes a transistor part and a diode part. The transistor part includes a first gate trench part provided closest to the diode part, and a first mesa part that is in contact with the first gate trench part and is provided between the first gate trench part and the diode part. A first floating region is provided below the first gate trench part, and the first mesa part has a non-covering region that does not overlap the first floating region.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Conventionally, semiconductor devices provided with transistors such as insulated gate bipolar transistors (IGBTs) have been known (see, for example, Patent Documents 1 to 4). [Prior art documents] [Patent Document 1] Japanese Patent No. 6472714 [Patent Document 2] Japanese Patent No. 4456013 [Patent Document 3] Japanese Patent Laid-Open No. 2020-21941 [Patent Document 4] Japanese Patent Laid-Open No. 2010-232627 General disclosure

[0003] (Problem to be Solved) In a semiconductor device, it is preferable to suppress the snapback phenomenon.

[0004] In order to solve the above problem, one aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface and a first conductivity type drift region. Any of the above semiconductor devices may include one or more transistor units having a second conductivity type collector region provided on the lower surface of the semiconductor substrate. Any of the above semiconductor devices may include one or more diode units having a first conductivity type cathode region provided on the lower surface of the semiconductor substrate and arranged alternately with the transistor units in a first direction. In any of the above semiconductor devices, each of the transistor units may include a plurality of trench units, including one or more gate trench units, arranged side by side in the first direction. In any of the above semiconductor devices, each of the transistor units may include a plurality of mesa units, which are regions sandwiched between the trench units in the first direction. In any of the above semiconductor devices, each of the transistor units may include a second conductivity type floating region provided for at least one of the gate trench units and below a lower end of the gate trench unit. In any of the above semiconductor devices, the one or more gate trench portions may include a first gate trench portion provided closest to the diode portion. In any of the above semiconductor devices, the multiple mesa portions may include a first mesa portion in contact with the first gate trench portion and provided between the first gate trench portion and the diode portion. In any of the above semiconductor devices, a first floating region may be provided below the first gate trench portion. In any of the above semiconductor devices, the first mesa portion may have an uncovered region that does not overlap with the first floating region.

[0005] In any of the above semiconductor devices, the plurality of trenches may include one or more dummy trenches. In any of the above semiconductor devices, the first mesa may be sandwiched between the first gate trench and a first dummy trench. In any of the above semiconductor devices, the first floating region provided below the lower end of the first gate trench may not extend below the lower end of the first dummy trench.

[0006] In any of the above semiconductor devices, the first floating region may not be in contact with the first dummy trench portion in a top view.

[0007] In any of the above semiconductor devices, the plurality of trenches may include a second dummy trench located on an opposite side of the first gate trench from the first dummy trench. In any of the above semiconductor devices, the distance between the first floating region and the second dummy trench in the first direction may be smaller than the distance between the first floating region and the first dummy trench.

[0008] In any of the above semiconductor devices, the first floating region may be in contact with the second dummy trench portion in a top view.

[0009] In any of the above semiconductor devices, the first mesa may have an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the first mesa may have a base region of a second conductivity type provided between the emitter region and the drift region. In any of the above semiconductor devices, the first mesa may have a longitudinal length in a second direction. In any of the above semiconductor devices, the first mesa may have the uncovered region in an intermediate region between both ends of the emitter region in the second direction.

[0010] In any of the semiconductor devices described above, a plurality of the uncovered regions may be arranged discretely in the second direction in the intermediate region.

[0011] In the intermediate region of any of the above semiconductor devices, the sum of the lengths of the multiple uncovered regions in the second direction may be smaller than the sum of the lengths of the regions overlapping with the first floating region in the second direction.

[0012] In any of the above semiconductor devices, the first mesa portion may have contact regions of a second conductivity type provided in contact with the upper surface of the semiconductor substrate and arranged alternately with the emitter regions in the second direction. In any of the above semiconductor devices, the first floating region may be arranged below at least one of the emitter regions, and at least a portion of the contact region may be the uncovered region.

[0013] In any of the semiconductor devices described above, the first floating region may entirely overlap at least one of the emitter regions. In any of the semiconductor devices described above, the uncovered region may be provided for each of the contact regions.

[0014] Any of the above semiconductor devices may further include a well region of a second conductivity type that is disposed outside the first mesa portion in the second direction and has a higher concentration than the base region, and a first extension region of the second conductivity type that extends in the second direction from the well region to a position overlapping with the emitter region.

[0015] In any of the semiconductor devices described above, the well region may also be disposed outside the emitter region in the first direction. Any of the semiconductor devices described above may further include a second extension region of a second conductivity type extending in the first direction from the well region to a position overlapping with the emitter region.

[0016] In any of the semiconductor devices described above, the diode section may have a plurality of dummy trench sections arranged side by side in the first direction, and a mesa section sandwiched between the dummy trench sections in the first direction. In any of the semiconductor devices described above, the floating region may also be provided below a lower end of at least one of the dummy trench sections in the diode section.

[0017] In the diode section of any of the above semiconductor devices, the period at which the floating regions are provided in the first direction may be the same as the period at which the floating regions are provided in the first direction in the transistor section.

[0018] The transistor portion of any of the semiconductor devices described above may have a boundary region between the first gate trench portion and the diode portion, the boundary region having one or more trench portions and one or more mesa portions. In any of the semiconductor devices described above, the floating region may also be provided below a lower end of at least one of the trench portions in the boundary region.

[0019] In the boundary region of any of the above semiconductor devices, the period at which the floating regions are provided in the first direction may be the same as the period at which the floating regions are provided in the first direction in the transistor portion other than the boundary region.

[0020] In any of the above semiconductor devices, the area of ​​the uncovered region in the first mesa portion may be larger than the area of ​​the region that does not overlap with the floating region in the mesa portion that contacts the gate trench portion other than the first gate trench portion.

[0021] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions.

[0022] 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. It is an enlarged view of region D in FIG. 1. It is a diagram showing an example of an e-e cross section in FIG. 2. It is a diagram showing an example of an arrangement of floating regions 202 in a top view. It is a diagram showing another example of an arrangement of floating regions 202 in a top view. It is a diagram showing another example of an e-e cross section. It is a diagram showing another example of an e-e cross section. It is a top view showing an example of a transition region 92. It is a diagram showing an example of an f-f cross section in FIG. 8. It is an XZ cross section showing another structural example of a boundary region 90 and a diode section 80. It is a diagram showing collector voltage-collector current characteristics in an example and a reference example. It is a diagram showing the trade-off characteristics of turn-on loss and reverse recovery dV / dt in a reference example and an example.

[0023] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0024] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0025] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0026] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0027] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0028] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0029] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0030] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0031] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0032] In this specification, chemical concentration refers to the atomic density of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0033] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. ３ , or / cm ３ This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms notation may be omitted.

[0034] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects or the like.

[0035] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0036] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0037] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two pairs of end edges 162 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to either of the end edges 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0038] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted from FIG. 1 . The active portion 160 may refer to a region that overlaps with the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0039] The active section 160 is provided with a transistor section 70 including a transistor element such as an insulated gate bipolar transistor (IGBT). The active section 160 may further be provided with a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1 , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the top surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0040] In FIG. 1 , the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1 ). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0041] The diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 that extends the diode section 80 in the Y-axis direction to the gate wiring described below may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0042] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has a gate structure, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0043] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0044] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with diagonal lines.

[0045] The gate wiring in this example has a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0046] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0047] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0048] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0049] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 extends in the X axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 that sandwich the active section 160, crossing the active section 160 at approximately the center in the Y axis direction. When the active section 160 is divided by the active side gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X axis direction in each divided region.

[0050] The semiconductor device 100 may include a temperature sensing section (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting section (not shown) which simulates the operation of a transistor section provided in the active section 160.

[0051] In the present example, the semiconductor device 100 includes an edge termination structure 190 between the active section 160 and the edge 162 when viewed from above. The edge termination structure 190 in the present example is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 190 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 190 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active section 160.

[0052] 2 is an enlarged view of region D in FIG. 1 . Region D includes a transistor section 70, a diode section 80, and an active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0053] An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is not shown in FIG. 2 . In this example, a contact portion 54 is provided in the interlayer insulating film so as to penetrate the interlayer insulating film. The contact portion 54 may include a contact hole provided in the interlayer insulating film and a conductive member filled in the contact hole. In FIG. 2 , each contact portion 54 is hatched with diagonal lines.

[0054] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is connected to the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 via a contact portion 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.

[0055] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0056] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. Furthermore, the contact hole may have a plug formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0057] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active side gate wiring 131. In this example, the well region 11 is provided away from the end of the contact portion 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a doping concentration higher than that of the base region 14. In this example, the base region 14 is P- type, and the well region 11 is P+ type.

[0058] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0059] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0060] At least a portion of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0061] In the transistor section 70, the dummy trench section 30 is provided between each of the straight line sections 39 of the gate trench section 40. One or more dummy trench sections 30 may be provided between each of the straight line sections 39. The dummy trench section 30 may have a linear shape extending in the extension direction, and may have a straight line section 29 and a tip section 31, similar to the gate trench section 40.

[0062] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0063] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench.

[0064] In this example, the transistor section 70 is provided with a mesa section 60, and the diode section 80 is provided with a mesa section 61. The transistor section 70 in this example has a boundary region 90. The boundary region 90 is an end of the transistor section 70 in the X-axis direction and is in contact with the diode section 80. The boundary region 90 has a collector region 22 provided on the lower surface 23 of the semiconductor substrate 10. The boundary region 90 may include one or more trench sections. The boundary region 90 may be provided with a gate trench section 40, a dummy trench section 30, or both trench sections. The boundary region 90 is provided with a mesa section 62. In this specification, the term "mesa section" refers to each of the mesa section 60, the mesa section 61, and the mesa section 62. The mesa section 62 may have the same structure as the mesa section 61. The boundary region 90 may be a region whose structure on the upper surface 21 side is similar to that of the diode section 80 and whose structure on the lower surface 23 side is similar to that of the transistor section 70. The transistor section 70 does not need to have the boundary region 90. In this case, the mesa section 60 of the transistor section 70 and the mesa section 61 of the diode section 80 are disposed adjacent to each other at the boundary between the transistor section 70 and the diode section 80.

[0065] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active-side gate wiring 131 is referred to as the base region 14-e. While FIG. 2 shows the base region 14-e located at one end of each mesa portion in the extension direction, a base region 14-e is also located at the other end of each mesa portion. Each mesa portion may be provided with at least one of a first-conductivity-type emitter region 12 and a second-conductivity-type contact region 15 in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type with a higher concentration than the base region 14. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0066] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0067] The emitter region 12 in the mesa portion 60 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 is also provided in a region overlapping with the contact portion 54.

[0068] The contact region 15 in the mesa portion 60 is provided in a region overlapping with the contact portion 54. The contact region 15 may or may not be in contact with the gate trench portion 40. The contact region 15 may or may not be in contact with the dummy trench portion 30.

[0069] 2 , the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction. The contact region 15 in the mesa portion 60 may also be provided from one trench portion to the other trench portion in the X-axis direction. The contact region 15 does not have to be in contact with either of the two trench portions that sandwich the mesa portion 60. In this case, a base region 14 may be provided between the contact region 15 and the trench portion.

[0070] 2, the contact regions 15 and emitter regions 12 of the mesa portion 60 are alternately arranged along the extension direction (Y-axis direction) of the trench portion. In another example, the contact regions 15 and emitter regions 12 of the mesa portion 60 may be provided in stripes along the extension direction (Y-axis direction) of the trench portion. For example, the emitter regions 12 are provided in regions in contact with the trench portion, and the contact regions 15 are provided in regions sandwiched between the emitter regions 12. Alternatively, the mesa portion 60 may be provided with emitter regions 12 instead of contact regions 15. For example, the emitter regions 12 may be provided in the entire region sandwiched between the base regions 14-e in the Y-axis direction.

[0071] The mesa portion 61 of the diode portion 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15. The mesa portion 62 in the boundary region 90 of this example has a structure similar to that of the mesa portion 61.

[0072] A contact portion 54 is provided above each mesa portion. The contact portion 54 is arranged in a region sandwiched between the base regions 14-e. In this example, the contact portion 54 is provided above each of the contact region 15, the base region 14, and the emitter region 12. The contact portion 54 is not provided in a region corresponding to the base region 14-e and the well region 11. The contact portion 54 may be arranged in the center of the arrangement direction (X-axis direction) of the mesa portions 60.

[0073] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2 , the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0074] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact portion 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact portion 54.

[0075] Fig. 3 is a diagram showing an example of the e-e cross section in Fig. 2. The e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0076] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact portion 54 described with reference to FIG. 2 .

[0077] The contact portion 54 penetrates the interlayer insulating film 38. The contact portion 54 may be formed of a metal different from that of the emitter electrode 52. The contact portion 54 may contain tungsten. A barrier metal layer including at least one of a titanium film and a titanium nitride film may be provided at the bottom of the contact portion 54. The contact portion 54 may be provided up to the upper surface 21 of the semiconductor substrate 10, or may be provided up to the interior of the semiconductor substrate 10. In the example of FIG. 3 , the contact portion 54 is a contact trench provided from the upper surface 21 of the semiconductor substrate 10 to the interior of each mesa portion. This increases the contact area between the contact portion 54 and the semiconductor substrate 10. In the cross section, the lower end of the contact portion 54 of the transistor portion 70 contacts the emitter region 12. In the cross section, the lower end of the contact portion 54 of the diode portion 80 contacts the base region 14.

[0078] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is connected to the semiconductor substrate 10 via a contact portion 54. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0079] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0080] In the mesa portion 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0081] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0082] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0083] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. That is, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0084] A P-type base region 14 is provided in the mesa portion 61 of the diode section 80 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided below the base region 14 in the mesa portion 61.

[0085] A P-type base region 14 is provided in the mesa portion 62 of the boundary region 90, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided below the base region 14 in the mesa portion 62. The mesa portion 62 of this example has a structure similar to that of the mesa portion 61. In each example in this specification, the center of the trench portion in the X-axis direction may be defined as the end portion of the boundary region 90 in the X-axis direction.

[0086] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Furthermore, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0087] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be located at the same depth as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0088] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0089] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors in each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0090] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include trenches formed in the order of forming the trenches and then forming the doped regions.

[0091] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. The diode section 80 is provided with the dummy trench section 30, but is not provided with the gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0092] In this example, the boundary region 90 is provided with a dummy trench portion 30, but is not provided with a gate trench portion 40. The trench portion at the end of the boundary region 90 on the transistor portion 70 side may be the gate trench portion 40.

[0093] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0094] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0095] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0096] In this example, the gate trench 40 and the dummy trench 30 are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may have a downwardly convex curved shape (a curved shape in cross section). In this specification, the depth position of the lower end 43 of the gate trench 40 is designated Zt.

[0097] The semiconductor device 100 of this example includes a P-type floating region 202 provided below the lower end 43 of the gate trench portion 40. The lower end 43 of the gate trench portion 40 refers to the portion of the gate trench portion 40 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of FIG. 3, the lower end 43 of the gate trench portion 40 is located at the center of the gate trench portion 40 in the X-axis direction. Furthermore, the lower end 33 of the dummy trench portion 30 refers to the portion of the dummy trench portion 30 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of FIG. 3, the lower end 33 of the dummy trench portion 30 is located at the center of the dummy trench portion 30 in the X-axis direction.

[0098] At least a portion of the floating region 202 is provided at a position overlapping with the lower end 43 in a top view and is disposed below the lower end 43 in the Z-axis direction. The floating region 202 may include a portion that does not overlap with the lower end 43 in a top view. The floating region 202 may include a portion that is provided above the lower end 43. The floating region 202 may be in contact with the lower end 43 or may be separated from the lower end 43. In the example of FIG. 3 , the floating region 202 is in contact with the entire curved portion of the gate trench portion 40, including the lower end 43. The floating region 202 may be formed by implanting a P-type dopant near the lower end of the trench structure after forming the trench structure of the gate trench portion 40 and before forming the gate conductive portion 44.

[0099] The floating region 202 is electrically floating relative to an electrode such as a metal or polysilicon electrode. At least one of an N-type region and an insulating film is disposed between the floating region 202 and the electrode. In other words, the floating region 202 and the electrode are not connected by a P-type region or a conductive material. The doping concentration of the floating region 202 may be equal to or lower than the doping concentration of the base region 14, or may be higher than the doping concentration of the base region 14. In this example, the doping concentration of the floating region 202 is higher than the doping concentration of the base region 14. The doping concentration is 1×10 １５ cm －３ That's it, 1 x 10 １７ cm －３ It may be the following:

[0100] The floating region 202 is disposed apart from the base region 14. An N-type region (at least one of the accumulation region 16 and the drift region 18 in this example) is provided between the floating region 202 and the base region 14.

[0101] Each transistor portion 70 has one or more floating regions 202. Each transistor portion 70 may have multiple floating regions 202. In each transistor portion 70, a floating region 202 may be provided in at least one gate trench portion 40, a floating region 202 may be provided in 50% or more of the gate trench portions 40, a floating region 202 may be provided in 80% or more of the gate trench portions 40, or a floating region 202 may be provided in all of the gate trench portions 40.

[0102] In at least one transistor portion 70, a floating region 202 is provided in the gate trench portion 40 closest to the diode portion 80. In multiple transistor portions 70, a floating region 202 may be provided in the gate trench portion 40 closest to the diode portion 80. In all transistor portions 70, a floating region 202 may be provided in the gate trench portion 40 closest to the diode portion 80.

[0103] In this specification, of the one or more gate trench portions 40 in the transistor portion 70, the one that is located closest to the diode portion 80 in the first direction is referred to as the first gate trench portion 40-1. Of the one or more dummy trench portions 30 in the transistor portion 70, those that are located adjacent to the first gate trench portion 40-1 are referred to as the first dummy trench portion 30-1 and the second dummy trench portion 30-2. The first dummy trench portion 30-1 is located outside the first gate trench portion 40-1. In other words, the first dummy trench portion 30-1 is located between the first gate trench portion 40-1 and the diode portion 80. In this example, the first dummy trench portion 30-1 is located at the end of the boundary region 90. The second dummy trench portion 30-2 is located inside the first gate trench portion 40-1. That is, the second dummy trench portion 30-2 is disposed on the opposite side of the first gate trench portion 40-1 from the first dummy trench portion 30-1.

[0104] Of the multiple mesa portions 60, the one that contacts the first gate trench portion 40-1 and is provided between the first gate trench portion 40-1 and the diode portion 80 is referred to as the first mesa portion 60-1. The first mesa portion 60-1 is the mesa portion 60 sandwiched between the first gate trench portion 40-1 and the first dummy trench portion 30-1.

[0105] The mesa 60 that is in contact with the first gate trench 40-1 and is located on the opposite side of the first mesa 60-1 is referred to as the second mesa 60-2. The second mesa 60-2 is the mesa 60 sandwiched between the first gate trench 40-1 and the second dummy trench 30-2.

[0106] Of the one or more floating regions 202, the one provided below the first gate trench portion 40-1 is referred to as the first floating region 202. Each floating region 202 may or may not extend below the lower end 33 of the trench portion (dummy trench portion 30 in this example) located next to the corresponding gate trench portion 40. Each floating region 202 may or may not contact the trench portion adjacent to the gate trench portion 40. In this example, each floating region 202 does not extend in the X-axis direction beyond the trench portion adjacent to the gate trench portion 40. Each floating region 202 does not extend below the mesa portion 60 that is not in contact with the gate trench portion 40.

[0107] 3 shows the first gate trench portion 40-1, the first floating region 202-1, the first mesa portion 60-1, and the second mesa portion 60-2 provided at one end in the X-axis direction of the transistor portion 70. When the transistor portion 70 is sandwiched between two diode portions 80, the transistor portion 70 is provided with the first gate trench portion 40-1, the first floating region 202-1, the first mesa portion 60-1, and the second mesa portion 60-2 at each of the ends on both sides in the X-axis direction.

[0108] The lower end 33 of each dummy trench portion 30 may be in contact with an N-type region (drift region 18 in this example). In this example, on the upper surface 21 side of the semiconductor substrate 10, no P-type region is provided below the lower end 33, but an N-type region (drift region 18 in this example) is provided.

[0109] By providing the floating region 202, when the transistor section 70 is turned on, electrons are prevented from flowing to the lower end 43 of the first gate trench section 40-1, and a depletion layer can be left near the lower end 43. This reduces the reverse recovery dV / dt. The reverse recovery dV / dt is the slope of the time waveform of the anode-cathode voltage during reverse recovery of the diode section 80. Furthermore, when the semiconductor device 100 is used in a circuit such as a three-phase inverter, the tail of the voltage waveform of the IGBT provided in the opposing arm can be reduced. This improves the trade-off characteristics between turn-on loss and reverse recovery dV / dt.

[0110] On the other hand, in a semiconductor device 100 in which a transistor section 70 and a diode section 80 are provided side by side, some of the electrons injected from the emitter region 12 of the transistor section 70 flow into the cathode region 82 of the diode section 80. This makes it difficult for the potential of the PN junction at the end of the collector region 22 of the transistor section 70 to rise, which may result in snapback when the transistor section 70 is turned on. If the floating region 202 is provided, the electron current from the emitter region 12 is inhibited, which makes it even more difficult for the potential of the PN junction at the end of the collector region 22 to rise, making snapback more likely to occur.

[0111] In this example, a non-covered region that does not overlap with the first floating region is provided in the first mesa portion 60-1 disposed near the diode portion 80. This allows electrons from the first mesa portion 60-1 to flow more easily, thereby suppressing snapback. In other words, snapback can be suppressed while improving the trade-off characteristics described above.

[0112] 4 is a diagram showing an example of the arrangement of the floating region 202 as viewed from above. Fig. 4 shows an enlarged view of the transistor section 70 in the vicinity of the boundary region 90. Fig. 4 also shows the well region 11 arranged outside the emitter region 12 in the Y-axis direction. Above the well region 11, the peripheral gate wiring 130 described in Fig. 1 extends in the X-axis direction.

[0113] In at least one transistor portion 70, the first mesa portion 60-1 has an uncovered region 212 that does not overlap with the first floating region 202-1. The uncovered region 212 may be provided in the first mesa portion 60-1 in multiple transistor portions 70, or the uncovered region 212 may be provided in the first mesa portion 60-1 in all transistor portions 70. In this example, the uncovered region 212 is provided across the entire first mesa portion 60-1 in the X-axis direction.

[0114] Each mesa portion 60 has a longitudinal direction in the Y-axis direction. The extension direction of the longest straight line among the end sides of the mesa portion 60 in a top view may be defined as the longitudinal direction of the mesa portion 60. In each mesa portion 60, the intermediate region 210 is defined as the region between both ends of the emitter region 12 in the Y-axis direction. In the mesa portion 60 of this example, the emitter regions 12 are arranged discretely in the Y-axis direction. In this case, the outer ends of the two emitter regions 12 arranged at both ends in the Y-axis direction are defined as both ends of the intermediate region 210. In the mesa portion 60, the emitter regions 12 and the contact regions 15 may be arranged alternately in the Y-axis direction.

[0115] The uncovered region 212 may be provided in the intermediate region 210 of the first mesa portion 60-1. In this example, a plurality of first floating regions 202-1 are arranged discretely along the Y axis in the intermediate region 210 of the first mesa portion 60-1. A plurality of uncovered regions 212 are also arranged discretely along the Y axis in the intermediate region 210 of the first mesa portion 60-1. This facilitates the flow of electrons from the first mesa portion 60-1, thereby suppressing snapback.

[0116] The first floating region 202-1 may overlap with or be separated from the first dummy trench portion 30-1 in top view. When the first floating region 202-1 is separated from the first dummy trench portion 30-1, snapback can be further suppressed.

[0117] In the intermediate region 210 of the first mesa portion 60-1, the sum of the lengths L2 in the Y-axis direction of the multiple uncovered regions 212 may be smaller than the sum of the lengths L1 in the Y-axis direction of the regions overlapping with the first floating region 202-1. This facilitates improving the trade-off characteristics between turn-on loss and reverse recovery dV / dt. The sum of the lengths L2 may be 70% or less of the sum of the lengths L1, or may be 50% or less. The sum of the lengths L2 may be 10% or more of the sum of the lengths L1, or may be 30% or more, or may be 50% or more.

[0118] The sum of the lengths L2 may be greater than the sum of the lengths L1. This makes it easier to suppress snapback. The sum of the lengths L2 may be 1.3 times or more, 1.5 times or more, or even 2 times or more the sum of the lengths L1. The sum of the lengths L2 may be 10 times or less, 3 times or less, or even 2 times or less the sum of the lengths L1.

[0119] The uncovered region 212 may also be provided in the intermediate region 210 of the second mesa portion 60-2. The arrangement of the first floating region 202-1 and the uncovered region 212 of the second mesa portion 60-2 in the Y-axis direction may be the same as that of the first mesa portion 60-1. The first floating region 202-1 of the second mesa portion 60-2 may overlap with or be separated from the second dummy trench portion 30-2 in a top view. As an example, the first floating region 202-1 may overlap with the second dummy trench portion 30-2 and be separated from the first dummy trench portion 30-1.

[0120] In this example, the first floating region 202-1 is disposed below at least one emitter region 12 of the first mesa portion 60-1. The first floating region 202-1 may overlap the entire corresponding emitter region 12. The first floating region 202-1 may be disposed below a plurality of emitter regions 12. The first floating region 202-1 may be disposed for all emitter regions 12 except for the emitter regions 12 disposed at both ends in the Y-axis direction. Alternatively, the first floating region 202-1 may be disposed for all emitter regions 12, including the emitter regions 12 disposed at both ends in the Y-axis direction. By providing the first floating region 202-1 so as to overlap the emitter region 12, the trade-off characteristics of turn-on loss and reverse recovery dV / dt are easily improved.

[0121] In this example, at least a portion of the contact region 15 is the uncovered region 212. Each contact region 15 may be provided with the uncovered region 212. In each contact region 15, the portion that contacts the emitter region 12 may overlap with the first floating region 202-1. Each contact region 15 does not have to overlap with the first floating region 202-1.

[0122] In another example, the first floating region 202-1 may be arranged below at least one contact region 15 of the first mesa portion 60-1. The first floating region 202-1 may be arranged below multiple contact regions 15. The first floating region 202-1 may be arranged for all contact regions 15 except for the contact regions 15 arranged at both ends in the Y-axis direction. Furthermore, the first floating region 202-1 may be arranged for all contact regions 15, including the contact regions 15 arranged at both ends in the Y-axis direction.

[0123] In this case, at least a portion of the emitter region 12 is the uncovered region 212. The uncovered region 212 may be provided in each emitter region 12. In each emitter region 12, the portion that contacts the contact region 15 may overlap with the first floating region 202-1. Each emitter region 12 does not have to overlap with the first floating region 202-1. By providing the first floating region 202-1 so as to overlap with the contact region 15, electrons can flow more easily, making it easier to suppress snapback.

[0124] Each mesa 60 other than the first mesa 60-1 and the second mesa 60-2 may be provided with one floating region 202. The length of the floating region 202 in the Y-axis direction of the mesa 60 is greater than the length L1 of one first floating region 202-1 in the Y-axis direction. The length of the floating region 202 in this example is equal to the sum of the lengths L1 and L2. The positions of both ends of the floating region 202 in the Y-axis direction are the same as the positions of the outer ends of the first floating regions 202-1 arranged at both ends in the Y-axis direction. The length of the floating region 202 in the Y-axis direction may be 50% or more, 70% or more, or 90% or more of the length of the straight portion 39 of the gate trench 40 in the Y-axis direction.

[0125] The area of ​​the uncovered region 212 in the first mesa portion 60-1 in a top view (referred to as the first area) may be larger than the area of ​​the region that does not overlap with the floating region 202 in the mesa portion 60 that contacts the gate trench portion 40 other than the first gate trench portion 40-1 (referred to as the second area). The first area is the value obtained by multiplying the width of the first mesa portion 60-1 in the X-axis direction by the sum of the lengths L2. The second area is the value obtained by multiplying the width of the mesa portion 60 in the X-axis direction by the sum of the lengths of the region that does not overlap with the floating region 202 in the Y-axis direction. The second area may be 0.

[0126] As shown in FIG. 4 , a first extension region 204 may be provided, extending from the well region 11 to a position where it overlaps with the emitter region 12. The first extension region 204 is a P-type region. The first extension region 204 is connected to the well region 11. The well region 11 is connected to the emitter electrode 52. The first extension region 204 may be provided at the same depth as the floating region 202. The first extension region 204 may have the same doping concentration as the floating region 202. The first extension region 204 is separated from the floating region 202.

[0127] In this example, the first extension region 204 overlaps the entire emitter region 12 closest to the well region 11. The first extension region 204 does not need to overlap the emitter region 12 that is second closest to the well region 11. By providing the first extension region 204, the region from the well region 11 to below the outermost emitter region 12 can be at emitter potential. This makes the electric field distribution in the region where the first extension region 204 is provided uniform, thereby suppressing a decrease in breakdown voltage. The first extension region 204 may be provided over the entire X-axis direction of the transistor section 70. The first extension region 204 may be provided over the entire X-axis direction of the diode section 80.

[0128] 5 is a diagram showing another example of the arrangement of floating areas 202 in a top view. The arrangement of the first floating area 202-1 is the same as the example in FIG. 4. In this example, the floating areas 202 other than the first floating area 202-1 are also arranged discretely in the Y-axis direction, similar to the first floating area 202-1. In this example, the length in the Y-axis direction of the floating areas 202 other than the first floating area 202-1 may be the same as the length L1 of the first floating area 202-1. The spacing in the Y-axis direction of the floating areas 202 other than the first floating area 202-1 may be the same as the spacing L2 of the first floating area 202-1.

[0129] At least one of the floating areas 202 other than the first floating area 202-1 may be arranged discretely in the Y-axis direction. For example, the floating area 202 adjacent to the first floating area 202-1 may be arranged discretely in the Y-axis direction. The other floating areas 202 may be arranged contiguously in the Y-axis direction, as in the example of Figure 4. As shown in Figure 5, all of the floating areas 202 may be arranged discretely in the Y-axis direction.

[0130] 6 is a diagram showing another example of the e-e cross section. In this example, the arrangement of the first floating region 202-1 differs from the example described in FIG. 3. The other structures may be similar to any of the examples described in FIG. 3 to FIG. 5.

[0131] In this example, the first floating region 202-1 does not extend in the X-axis direction below the lower end 33 of the first dummy trench portion 30-1. The first floating region 202-1 does not contact the first dummy trench portion 30-1 in a top view. An uncovered region 212 is provided between the first floating region 202-1 and the first dummy trench portion 30-1. The first floating region 202-1 may or may not extend below the contact portion 54 of the first mesa portion 60-1. The first floating region 202-1 may or may not extend to the center of the first mesa portion 60-1 in the X-axis direction.

[0132] The first floating region 202-1 may be arranged discretely in the Y-axis direction, similar to the examples in Figures 4 and 5. In another example, only one first floating region 202-1 may be provided continuously in the Y-axis direction, similar to the floating region 202 in Figures 4 and 5. Even in this case, snapback can be suppressed because the uncovered region 212 is provided between the first dummy trench portion 30-1 and the first floating region 202.

[0133] The width of the first mesa portion 60-1 in the X-axis direction is defined as X1. The width of the uncovered region 212 in the X-axis direction may be 10% or more, 20% or more, or 30% or more of the width X1. The width of the uncovered region 212 in the X-axis direction may be 90% or less, 80% or less, or 70% or less of the width X1. As shown in FIG. 6 , the width of the uncovered region 212 in the X-axis direction may be 50% or less of the width X1.

[0134] The first floating region 202-1 may be in contact with the second dummy trench portion 30-2 in top view. In this example, the first floating region 202-1 is in contact with the second dummy trench portion 30-2 in the XZ cross section.

[0135] The width of the second mesa portion 60-2 in the X-axis direction is defined as X2. Width X2 may be smaller than width X1. In other words, the first gate trench portion 40-1 is disposed between the first dummy trench portion 30-1 and the second dummy trench portion 30-2, and is offset toward the second dummy trench portion 30-2. With this configuration, when the first floating region 202-1 is formed by injecting and diffusing a P-type dopant through the trench structure of the first gate trench portion 40-1, it becomes easy to separate the first floating region 202-1 from the first dummy trench portion 30-1 and bring the first floating region 202-1 into contact with the second dummy trench portion 30-2.

[0136] 7 is a diagram showing another example of the e-e cross section. In this example, the arrangement of the first floating region 202-1 differs from the example described in FIG. 6. The other structures may be similar to any of the examples described in FIG.

[0137] In this example, the first floating region 202-1 is also disposed at a distance from the second dummy trench portion 30-2 in a top view. The distance between the first floating region 202-1 and the first dummy trench portion 30-1 in the X-axis direction is defined as X3, and the distance between the first floating region 202-1 and the second dummy trench portion 30-2 is defined as X4. The distance X4 may be smaller than the distance X3. The distance X4 may be 50% or less of the distance X3, or may be 30% or less. The distance X4 may be 0, as in the example of FIG. 6. This example also makes it possible to suppress snapback.

[0138] The floating areas 202 other than the first floating area 202-1 may be similar to the example in Fig. 6. In another example, all of the floating areas 202 may have a structure similar to the first floating area 202-1 in Fig. 7.

[0139] FIG. 8 is a top view showing an example of a transition region 92. The structure of the transition region 92 described in FIG. 8 may be combined with any of the examples described herein. The structure of the transition region 92 described in FIG. 8 may be combined with the structure of the floating region 202 of any of the examples described herein. In other examples, the floating region 202 in the semiconductor device 100 described in FIG. 8 may have a structure different from that in the examples of FIGS. 1 to 7. Alternatively, the semiconductor device 100 described in FIG. 8 may not have a floating region 202. The semiconductor device 100 described in FIG. 8 may not include a diode section 80.

[0140] In this example, the well region 11 is also disposed outside the emitter region 12 in the X-axis direction. Above the well region 11 in this example, a peripheral gate wiring 130 extending in the Y-axis direction is disposed.

[0141] The transition region 92 is disposed between the emitter region 12 (or the transistor portion 70) and the well region 11 in the X-axis direction. The transition region 92 has one or more trench portions arranged side by side in the X-axis direction. The transition region 92 may have one or more dummy trench portions 30, one or more gate trench portions 40, or both a dummy trench portion 30 and a gate trench portion 40. The transition region 92 of this example has trench portions arranged in the same pattern as the transistor portion 70. The transistor portion 70 of this example has one gate trench portion 40 and two dummy trench portions 30 arranged alternately. The transition region 92 may also have one gate trench portion 40 and two dummy trench portions 30 arranged alternately.

[0142] One or more trench portions may also be arranged inside the well region 11. In this example, two dummy trench portions 30 are arranged inside the well region 11.

[0143] The transition region 92 may have a collector region 22 at a position where it contacts the lower surface 23. The transition region 92 may have a cathode region 82 at a position where it contacts the lower surface 23. The transition region 92 has one or more mesas 63. The drift region 18 may be exposed on the upper surface 21 of the mesa portion 63. In another example, the base region 14 may be provided on the upper surface 21 of the mesa portion 63.

[0144] The semiconductor device 100 of this example includes a second extension region 220 provided in the transition region 92. The second extension region 220 is a P-type region that extends in the X-axis direction from the well region 11 to a position where it overlaps with the emitter region 12. The second extension region 220 is connected to the well region 11. The second extension region 220 may be provided at the same depth as the floating region 202. The second extension region 220 may have the same doping concentration as the floating region 202.

[0145] In this example, the second extension region 204 overlaps the entire emitter region 12 of the mesa portion 60 that is closest to the well region 11 in the X-axis direction. The second extension region 204 may also overlap the entire emitter regions 12 of two or more mesa portions 60 that are closest to the well region 11. When a contact region 15 is provided in the mesa portion 60, the second extension region 204 also overlaps the contact region 15. The second extension region 204 is not connected to the floating region 202.

[0146] By providing the second extension region 220, the transition region 92 can be set to the emitter potential. This makes the electric field distribution in the transition region 92 uniform, thereby suppressing a decrease in breakdown voltage. The second extension region 220 may be provided over a wider range in the Y-axis direction than the floating region 202. The second extension region 220 may be connected at its end in the Y-axis direction to the first extension region 204 described with reference to FIG. 4 and the like.

[0147] 9 is a diagram showing an example of the ff cross section in FIG. 8. The ff cross section is an XZ plane including the well region 11, the transition region 92, and the transistor section 70. As described above, the peripheral gate wiring 130 is disposed above the well region 11. The peripheral gate wiring 130 and the well region 11 are insulated by an insulating film 221 such as an oxide film. In FIG. 9, the upper surface structure, such as the emitter electrode 52 and the interlayer insulating film 38, and the lower surface structure, such as the collector electrode 24, are omitted.

[0148] The second extension region 220 is provided below the lower ends of one or more trench portions provided in the transition region 92. The second extension region 220 may contact the lower ends of each trench portion. The second extension region 220 extends in the X-axis direction beyond the transition region 92 to the transistor portion 70.

[0149] The second extension region 220 extends to below the emitter region 12. The second extension region 220 may extend to below the lower end of at least one gate trench portion 40 of the transistor portion 70. No floating region 202 is provided below the gate trench portion 40. By providing the second extension region 220, the electric field distribution in the transition region 92 can be made uniform, thereby suppressing a decrease in breakdown voltage.

[0150] 10 is an XZ cross section showing another example of the structure of the boundary region 90 and the diode section 80. In FIG. 10, the upper surface structure, such as the emitter electrode 52 and the interlayer insulating film 38, and the lower surface structure, such as the collector electrode 24, are omitted.

[0151] In the examples described in FIGS. 1 to 9 , the boundary region 90 and the diode section 80 do not have a floating region 202. In this example, a floating region 202 is provided in at least one of the boundary region 90 and the diode section 80. The structure described in FIG. 10 can be applied to any of the examples described in FIGS. 1 to 9 . By providing the floating region 202 in the boundary region 90, the electric field distribution can be made uniform between the boundary region 90 and the transistor section 70 other than the boundary region 90. By providing the floating region 202 in the diode section 80, the electric field distribution can be made uniform between the transistor section 70 and the diode section 80.

[0152] In the example of Fig. 10, the arrangement pattern of the trench portions in the transistor portion 70 is different from the examples of Fig. 3 and the like. In the example of Fig. 10, one gate trench portion 40 and one dummy trench portion 30 are alternately arranged in the X-axis direction. The arrangement pattern of the trench portions in the transistor portion 70 may be either the pattern of Fig. 3 or Fig. 10, or may be another pattern. In the transistor portion 70 of this example, a floating region 202 is provided in each gate trench portion 40.

[0153] 10 does not extend to a position where it overlaps with a trench portion (the dummy trench portion 30 in this example) arranged adjacent to the corresponding gate trench portion 40. The floating region 202 may extend to a position where it overlaps with at least one trench portion arranged adjacent to the gate trench portion 40, as described with reference to FIGS.

[0154] 10 , the boundary region 90 has a plurality of dummy trench portions 30, a plurality of mesa portions 62, and one or more floating regions 202. The floating regions 202 are provided below the lower end of at least one trench portion in the boundary region 90. The period F2 at which the floating regions 202 are provided in the X-axis direction in the boundary region 90 may be the same as the period F1 at which the floating regions 202 are provided in the X-axis direction in the transistor portion 70 other than the boundary region 90. By making the periods at which the floating regions 202 are provided the same, the electric field distribution can be further uniformed. The period at which the floating regions 202 are provided is the distance between the center positions of the respective floating regions 202 in the X-axis direction.

[0155] 10 , a floating region 202 is also provided below the lower end of at least one trench portion of the diode portion 80. In the diode portion 80, the period F3 at which the floating regions 202 are provided in the X-axis direction may be the same as the period F1 in the transistor portion 70. By making the periods at which the floating regions 202 are provided the same, the electric field distribution can be made even more uniform.

[0156] The floating regions 202 in the boundary region 90 may be arranged in a plurality of discrete positions in the Y-axis direction, or may be provided in a single continuous position. The floating regions 202 in the diode section 80 may be arranged in a plurality of discrete positions in the Y-axis direction, or may be provided in a single continuous position.

[0157] The periods F1, F2, and F3 of the floating region 202 do not have to be the same. The period F1 may be larger or smaller than the period F2. The period F1 may be larger or smaller than the period F3. The period F3 may be larger or smaller than the period F2. By adjusting the periods F1 to F3, the breakdown voltage distribution of the transistor section 70, the boundary region 90, and the diode section 80 can be adjusted. For example, by increasing the period F1, the breakdown voltage of the transistor section 70 can be lowered and the breakdown voltage of the diode section 80 can be relatively increased. Conversely, by increasing the period F3, the breakdown voltage of the diode section 80 can be lowered and the breakdown voltage of the transistor section 70 can be relatively increased. Furthermore, the periods F1 to F3 may be adjusted so that the breakdown voltages of the transistor section 70, the boundary region 90, and the diode section 80 are the same.

[0158] The intervals in the X-axis direction of all trench portions in the semiconductor device 100 may be the same. In another example, the intervals in the X-axis direction of the trench portions may not be uniform.

[0159] 11 is a diagram showing the collector voltage-collector current characteristics in the example and the reference example. The reference example is an example in which the uncovered region 212 is not provided in the first mesa portion 60-1. The example is an example in which the uncovered region 212 is provided in the first mesa portion 60-1.

[0160] In the reference example, the floating region 202 makes it difficult for the electron current in the first mesa portion 60-1 to flow to the collector region 22. For this reason, in the reference example, snapback occurs, in which almost no collector current flows until the collector voltage exceeds a predetermined voltage, as shown in FIG. 11 . In contrast, in the semiconductor device 100 according to the example, the electron current in the first mesa portion 60-1 easily flows to the collector region 22. For this reason, snapback does not occur.

[0161] 12 is a diagram showing the trade-off characteristics between turn-on loss and reverse recovery dV / dt in the reference example and the working example, showing the trade-off relationship in which a decrease in reverse recovery dV / dt increases turn-on loss.

[0162] The reference example in Fig. 12 is a semiconductor device that does not have a floating region 202. The semiconductor device of the example is the semiconductor device 100 described with reference to Figs. 1 to 10. The semiconductor device 100 of the example has an improved trade-off characteristic by having the floating region 202. For example, when the reverse recovery dV / dt is the same, the turn-on loss of the example is smaller than that of the reference example.

[0163] 12, the semiconductor device 100 can improve the trade-off characteristics between the turn-on loss and the reverse recovery dV / dt. As described with reference to FIG. 11, the semiconductor device 100 can suppress snapback.

[0164] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0165] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0166] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 20...Buffer region, 21...Upper surface, 22...Collector region, 23...Lower surface, 24...Collector electrode, 29...Straight portion, 30...Dummy trench portion, 30-1...First dummy trench portion, 30-2...Second dummy trench portion, 31...Tip portion, 32...Dummy insulating film, 33...Lower end, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Straight portion, 40...Gate trench portion, 40-1...First gate trench portion, 41...Tip portion, 42...Gate insulating film, 43...Lower end, 44...Gate Conductive portion, 45... trench, 52... emitter electrode, 54... contact portion, 60, 61, 62, 63... mesa portion, 60-1... first mesa portion, 60-2... second mesa portion, 70... transistor portion, 80... diode portion, 81... extension region, 82... cathode region, 90... boundary region, 92... transition region, 100... semiconductor device, 130... peripheral gate wiring, 131... active side gate wiring, 160... active portion, 162... edge, 164... gate pad, 190... edge termination structure portion, 202... floating region, 202-1... first floating region, 204... first extension region, 212... uncovered region, 220... second extension region, 221... insulating film

Claims

1. A semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type; one or more transistor sections having a collector region of a second conductivity type provided on the lower surface of the semiconductor substrate; and one or more diode sections having a cathode region of the first conductivity type provided on the lower surface of the semiconductor substrate and arranged alternately with the transistor sections in a first direction, wherein each of the transistor sections has: a plurality of trench sections including one or more gate trench sections arranged side by side in the first direction; a plurality of mesa sections which are regions sandwiched between the trench sections in the first direction; and a floating region of a second conductivity type provided for at least one of the gate trench sections and below a lower end of the gate trench section, wherein the one or more gate trench sections include a first gate trench section provided closest to the diode section, and the plurality of mesa sections include a first mesa section in contact with the first gate trench section and provided between the first gate trench section and the diode section, A semiconductor device comprising: a first floating region provided below the first gate trench portion; and the first mesa portion having an uncovered region that does not overlap with the first floating region.

2. The semiconductor device according to claim 1, wherein the plurality of trench portions include one or more dummy trench portions, the first mesa portion is sandwiched between the first gate trench portion and a first dummy trench portion, and a first floating region provided below the lower end of the first gate trench portion does not extend below the lower end of the first dummy trench portion.

3. The semiconductor device according to claim 2, wherein the first floating region is not in contact with the first dummy trench portion when viewed from above.

4. The semiconductor device described in claim 3, wherein the plurality of trench portions include a second dummy trench portion arranged on an opposite side of the first gate trench portion from the first dummy trench portion, and the distance between the first floating region and the second dummy trench portion in the first direction is smaller than the distance between the first floating region and the first dummy trench portion.

5. The semiconductor device according to claim 4, wherein the first floating region is in contact with the second dummy trench portion when viewed from above.

6. The semiconductor device according to claim 1, wherein the first mesa portion has an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate, and a base region of a second conductivity type provided between the emitter region and the drift region, the first mesa portion having a longitudinal direction in a second direction, and the first mesa portion having the uncovered region in an intermediate region between both ends of the emitter region in the second direction.

7. The semiconductor device according to claim 6, wherein a plurality of said uncovered regions are arranged discretely in said second direction in said intermediate region.

8. The semiconductor device according to claim 7, wherein in the intermediate region, the sum of the lengths in the second direction of the plurality of uncovered regions is smaller than the sum of the lengths in the second direction of the regions overlapping with the first floating region.

9. The semiconductor device described in claim 7, wherein the first mesa portion is provided in contact with the upper surface of the semiconductor substrate and has second conductivity type contact regions arranged alternately with the emitter regions in the second direction, the first floating region is arranged below at least one of the emitter regions, and at least a portion of the contact region is the uncovered region.

10. The semiconductor device according to claim 9, wherein the first floating region overlaps entirely with at least one of the emitter regions, and each of the contact regions is provided with an uncovered region.

11. The semiconductor device according to claim 6, further comprising: a well region of a second conductivity type arranged outside the first mesa portion in the second direction and having a higher concentration than the base region; and a first extension region of the second conductivity type extending in the second direction from the well region to a position overlapping with the emitter region.

12. The semiconductor device according to claim 6, further comprising: a well region of a second conductivity type arranged outside the emitter region in the first direction and having a higher concentration than the base region; and a second extension region of the second conductivity type extending in the first direction from the well region to a position overlapping with the emitter region.

13. The semiconductor device according to claim 1, wherein the diode section has a plurality of dummy trench sections arranged in the first direction and a mesa section sandwiched between the dummy trench sections in the first direction, and the floating region is also provided below a lower end of at least one of the dummy trench sections of the diode section.

14. The semiconductor device according to claim 13, wherein the period at which the floating regions are provided in the first direction in the diode section is the same as the period at which the floating regions are provided in the first direction in the transistor section.

15. The semiconductor device described in claim 1, wherein the transistor section has a boundary region between the first gate trench section and the diode section, the boundary region having one or more of the trench sections and one or more of the mesa sections, and the floating region is also provided below a lower end of at least one of the trench sections in the boundary region.

16. The semiconductor device according to claim 15, wherein the period at which the floating regions are provided in the first direction in the boundary region is the same as the period at which the floating regions are provided in the first direction in the transistor portion other than the boundary region.

17. A semiconductor device according to any one of claims 1 to 16, wherein the area of ​​the uncovered region in the first mesa portion is larger than the area of ​​a region that does not overlap with the floating region in the mesa portion that contacts the gate trench portion other than the first gate trench portion.

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