Optical semiconductor element and method for manufacturing same

Abstract

This invention improves the characteristics of an optical semiconductor element.　An optical semiconductor element according to the present invention comprises: a first active layer having a light-reception / emission wavelength of a first wavelength; a tunnel junction layer on the first active layer; and a second active layer on the tunnel junction layer, the second active layer having a light-reception / emission wavelength of a second wavelength. The first active layer and the second active layer include Sb. The tunnel junction layer has a p-type InAs layer and an n-type InAs layer.

Description

Optical semiconductor element and manufacturing method thereof

[0001] The present invention relates to an optical semiconductor element and a method for manufacturing the same.

[0002] Optical semiconductor devices are known that have two or more vertically stacked active layers with a tunnel junction layer sandwiched between them. Such optical semiconductor devices are used as light-emitting devices to improve optical output when the wavelengths of the stacked active layers are close, or to emit different wavelengths when the wavelengths of the stacked active layers are separated. Similarly, they are used as light-receiving devices to improve light-receiving efficiency when the wavelengths of the stacked active layers are close, or to have sensitivity to different wavelength bands when the wavelengths of the stacked active layers are separated.

[0003] In such optical semiconductor devices, multiple active layers are stacked vertically, so that the active layers are connected in series. In light-emitting devices, when a forward current flows through the active layers, each of the active layers can emit light. In this case, the active layers are generally pn junctions.

[0004] The tunnel junction layer is formed from a highly doped p-type semiconductor layer and an n-type semiconductor layer, and when a forward voltage is applied to the active layer, a reverse voltage is applied. Normally, if the junctions are in the order of p-type, n-type, p-type (or n-type, p-type, n-type), a thyristor is formed and no current flows, but because the tunnel junction layer sandwiched between the active layers is highly doped, a tunnel effect occurs within the tunnel junction layer, allowing current to flow.

[0005] JP 2009-522755 A JP 2018-201009 A

[0006] Patent Document 1 describes that only Al, Ga, In, and P are preferable as basic constituent materials of the crystal lattice that constitutes the optical semiconductor element, but these materials alone cannot be expected to emit light at a long wavelength exceeding 3000 nm. Also, as described in Patent Document 2, conventionally, a tunnel junction layer is formed by using an n-type dopant with a concentration of 1.0×10 １９ atoms / cm ３A high concentration of at least 1000 uF is considered preferable, but if an n-type semiconductor layer and a p-type semiconductor layer containing a high concentration of dopant are present between vertically stacked active layers, the dopant may diffuse into the active layer, possibly causing a decrease in reliability or an increase in leakage current.

[0007] The present invention has been made in view of the above circumstances, and has an object to improve the characteristics of optical semiconductor elements.

[0008] The present inventors have conducted extensive research into ways to solve the above problems and have discovered an optical semiconductor device in which the first and second active layers contain Sb and the tunnel junction layer has a p-type InAs layer and an n-type InAs layer, as well as a method for manufacturing the same, thereby completing the present invention. It has also been found that the tunnel junction layer of the present invention exhibits a tunnel effect at a dopant concentration lower than that previously considered necessary. The gist of the present invention is as follows:

[0009] (1) An optical semiconductor element having a first active layer that receives and emits light at a first wavelength, a tunnel junction layer on the first active layer, and a second active layer that receives and emits light at a second wavelength and is on the tunnel junction layer, wherein the first active layer and the second active layer contain Sb, and the tunnel junction layer has a p-type InAs layer and an n-type InAs layer.

[0010] (2) The tunnel junction layer has a dopant concentration of 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ The optical semiconductor element according to (1) above, wherein the optical semiconductor element has a thickness of less than 100 nm.

[0011] (3) The optical semiconductor element according to (1) or (2), wherein the first active layer and the second active layer have a quantum well structure, and the first wavelength and the second wavelength are 3000 nm or longer.

[0012] (4) The optical semiconductor element according to any one of (1) to (3), wherein the first wavelength and the second wavelength are the same.

[0013] (5) The optical semiconductor element according to any one of (1) to (4), wherein the p-type InAs layer is located on the first active layer side of the tunnel junction layer, a p-type electron blocking layer is located between the first active layer and the tunnel junction layer, and the thickness of the layer between the first active layer and the tunnel junction layer is 100 nm or less.

[0014] (6) The optical semiconductor element according to any one of (1) to (5), wherein the n-type InAs layer is located on the second active layer side of the tunnel junction layer, a spacer layer is provided between the tunnel junction layer and the second active layer, and a film thickness between the tunnel junction layer and the second active layer is 100 nm or less.

[0015] (7) A method for manufacturing an optical semiconductor device, comprising: forming a first active layer on a substrate, the first active layer having an emission and reception wavelength of a first wavelength; forming a tunnel junction layer on the first active layer; and forming a second active layer on the tunnel junction layer, the second active layer having an emission and reception wavelength of a second wavelength, wherein the first active layer and the second active layer contain Sb, and the step of forming the tunnel junction layer comprises forming an n-type InAs layer and forming a p-type InAs layer on the n-type InAs layer.

[0016] (8) The tunnel junction layer has a dopant concentration of 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ (8) The method for producing an optical semiconductor element according to (7), wherein the

[0017] It is possible to provide an optical semiconductor element with improved characteristics and a method for manufacturing the same. For example, when used as a light-emitting element, it is possible to provide an optical semiconductor element with high light output and forward voltage and a center wavelength of 3000 nm or more, and a method for manufacturing the same. Furthermore, because the leakage current is reduced in the light-emitting element, it is also possible to provide an optical semiconductor element with low dark current and high shunt resistance when used as a light-receiving element, and a method for manufacturing the same.

[0018] FIG. 1 is a cross-sectional view illustrating a first embodiment of an optical semiconductor element according to the present invention. FIG. 2 is a cross-sectional view illustrating a second embodiment of an optical semiconductor element according to the present invention. FIG. 3 is a cross-sectional view illustrating an example of a manufacturing method for the second embodiment of an optical semiconductor element according to the present invention. FIG. 4 is a cross-sectional view illustrating an example of a manufacturing method following FIG. 5. FIG. 6 is a cross-sectional view illustrating a third embodiment of an optical semiconductor element according to the present invention. FIG. 7 is a graph showing the results of measuring the diffusion state of Te ions in Example 1 by secondary ion mass spectrometry (SIMS). FIG. 8 is a graph showing the results of measuring the diffusion state of Zn ions in Example 1 by secondary ion mass spectrometry (SIMS).

[0019] Prior to describing the embodiments according to the present invention, the following points will be explained in advance.

[0020] In this embodiment, the active layer containing Sb is InAs ｘ Sb １－ｘ (0<x<1) means a compound that is also expressed as (0<x<1). When an InAs layer, an AlInAs layer, or an InAsP layer is referred to, it means that Sb is not included in the composition ratio. However, it is acceptable that no Sb source gas was used during the growth of the layer, and Sb may be included as an unavoidable dopant element due to residual Sb in the chamber or diffusion from an adjacent Sb-containing layer. Furthermore, when the term "AlInAsSb" is used in this specification without specifying the composition ratio, it means any compound in which the chemical composition ratio of group III elements (the sum of Al and In) to group V elements (the sum of As and Sb) is 1:1, and the ratios of the group III elements Al and In and the group V elements As and Sb are indefinite. This includes cases in which the group III elements do not contain either Al or In, and also includes cases in which the group V elements do not contain either As or Sb. The composition ratio of each III-V element in AlInAsSbP can be measured by photoluminescence measurement, X-ray diffraction measurement, or the like.

[0021] In this specification, the term "undoped" refers to a layer in which a specific dopant such as Zn, Te, or Si is not intentionally added. An undoped layer may contain unavoidable dopants during the manufacturing process. The values ​​of the dopant concentrations of Zn, Te, Si, etc. are determined by SIMS analysis.

[0022] The III-V compound semiconductor of this embodiment contains at least one of Al, Ga, and In as a group III element, and at least P, As, and Sb as a group V element.

[0023] The thickness of each layer formed by epitaxial growth can be calculated from cross-sectional observation of the grown layer using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). It is preferable to use an SEM when the film thickness is 10 nm or more, and a TEM when the film thickness is less than 10 nm.

[0024] In this specification, the central wavelengths of the emission wavelengths of different active layers are compared, and the description is given assuming that the emission wavelengths are identical, but this is not limited thereto. The central wavelengths of the emission wavelengths may be distant from each other or may be close to each other. When the central wavelengths are distant from each other, different roles can be assigned to the respective central wavelengths. In this specification, "the central wavelengths of the emission wavelengths are close to each other" means that the central wavelengths are positioned so that the ranges of the full width at half maximum in the emission spectra overlap, for example, meaning that the wavelength difference is within the value of the full width at half maximum (for example, within 100 nm). When the central wavelengths are identical or close to each other, the emission spectra are combined, which is effective in improving the emission intensity. The above description is given in the case of a light-emitting element, but the same applies to a light-receiving element.

[0025] An optical semiconductor device according to the present invention includes a first active layer having an emitting and receiving wavelength of a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer having an emitting and receiving wavelength of a second wavelength, wherein the first active layer and the second active layer contain Sb, and the tunnel junction layer includes a p-type InAs layer and an n-type InAs layer.

[0026] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the aspect ratios of the substrate and each layer are exaggerated from their actual ratios for the sake of convenience. In the following, III-V compound semiconductors composed of three or more elements may be described without specifying the composition ratio of each element (e.g., "InAsSb").

[0027] 1 , an example of an optical semiconductor element 100, which is a first embodiment of an optical semiconductor element according to the present invention, will be described together with a manufacturing method. The optical semiconductor element 100 includes a growth substrate 105 and a semiconductor laminate 140 that emits light when current is applied, and is made up of multiple semiconductor layers stacked on the growth substrate 105. As will be described in detail later, the semiconductor laminate 140 has multiple stacked active layers made up of pn junctions, and a tunnel junction layer through which current flows in the reverse direction (from the n-type layer to the p-type layer) due to the tunnel effect sandwiched between these active layers, functioning as a so-called double-stack light-emitting diode.

[0028] The first embodiment is an embodiment of semiconductor light-emitting element 100 in which an n-type contact layer 141, an n-type window layer 142, a first spacer layer 143, a first active layer 144, a p-type intermediate layer (a first p-type electron blocking layer 145 and a first p-type window layer 146), a tunnel junction layer 147 (a p-type tunnel junction layer 1471 and an n-type tunnel junction layer 1472), an n-type intermediate layer (a second spacer layer 148), a second active layer 149, a second p-type electron blocking layer 150, a second p-type window layer 151, and a p-type contact layer 152 are sequentially formed on a growth substrate 105, and the growth substrate 105 is used as a substrate as it is.

[0029] <Substrate> A description will be given of a substrate applicable to the optical semiconductor element 100. The substrate used in the present invention may be any substrate having a thickness sufficient to mechanically maintain the shape of the semiconductor stack 140 including the first active layer 144, the tunnel junction layer 147, and the second active layer 149, and may be the growth substrate 105 used for epitaxial growth when forming the semiconductor stack 140 of the optical semiconductor element 100.

[0030] <<Growth Substrate>> The growth substrate 105 can be a compound substrate such as GaAs, InP, InAs, GaSb, or InSb. To form an active layer containing Sb, it is ideal to use an InAs, GaSb, or InSb substrate. However, these substrates are expensive, so from a cost perspective, it is preferable to use a GaAs substrate. The GaAs substrate is preferably Si-doped to form an n-type substrate, and the semiconductor laminate 140 is preferably laminated on the (100) plane of the GaAs substrate. Furthermore, the thickness of the GaAs substrate is preferably 200 μm or more and 900 μm or less.

[0031] When a GaAs substrate or an InP substrate is used, it is also preferable to provide a buffer layer between the growth substrate 105 and the n-type contact layer 141 to alleviate lattice mismatch, and the buffer layer may include an InAs buffer layer grown at a low temperature. α Ga １－α As β Sb １－β The buffer layer may have a composition gradient in which the compositions α and β of the layers are varied within the range of 0 to 1, or may have a superlattice structure.

[0032] <<N-Type Contact Layer>> An n-type contact layer 141 made of a III-V compound semiconductor layer may be provided on the growth substrate 105. The n-type contact layer 141 has high conductivity and is advantageous for forming an electrode. The thickness is preferably 20 nm or more and 500 nm or less. Dopants that can be used here include Si, Te, S, Ge, Sn, Se, etc. The dopant concentration is preferably higher than the dopant concentration of the n-type window layer 142, which will be described next, and is 8.0×10 １８ / cm ３ Above 3.0 x 10 １９ / cm ３ It is more preferable to set the following:

[0033] <<N-Type Window Layer>> An n-type window layer 142 made of a III-V compound semiconductor layer may be provided on the n-type contact layer 141, and its thickness is preferably 500 nm to 6000 nm. Examples of dopants that can be used here include Si, Te, S, Ge, Sn, and Se. When the growth substrate 105 and the first active layer 144 have different lattice constants, defects propagate to the first active layer 144 if the n-type window layer 142 is thinner than 500 nm. Furthermore, a thickness of the n-type window layer 142 thinner than 500 nm is undesirable because a sufficient number of carriers are not supplied to the first active layer 144, resulting in low light emission output. On the other hand, a thickness of the n-type window layer 142 thicker than 6000 nm is also undesirable because significant improvement in characteristics cannot be expected and the growth time is long, increasing the cost of raw materials, resulting in productivity problems.

[0034] The dopant concentration of the n-type window layer 142 is preferably lower than that of the n-type contact layer 141, and is 1.0×10 １８ / cm ３ Above 8.0 x 10 １８ / cm ３ It is preferable to do the following:

[0035] Furthermore, the composition of the n-type window layer 142 is preferably a composition that lattice matches the composition of the first active layer 144. The composition of the n-type window layer 142 is preferably AlInAs, which has a smaller Al composition ratio (i.e., a smaller band gap) than the first p-type electron blocking layer 145 described below, and is more preferably InAs.

[0036] <First Spacer Layer> A first spacer layer 143 made of an undoped III-V compound semiconductor layer may be provided on the n-type window layer 142, and its thickness is preferably 1 nm or more and 100 nm or less. The first spacer layer 143 preferably has the same composition as the barrier layer of the first active layer 144 or the n-type window layer 142, and is a layer that is not doped with an n-type dopant. This first spacer layer 143 reduces the amount of n-type dopant diffusing from the n-type window layer 142 to the first active layer 144.

[0037] <First Active Layer> The first active layer 144 containing Sb is provided on the first spacer layer 143. The first active layer 144 is an InAs light-emitting layer. ｘ１ Sb １－ｘ１ In FIG. 1, the first active layer 144 includes an InAs ｙ１ P １－ｙ１ layer (0<y1<1), and ｘ１ Sb １－ｘ１ The layer is the well layer 144w of the first active layer, and InAs ｙ１ P １－ｙ１ The quantum well structure in which the barrier layer 144b of the first active layer is an InAs layer is shown as an example. ｘ１ Sb １－ｘ１ A single-layer structure of well layers may also be used. The composition other than Sb is not limited to In and As, and other III-V group compound semiconductors may also be used. It is also preferable to adjust the composition difference between the well layer 144w of the first active layer and the barrier layer 144b of the first active layer to apply strain to the well layer. The first active layer 144 preferably has a multiple quantum well (MQW) structure as shown in FIG. 1 to improve optical output by suppressing crystal defects. This multiple quantum well structure can be formed by alternating the well layers and barrier layers. When using a multiple quantum well structure, the number of combinations of well layers and barrier layers is preferably 3 to 40. That is, 3.5 to 40.5 combinations, including the first barrier layer, is preferable. Furthermore, the thickness of each well layer is preferably 5 to 40 nm, and the thickness of each barrier layer is preferably 10 to 50 nm. The first active layer 144 is preferably undoped. The first active layer 144 has a wavelength range in which the central emission wavelength is 3000 nm or greater. The barrier layer may be made of AlInAs instead of InAsP.

[0038] <P-Type Intermediate Layer Between First Active Layer and Tunnel Junction Layer> A p-type intermediate layer is provided between the first active layer 144 and the tunnel junction layer 147 described below. The thickness of the layer between the first active layer 144 and the tunnel junction layer 147 is preferably 100 nm or less. This p-type intermediate layer preferably includes a p-type electron blocking layer.

[0039] <First p-type electron blocking layer> A first p-type electron blocking layer 145 made of a III-V compound semiconductor layer may be provided on the first active layer 144, and the thickness thereof is preferably 5 nm to 60 nm. Dopants that can be used here include Mg, Zn, C, and Be. The p-type dopant concentration is 1.0×10 １８ / cm ３ Above 5.0 x 10 １８ / cm ３ The first p-type electron blocking layer 145 is a layer that injects and confines carriers into the first active layer 144. The first p-type electron blocking layer 145 also has the effect of reducing the diffusion of p-type dopants from the tunnel junction layer 147 (described later) to the first active layer 144.

[0040] The composition of the first p-type electron blocking layer 145 is Al ｚ１ In １－ｚ１ As (0.05≦z1≦0.40) is preferred, and Al ｚ１ In １－ｚ１ It is more preferable that the Al composition z1 is As (0.10≦z1≦0.35). This is because the luminous efficiency of the first p-type electron blocking layer 145 can be improved by setting the Al composition z1 to 0.05 or more, and the luminous efficiency can be prevented from decreasing due to an increase in forward voltage by setting the Al composition z1 to 0.40 or less. In addition, the p-type dopant concentration of the first p-type electron blocking layer 145 is preferably lower than the p-type dopant concentration doped in the p-type tunnel junction layer 1471 described below.

[0041] A first p-type window layer 146 may be further provided on the first p-type electron blocking layer 145. The composition of the first p-type window layer 146 preferably has a smaller Al composition than the composition z1 of the first p-type electron blocking layer 145, and is, for example, InAs. The p-type dopant concentration is 1.0×10 １８ / cm ３ Above 5.0 x 10 １８ / cm ３ It is preferable that:

[0042] The p-type intermediate layer between the first active layer 144 and the tunnel junction layer 147 may include a layer other than the first p-type electron blocking layer 145 or the first p-type window layer 146. Even in this case, in the present invention, the dopant concentration in the tunnel junction layer 147 can be kept low, so that even if p-type dopant diffusion from the p-type tunnel junction layer 1471 occurs, the p-type dopant concentration in the p-type intermediate layer can be kept low, for example, at 5.0×10 １８ / cm ３ The total thickness between the first active layer 144 and the tunnel junction layer 147 can be reduced to 100 nm or less. By reducing the thickness in this manner while suppressing the amount of dopant diffusion, it is expected that the forward voltage of the entire device can be reduced.

[0043] <Tunnel Junction Layer> A tunnel junction layer 147 composed of a p-type tunnel junction layer 1471 and an n-type tunnel junction layer 1472 made of InAs is provided on the first p-type window layer 146. The thickness of the tunnel junction layer 147 is preferably 10 nm to 200 nm. Dopants that can be used for the p-type tunnel junction layer 1471 include Mg, Zn, C, and Be, while dopants that can be used for the n-type tunnel junction layer 1472 include Si, Te, S, Ge, Sn, and Se. The p-type tunnel junction layer 1471 faces the first active layer 144, and the n-type tunnel junction layer 1472 faces the second active layer 149. The thicknesses and dopant concentrations of the p-type tunnel junction layer 1471 and the n-type tunnel junction layer 1472 may be the same or different. Furthermore, the dopant concentrations of the p-type tunnel junction layer 1471 and the n-type tunnel junction layer 1472 do not need to be uniform within the layers, and may have a concentration gradient.

[0044] Normally, to form a tunnel junction, the doping rate of the semiconductor must be extremely high, and the depletion layer that occurs at the junction between the n-type semiconductor layer and the p-type semiconductor layer must be thin enough to allow quantum tunneling. For compound semiconductors, this requires a doping rate of at least 1.0 × 10 １９ / cm ３ or more (preferably 1.0 × 10 ２０ / cm ３ However, in the present invention, a dopant concentration of 1.0×10１８ / cm ３ Above 1.0 x 10 １９ / cm ３ The tunnel junction layer 147 has a dopant concentration of 5.0×10 １８ / cm ３ Above 9.0 x 10 １８ / cm ３ Since less diffusion of dopants into the first active layer 144 and the second active layer 149 leads to improved characteristics such as reliability, it is preferable that the dopant concentration in the tunnel junction layer 147 be low as long as quantum tunneling can be generated.

[0045] <<P-Type Tunnel Junction Layer>> The p-type dopant concentration in the p-type tunnel junction layer 1471 is 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ Preferably, it is less than 9.0 × 10 １８ atoms / cm ３ The film thickness is preferably 5 nm or more and 100 nm or less.

[0046] <<N-Type Tunnel Junction Layer>> The n-type dopant concentration in the n-type tunnel junction layer 1472 is 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ Preferably, it is less than 9.0 × 10 １８ atoms / cm ３ The film thickness is preferably 5 nm or more and 100 nm or less.

[0047] <N-Type Intermediate Layer Between Tunnel Junction Layer and Second Active Layer> An n-type intermediate layer is provided between the tunnel junction layer 147 and the second active layer 149 described below. The n-type intermediate layer may be an undoped layer. The film thickness between the tunnel junction layer 147 and the second active layer 149 is preferably 100 nm or less. This n-type intermediate layer preferably includes a spacer layer.

[0048] <Second Spacer Layer> A second spacer layer 148 may be provided on the tunnel junction layer 147, and its thickness is preferably 1 nm to 100 nm. The second spacer layer 148 may have the same composition as the n-type tunnel junction layer 1472 of the tunnel junction layer 147 or the barrier layer of the second active layer 149, or may have a composition that provides a larger band gap than the barrier layer. It is preferable that the second spacer layer 148 be an undoped layer that is not intentionally doped by not flowing an n-type dopant source gas during growth. This second spacer layer 148 reduces the diffusion of n-type dopants from the n-type tunnel junction layer 1472 of the tunnel junction layer 147 into the second active layer 149.

[0049] A layer other than the second spacer layer 148 may be included between the second active layer 149 and the tunnel junction layer 147. Even in this case, the present invention can keep the dopant concentration in the tunnel junction layer 147 low, so that even if n-type dopant diffusion occurs from the n-type tunnel junction layer 1472, the n-type dopant concentration in the n-type intermediate layer can be kept low, for example, 5.0×10 １８ / cm ３ It is also possible to suppress the total film thickness between the second active layer 149 and the tunnel junction layer 147 to 100 nm or less. By reducing the thickness in this manner while suppressing the amount of dopant diffusion, it is expected that the forward voltage of the entire device can be reduced.

[0050] <Second Active Layer> A second active layer 149 containing Sb is provided on the second spacer layer 148. The second active layer 149 preferably has the same structure as the first active layer 144. For example, in FIG. 1, the second active layer 149 is an InAs well layer that serves as a light-emitting layer. ｘ２ Sb １－ｘ２ layer (0<x2<1) and barrier layer InAs ｙ２ P １－ｙ２ Although the figure shows a quantum well structure consisting of layers (0<y2<1), it is preferable that the well layer 149w of the second active layer has the same structure as the well layer 144w of the first active layer, and that the barrier layer 149b of the second active layer has the same structure as the barrier layer 144b of the first active layer. Furthermore, the first active layer 144 and the second active layer 149 have the same emission wavelength, and have a wavelength range in which the emission center wavelength is 3000 nm or more.

[0051] <Second p-type electron blocking layer> A second p-type electron blocking layer 150 made of a III-V compound semiconductor layer may be provided on the second active layer 149, and the thickness thereof is preferably 5 nm to 60 nm. Dopants that can be used here include Mg, Zn, C, and Be. The dopant concentration is 1.0×10 １８ / cm ３ Above 5.0 x 10 １８ / cm ３ The second p-type electron blocking layer 150 is a layer that injects and confines carriers into the second active layer 149. The second p-type electron blocking layer 150 also has the effect of reducing the diffusion of dopants from the second p-type window layer 151 to the second active layer 149.

[0052] The composition of the second p-type electron blocking layer 150 is Al ｚ２ In １－ｚ２ As (0.05≦z2≦0.4) is preferred, and Al ｚ２ In １－ｚ２ It is more preferable that the Al composition z2 is As (0.10≦z2≦0.35). By setting the Al composition z2 to 0.05 or more, the light-emitting efficiency of the second p-type electron blocking layer 150 can be improved, and by setting it to 0.40 or less, it is possible to prevent a decrease in light-emitting efficiency due to an increase in forward voltage. In addition, the p-type dopant concentration of the second p-type electron blocking layer 150 is preferably lower than the p-type dopant concentration doped in the p-type tunnel junction layer 1471.

[0053] <Second p-type window layer> A second p-type window layer 151 made of a III-V compound semiconductor layer may be provided on the second p-type electron blocking layer 150, and its thickness is preferably 500 nm or more and 2000 nm or less. If the second p-type window layer 151 is thicker than this, the current will spread to the edge of the LED chip, increasing surface recombination, and the ohmic resistance of the element will increase, reducing the light-emitting efficiency, which is undesirable. On the other hand, if the second p-type window layer 151 is thinner than this, it will emit light directly below the electrode, which will hinder light extraction, which is undesirable. Dopants that can be used here include Mg, Zn, C, Be, etc. The dopant concentration of the second p-type window layer 151 should be 1.0 x 10 １８ atoms / cm３ Above 5.0 x 10 １８ atoms / cm ３ It is preferable that:

[0054] <P-Type Contact Layer> A p-type contact layer 152 made of a III-V compound semiconductor layer may be provided on the second p-type window layer 151. The thickness of the p-type contact layer 152 is preferably 20 nm or more and 300 nm or less. The dopant concentration of the p-type contact layer 152 is higher than that of the second p-type window layer 151, and is 8.0×10 １８ atoms / cm ３ Above 3.0 x 10 １９ atoms / cm ３ It is preferable that:

[0055] An example of an embodiment of the manufacturing method of the optical semiconductor device 100 described above will be described below. When the growth substrate 105 is n-type or undoped, the optical semiconductor device 100 is manufactured through a process of epitaxially growing a first active layer 144, a tunnel junction layer 147 made of InAs, and a second active layer 149 in sequence. Here, the first active layer 144 and the second active layer 149 contain Sb, and the tunnel junction layer 147 is formed by vertically stacking a p-type tunnel junction layer 1471 formed of a p-type InAs layer and an n-type tunnel junction layer 1472 formed of an n-type InAs layer. The first active layer 144 and the p-type tunnel junction layer 1471 face each other, and the n-type tunnel junction layer 1472 and the second active layer 149 face each other. The dopant concentration of the tunnel junction layer 147 is 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ is less than.

[0056] A first p-type electron blocking layer 145 or a first p-type window layer 146 having a total thickness of 100 nm or less may be formed between the first active layer 144 and the tunnel junction layer 147, and an undoped second spacer layer 148 having a thickness of 100 nm or less may be formed between the tunnel junction layer 147 and the second active layer 149.

[0057] Furthermore, one or more layers of an n-type contact layer 141, an n-type window layer 142, and a first spacer layer 143 may be formed between the growth substrate 105 and the first active layer 144, and one or more layers of a second p-type electron blocking layer 150, a second p-type window layer 151, and a p-type contact layer 152 may be formed on the second active layer.

[0058] On the other hand, if the growth substrate 105 for epitaxially growing each semiconductor layer of the semiconductor stack 140 is p-type, the second active layer 149, the tunnel junction layer 147, and the first active layer 144 are formed in this order on the growth substrate 105. At this time, the second active layer 149 and the n-type tunnel junction layer 1472 face each other, and the p-type tunnel junction layer 1471 and the first active layer 144 face each other.

[0059] Each semiconductor layer can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). For example, a semiconductor layer can be formed by using trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) or triethylgallium (TEGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, and arsine (AsH) as an As source. ３ ) or tertiarybutylarsine (TBAs), trimethylantimony (TMSb), triethylantimony (TESb), or trisdimethylaminoantimony (TDMASb) as an Sb source, phosphine (PH ３ ) or tertiary butyl phosphine (TBP) are used in a predetermined mixture ratio, and these source gases are vapor-phase grown using a carrier gas, allowing the desired thickness to be formed depending on the growth time. When doping each layer to p-type or n-type, a dopant source gas may be further used as desired. For example, when doping with Zn, DEZn (diethyl zinc) gas may be used. Note that InAs is also n-type even when undoped.

[0060] In FIG. 1 , a lower electrode 195 is provided on the back surface of the growth substrate 105. Furthermore, an upper electrode 191 is provided on a portion of the p-type contact layer 152. The upper electrode 191 may include a wiring portion and a pad portion of an ohmic electrode, and although not shown, the pad portion may have a metal layer or solder for bonding. Known metal materials and formation methods can be used for the upper electrode 191 and the lower electrode 195. Examples of usable metal materials include Ti, Pt, Au, Ag, Al, Zn, and Ni.

[0061] When a forward voltage is applied from the upper electrode 191 to the lower electrode 195, the forward voltage is applied to the first active layer 144 and the second active layer 149, causing both the first active layer 144 and the second active layer 149 to emit light. At this time, a reverse voltage is applied to the tunnel junction (pn junction) in the tunnel junction layer 147. As a result, a current flows in the tunnel junction layer 147 due to the tunnel effect.

[0062] Second Embodiment An optical semiconductor element 200 according to a second embodiment of the present invention will be described with reference to FIG. 2 . The optical semiconductor element 200 is a bonded-type optical semiconductor element obtained by bonding a support substrate and then removing the growth substrate. In principle, components identical to those of the optical semiconductor element 100 are designated by the same reference numerals, the last two digits of which are three digits, and redundant explanations will be omitted. The optical semiconductor element 200 includes at least a support substrate 280, a metal bonding layer 279 and a metal reflective layer 271 provided on the surface of the support substrate 280, a power distribution unit 260 having a transparent insulating layer 261 with through-holes on the metal reflective layer 271 and ohmic electrode portions 265 provided in the through-holes, and a semiconductor laminate 240 provided on the power distribution unit 260.

[0063] The semiconductor laminate 240 in the optical semiconductor element 200 in FIG. 2 has, in order from the side opposite to the support substrate 280, an n-type contact layer 241, an n-type window layer 242, a first spacer layer 243, a first active layer 244, a first p-type electron blocking layer 245, a first p-type window layer 246, a tunnel junction layer 247, a second spacer layer 248, a second active layer 249, a second p-type electron blocking layer 250, a second p-type window layer 251, and a p-type contact layer 252.

[0064] The support substrate 280, which is different from the growth substrate, is preferably cheaper and has higher thermal conductivity than the growth substrate, and may be, for example, a compound substrate such as Si, Ge, or GaAs, or a metal substrate using a metal that can suppress the thermal expansion coefficient, such as copper alloy, molybdenum, tungsten, or Kovar, or a submount substrate in which a metal is attached to a ceramic substrate such as AlN. From the standpoint of processability and cost, it is also preferable to use a Si substrate as the support substrate 280.

[0065] An example of an embodiment of the optical semiconductor element 200 and a manufacturing method thereof will be described in more detail below with reference to FIGS. 3 to 5. First, a growth substrate 205 is prepared. Then, with reference to FIG. 3, a semiconductor laminate 240 is formed. At this time, an etching stop layer (not shown) may be formed on the growth substrate 205. The semiconductor laminate 240 is similar to the semiconductor laminate 140 described above.

[0066] <Formation of Power Distribution Section> A power distribution section 260 including a transparent insulating layer 261 with through holes and ohmic electrode sections 265 provided in the through holes is formed on the p-type contact layer 252. Any specific method may be used to form the power distribution section 260, but an example of a specific mode for forming the power distribution section 260 will be described below with reference to FIGS.

[0067] First, the transparent insulating layer 261 is formed on the semiconductor stack 240. Known techniques such as plasma CVD and sputtering can be used as the film formation method. Then, a resist pattern for the power distribution section is formed on the transparent insulating layer 261 using a photomask. Next, a portion of the transparent insulating layer 261 is removed by etching using the resist pattern to form a through-hole. By providing the through-hole, a portion of the outermost surface of the semiconductor stack 240 is exposed. The ohmic electrode section 265 is then formed, followed by lift-off using the resist pattern, thereby forming the power distribution section 260. The transparent insulating layer 261 and the ohmic electrode section 265 are arranged in parallel in the power distribution section 260. For simplification, the ohmic electrode section 265 is illustrated filling the through-hole, but this is not limited thereto, and a gap may be formed between the transparent insulating layer 261 and the ohmic electrode section 265.

[0068] The ohmic electrode portions 265 can be formed by dispersing them in islands in a predetermined pattern. For example, Au, AuZn, AuBe, AuTi, etc. can be used as the ohmic electrode portions 265, and it is also preferable to use a laminate structure of these. For example, Ti / Au can be used as the ohmic electrode portions 265. The film thickness (or total film thickness) of the ohmic electrode portions 265 is not limited, but can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm.

[0069] <Formation of Metal Reflective Layer> As shown in FIG. 4 , it is also preferable to form a metal reflective layer 271 on the power distribution unit 260. The metal reflective layer 271 may include multiple metal layers. The metal reflective layer 271 may include, in addition to Au, Al, Pt, Ti, Ag, or the like. For example, the metal reflective layer 271 may be a single layer composed of Au alone, or may include two or more Au metal layers. The metal reflective layer 271 preferably contains 50% or more by mass of Au in its composition. To ensure reliable bonding with the metal bonding layer 279 in a subsequent process, it is preferable that the outermost layer of the metal reflective layer 271 (the surface opposite the semiconductor laminate 240) be an Au metal layer.

[0070] For example, metal reflective layer 271 can be formed by depositing metals in the order of Al, Au, Pt, and Au on power distribution section 260 (including the gap if one is provided). The thickness of the Au layer in metal reflective layer 271 can be, for example, 400 nm to 2000 nm, and the thickness of the metal layers made of metals other than Au can be, for example, 5 nm to 200 nm. Metal reflective layer 271 can be formed by deposition using a common method such as vapor deposition.

[0071] <Bonding to Support Substrate> The bonding to the support substrate 280 will be described with reference to Fig. 4. The semiconductor stack 240 and the power distribution section 260 are bonded to the support substrate 280 via at least a metal bonding layer 279. By providing a metal reflective layer 271, the metal reflective layer 271 and the metal bonding layer 279 may be bonded. The metal bonding layer 279 and the metal reflective layer 271 can be bonded by arranging them facing each other and bonding them together, and performing thermal compression bonding at a temperature of about 250°C to 500°C.

[0072] <Metal Bonding Layer> The metal bonding layer 279 can be formed using a metal such as Ti, Pt, or Au, or a metal that forms a eutectic alloy with Au (such as Sn), or solder, and is preferably formed by stacking these. For example, the metal bonding layer 279 can be formed by stacking, in order from the surface of the support substrate 280, Ti with a thickness of 400 nm to 800 nm, Pt with a thickness of 5 nm to 20 nm, and Au with a thickness of 700 nm to 1200 nm. For example, when bonding the metal reflective layer 271 and the metal bonding layer 279, the outermost layer of the metal bonding layer 279 can be made of Au metal, and the outermost layer of the metal reflective layer 271 can also be made of Au, and bonding between the Au layers can be performed by Au-Au diffusion.

[0073] <Support Substrate> The support substrate 280 may be a substrate of a different type from the growth substrate 205, and may be a submount substrate based on the semiconductor substrate, metal substrate, or ceramic substrate described above. Because the above-described bonding method is used, the support substrate 280 may be lattice-mismatched with the semiconductor layers formed in this embodiment. While the support substrate 280 may be insulating depending on the application, a conductive substrate is preferred. From the standpoints of processability and cost, a Si substrate is preferably used for the support substrate 280. By using a Si substrate, the thickness of the support substrate 280 can be significantly reduced compared to conventional substrates, making it suitable for implementation in combination with various semiconductor devices. Furthermore, Si substrates are advantageous in terms of heat dissipation compared to InAs substrates.

[0074] <Removal of Growth Substrate> The removal of the growth substrate will be described with reference to FIG. 5 . After bonding the support substrate 280, the growth substrate 205 is removed. When the growth substrate 205 is a GaAs substrate, the growth substrate 205 can be wet-etched using, for example, an ammonia-hydrogen peroxide mixture. When an etching stop layer is used, the etching stop layer may be sequentially removed following the removal of the growth substrate 205. Furthermore, by leaving a portion of the etching stop layer, it may be used as an n-type contact layer that reduces contact resistance with the upper electrode 291.

[0075] Furthermore, as shown in FIG. 2 , an upper electrode 291 may be formed on the semiconductor laminate 240, and a back electrode 295 may be formed on the back surface of the support substrate 280. The upper electrode 291 may include a wiring portion and a pad portion. The upper electrode 291 and the back electrode 295 can be formed by a known method, such as sputtering, electron beam evaporation (also referred to as evaporation), or resistance heating. The electrode pattern can be formed by a method using a metal mask, or by a method using a combination of photolithography, lift-off, and metal etching.

[0076] The above manufacturing method can provide the optical semiconductor element 200 shown in Fig. 2. These embodiments are merely examples and are not limiting, and suitable modifications are possible, such as providing a slope on the side surface of the element during mesa etching, or the electrode shape may be two electrodes on the top surface or a flip chip.

[0077] Third Embodiment Next, an optical semiconductor device 300 according to a third embodiment of the present invention will be described with reference to FIG. 6 . The third embodiment is an embodiment in which a tunnel junction layer and an active layer are further formed on the second p-type window layer of the first embodiment. Specifically, the semiconductor light emitting device of FIG. 6 has a second tunnel junction layer 352, a third active layer 354, a third tunnel junction layer 357, and a fourth active layer 359, sequentially formed on the second p-type window layer. Each component will be described in detail below.

[0078] The second tunnel junction layer 352 has a p-type InAs layer 3521 and an n-type InAs layer 3522, similar to the tunnel junction layer 147 of the first embodiment. The p-type InAs layer 3521 faces the second active layer, and the n-type InAs layer 3521 faces the third active layer 354. The second tunnel junction layer 352 may have the same composition and film thickness as the first tunnel junction layer, or may have different composition and film thickness.

[0079] The third active layer 354 is an InAs layer that serves as a light-emitting layer similar to the first active layer. ｘ３ Sb １－ｘ３ The third active layer 354 includes a layer (0<x3<1) and has the same emission wavelength as the first active layer. The third active layer 354 may have the same composition and thickness as the first active layer, or may have a different composition and thickness.

[0080] The third tunnel junction layer 357 has a p-type InAs layer 3571 and an n-type InAs layer 3572, similar to the tunnel junction layer 147 of the first embodiment. The p-type InAs layer 3571 faces the third active layer 354, and the n-type InAs layer 3572 faces the fourth active layer 359. The third tunnel junction layer 357 may have the same composition and film thickness as the first tunnel junction layer, or may have different composition and film thickness.

[0081] The fourth active layer 359 is an InAs light-emitting layer, similar to the first active layer. ｘ４ Sb１－ｘ４ The fourth active layer 359 includes a layer (0<x4<1) and has the same emission wavelength as the first active layer. The fourth active layer 359 may have the same composition and film thickness as the first active layer, or may have a different composition and film thickness.

[0082] The layers above the fourth active layer 359 have the same configuration as the layers above the second active layer 149 in the first embodiment.

[0083] In the third embodiment described above, a total of three tunnel junction layers and four active layers are formed by depositing the second tunnel junction layer 352, the third active layer 354, the third tunnel junction layer 357, and the fourth active layer 359 on the second electron blocking layer. In this embodiment, instead of the embodiment shown in FIG. 6 , a total of N tunnel junction layers (where N is an integer equal to or greater than N) may be formed, and a total of (N+1) active layers may be formed. For example, a total of two tunnel junction layers may be formed, and a total of three active layers may be formed, or a total of four tunnel junction layers may be formed, and a total of five active layers may be formed. The embodiment shown in FIG. 6 is a specific example where N is 3. Even in this case, the dopant concentration of each tunnel junction layer is 1×10 １８ atoms / cm ３ 1x10 or more １９ atoms / cm ３ The wavelengths of the active layers are equal to or greater than 3000 nm and have the same center wavelength.

[0084] (Fourth Embodiment: Photodetector) A semiconductor optical photodetector according to a fourth embodiment of the present invention will be described. For example, by replacing the first active layer 144 and the second active layer 149 in the first embodiment with an InAsSb first optical absorption layer and an InAsSb second optical absorption layer, the semiconductor optical photodetector of the present invention can be used as a semiconductor optical photodetector. Furthermore, since the semiconductor photodetector according to the present invention has two absorption layers via a tunnel junction layer, dark current is reduced compared to a case where only one absorption layer is used, and a semiconductor photodetector with high shunt resistance and excellent characteristics can be realized.

[0085] Experimental Example 1 (Example 1) First, a high dopant concentration (Te concentration 1.0×10 １９ / cm ３ ) n-type InAs contact layer (thickness: 0.3 μm), Te-doped n-type InAs window layer (thickness: 4.9 μm, Te concentration: 3.0×10 １８ / cm ３ Then, a first active layer (total thickness: 430 nm) with a quantum well structure having a central emission wavelength of 4300 nm was formed. The active layer with the quantum well structure was made of undoped InAs. ０．９０ P ０．１０ Barrier layer (thickness: 30 nm) and InAs ０．８７ Sb ０．１３ After stacking 10 well layers (10 nm after film formation) alternately, InAs ０．９０ P ０．１０ The barrier layers were grown to form 10.5 sets, including the last barrier layer. Zn-doped p-type Al was grown on the first active layer. ０．３２ In ０．６８ As electron blocking layer (thickness: 15 nm, Zn concentration: 2.5×10 １８ / cm ３ ) and a Zn-doped p-type InAs window layer (thickness: 50 nm, Zn concentration: 2.5×10 １８ / cm ３ ) was formed on the substrate, and a tunnel junction layer was formed thereon.

[0086] The tunnel junction layer is a Zn-doped InAs layer (thickness: 50 nm, Zn concentration during growth: 8×10 １８ / cm ３ ), a Te-doped InAs layer (thickness: 50 nm, Te concentration during growth: 8×10 １８ / cm ３ The tunnel junction layer was grown under a pressure of 50 Torr, with the ratio of group V elements to group III elements (VIII ratio) in the source gas being 50.

[0087] Next, an undoped InAs spacer layer (thickness: 75 nm) was formed on the tunnel junction layer, and a second active layer (total thickness: 430 nm) identical to the first active layer was formed on the undoped InAs spacer layer. Zn-doped p-type Al ０．３２ In ０．６８As electron blocking layer (thickness: 15 nm, Zn concentration: 2.5×10 １８ / cm ３ Furthermore, a Zn-doped p-type InAs window layer (thickness: 900 nm, Zn concentration: 2.5×10 １８ / cm ３ ) and then a high dopant concentration (Zn concentration 1.0×10 １９ / cm ３ A p-type InAs contact layer (thickness: 100 nm) was formed on the substrate. Table 1 below lists the composition and thickness of each layer, the type of dopant, the (designed) dopant concentration during growth, and the dopant concentration determined by SIMS analysis, including dopant diffusion, after all epitaxial growth was completed and the substrate was removed from the MOCVD reactor. The source gases selected for forming each layer were trimethylindium (TMIn) as the In source, trimethylgallium (TMGa) as the Ga source, trimethylaluminum (TMAl) as the Al source, and arsine (AsH) as the As source. ３ ), triethylantimony (TESb) as an Sb source, phosphine (PH ３ ) In addition, DEZn (diethyl zinc) and DETe (diethyl tellurium) were used as dopant gases.

[0088] The composition of each layer was measured using a BRUKER JV-QC3 XRD device. The composition of each layer was calculated by fitting using analytical software (Jordan Valley RADS). The thickness of each layer was calculated from cross-sectional observation of the grown layer using a SEM (scanning electron microscope) or TEM (transmission electron microscope).

[0089]

[0090] Next, SiO is deposited on the entire surface of the p-type InAs contact layer by plasma CVD. ２ A transparent insulating layer (film thickness: 550 nm) made of SiO was formed on the insulating layer. A power distribution pattern was formed on the insulating layer using resist, and the SiO was removed from the area not covered by the resist. ２The Zn-doped p-type InAs contact layer was exposed by etching. Next, Ti (film thickness: 10 nm) and Au (film thickness: 530 nm) were deposited as ohmic metal layers by vapor deposition. The resist pattern for the power distribution section was then removed along with the metal deposited thereon, leaving only the ohmic metal layer formed on the exposed Zn-doped p-type InAs contact layer. This resulted in a power distribution section in which the ohmic metal layer and the transparent insulating film were arranged in parallel. Next, a metal reflective layer (Al (film thickness: 10 nm / Au (film thickness: 650 nm) / Pt (film thickness: 100 nm) / Au (film thickness: 900 nm))) was formed on the power distribution section by vapor deposition.

[0091] Next, a metal bonding layer (Ti (film thickness: 650 nm) / Pt (film thickness: 20 nm) / Au (film thickness: 900 nm)) was formed on a support substrate (Si substrate) by vapor deposition. Next, the metal reflective layer and the metal bonding layer were arranged facing each other and subjected to thermal compression bonding at 300°C. Next, the growth substrate was removed by wet etching using an ammonia-hydrogen peroxide mixture to expose the n-type contact layer. Next, Ti (film thickness: 150 nm) / Au (film thickness: 1250 nm) was formed on the n-type contact layer by vapor deposition to form an n-type ohmic electrode. Next, a pad electrode (Ti (film thickness: 150 nm) / Pt (film thickness: 100 nm) / Au (film thickness: 2500 nm)) was formed on the n-type ohmic electrode by vapor deposition, and the n-type ohmic electrode and pad electrode combined to form an upper electrode. The electrode pattern was formed using a resist lift-off method.

[0092] Next, mesa etching was performed to remove the semiconductor stack between each element (width: 60 μm) to form dicing lines. Then, a back electrode (Ti (film thickness: 10 nm) / Pt (film thickness: 50 nm) / Au (film thickness: 200 nm)) was formed on the back side of the support substrate by vapor deposition, and alloyed by heat treatment at 300°C for 1 minute. Next, the entire wafer was immersed in a nitric acid solution maintained at 8°C ± 1°C for 5 seconds to roughen the surface of the semiconductor stack except for the area where the upper electrode was formed. After that, it was immersed in ammonia water for 1 minute and then washed with pure water for 1 minute. Finally, the wafer was diced into individual chips to produce the optical semiconductor element according to Example 1. The chip size was 500 μm × 500 μm.

[0093] 7 is a graph showing the results of measurement by secondary ion mass spectrometry (SIMS) of the diffusion state of Te ions in the optical semiconductor element fabricated in Example 1. In FIG. 7, the horizontal axis represents depth (μm), and the vertical axis on the left represents the concentration (atoms / cm) of n-type dopants (here, Te, Si, C, H, and O). ３ ), and the vertical axis on the right side represents the secondary ion intensity (counts / sec) of Sb. In the case of Example 1, the maximum concentration of Te, which is an n-type dopant doped into the semiconductor laminate 140, is 8.0×10 １８ atoms / cm ３ The position where the maximum value was reached was the position corresponding to the n-type tunnel junction layer, and diffusion of Te from the n-type tunnel junction layer toward the undoped spacer layer and the first barrier layer was observed. However, even if the Te concentration in the spacer layer and the first barrier layer increased due to diffusion, it was still 4.0 × 10 １８ atoms / cm ３ The Te concentration was able to be kept within a preferable range.

[0094] 8 is a graph showing the results of measuring, by SIMS, the state of diffusion of Zn ions in the optical semiconductor element fabricated in Example 1. In FIG. 8, the horizontal axis represents depth (μm), and the vertical axis on the left represents the concentration (atoms / cm) of the p-type dopant (Zn in this case). ３ ), and the vertical axis on the right side represents the secondary ion intensity (counts / sec). In the case of Example 1, the maximum concentration of Zn, which is a p-type dopant doped into the semiconductor laminate 140, is 6.0×10 １８ atoms / cm ３ The position where the maximum value was reached was the position corresponding to the p-type tunnel junction layer, and Zn diffusion from the p-type tunnel junction layer toward the p-type window layer and the electron block layer was observed. However, even if the Zn concentration in the p-type window layer and the electron block layer increased due to diffusion, it was still within 5.0 × 10 １８ atoms / cm ３ The Zn concentration was kept within the preferred range.

[0095] Example 2 Similar to Example 1, each semiconductor layer up to the second active layer was epitaxially grown. Next, a second tunnel junction layer, a third active layer, a third tunnel junction layer, and a fourth active layer were formed in that order on the second active layer. Similar to Example 1, an electron block layer, a p-type window layer, and a p-type contact layer were formed in that order on the fourth active layer. The third active layer and the fourth active layer had the same film thickness and composition as the first active layer, and the second tunnel junction layer and the third tunnel junction layer had the same film thickness and composition as the first tunnel junction layer. Between the second active layer and the second tunnel junction layer and between the third active layer and the third tunnel junction layer, electron block layers with the same film thickness and composition as the electron block layer between the first active layer and the first tunnel junction layer were formed. Furthermore, between the second tunnel junction layer and the third active layer and between the third tunnel junction layer and the fourth active layer, spacer layers with the same film thickness and composition as the spacer layer between the first tunnel junction layer and the second active layer were formed. The composition and thickness of each layer, the type of dopant and the dopant concentration during growth, and the dopant concentration determined by SIMS analysis, including dopant diffusion, are shown in Table 2. The dopant concentration was diffused in the same manner as in Example 1, and the amount of diffusion was kept within a preferred range.

[0096]

[0097] Comparative Example 1 An optical semiconductor device according to Comparative Example 1 was obtained in the same manner as in Example 1, except that the film thickness of the second active layer was changed from 430 nm to 0 nm, the film thickness of the spacer layer on the tunnel junction layer was changed from 75 nm to 0 nm, the film thickness of the Te-doped InAs layer in the tunnel junction layer was changed from 50 nm to 0 nm, the film thickness of the Zn-doped InAs layer in the tunnel junction layer was changed from 50 nm to 0 nm, and the film thickness of the electron blocking layer below the tunnel junction layer was changed from 15 nm to 0 nm, and the number of well layers and barrier layers in the quantum well structure of the first active layer was 20.5 pairs (total film thickness: 860 nm).

[0098] <Evaluation: Light Emission Output Evaluation> A current of 100 mA was applied to the optical semiconductor devices obtained from the above Examples and Comparative Examples using a constant current voltage power supply. The forward voltage Vf (V) and light emission output Po (W) were measured using an integrating sphere. The leakage current (A) was also measured when a reverse voltage of -0.1 V was applied. The results are shown in Table 3.

[0099]

[0100] From the above results, it was confirmed that increasing the number of PN junctions (number of active layers) and the number of tunnel junctions increases the light emission output and forward voltage, and further reduces the leakage current.

[0101] According to the present invention, it is possible to provide an optical semiconductor device comprising two or more active layers containing Sb with a tunnel junction layer made of InAs interposed therebetween, and a method for manufacturing the same.

[0102] 100 Optical semiconductor element 105 Growth substrate 140 Semiconductor laminate 141 n-type contact layer 142 n-type window layer 143 First spacer layer 144 First active layer 144b Barrier layer of first active layer 144w Well layer of first active layer 145 First p-type electron blocking layer 146 First p-type window layer 147 Tunnel junction layer 1471 P-type tunnel junction layer 1472 N-type tunnel junction layer 148 Second spacer layer 149 Second active layer 149b Barrier layer of second active layer 149w Well layer of second active layer 150 Second p-type electron blocking layer 151 Second p-type window layer 152 P-type contact layer 191 Upper electrode 195 Lower electrode 200 Optical semiconductor element 205 Growth substrate 240 Semiconductor laminate 241 N-type contact layer 242 n-type window layer 243 First spacer layer 244 First active layer 245 First p-type electron blocking layer 246 First p-type window layer 247 Tunnel junction layer 248 Second spacer layer 249 Second active layer 250 Second p-type electron blocking layer 251 P-type window layer 252 P-type contact layer 260 Power distribution section 261 Transparent insulating layer 265 Ohmic electrode section 271 Metal reflective layer 279 Metal junction layer 280 Support substrate 291 Upper electrode 295 Back electrode 300 Optical semiconductor element 352 Second tunnel junction layer 3521 P-type InAs layer of second tunnel junction layer 3522 N-type InAs layer of second tunnel junction layer 354 Third active layer 357 Third tunnel junction layer 3571 P-type InAs layer of third tunnel junction layer 3572 n-type InAs layer of the third tunnel junction layer359 4th active layer

Claims

1. An optical semiconductor element having a first active layer having an emission and reception wavelength of a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer having an emission and reception wavelength of a second wavelength, wherein the first active layer and the second active layer contain Sb, and the tunnel junction layer has a p-type InAs layer and an n-type InAs layer.

2. The tunnel junction layer has a dopant concentration of 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ The optical semiconductor device according to claim 1 , 3. The optical semiconductor element according to claim 1 or 2, wherein the first active layer and the second active layer have a quantum well structure, and the first wavelength and the second wavelength are 3000 nm or longer.

4. The optical semiconductor element according to claim 1 or 2, wherein the first wavelength and the second wavelength are the same.

5. The optical semiconductor element according to claim 1 or 2, wherein the p-type InAs layer is on the first active layer side of the tunnel junction layer, a p-type electron blocking layer is between the first active layer and the tunnel junction layer, and a film thickness between the first active layer and the tunnel junction layer is 100 nm or less.

6. The optical semiconductor element according to claim 1 or 2, wherein the n-type InAs layer is disposed on the second active layer side of the tunnel junction layer, a spacer layer is disposed between the tunnel junction layer and the second active layer, and a film thickness between the tunnel junction layer and the second active layer is 100 nm or less.

7. A method for manufacturing an optical semiconductor device, comprising: forming a first active layer on a substrate, the first active layer having an emission and reception wavelength of a first wavelength; forming a tunnel junction layer on the first active layer; and forming a second active layer on the tunnel junction layer, the second active layer having an emission and reception wavelength of a second wavelength, wherein the first active layer and the second active layer contain Sb, and the step of forming the tunnel junction layer comprises the steps of forming an n-type InAs layer and forming a p-type InAs layer on the n-type InAs layer.

8. The tunnel junction layer has a dopant concentration of 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ The method for producing an optical semiconductor device according to claim 7 , wherein the

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