Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate is provided with a plurality of sub-pixels arranged in an array, and at least one of the sub-pixels comprises: a pixel driving circuit. The display substrate comprises: a base substrate and a driving structure layer arranged on the base substrate, and the pixel driving circuit is arranged on the driving structure layer. The driving structure layer at least comprises: a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fifth insulating layer, and a fourth conductive layer which are sequentially stacked on the base substrate. The fifth insulating layer is provided with a plurality of via holes, at least one of the via holes in the fifth insulating layer exposes the first planarization layer, and the thickness of the first planarization layer is greater than the thickness of the fifth insulating layer.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate having a plurality of sub-pixels arranged in an array, at least one sub-pixel including a pixel driving circuit, the display substrate including a substrate and a driving structure layer disposed on the substrate, the pixel driving circuit being disposed on the driving structure layer;

[0006] The driving structure layer at least includes: a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fifth insulating layer and a fourth conductive layer sequentially stacked on the substrate;

[0007] A plurality of via holes are provided on the fifth insulating layer, and at least one via hole on the fifth insulating layer exposes the first planar layer;

[0008] The thickness of the first planarizing layer is greater than the thickness of the fifth insulating layer.

[0009] In an exemplary embodiment, the pixel driving circuit includes: first to fifth transistors, the driving structure layer further includes: a first scan signal line, a second scan signal line, a third scan signal line, an initial signal line, a data signal line, a light emitting signal line, a reference signal line, and a first power line, the first transistor is electrically connected to the third scan signal line and the initial signal line, respectively, the second transistor is electrically connected to the second scan signal line and the reference signal line, respectively, the fourth transistor is electrically connected to the first scan signal line and the data signal line, respectively, and the fifth transistor is electrically connected to the light emitting signal line and the first power line, respectively;

[0010] Any one of the first scan signal line, the second scan signal line, the third scan signal line, the initial signal line, the light emitting signal line, the reference signal line and the first power line at least partially extends along a first direction, and the data signal line at least partially extends along a second direction, and the first direction intersects the second direction;

[0011] The reference signal line, the second scanning signal line, the first scanning signal line, the light emitting signal line, the first power line, the third scanning signal line and the initial signal line connected to any sub-pixel are arranged in sequence along the second direction;

[0012] The first planar layer is provided with first to fourth via holes, wherein an orthographic projection of the first via hole on the substrate is located within the range of an orthographic projection of the second electrode of the third transistor on the substrate, and exposes a surface of the second electrode of the third transistor; an orthographic projection of the second via hole on the substrate is located within the range of an orthographic projection of the first electrode of the fourth transistor on the substrate, and exposes a surface of the first electrode of the fourth transistor; an orthographic projection of the third via hole on the substrate is located within the range of an orthographic projection of the reference signal line on the substrate, and exposes the surface of the reference signal line; and an orthographic projection of the fourth via hole on the substrate is located within the range of an orthographic projection of the first power line on the substrate, and exposes a surface of the first power line;

[0013] The third via hole is located on a midline extending along the second direction between two adjacent fourth via holes.

[0014] In an exemplary embodiment, the fifth insulating layer is provided with fifth to eighth via holes, wherein:

[0015] The orthographic projection of the fifth via hole on the substrate is located within the range of the orthographic projection of the first via hole and the first flat layer on the substrate, the orthographic projection of the sixth via hole on the substrate is located within the range of the orthographic projection of the second via hole and the first flat layer on the substrate, the orthographic projection of the seventh via hole on the substrate is located within the range of the orthographic projection of the third via hole and the first flat layer on the substrate, and the orthographic projection of the eighth via hole on the substrate is located within the range of the orthographic projection of the fourth via hole and the first flat layer on the substrate.

[0016] In an exemplary embodiment, a length of the fifth via hole along the first direction is less than a length of the first via hole along the first direction, and a length of the fifth via hole along the second direction is less than a length of the first via hole along the second direction;

[0017] The length of the sixth via hole along the first direction is less than the length of the second via hole along the first direction, and the length of the sixth via hole along the second direction is less than the length of the second via hole along the second direction;

[0018] The length of the seventh via hole along the first direction is less than the length of the third via hole along the first direction, and the length of the seventh via hole along the second direction is less than the length of the third via hole along the second direction;

[0019] The length of the eighth via hole along the first direction is shorter than the length of the fourth via hole along the first direction, and the length of the eighth via hole along the second direction is shorter than the length along the second direction.

[0020] In an exemplary embodiment, within any sub-pixel, boundaries of the via hole include: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the first signal line, the second boundary of the via hole is a boundary of the via hole away from the first signal line, the third boundary of the via hole is a boundary located on one side of a first center line, and the fourth boundary of the via hole is a boundary located on the other side of the first center line. The via hole includes: a first via hole and a fifth via hole, the first signal line is one of a light emitting signal line, a first power line, a third scanning signal line, and an initial signal line connected to the sub-pixel, the first center line is a center line of the first via hole extending along the second direction, the third boundary of the first via hole and the third boundary of the fifth via hole are located on the same side of the first center line, and the fourth boundary of the first via hole and the fourth boundary of the fifth via hole are located on the same side of the first center line.

[0021] The distance between the orthographic projection of the first boundary of the first via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the fifth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the orthographic projection of the second boundary of the first via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the fifth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the third boundary of the first via and the first center line is greater than the distance between the orthographic projection of the third boundary of the fifth via on the substrate and the orthographic projection of the first center line on the substrate, and the distance between the fourth boundary of the first via and the first center line is greater than the distance between the orthographic projection of the fourth boundary of the fifth via on the substrate and the orthographic projection of the first center line on the substrate.

[0022] In an exemplary embodiment, within any sub-pixel, a distance between an orthographic projection of a first boundary of the first via hole and an orthographic projection of a first boundary of the fifth via hole on the substrate is greater than a distance between an orthographic projection of a third boundary of the first via hole and an orthographic projection of a third boundary of the fifth via hole on the substrate, and is less than a distance between an orthographic projection of a second boundary of the first via hole and an orthographic projection of a second boundary of the fifth via hole on the substrate.

[0023] A distance between an orthographic projection of a first boundary of the first via hole on the substrate and an orthographic projection of a first boundary of the fifth via hole on the substrate is approximately 1 micrometer to 2 micrometers.

[0024] In an exemplary embodiment, within any sub-pixel, boundaries of the via hole include: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the first signal line, the second boundary of the via hole is a boundary of the via hole away from the first signal line, the third boundary of the via hole is a boundary located on one side of a second center line, and the fourth boundary of the via hole is a boundary located on the other side of the second center line. The via hole includes: a second via hole and a sixth via hole. The first signal line is one of a light emitting signal line, a first power line, a third scanning signal line, and an initial signal line connected to the sub-pixel. The second center line is a center line of the second via hole extending along the second direction. The third boundary of the second via hole and the third boundary of the sixth via hole are located on the same side of the second center line. The fourth boundary of the second via hole and the fourth boundary of the sixth via hole are located on the same side of the second center line.

[0025] The distance between the orthographic projection of the first boundary of the second via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the sixth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the orthographic projection of the second boundary of the second via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the sixth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the third boundary of the second via and the second center line is greater than the distance between the orthographic projection of the third boundary of the sixth via on the substrate and the orthographic projection of the second center line on the substrate, and the distance between the fourth boundary of the second via and the second center line is greater than the distance between the orthographic projection of the fourth boundary of the sixth via on the substrate and the orthographic projection of the second center line on the substrate.

[0026] In an exemplary embodiment, within any sub-pixel, a distance between an orthographic projection of a first boundary of the second via hole and an orthographic projection of a first boundary of the sixth via hole on the substrate is greater than a distance between an orthographic projection of a third boundary of the second via hole and an orthographic projection of a third boundary of the sixth via hole on the substrate, and is less than a distance between an orthographic projection of a second boundary of the second via hole and an orthographic projection of a second boundary of the sixth via hole on the substrate.

[0027] A distance between an orthographic projection of a first boundary of the second via hole on the substrate and an orthographic projection of a first boundary of the sixth via hole on the substrate is approximately 1 micrometer to 2 micrometers.

[0028] In an exemplary embodiment, boundaries of the via hole include: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the second signal line, the second boundary of the via hole is a boundary of the via hole away from the second signal line, the third boundary of the via hole is a boundary located on one side of a third center line, and the fourth boundary of the via hole is a boundary located on the other side of the third center line. The via hole includes: a third via hole and a seventh via hole, the second signal line is one of a light emitting signal line, a first power line, a first scan signal line, a second scan signal line, a third scan signal line, an initial signal line, and a light emitting signal line connected to a sub-pixel connected to a reference signal line exposed by the third via hole, the third center line is a center line of the third via hole extending along the second direction, the third boundary of the third via hole and the third boundary of the seventh via hole are located on the same side of the third center line, and the fourth boundary of the third via hole and the fourth boundary of the seventh via hole are located on the same side of the third center line.

[0029] The distance between the orthographic projection of the first boundary of the third via on the substrate and the orthographic projection of the second signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the seventh via on the substrate and the orthographic projection of the second signal line on the substrate, the distance between the orthographic projection of the second boundary of the third via on the substrate and the orthographic projection of the second signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the seventh via on the substrate and the orthographic projection of the second signal line on the substrate, the distance between the third boundary of the third via and the third center line is greater than the distance between the orthographic projection of the third boundary of the seventh via on the substrate and the orthographic projection of the third center line on the substrate, and the distance between the fourth boundary of the third via and the third center line is greater than the distance between the orthographic projection of the fourth boundary of the seventh via on the substrate and the orthographic projection of the third center line on the substrate.

[0030] In an exemplary embodiment, a distance between an orthographic projection of a first boundary of the third via hole on the substrate and an orthographic projection of a first boundary of the seventh via hole on the substrate is greater than a distance between an orthographic projection of a third boundary of the third via hole on the substrate and an orthographic projection of a third boundary of the seventh via hole on the substrate, and is less than a distance between an orthographic projection of a second boundary of the third via hole on the substrate and an orthographic projection of a second boundary of the seventh via hole on the substrate;

[0031] A distance between an orthographic projection of a first boundary of the third via hole on the substrate and an orthographic projection of a first boundary of the seventh via hole on the substrate is approximately 1 micrometer to 2 micrometers.

[0032] In an exemplary embodiment, boundaries of the via hole include: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the third signal line, the second boundary of the via hole is a boundary of the via hole away from the third signal line, the third boundary of the via hole is a boundary located on one side of a fourth center line, and the fourth boundary of the via hole is a boundary located on the other side of the fourth center line. The via hole includes: a fourth via hole and an eighth via hole. The third signal line is any one of a third scanning signal line and an initial signal line connected to a sub-pixel connected to a first power line exposed by the fourth via hole. The fourth center line is a center line of the fourth via hole extending along the second direction. The third boundary of the fourth via hole and the third boundary of the eighth via hole are located on the same side of the fourth center line, and the fourth boundary of the fourth via hole and the fourth boundary of the eighth via hole are located on the same side of the fourth center line.

[0033] The distance between the orthographic projection of the first boundary of the fourth via on the substrate and the orthographic projection of the third signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the eighth via on the substrate and the orthographic projection of the third signal line on the substrate, the distance between the orthographic projection of the second boundary of the fourth via on the substrate and the orthographic projection of the third signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the eighth via on the substrate and the orthographic projection of the third signal line on the substrate, the distance between the third boundary of the fourth via and the fourth center line is greater than the distance between the orthographic projection of the third boundary of the eighth via on the substrate and the orthographic projection of the fourth center line on the substrate, and the distance between the fourth boundary of the fourth via and the fourth center line is greater than the distance between the orthographic projection of the fourth boundary of the eighth via on the substrate and the orthographic projection of the fourth center line on the substrate.

[0034] In an exemplary embodiment, a distance between an orthographic projection of a first boundary of the fourth via hole on the substrate and an orthographic projection of a first boundary of the eighth via hole on the substrate is greater than a distance between an orthographic projection of a third boundary of the fourth via hole on the substrate and an orthographic projection of a third boundary of the eighth via hole on the substrate, and is less than a distance between an orthographic projection of a second boundary of the fourth via hole on the substrate and an orthographic projection of a second boundary of the eighth via hole on the substrate;

[0035] A distance between an orthographic projection of a first boundary of the fourth via hole on the substrate and an orthographic projection of a first boundary of the eighth via hole on the substrate is approximately 1 micrometer to 2 micrometers.

[0036] In an exemplary embodiment, the fifth insulating layer is provided with fifth to eighth via holes, wherein:

[0037] The orthographic projection of the fifth via on the substrate is within the range of the orthographic projection of the first via on the substrate, the orthographic projection of the sixth via on the substrate is within the range of the orthographic projection of the second via on the substrate, the orthographic projection of the seventh via on the substrate is within the range of the orthographic projection of the third via on the substrate, and the orthographic projection of the eighth via on the substrate is within the range of the orthographic projection of the fourth via on the substrate.

[0038] In an exemplary embodiment, the fifth insulating layer is further provided with any one of the first and second ventilation holes;

[0039] The orthographic projections of the first vent hole and the second vent hole on the substrate partially overlap with the orthographic projection of the first flat layer on the substrate, and the first flat layer is exposed;

[0040] There is no overlapping area between the orthographic projections of the first air vent and the second air vent on the substrate and the orthographic projections of the active pattern, gate electrode, first pole and second pole of any transistor, as well as the reference signal line, first scanning signal line, second scanning signal line, third scanning signal line, initial signal line, first power supply line and light-emitting signal line on the substrate.

[0041] In an exemplary embodiment, the length of the first ventilation hole along the first direction is greater than the length of the boundary between the second electrode of the third transistor and the first scan signal line, and the length of the first ventilation hole along the second direction is greater than the length of the fifth via hole along the second direction;

[0042] The orthographic projection of the first vent hole on the substrate is at least arranged around at least one side of the orthographic projection of the first via hole on the substrate;

[0043] The distance between the orthographic projection of the first vent hole on the substrate and the orthographic projection of the fifth via hole on the substrate is smaller than the distance between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the fifth via hole on the substrate.

[0044] In an exemplary embodiment, the length of the second ventilation hole along the second direction is greater than the length of the sixth via hole along the second direction, and the length of the second ventilation hole along the first direction is less than the length of the sixth via hole along the first direction;

[0045] The second ventilation holes and the sixth via holes are arranged along the second direction, and the distance between the orthographic projection of the sixth via hole on the substrate and the orthographic projection of the first scan signal line on the substrate is greater than the distance between the second ventilation holes and the sixth via holes.

[0046] In an exemplary embodiment, the fifth insulating layer is further provided with a third vent hole;

[0047] The orthographic projection of the third vent hole on the substrate partially overlaps with the orthographic projection of the first flat layer on the substrate, and the first flat layer is exposed;

[0048] The orthographic projection of the third air vent on the substrate is located between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the light-emitting signal line on the substrate, and there is no overlapping area with the active pattern, gate electrode, first pole and second pole of any transistor and the orthographic projection of the reference signal line, first scanning signal line, second scanning signal line, third scanning signal line, initial signal line, first power line and light-emitting signal line on the substrate.

[0049] In an exemplary embodiment, the fifth insulating layer is further provided with at least one of a fourth ventilation hole and a fifth ventilation hole;

[0050] The orthographic projections of the fourth vent hole and the fifth vent hole on the substrate partially overlap with the orthographic projection of the first flat layer on the substrate, and the first flat layer is exposed;

[0051] The orthographic projection of the fourth vent on the substrate at least partially overlaps with the orthographic projection of the reference signal line on the substrate, and does not overlap with the orthographic projections of the active pattern, gate electrode, first electrode, second electrode, first scanning signal line, second scanning signal line, third scanning signal line, initial signal line, first power supply line, and light-emitting signal line of any transistor on the substrate;

[0052] The orthographic projection of part of the fifth air holes on the substrate does not overlap with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor, as well as the reference signal line, first scanning signal line, second scanning signal line, third scanning signal line, initial signal line, first power line and light-emitting signal line on the substrate; the orthographic projection of another part of the fifth air holes on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate, and does not overlap with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor, as well as the reference signal line, first scanning signal line, second scanning signal line, third scanning signal line, initial signal line and light-emitting signal line on the substrate.

[0053] In an exemplary embodiment, the length of the fourth vent hole along the second direction is greater than the length of the third via hole along the second direction, and the length of the fourth vent hole along the first direction is less than the length of the third via hole along the first direction;

[0054] The fourth air vent and the seventh via are arranged along the first direction, and the distance between the orthographic projection of the fourth air vent and the seventh via on the substrate and the orthographic projection of the gate electrode of the first transistor of the adjacent sub-pixel on the substrate is smaller than the distance between the orthographic projection of the seventh via on the substrate and the orthographic projection of the gate electrode of the first transistor of the adjacent sub-pixel on the substrate.

[0055] In an exemplary embodiment, the length of the fifth ventilation hole along the second direction is greater than the length of the fourth via hole along the second direction, and the length of the fifth ventilation hole along the first direction is less than the length of the fourth via hole along the first direction;

[0056] The fifth vent hole and the eighth via hole are arranged along the first direction, and the distance between their orthographic projection on the substrate and the orthographic projection of the fourth via hole on the substrate is smaller than the distance between the orthographic projection of the fourth via hole on the substrate and the orthographic projection of the gate electrode of the first transistor on the substrate.

[0057] In an exemplary embodiment, the pixel driving circuit further includes: a capacitor, the capacitor including: a first plate, a second plate, and a third plate, the first plate being electrically connected to the third plate;

[0058] The semiconductor layer includes at least: an active pattern of at least one transistor;

[0059] The first conductive layer includes at least: a gate electrode of at least one transistor and a first plate of a capacitor;

[0060] The second conductive layer includes at least: a second plate of the capacitor;

[0061] The third conductive layer at least includes: a first electrode and a second electrode of at least one transistor, a first scanning signal line, a second scanning signal line, a third scanning signal line, a light emitting signal line, an initial signal line, a reference signal line, a first power supply line and a third plate of a capacitor;

[0062] The fourth conductive layer at least includes: a data signal line.

[0063] In an exemplary embodiment, the first plate of the capacitor includes: a first gate connection portion and a second gate connection portion, wherein the second gate connection portion of the sub-pixels in the current column is located on a side of the first gate connection portion closer to the sub-pixels in the next column, and a distance between a boundary of the first gate connection portion close to the gate electrode of the fifth transistor and the gate electrode of the fifth transistor is smaller than a distance between a boundary of the second gate connection portion close to the gate electrode of the fifth transistor and the gate electrode of the fifth transistor, and a distance between a boundary of the first gate connection portion away from the gate electrode of the fifth transistor and the gate electrode of the fifth transistor is smaller than a distance between a boundary of the second gate connection portion away from the gate electrode of the fifth transistor and the gate electrode of the fifth transistor;

[0064] The length of the first gate connection portion along the first direction is greater than the length of the second gate connection portion along the first direction, and the length of the first gate connection portion along the second direction is greater than the length of the second gate connection portion along the second direction.

[0065] In an exemplary embodiment, an orthographic projection of the second plate of the capacitor on the substrate at least partially overlaps an orthographic projection of the first plate of the capacitor on the substrate;

[0066] The second plates of the capacitors of the sub-pixels in the same column have the same shape and area, and the area of ​​the second plates of the capacitors of the sub-pixels in the 3k+1th column is smaller than either the area of ​​the second plates of the capacitors of the sub-pixels in the 3k+2th column or the area of ​​the second plates of the capacitors of the sub-pixels in the 3k+3th column.

[0067] The area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the sub-pixel in the 3k+1th column is smaller than the area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the sub-pixel in the 3k+2th column, and the area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the sub-pixel in the 3k+2th column is smaller than the area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the sub-pixel in the 3k+3th column;

[0068] The area of ​​the overlap between the second plate of the capacitor and the first gate connection portion of the sub-pixel in the 3k+1 column is smaller than the area of ​​the overlap between the second plate of the capacitor and the first gate connection portion of the sub-pixel in the 3k+2 column, and the area of ​​the overlap between the second plate of the capacitor and the first gate connection portion of the sub-pixel in the 3k+2 column is smaller than the area of ​​the overlap between the second plate of the capacitor and the first gate connection portion of the sub-pixel in the 3k+3 column.

[0069] The area of ​​the overlapping area between the second plate and the second gate connection portion of the capacitor of the 3k+1th column of sub-pixels is smaller than the area of ​​the overlapping area between the second plate and the second gate connection portion of the capacitor of the 3k+2th column of sub-pixels, and the area of ​​the overlapping area between the second plate and the second gate connection portion of the capacitor of the 3k+3th column of sub-pixels is smaller than the area of ​​the overlapping area between the second plate and the second gate connection portion of the capacitor of the 3k+2th column of sub-pixels.

[0070] In an exemplary embodiment, the orthographic projection of the third plate of the capacitor on the substrate at least partially overlaps with the orthographic projections of the first plate of the capacitor and the second plate of the capacitor on the substrate, respectively, and the orthographic projection on the substrate has a non-overlapping area with the orthographic projection of the first plate of the capacitor on the substrate, and has a non-overlapping area with the orthographic projection of the second plate of the capacitor on the substrate.

[0071] In an exemplary embodiment, the further comprising: an initial connection line located in the first conductive layer, the initial connection line at least partially extending along the second direction, the initial connection line being electrically connected to the initial signal line;

[0072] Two initial connection lines are provided between at least two columns of sub-pixels, and the two initial connection lines between at least two adjacent sub-pixels are symmetrically arranged relative to a midline extending along the second direction between the two adjacent sub-pixels;

[0073] An orthographic projection of the sixth via hole on the substrate does not overlap with an orthographic projection of the initial connection line on the substrate.

[0074] In an exemplary embodiment, the further comprising: at least one of a power connection line and a reference connection line located in the fourth conductive layer, wherein at least a portion of the power connection line and the reference connection line extends along the second direction;

[0075] The power connection line is electrically connected to the first power line, and the reference connection line is electrically connected to the reference signal line;

[0076] The orthographic projection of at least part of the reference connection line on the substrate is between the orthographic projections of two initial connection lines located between two adjacent sub-pixels on the substrate, and the orthographic projection of the power connection line on the substrate and the orthographic projection of the initial connection line on the substrate are away from the side of the orthographic projection of the reference connection line on the substrate.

[0077] In an exemplary embodiment, the fifth insulating layer is provided with at least one of the first to fifth ventilation holes;

[0078] The orthographic projections of the first to fifth vent holes on the substrate and the orthographic projections of the power connection line, the reference connection line, and the data signal line on the substrate do not overlap;

[0079] The orthographic projection of the fourth vent hole on the substrate partially overlaps with the orthographic projection of the initial connection line on the substrate.

[0080] In an exemplary embodiment, the sub-pixel further includes a light-emitting structure layer, the sub-pixel further includes a light-emitting device, the light-emitting device includes a first electrode, an organic light-emitting layer, and a second electrode, the light-emitting structure layer includes a light-emitting device, and the light-emitting structure layer includes a fifth conductive layer, a first pixel definition layer, a second pixel definition layer, a light-emitting material layer, and a sixth conductive layer sequentially stacked on a side of the driving structure layer away from the substrate;

[0081] The fifth conductive layer at least includes: a first electrode;

[0082] The light-emitting material layer at least includes: an organic light-emitting layer;

[0083] The sixth conductive layer at least includes: a second electrode;

[0084] The light transmittance of the first pixel definition layer is lower than the light transmittance of the second pixel definition layer.

[0085] In an exemplary embodiment, the fifth insulating layer has a thickness of approximately 1200 angstroms to 1600 angstroms;

[0086] The thickness of the first planar layer is about 18,000 angstroms to 22,000 angstroms, and the material of the first planar layer includes polyimide.

[0087] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0088] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0089] Summary of the Figures

[0090] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0091] FIG1 is a schematic structural diagram of a display device;

[0092] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0093] FIG3 is a second schematic diagram of a planar structure of a display substrate;

[0094] FIG4 is a third schematic diagram of a planar structure of a display substrate;

[0095] FIG5A is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0096] FIG5B is a timing diagram of the operation of the pixel driving circuit provided in FIG5A ;

[0097] FIG6 is a schematic diagram of a display substrate;

[0098] FIG7A is a first structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0099] FIG7B is a second structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0100] FIG8A is a schematic diagram of a portion of film layers of the display substrate provided in FIG7A ;

[0101] FIG8B is a schematic diagram of a portion of the film layers of the display substrate provided in FIG7B ;

[0102] FIG9A is an enlarged schematic diagram of a region A in the display substrate provided in FIG8A ;

[0103] FIG9B is an enlarged schematic diagram of a region B in the display substrate provided in FIG8A ;

[0104] FIG9C is an enlarged schematic diagram of a region C in the display substrate provided in FIG8A ;

[0105] FIG9D is an enlarged schematic diagram of a region D in the display substrate provided in FIG8A ;

[0106] FIG10 is a schematic diagram showing the capacitance of a display substrate as shown in FIG7A and FIG7B ;

[0107] FIG11 is a schematic diagram of a portion of the film layers of a capacitor of a display substrate provided in FIG10 for FIG7A and FIG7B;

[0108] FIG12 is a schematic diagram of the semiconductor layer pattern in FIG7A and FIG7B ;

[0109] FIG13 is a schematic diagram of the first conductive layer pattern in FIG7A and FIG7B ;

[0110] FIG14 is a schematic diagram of FIG7A and FIG7B after forming a first conductive layer pattern;

[0111] FIG15 is a schematic diagram of the second conductive layer pattern in FIG7A and FIG7B ;

[0112] FIG16 is a schematic diagram of FIG7A and FIG7B after forming a second conductive layer pattern;

[0113] FIG17 is a schematic diagram of FIG7A and FIG7B after forming a fourth insulating layer pattern;

[0114] FIG18 is a schematic diagram of a third conductive layer pattern in FIG7A and FIG7B ;

[0115] FIG19 is a schematic diagram of FIG7A and FIG7B after forming a third conductive layer pattern;

[0116] FIG20 is a schematic diagram of FIG7A and FIG7B after forming a first planar layer pattern;

[0117] FIG21 is a schematic diagram of FIG7A after forming a fifth insulating layer pattern;

[0118] FIG22 is a schematic diagram of FIG7B after forming a fifth insulating layer pattern;

[0119] FIG23 is a schematic diagram of the fourth conductive layer pattern in FIG7A and FIG7B ;

[0120] FIG24 is a schematic diagram of FIG7A after forming a fourth conductive layer pattern;

[0121] FIG25 is a schematic diagram of FIG7B after forming a fourth conductive layer pattern;

[0122] FIG26 is a schematic diagram of FIG7A after forming a sixth insulating layer pattern;

[0123] FIG27 is a schematic diagram of FIG7B after forming a sixth insulating layer pattern;

[0124] FIG28 is a schematic diagram of FIG7A after forming a second planar layer pattern;

[0125] FIG29 is a schematic diagram of FIG7B after forming a second planar layer pattern;

[0126] FIG30 is a schematic diagram of the fifth conductive layer pattern in FIG7A and FIG7B ;

[0127] FIG31 is a schematic diagram of FIG7A after forming a fifth conductive layer pattern;

[0128] FIG32 is a schematic diagram of FIG7B after forming a fifth conductive layer pattern;

[0129] FIG33 is a schematic diagram of FIG7A after forming a first pixel definition layer pattern;

[0130] FIG34 is a schematic diagram of FIG7B after forming the first pixel definition layer;

[0131] FIG35 is a schematic diagram of FIG7A after forming a second pixel definition layer pattern;

[0132] FIG. 36 is a schematic diagram illustrating the second pixel definition layer after patterning is formed in FIG. 7B .

[0133] Details

[0134] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0135] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0136] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0137] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0138] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0139] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0140] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0141] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0142] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0143] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0144] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0145] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0146] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0147] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to multiple data signal lines (D1 to Dn), the scan driver is respectively connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is respectively connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines.

[0148] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, can provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and can provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver.

[0149] In an exemplary embodiment, the data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, ..., and Dn using the grayscale values ​​and control signals received from the timing controller. For example, the data driver may sample the grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.

[0150] In an exemplary embodiment, the scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driver may sequentially provide scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals by sequentially transmitting the scan start signal provided in the form of on-level pulses to the next stage circuit under the control of a clock signal. m may be a natural number.

[0151] In an exemplary embodiment, the light emitting driver may generate emission signals to be provided to the light emitting signal lines E1, E2, E3, ..., and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light emitting driver may sequentially provide emission signals having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate emission signals by sequentially transmitting the emission stop signal provided in the form of an off-level pulse to the next stage circuit under the control of a clock signal. o may be a natural number.

[0152] FIG2 is a schematic diagram of a planar structure of a display substrate (I), FIG3 is a schematic diagram of a planar structure of a display substrate (II), and FIG4 is a schematic diagram of a planar structure of a display substrate (III). As shown in FIG2 to FIG4, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel in which they are located. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel in which they are located.

[0153] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the shape of the subpixels may be rectangular, diamond, pentagonal, or hexagonal.

[0154] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally, vertically, or in a herringbone pattern, etc., without limitation in this disclosure. Figures 2 and 3 illustrate an example of a pixel unit including three sub-pixels. The three sub-pixels in Figure 2 are arranged horizontally, and the three sub-pixels in Figure 3 are arranged in a herringbone pattern.

[0155] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally, vertically, or in a square arrangement, etc., which is not limited in this disclosure. FIG4 illustrates an example in which a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square arrangement.

[0156] In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a base, a light-emitting structure layer disposed on a side of the driving structure layer away from the base, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the base. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0157] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0158] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0159] In an exemplary embodiment, the driving structure layer may include multiple transistors and storage capacitors that constitute a pixel driving circuit, and the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode. The anode is connected to the drain electrode of the transistor therein through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding color under the drive of the anode and the cathode.

[0160] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the emissive layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0161] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0162] In an exemplary embodiment, the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

[0163] FIG5A is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG5A , the pixel driving circuit may include five transistors (a first transistor T1 to a fifth transistor T5), a capacitor C, and the pixel driving circuit may be connected to seven signal lines (a data signal line Data, a first scan signal line G1, a second scan signal line G2, a third scan signal line G3, an emission signal line EM, an initial signal line INIT, a reference signal line REF, and a first power line VDD). The light-emitting device L is connected to the second power line VSS.

[0164] In an exemplary embodiment, as shown in FIG5A , a gate electrode of the first transistor T1 is electrically connected to the third scan signal line G3, a first electrode of the first transistor T1 is electrically connected to the initial signal line INIT, a second electrode of the first transistor T1 is electrically connected to the first node N1, a gate electrode of the second transistor T2 is electrically connected to the second scan signal line G2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, a second electrode of the second transistor T2 is electrically connected to the second node N2, a gate electrode of the third transistor T3 is electrically connected to the second node N2, a first electrode of the third transistor T3 is electrically connected to the third node N3, and a second electrode of the third transistor T3 is electrically connected to the first node N1. The gate electrode of the fourth transistor T4 is electrically connected to the first scan signal line G1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, the second electrode of the fourth transistor T4 is electrically connected to the second node N4, the gate electrode of the fifth transistor T5 is electrically connected to the light emitting signal line EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3. The capacitor C includes: a first electrode plate C1, a second electrode plate C2, and a third electrode plate C3 stacked in sequence on the substrate, wherein the first electrode plate C1 and the third electrode plate C3 are electrically connected to the second node N2, and the second electrode plate C2 is electrically connected to the first node N1.

[0165] In an exemplary embodiment, the first transistor T1 may be referred to as a reset transistor, and when the signal of the third scan signal line G3 is an active level signal, the first transistor T1 transmits the signal of the initial signal line to the first node N1 to reset the charge amount of the first electrode of the light emitting device L.

[0166] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the magnitude of a driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between its gate electrode and the first electrode.

[0167] In an exemplary embodiment, the fourth transistor T4 may be referred to as a switching transistor, a scan transistor, etc., and inputs a data voltage of the data signal line Data to the second node N2 when an on-level scan signal is applied to the first scan signal line S1.

[0168] In an exemplary embodiment, the fifth transistor T5 may be referred to as a light emitting transistor. When an on-level light emitting signal is applied to the light emitting signal line EM, the fifth transistor T5 enables the light emitting device L to emit light by forming a driving current path between the first power line VDD and the second power line VSS.

[0169] 5A , the number of any one of the first transistor T1 , the second transistor T2 , and the fourth transistor T4 may be at least one. FIG5A is illustrative of one first transistor T1 , one second transistor T2 , and one fourth transistor T4 .

[0170] In an exemplary embodiment, when the number of the first transistors T1 may be at least two, the gate electrodes of all the first transistors are electrically connected to the third scan signal line, at least two first transistors are arranged in series, the first electrode of the first first transistor is electrically connected to the initial signal line, and the second electrode of the last first transistor is electrically connected to the first node N1.

[0171] In an exemplary embodiment, when the number of the second transistors T2 may be at least two, the gate electrodes of all the second transistors are electrically connected to the second scan signal line, at least two second transistors are arranged in series, the first electrode of the first second transistor is electrically connected to the reference signal line, and the second electrode of the last second transistor is electrically connected to the second node N2.

[0172] In an exemplary embodiment, when the number of the fourth transistors T4 may be at least two, the gate electrodes of all the fourth transistors are electrically connected to the first scan signal line, at least two fourth transistors are arranged in series, the first electrode of the first fourth transistor is electrically connected to the data signal line, and the second electrode of the last fourth transistor is electrically connected to the second node N2.

[0173] In an exemplary embodiment, as shown in FIG. 5A , a first electrode of the light emitting device L is electrically connected to the first node N1 , and a second electrode of the light emitting device L is connected to the second power line VSS.

[0174] In an exemplary embodiment, the first power line VDD continuously provides a high level signal, and the second power line VSS continuously provides a low level signal.

[0175] In an exemplary embodiment, a voltage value of a signal of the initial signal line INIT may be lower than a voltage value of a signal of the second power line VSS, and erroneous light emission of the light emitting device may be avoided.

[0176] In an exemplary embodiment, the first scanning signal line G1 is a scanning signal line in the pixel driving circuit of the current display row, and the third scanning signal line G3 is a scanning signal line in the pixel driving circuit of the previous display row. The third scanning signal line G3 of the current display row and the first scanning signal line G1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display substrate and realize a narrow frame of the display substrate.

[0177] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0178] In an exemplary embodiment, the first to fifth transistors T1 to T5 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process, reduce the difficulty of display substrate processing, and improve product yield.

[0179] In an exemplary embodiment, the first to fifth transistors T1 to T5 are all N-type transistors.

[0180] In an exemplary embodiment, the first power line VDD continuously provides a high level signal, the second power line VSS continuously provides a low level signal, and the reference signal line REF continuously provides a reference signal, wherein the voltage of the reference signal is 0V.

[0181] FIG5B is an operating timing diagram of the pixel driving circuit shown in FIG5A. The following describes exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit shown in FIG5A. The pixel driving circuit in FIG5B includes five transistors (first transistor T1 to fifth transistor T5) and one capacitor C. All five transistors are N-type transistors.

[0182] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0183] The first phase P1, known as the reset phase, is characterized by high-level signals on the second scan signal line G2 and the third scan signal line G3, while low-level signals on the first scan signal line G1 and the emission signal line EM. The second scan signal line G2 is high, turning on the second transistor T2. The signal on the reference signal line REF is supplied to the second node N2, initializing (resetting) the signal on the second node N2 and clearing any existing charge in the second node N2. The third scan signal line G3 is high, turning on the first transistor T1, and supplying the signal on the initialization signal line INIT to the first node N1. This initializes (resets) the anode of the light-emitting device L and clears any existing charge in the anode of the light-emitting device L. The first scan signal line G1 and the emission signal line EM are low, turning off the fourth transistor T4 and the fifth transistor T5. During this phase, the light-emitting device L does not emit light.

[0184] In the second stage P2, i.e., the threshold compensation stage, the signals of the second scanning signal line G2 and the light-emitting signal line EM are high-level signals, the signals of the first scanning signal line G1 and the third scanning signal line G3 are low-level signals, the signal of the second scanning signal line G2 is a high-level signal, the second transistor T2 is turned on, the signal of the reference signal line REF is continuously provided to the second node N2, the signal of the light-emitting signal line EM is a high-level signal, the fifth transistor T5 is turned on, and the signal of the first power line VDD is written into the first node N1 through the turned-on fifth transistor T5, the third node N3 and the turned-on third transistor T3 until the voltage V2 of the signal at the second node N1 is Vref-Vth, where Vref is the voltage value of the signal of the initial signal line REF, Vth is the threshold voltage of the third transistor T3, and the capacitor C stores the voltage difference Vth between the signals at the first node N1 and the second node N2.

[0185] In the third phase P3, the data writing phase, the signal on the first scan signal line G1 is high, while the signals on the second scan signal line G2, the third scan signal line G3, and the light-emitting signal line EM are low. The data signal line Data outputs a data voltage. The signal on the first scan signal line G1 is high, and the fourth transistor T4 is turned on. The data voltage on the data signal line Data is written to the second node N2. At this point, the voltage V2 of the second node N2 equals Vdata, where Vdata is the data voltage of the data signal line. The signal on the second node N2 jumps from the voltage value in the current phase to the voltage value in the previous phase. Therefore, under the action of capacitor C, the signal on the first node N1 also jumps. At this point, the voltage V1 of the signal on the first node N1 equals Vref - Vth + α(Vdata - Vref). The signals on the second scan signal line G2, the third scan signal line G3, and the light-emitting signal line EM are low, and the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off. During this phase, the light-emitting device L does not emit light.

[0186] In the fourth phase P4, i.e., the light-emitting phase, the signal on the light-emitting signal line EM is a high-level signal, while the signals on the first scanning signal line G1, the second scanning signal line G2, and the third scanning signal line G3 are low-level signals. With the signal on the light-emitting signal line EM being a high-level signal, the fifth transistor T5 is turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5 and the third transistor T3, driving the light-emitting device L to emit light.

[0187] During the pixel driving circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode (also the second node N2) and the first electrode (also the first node N1). Since the voltage value of the signal at the first node V1 = Vref - Vth + α (Vdata - Vref), and the voltage value of the signal at the second node N1 V1 = Vdata, the driving current of the third transistor T3 is: I = K * (Vgs - Vth) 2 =K*[Vdata-Vref+Vth-α(Vdata-Vref)] 2 =K*[(1-α)(Vdata-Vref)] 2

[0188] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0189] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0190] FIG6 is a schematic diagram of a display substrate. As shown in FIG6 , the driving structure layer of the display substrate includes: a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, wherein a flat layer and an insulating layer are provided between the third conductive layer and the fourth conductive layer, wherein the insulating layer covers the flat layer. The flat layer is made of a polyimide material, which can achieve good flattening. When the fourth conductive layer is subsequently formed, since the fourth conductive layer is prepared in a high-temperature environment, the high temperature will cause the residual water vapor in the flat layer to gather, resulting in bulging 10, causing the display substrate to have poor bulging, thereby resulting in low reliability of the display product, thereby affecting the display effect of the display product.

[0191] Figure 7A is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure. Figure 7B is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure. Figure 8A is a schematic diagram of a portion of the membrane layer of the display substrate provided in Figure 7A. Figure 8B is a schematic diagram of a portion of the membrane layer of the display substrate provided in Figure 7B. As shown in Figures 7A, 7B, 8A, and 8B, an embodiment of the present disclosure provides a display substrate having a plurality of sub-pixels arranged in an array, at least one of which includes a pixel driving circuit. The display substrate includes a substrate and a driving structure layer provided on the substrate, with the pixel driving circuit provided in the driving structure layer.

[0192] In an exemplary embodiment, the drive structure layer includes at least: a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fifth insulating layer, and a fourth conductive layer, stacked sequentially on a substrate. Figures 7A and 7B illustrate the first insulating layer, semiconductor layer, second insulating layer, first conductive layer, third insulating layer, second conductive layer, fourth insulating layer, third conductive layer, first planar layer, and fifth insulating layer.

[0193] As shown in FIG. 7A and FIG. 7B , a plurality of via holes are provided on the fifth insulating layer, and at least one via hole on the fifth insulating layer exposes the first planar layer.

[0194] As shown in FIG. 7A and FIG. 7B , the thickness of the first planarization layer may be greater than the thickness of the fifth insulating layer.

[0195] In an exemplary embodiment, the fifth insulating layer has a thickness of about 1200 angstroms to about 1600 angstroms. Exemplarily, the fifth insulating layer has a thickness of about 1400 angstroms.

[0196] In an exemplary embodiment, the thickness of the first planar layer is about 18,000 angstroms to about 22,000 angstroms. For example, the thickness of the first planar layer is about 20,000 angstroms.

[0197] In an exemplary embodiment, the material of the first planar layer may include polyimide.

[0198] The present disclosure forms a degassing channel by exposing the first flat layer through at least one via on the fifth insulating layer, so that residual water vapor in the first flat layer in subsequent production processes can be released, thereby avoiding bulging defects in the display substrate, improving the reliability of the display substrate, and thus ensuring the display effect of the display product.

[0199] In an exemplary embodiment, in combination with Figures 7A to 7B, the pixel driving circuit may include: first to fifth transistors, the driving structure layer further includes: a first scan signal line G1, a second scan signal line G2, a third scan signal line G3, an initial signal line INIT, a data signal line Data, a light emitting signal line EM, a reference signal line REF and a first power line VDD, the first transistor is electrically connected to the third scan signal line G3 and the initial signal line INIT, respectively, the second transistor is electrically connected to the second scan signal line G2 and the reference signal line REF, respectively, the fourth transistor is electrically connected to the first scan signal line G1 and the data signal line Data, respectively, and the fifth transistor is electrically connected to the light emitting signal line EM and the first power line VDD, respectively.

[0200] In an exemplary embodiment, any one of the first scan signal line G1, the second scan signal line G2, the third scan signal line G3, the initial signal line INIT, the light emitting signal line EM, the reference signal line REF, and the first power line VDD at least partially extends along the first direction D1, and the data signal line Data at least partially extends along the second direction D2, and the first direction D1 intersects the second direction D2;

[0201] In an exemplary embodiment, the reference signal line REF, the second scan signal line G2, the first scan signal line G1, the emission signal line EM, the first power line VDD, the third scan signal line G3 and the initial signal line INIT connected to any sub-pixel are sequentially arranged along the second direction D2.

[0202] In an exemplary embodiment, as shown in FIG8A and FIG8B , first to fourth via holes V1 to V4 are defined on the first planar layer, wherein the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the second electrode 34 of the third transistor on the substrate, and exposes the surface of the second electrode 34 of the third transistor; the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the first electrode 43 of the fourth transistor on the substrate, and exposes the surface of the first electrode 43 of the fourth transistor; the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the reference signal line REF on the substrate, and exposes the surface of the reference signal line REF; the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first power line VDD on the substrate, and exposes the surface of the first power line VDD;

[0203] In an exemplary embodiment, as shown in FIG. 8A and FIG. 8B , the third via hole V3 is located on a center line extending along the second direction D2 between two adjacent fourth via holes V4 .

[0204] In an exemplary embodiment, as shown in FIG8A , fifth to eighth via holes V5 to V8 are formed on the fifth insulating layer. The orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the first via hole V1 and the first planar layer on the substrate. The orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the second via hole V2 and the first planar layer on the substrate. The orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the third via hole V3 and the first planar layer on the substrate. The orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the fourth via hole V4 and the first planar layer on the substrate. In an exemplary embodiment, the orthographic projection of any via hole from the fifth via hole V5 to the eighth via hole V8 on the substrate overlaps with the orthographic projection of the first flat layer on the substrate, that is, any via hole from the fifth via hole V5 to the eighth via hole V8 exposes the first flat layer, which can be used as a degassing channel, so that the water vapor remaining in the first flat layer in the subsequent production process can be released, thereby avoiding bulging defects of the display substrate, improving the reliability of the display substrate, and thus ensuring the display effect of the display product.

[0205] Figure 9A is an enlarged schematic diagram of area A in the display substrate provided in Figure 8A, Figure 9B is an enlarged schematic diagram of area B in the display substrate provided in Figure 8A, Figure 9C is an enlarged schematic diagram of area C in the display substrate provided in Figure 8A, and Figure 9D is an enlarged schematic diagram of area D in the display substrate provided in Figure 8A.

[0206] In an exemplary embodiment, as shown in FIG8A and FIG9A, the length of the fifth via hole V5 along the first direction D1 is less than the length of the first via hole V1 along the first direction D1, and the length of the fifth via hole V5 along the second direction D2 is less than the length of the first via hole V1 along the second direction D2.

[0207] In an exemplary embodiment, as shown in FIG8A , within any sub-pixel, the boundaries of the via hole include: a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary of the via hole is the boundary of the via hole close to the first signal line, the second boundary of the via hole is the boundary of the via hole away from the first signal line, the third boundary of the via hole is the boundary located on one side of the first center line O1, and the fourth boundary of the via hole is the boundary located on the other side of the first center line O1. The via holes include: a first via hole V1 and a fifth via hole V5. The first signal line is one of the emission signal line EM, the first power line VDD, the third scan signal line G3, and the initial signal line INIT connected to the sub-pixel. The first center line O1 is the center line of the first via hole extending along the second direction D2. The third boundary of the first via hole V1 and the third boundary of the fifth via hole V5 are located on the same side of the first center line, and the fourth boundary of the first via hole V1 and the fourth boundary of the fifth via hole V5 are located on the same side of the first center line.

[0208] In an exemplary embodiment, as shown in FIG8A , the distance between the orthographic projection of the first boundary of the first via V1 on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the fifth via V5 on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the orthographic projection of the second boundary of the first via V1 on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the fifth via V5 on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the third boundary of the first via V1 and the first center line O1 is greater than the distance between the orthographic projection of the third boundary of the fifth via V5 on the substrate and the orthographic projection of the first center line O1 on the substrate, and the distance between the fourth boundary of the first via V1 and the first center line O1 is greater than the distance between the orthographic projection of the fourth boundary of the fifth via V5 on the substrate and the orthographic projection of the first center line O1 on the substrate.

[0209] In an exemplary embodiment, as shown in FIG9A , within any sub-pixel, a distance d11 between an orthographic projection of a first boundary of the first via hole V1 and an orthographic projection of a first boundary of the fifth via hole V5 on the substrate is greater than a distance d12 between an orthographic projection of a third boundary of the first via hole V1 and an orthographic projection of a third boundary of the fifth via hole V5 on the substrate, and is less than a distance d13 between an orthographic projection of a second boundary of the first via hole V1 and an orthographic projection of a second boundary of the fifth via hole V5 on the substrate. In the present disclosure, d11>d12, d13>d11 can facilitate degassing of the first planar layer on the basis of saving space for the fifth via hole.

[0210] In an exemplary embodiment, as shown in FIG9A , a distance d11 between an orthographic projection of a first boundary of the first via hole V1 and an orthographic projection of a first boundary of the fifth via hole V5 on the substrate is approximately 1 to 2 micrometers. For example, the distance d11 between the orthographic projection of the first boundary of the first via hole V1 and the orthographic projection of the first boundary of the fifth via hole V5 on the substrate may be approximately 1.5 micrometers.

[0211] 8A and 9B , the length of the sixth via V6 along the first direction D1 is less than the length of the second via V2 along the first direction D1 , and the length of the sixth via V6 along the second direction D2 is less than the length of the second via V2 along the second direction D2 .

[0212] In an exemplary embodiment, as shown in FIG8A , within any sub-pixel, boundaries of the via hole include: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the first signal line, the second boundary of the via hole is a boundary of the via hole away from the first signal line, the third boundary of the via hole is a boundary located on one side of the second center line O2, and the fourth boundary of the via hole is a boundary located on the other side of the second center line O2. The via hole includes: a second via hole V2 and a sixth via hole V6. The first signal line is one of the emission signal line EM, the first power line VDD, the third scan signal line G3, and the initial signal line INIT connected to the sub-pixel. The second center line O2 is a center line of the second via hole V2 extending along the second direction. The third boundary of the second via hole V2 and the third boundary of the sixth via hole V6 are located on the same side of the second center line O2. The fourth boundary of the second via hole V2 and the fourth boundary of the sixth via hole V6 are located on the same side of the second center line O2.

[0213] In an exemplary embodiment, as shown in FIG8A , the distance between the orthographic projection of the first boundary of the second via V2 on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the sixth via V6 on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the orthographic projection of the second boundary of the second via V2 on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the sixth via V6 on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the third boundary of the second via V2 and the second center line O2 is greater than the distance between the orthographic projection of the third boundary of the sixth via V6 on the substrate and the orthographic projection of the second center line O2 on the substrate, and the distance between the fourth boundary of the second via V2 and the second center line O2 is greater than the distance between the orthographic projection of the fourth boundary of the sixth via V6 on the substrate and the orthographic projection of the second center line O2 on the substrate.

[0214] In an exemplary embodiment, as shown in FIG9B , within any subpixel, the distance d21 between the orthographic projection of the first boundary of the second via hole V2 and the orthographic projection of the first boundary of the sixth via hole V6 on the substrate is greater than the distance d22 between the orthographic projection of the third boundary of the second via hole V2 and the orthographic projection of the third boundary of the sixth via hole V6 on the substrate, and is less than the distance d23 between the orthographic projection of the second boundary of the second via hole V2 and the orthographic projection of the second boundary of the sixth via hole V6 on the substrate. In the present disclosure, d21>d22 and d23>d21 can facilitate degassing of the first planarization layer while saving space for the sixth via hole.

[0215] In an exemplary embodiment, as shown in FIG9B , the distance between the orthographic projection of the first boundary of the second via hole V2 and the orthographic projection of the first boundary of the sixth via hole V6 on the substrate is approximately 1 to 2 micrometers. For example, the distance between the orthographic projection of the first boundary of the second via hole V2 and the orthographic projection of the first boundary of the sixth via hole V6 on the substrate may be approximately 1.5 micrometers.

[0216] In an exemplary embodiment, as shown in Figures 8A and 9C, the length of the seventh via V7 along the first direction D1 is less than the length of the third via V3 along the first direction D1, and the length of the seventh via V7 along the second direction D2 is less than or equal to the length of the third via V3 along the second direction D2.

[0217] In an exemplary embodiment, as shown in FIG8A , the boundaries of the via hole include: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the second signal line, the second boundary of the via hole is a boundary of the via hole away from the second signal line, the third boundary of the via hole is a boundary located on one side of the third center line O3, and the fourth boundary of the via hole is a boundary located on the other side of the third center line O3. The via hole includes: a third via hole V3 and a seventh via hole V7. The second signal line is a reference signal line REF exposed by the third via hole V3. The connected sub-pixel is connected to one of the signal lines among the light-emitting signal line EM, the first power line VDD, the first scanning signal line G1, the second scanning signal line G2, the third scanning signal line G3, the initial signal line INIT and the light-emitting signal line EM, the third center line O3 is the center line of the third via hole V3 extending along the second direction D2, the third boundary of the third via hole V3 and the third boundary of the seventh via hole V7 are located on the same side of the third center line O3, and the fourth boundary of the third via hole V3 and the fourth boundary of the seventh via hole V7 are located on the same side of the third center line O3.

[0218] In an exemplary embodiment, as shown in FIG8A , the distance between the orthographic projection of the first boundary of the third via V3 on the substrate and the orthographic projection of the second signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the seventh via V7 on the substrate and the orthographic projection of the second signal line on the substrate, the distance between the orthographic projection of the second boundary of the third via V3 on the substrate and the orthographic projection of the second signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the seventh via V7 on the substrate and the orthographic projection of the second signal line on the substrate, the distance between the third boundary of the third via V3 and the third center line O3 is greater than the distance between the orthographic projection of the third boundary of the seventh via V7 on the substrate and the orthographic projection of the third center line O3 on the substrate, and the distance between the fourth boundary of the third via V3 and the third center line O3 is greater than the distance between the orthographic projection of the fourth boundary of the seventh via V7 on the substrate and the orthographic projection of the third center line O3 on the substrate.

[0219] In an exemplary embodiment, as shown in FIG9C , the distance d31 between the orthographic projection of the first boundary of the third via V3 and the orthographic projection of the first boundary of the seventh via V7 on the substrate is greater than the distance d33 between the orthographic projection of the third boundary of the third via V3 and the orthographic projection of the third boundary of the seventh via V7 on the substrate, and is less than the distance d33 between the orthographic projection of the second boundary of the third via V3 and the orthographic projection of the second boundary of the seventh via V7 on the substrate. In the present disclosure, d31>d32 and d33>d31 can facilitate degassing of the first planarization layer while saving space for the seventh via.

[0220] In an exemplary embodiment, as shown in FIG9C , a distance d31 between an orthographic projection of a first boundary of the third via hole V3 and an orthographic projection of a first boundary of the seventh via hole V7 on the substrate is approximately 1 to 2 micrometers. For example, the distance d31 between the orthographic projection of the first boundary of the third via hole V3 and the orthographic projection of the first boundary of the seventh via hole V7 on the substrate may be approximately 1.5 micrometers.

[0221] 8A and 9D , the length of the eighth via V8 along the first direction D1 is greater than the length of the fourth via V4 along the first direction D1 , and the length of the eighth via V8 along the second direction D2 is greater than or equal to the length of the fourth via V4 along the second direction D2 .

[0222] In an exemplary embodiment, as shown in FIG8A , boundaries of the via include: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary of the via is a boundary of the via close to the third signal line, the second boundary of the via is a boundary of the via away from the third signal line, the third boundary of the via is a boundary located on one side of the fourth center line O4, and the fourth boundary of the via is a boundary located on the other side of the fourth center line O4. The via includes: a fourth via V4 and an eighth via V8. The third signal line is any one of a third scanning signal line and an initial signal line connected to the sub-pixel connected to the first power line exposed by the fourth via V4. The fourth center line O4 is a center line of the fourth via V4 extending along the second direction D2. The third boundary of the fourth via V4 and the third boundary of the eighth via V8 are located on the same side of the fourth center line O4. The fourth boundary of the fourth via V4 and the fourth boundary of the eighth via V8 are located on the same side of the fourth center line O4.

[0223] In an exemplary embodiment, as shown in FIG8A , the distance between the orthographic projection of the first boundary of the fourth via V4 on the substrate and the orthographic projection of the third signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the eighth via V8 on the substrate and the orthographic projection of the third signal line on the substrate, the distance between the orthographic projection of the second boundary of the fourth via V4 on the substrate and the orthographic projection of the third signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the eighth via V8 on the substrate and the orthographic projection of the third signal line on the substrate, the distance between the third boundary of the fourth via V4 and the fourth center line O4 is greater than the distance between the orthographic projection of the third boundary of the eighth via V8 on the substrate and the orthographic projection of the fourth center line O4 on the substrate, and the distance between the fourth boundary of the fourth via V4 and the fourth center line O4 is greater than the distance between the orthographic projection of the fourth boundary of the eighth via V8 on the substrate and the orthographic projection of the fourth center line O4 on the substrate.

[0224] In an exemplary embodiment, as shown in FIG9D , a distance d41 between the orthographic projection of the first boundary of the fourth via V4 and the orthographic projection of the first boundary of the eighth via V8 on the substrate is greater than a distance d42 between the orthographic projection of the third boundary of the fourth via V4 and the orthographic projection of the third boundary of the eighth via V8 on the substrate, and is less than a distance d43 between the orthographic projection of the second boundary of the fourth via V4 and the orthographic projection of the second boundary of the eighth via V8 on the substrate. In the present disclosure, d41>d42 and d43>d41 can facilitate degassing of the first planar layer while saving space for the eighth via.

[0225] In an exemplary embodiment, as shown in FIG9D , a distance d41 between an orthographic projection of a first boundary of the fourth via hole V4 and an orthographic projection of a first boundary of the eighth via hole V8 on the substrate is approximately 1 to 2 micrometers. For example, the distance d41 between the orthographic projection of the first boundary of the fourth via hole V4 and the orthographic projection of the first boundary of the eighth via hole V8 on the substrate may be approximately 1.5 micrometers.

[0226] In an exemplary embodiment, as shown in FIG8B , fifth to eighth via holes V5 to V8 are defined in the fifth insulating layer. The orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the first via hole V1 on the substrate, the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the second via hole V2 on the substrate, the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the third via hole V3 on the substrate, and the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the fourth via hole V4 on the substrate.

[0227] In an exemplary embodiment, as shown in FIG8B , the fifth insulating layer is further provided with a first vent hole H1 or a second vent hole H2 .

[0228] In an exemplary embodiment, as shown in FIG. 8B , the orthographic projections of the first and second vent holes H1 and H2 on the substrate partially overlap with the orthographic projections of the first planar layer on the substrate, and the first planar layer is exposed.

[0229] In an exemplary embodiment, as shown in FIG8B , the orthographic projections of the first ventilation hole H1 and the second ventilation hole H2 on the substrate do not overlap with the orthographic projections of the active pattern, gate electrode, first electrode and second electrode of any transistor on the substrate, as well as the reference signal line REF, the first scan signal line G1, the second scan signal line G2, the third scan signal line G3, the initial signal line INIT, the first power line VDD and the light emitting signal line EM.

[0230] In an exemplary embodiment, as shown in FIG8B , the length of the first vent hole H1 along the first direction D1 is greater than the length of the boundary of the second electrode 34 of the third transistor close to the first scan signal line G1 , and the length of the first vent hole H1 along the second direction D2 is greater than the length of the sixth via hole V6 along the second direction D2 ;

[0231] In an exemplary embodiment, as shown in FIG8B , the orthographic projection of the first vent hole H1 on the substrate at least surrounds at least one side of the orthographic projection of the first via hole V1 on the substrate.

[0232] In an exemplary embodiment, as shown in FIG8B , the distance between the orthographic projection of the first ventilation hole H1 on the substrate and the orthographic projection of the fifth via hole V5 on the substrate is smaller than the distance between the projection of the first scan signal line G1 on the substrate and the orthographic projection of the fifth via hole V5 on the substrate, that is, the first ventilation hole H1 is arranged at the periphery of the sleeve hole including the fifth via hole V5 and the first via hole V1.

[0233] 8B , the length of the second ventilation hole H2 along the second direction D2 is greater than the length of the sixth via hole V6 along the second direction D2 , and the length of the second ventilation hole H2 along the first direction D1 is less than the length of the sixth via hole V6 along the first direction D1 .

[0234] In an exemplary embodiment, as shown in FIG. 8B , the second ventilation holes H2 and the sixth via holes V6 are arranged along the second direction D2 .

[0235] In an exemplary embodiment, as shown in FIG8B , the distance between the orthographic projection of the sixth via hole V6 on the substrate and the orthographic projection of the first scan signal line G1 on the substrate is greater than the distance between the second vent hole H2 and the sixth via hole V6. That is, the second vent hole is provided around the periphery of the sleeve hole including the second via hole V2 and the sixth via hole V6.

[0236] In an exemplary embodiment, as shown in Figure 8B, a third vent hole H3 is further formed on the fifth insulating layer, wherein the orthographic projection of the third vent hole H3 on the substrate partially overlaps with the orthographic projection of the first planar layer on the substrate, exposing the first planar layer.

[0237] In an exemplary embodiment, as shown in Figure 8B, the orthographic projection of the third air hole H3 on the substrate is located between the orthographic projection of the first scan signal line G1 on the substrate and the orthographic projection of the light-emitting signal line EM on the substrate, and there is no overlapping area with the active pattern, gate electrode, first pole and second pole of any transistor, and the orthographic projection of the reference signal line REF, the first scan signal line G1, the second scan signal line G2, the third scan signal line G3, the initial signal line INIT, the first power line VDD and the light-emitting signal line EM on the substrate.

[0238] In an exemplary embodiment, as shown in FIG8B , at least one of a fourth ventilation hole H4 and a fifth ventilation hole H5 is further formed on the fifth insulating layer. The orthographic projections of the fourth ventilation hole H4 and the fifth ventilation hole H5 on the substrate partially overlap with the orthographic projections of the first planar layer on the substrate, exposing the first planar layer.

[0239] In an exemplary embodiment, as shown in Figure 8B, the orthographic projection of the fourth air hole H4 on the substrate at least partially overlaps with the orthographic projection of the reference signal line REF on the substrate, and there is no overlapping area with the orthographic projections of the active pattern, gate electrode, first electrode and second electrode of any transistor and the first scan signal line G1, second scan signal line G2, third scan signal line G3, initial signal line INIT, first power line VDD and light emitting signal line EM on the substrate.

[0240] In an exemplary embodiment, as shown in Figure 8B, the orthographic projection of a portion of the fifth air hole H5 on the substrate does not overlap with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor, as well as the reference signal line REF, the first scan signal line G1, the second scan signal line G2, the third scan signal line G3, the initial signal line INIT, the first power line VDD and the light-emitting signal line EM on the substrate, and the orthographic projection of another portion of the fifth air hole H5 on the substrate at least partially overlaps with the orthographic projection of the first power line VDD on the substrate, and does not overlap with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor, as well as the reference signal line REF, the first scan signal line G1, the second scan signal line G2, the third scan signal line G3, the initial signal line INIT and the light-emitting signal line EM on the substrate. Illustratively, the orthographic projection of the fifth air vent located on the side of the first column of sub-pixels away from the second column of sub-pixels does not overlap with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor, as well as the reference signal line REF, the first scan signal line G1, the second scan signal line G2, the third scan signal line G3, the initial signal line INIT, the first power line VDD and the light-emitting signal line EM on the substrate. The orthographic projections of the remaining fifth air vents on the substrate at least partially overlap with the orthographic projection of the first power line VDD on the substrate, and do not overlap with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor, as well as the reference signal line REF, the first scan signal line G1, the second scan signal line G2, the third scan signal line G3, the initial signal line INIT and the light-emitting signal line EM on the substrate.

[0241] 8B , the length of the fourth ventilation hole H4 along the second direction D2 is greater than the length of the third via hole V3 along the second direction D2 , and the length of the fourth ventilation hole H4 along the first direction D1 is less than the length of the third via hole V3 along the first direction D1 .

[0242] In an exemplary embodiment, as shown in FIG8B , the fourth vent H4 and the seventh via V7 are arranged along the first direction D1, and the distance between the orthographic projection of the fourth vent H4 and the orthographic projection of the gate electrode 12 of the first transistor of the adjacent sub-pixel on the substrate is smaller than the distance between the orthographic projection of the seventh via V7 and the orthographic projection of the gate electrode 12 of the first transistor of the adjacent sub-pixel on the substrate. That is, the fourth vent H4 is located around the periphery of the casing hole including the third via V3 and the seventh via V7.

[0243] In an exemplary embodiment, as shown in FIG8B , the length of the fifth vent hole H5 along the second direction D2 is greater than the length of the fourth via hole V4 along the second direction D2, and the length of the fifth vent hole H5 along the first direction D1 is less than the length of the fourth via hole V4 along the first direction D1;

[0244] In an exemplary embodiment, as shown in FIG8B , the fifth vent H5 and the eighth via V8 are arranged along the first direction D1, and the distance between the orthographic projection of the fifth vent H5 on the substrate and the orthographic projection of the fourth via V4 on the substrate is smaller than the distance between the orthographic projection of the fourth via V4 on the substrate and the orthographic projection of the gate electrode 12 of the first transistor on the substrate. That is, the fifth vent H5 is located around the periphery of the casing including the fourth via V4 and the eighth via V8.

[0245] In an exemplary embodiment, FIG10 is a schematic diagram of a capacitor of a display substrate provided in FIG7A and FIG7B . In conjunction with FIG7A , FIG7B , and FIG10 , the pixel driving circuit further includes: a capacitor, the capacitor including: a first plate C1, a second plate C2, and a third plate C3, wherein the first plate C1 is electrically connected to the third plate C3;

[0246] The semiconductor layer includes at least: an active pattern of at least one transistor;

[0247] The first conductive layer includes at least: a gate electrode of at least one transistor and a first plate C1 of a capacitor;

[0248] The second conductive layer at least includes: a second plate C2 of the capacitor;

[0249] The third conductive layer at least includes: a first electrode and a second electrode of at least one transistor, a first scanning signal line G1, a second scanning signal line G2, a third scanning signal line G3, an emission signal line EM, an initial signal line INIT, a reference signal line REF, a first power line VDD and a third plate C3 of a capacitor;

[0250] The fourth conductive layer at least includes: a data signal line Data.

[0251] In an exemplary embodiment, as shown in Figure 10, the first plate C1 of the capacitor includes: a first gate connection portion and a second gate connection portion, the second gate connection portion of the sub-pixels in this column is located on a side of the first gate connection portion close to the sub-pixels in the next column, and the distance between the boundary of the first gate connection portion close to the gate electrode of the fifth transistor and the gate electrode of the fifth transistor is smaller than the distance between the boundary of the second gate connection portion close to the gate electrode of the fifth transistor and the gate electrode of the fifth transistor, and the distance between the boundary of the first gate connection portion away from the gate electrode of the fifth transistor and the gate electrode of the fifth transistor is smaller than the distance between the boundary of the second gate connection portion away from the gate electrode of the fifth transistor and the gate electrode of the fifth transistor.

[0252] In an exemplary embodiment, the length of the first gate connection portion in the first direction D1 is greater than the length of the second gate connection portion in the first direction D1 , and the length of the first gate connection portion in the second direction D2 is greater than the length of the second gate connection portion in the second direction D2 .

[0253] In an exemplary embodiment, Figure 11 is a schematic diagram of a portion of the film layers of a capacitor provided on a display substrate for Figures 7A and 7B, as shown in Figure 10. As shown in Figure 11, the orthographic projection of the second plate C2 of the capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the capacitor on the substrate.

[0254] In an exemplary embodiment, as shown in FIG11 , the second plates of the capacitors of the sub-pixels in the same column have the same shape and area, and the area of ​​the second plate of the capacitor of the sub-pixel in the 3k+1th column is smaller than either the area of ​​the second plate of the capacitor of the sub-pixel in the 3k+2th column or the area of ​​the second plate of the capacitor of the sub-pixel in the 3k+3th column.

[0255] In an exemplary embodiment, as shown in FIG11 , the area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the 3k+1th column of sub-pixels is smaller than the area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the 3k+2th column of sub-pixels, and the area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the 3k+2th column of sub-pixels is smaller than the area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the 3k+3th column of sub-pixels.

[0256] In an exemplary embodiment, as shown in FIG11 , the area of ​​the overlapping region between the second plate of the capacitor and the first gate connection portion of the 3k+1th column of sub-pixels is smaller than the area of ​​the overlapping region between the second plate of the capacitor and the first gate connection portion of the 3k+2th column of sub-pixels, and the area of ​​the overlapping region between the second plate of the capacitor and the first gate connection portion of the 3k+2th column of sub-pixels is smaller than the area of ​​the overlapping region between the second plate of the capacitor and the first gate connection portion of the 3k+3th column of sub-pixels.

[0257] In an exemplary embodiment, as shown in FIG11 , the area of ​​the overlapping region between the second plate and the second gate connection portion of the capacitor of the 3k+1th column of sub-pixels is smaller than the area of ​​the overlapping region between the second plate and the second gate connection portion of the capacitor of the 3k+2th column of sub-pixels, and the area of ​​the overlapping region between the second plate and the second gate connection portion of the capacitor of the 3k+3th column of sub-pixels is smaller than the area of ​​the overlapping region between the second plate and the second gate connection portion of the capacitor of the 3k+2th column of sub-pixels.

[0258] In an exemplary embodiment, as shown in FIG10 , the orthographic projection of the third plate of the capacitor on the substrate at least partially overlaps with the orthographic projections of the first plate of the capacitor and the second plate of the capacitor on the substrate, respectively, and the orthographic projection on the substrate has a non-overlapping area with the orthographic projection of the first plate of the capacitor on the substrate, and has a non-overlapping area with the orthographic projection of the second plate of the capacitor on the substrate.

[0259] In an exemplary embodiment, as shown in FIG. 7A , FIG. 7B , FIG. 8A and FIG. 8B , the display substrate may further include an initial connection line L1 located in the first conductive layer, the initial connection line L1 at least partially extending along the second direction D2 , and the initial connection line L1 being electrically connected to the initial signal line INIT.

[0260] In an exemplary embodiment, as shown in Figures 7A, 7B, 8A and 8B, two initial connection lines L1 are provided between at least two columns of sub-pixels, and the two initial connection lines L1 located between at least two adjacent sub-pixels are symmetrically arranged with respect to a midline extending along the second direction D2 between the two adjacent sub-pixels.

[0261] In an exemplary embodiment, the plurality of initial connection lines L1 and the plurality of initial signal lines INIT form a mesh structure, which can improve the display uniformity of the display substrate and further improve the reliability of the display substrate.

[0262] In an exemplary embodiment, as shown in FIG. 8A and FIG. 8B , the orthographic projection of the sixth via hole V6 on the substrate does not overlap with the orthographic projection of the initial connection line L2 on the substrate.

[0263] In an exemplary embodiment, as shown in Figures 7A and 7B, the display substrate may further include: at least one of a power connection line L2 and a reference connection line L3 located in the fourth conductive layer, and either of the power connection line L2 and the reference connection line L3 extends at least partially along the second direction D2.

[0264] In an exemplary embodiment, as shown in FIG. 7A and FIG. 7B , the power connection line L2 is electrically connected to the first power line VDD, and the reference connection line is electrically connected to the reference signal line REF.

[0265] In an exemplary embodiment, as shown in Figures 7A and 7B, between the orthographic projection of at least a portion of the reference connection line L3 on the substrate and the orthographic projections of two initial connection lines L1 located between two adjacent sub-pixels on the substrate, the orthographic projection of the power connection line L2 on the substrate and the orthographic projection of the initial connection line L1 on the substrate are away from the side of the orthographic projection of the reference connection line L3 on the substrate.

[0266] In an exemplary embodiment, multiple reference connection lines L3 and multiple reference signal lines REF form a mesh structure, and multiple power connection lines L2 and multiple first power lines VDD form a mesh structure, which can improve the display uniformity of the display substrate and further improve the reliability of the display substrate.

[0267] In an exemplary embodiment, as shown in FIG8B , when the fifth insulating layer is provided with at least one of the first to fifth ventilation holes H1 to H5, the orthographic projections of the first to fifth ventilation holes H1 to H5 on the substrate do not overlap with the orthographic projections of the power connection line L2, the reference connection line L3, and the data signal line Data on the substrate.

[0268] In an exemplary embodiment, as shown in FIG. 8B , the orthographic projection of the fourth vent hole H4 on the substrate partially overlaps with the orthographic projection of the initial connection line L1 on the substrate.

[0269] In an exemplary embodiment, the light-emitting structure layer is further included, the sub-pixel further includes a light-emitting device, the light-emitting device includes a first electrode, an organic light-emitting layer, and a second electrode, the light-emitting structure layer includes the light-emitting device, and the light-emitting structure layer includes a fifth conductive layer, a first pixel definition layer, a second pixel definition layer, a light-emitting material layer, and a sixth conductive layer sequentially stacked on a side of the driving structure layer away from the substrate;

[0270] The fifth conductive layer at least includes: a first electrode;

[0271] The light-emitting material layer at least includes: an organic light-emitting layer;

[0272] The sixth conductive layer includes at least a second electrode.

[0273] In an exemplary embodiment, light transmittance of the first pixel definition layer may be lower than light transmittance of the second pixel definition layer.

[0274] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0275] The following is an illustrative explanation using the preparation process of a display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0276] In an exemplary embodiment, taking six sub-pixels (one sub-pixel row, six sub-pixel columns, for example, first to sixth columns of sub-pixels) as an example, the preparation process of the display substrate may include the following operations.

[0277] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG12 , which is a schematic diagram of the semiconductor layer pattern in FIG7A and FIG7B .

[0278] In an exemplary embodiment, as shown in FIG. 12 , the semiconductor layer pattern may include at least active patterns 11 of first to fifth transistors 51 located in each sub-pixel.

[0279] In an exemplary embodiment, the active pattern 11 of the first transistor may be provided separately, the active pattern 21 of the second transistor and the active pattern 41 of the fourth transistor are connected as an integral structure, and the active pattern 31 of the third transistor and the active pattern 51 of the fifth transistor are connected as an integral structure.

[0280] In an exemplary embodiment, in the second direction D2, the integrated structure of the active pattern 21 of the second transistor and the active pattern 41 of the fourth transistor and the active pattern 11 of the first transistor are located on different sides of the integrated structure of the active pattern 31 of the third transistor and the active pattern 51 of the fifth transistor, respectively. The integrated structure of the active pattern 21 of the second transistor and the active pattern 41 of the fourth transistor of the present subpixel is located on the side of the integrated structure of the active pattern 31 of the third transistor and the active pattern 51 of the fifth transistor of the present subpixel that is closer to the subpixels in the previous row, while the active pattern 11 of the first transistor of the present subpixel is located on the side of the integrated structure of the active pattern 31 of the third transistor and the active pattern 51 of the fifth transistor of the present subpixel that is closer to the subpixels in the next row. The active pattern 41 of the fourth transistor is located on the side of the active pattern 21 of the second transistor that is closer to the active pattern 11 of the first transistor, and the active pattern 51 of the fifth transistor is located on the side of the active pattern 31 of the third transistor that is closer to the active pattern 11 of the first transistor.

[0281] In an exemplary embodiment, the active pattern 11 of the first transistor may include a first active connection portion 11A, a second active connection portion 11B, and a third active connection portion 11C. The first active connection portion 11A is located on a side of the second active connection portion 11B closer to the integrated structure of the active pattern 31 of the third transistor and the active pattern 51 of the fifth transistor. The third active connection portion 11C is located on a side of the second active connection portion 11B farther from the integrated structure of the active pattern 31 of the third transistor and the active pattern 51 of the fifth transistor. The first active connection portion 11A may have a strip shape and extend along the second direction D2. The second active connection portion 11B may have a strip shape and extend along the first direction D1. The third active connection portion 11C may have an L-shape. One end of the first active connection portion 11A is connected to one end of the second active connection portion 11B, and one end of the third active connection portion 11C is connected to the other end of the second active connection portion 11B.

[0282] In an exemplary embodiment, the active pattern 21 of the second transistor may be in a “┐” shape, the active pattern 31 of the third transistor may be in a left-rotated “Ω” shape, the active pattern 41 of the fourth transistor may be in an “n” shape, and the active pattern 51 of the fifth transistor may be in an “I” shape.

[0283] In an exemplary embodiment, the first active connection portion 11A and the active pattern 51 of the fifth transistor are arranged along the second direction D2.

[0284] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 21-2 of the active pattern 21 of the second transistor may serve as the second region 41-2 of the active pattern 41 of the fourth transistor, and the first region 31-1 of the active pattern 31 of the third transistor may serve as the second region 51-2 of the active pattern 51 of the fifth transistor. The first region 11-1 and the second region 11-2 of the active pattern 11 of the first transistor, the first region 21-1 of the active pattern 21 of the second transistor, the second region 31-2 of the active pattern 31 of the third transistor, the first region 41-1 of the active pattern 41 of the fourth transistor, and the first region 51-1 of the active pattern 51 of the fifth transistor may be provided separately.

[0285] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in Figures 13 and 14, where Figure 13 is a schematic diagram of the first conductive layer pattern in Figures 7A and 7B, and Figure 14 is a schematic diagram of Figures 7A and 7B after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0286] In an exemplary embodiment, the first conductive layer pattern may include at least: gate electrodes 12 to 52 of the first transistor and the first plate C1 of the capacitor in each sub-pixel, and two initial connection lines L1 between at least two columns of adjacent sub-pixels.

[0287] In an exemplary embodiment, the initial connection line L1 may be in the shape of a line with a main portion extending along the second direction D2, and at least two initial connection lines L1 between two adjacent sub-pixels are symmetrically arranged with respect to a midline extending along the second direction D2 between the two adjacent sub-pixels.

[0288] In an exemplary embodiment, the gate electrode 32 of the third transistor and the first plate C1 of the capacitor are connected as an integral structure. The gate electrode 12 of the first transistor, the gate electrode 22 of the second transistor, the gate electrode 42 of the fourth transistor, and the gate electrode 52 of the fifth transistor can be provided separately.

[0289] In an exemplary embodiment, the integrated structure of the gate electrode 32 of the third transistor and the first plate C1 of the capacitor includes: a first gate connection portion 32A and a second gate connection portion 32B. The shapes of the first gate connection portion 32A and the second gate connection portion 32B can be rectangular. The second gate connection portion 32B of the sub-pixels in this column is located on the side of the first gate connection portion 32A close to the sub-pixels in the next column. The distance between the boundary of the first gate connection portion 32A close to the gate electrode 52 of the fifth transistor and the gate electrode 52 of the fifth transistor is smaller than the distance between the boundary of the second gate connection portion 32B close to the gate electrode 52 of the fifth transistor and the gate electrode 52 of the fifth transistor. The distance between the boundary of the first gate connection portion 32A away from the gate electrode 52 of the fifth transistor and the gate electrode 52 of the fifth transistor is smaller than the distance between the boundary of the second gate connection portion 32B away from the gate electrode 52 of the fifth transistor and the gate electrode 52 of the fifth transistor.

[0290] In an exemplary embodiment, the length of the first gate connection portion 32A in the first direction D1 is greater than the length of the second gate connection portion 32B in the first direction D1, and the length of the first gate connection portion 32A in the second direction D2 is greater than the length of the second gate connection portion 32B in the second direction D2.

[0291] In an exemplary embodiment, the gate electrode 12 of the first transistor may include a first connecting segment 12A and two first branch segments 12B. The two first branch segments 12B are located on a side of the first connecting segment 12A close to the gate electrode 32 of the third transistor (also the first plate C1 of the capacitor) and are respectively connected to the first connecting segment 12A. One end of one of the first branch segments 12B is connected to the end of the first connecting segment 12A, and the other first branch segment 12B is connected to the middle of the first connecting segment 12A. The first connecting segment 12A may be strip-shaped and extend along a first direction D1. The first branch segments 12B extend along a second direction D2, and the two first branch segments 12B are arranged along the first direction D1.

[0292] In an exemplary embodiment, the length of the first branch segment 12A along the first direction D1 is less than the sum of the lengths of the first gate connection portion 32A and the second gate connection portion 32B along the first direction D1, and is greater than the length of the second gate connection portion 32B along the first direction D1. The first branch segment 12A of the sub-pixel in this column is close to the boundary of the sub-pixel in the next column, and the second gate connection portion 32B of the sub-pixel in this column is close to the boundary of the sub-pixel in the next column, and are arranged along the second direction D2.

[0293] In an exemplary embodiment, the gate electrode 22 of the second transistor may include a second connecting segment 22A and two second branch segments 22B. The two second branch segments 22B are located on a side of the second connecting segment 22A away from the gate electrode 32 of the third transistor (also the first plate C1 of the capacitor) and are respectively connected to the second connecting segment 22A. One end of one second branch segment 22B is connected to an end of the second connecting segment 22A, and the other second branch segment 22B is connected to the middle of the second connecting segment 22A. The second connecting segment 22A may be strip-shaped and extend along a first direction D1. The second branch segments 22B extend along a second direction D2, and the two second branch segments 22B are arranged along the first direction D1.

[0294] In an exemplary embodiment, the length of the second branch segment 22A along the first direction D1 is less than the length of the first gate connection portion 32A along the first direction D1, and the distance between the straight line where the second branch segment 22A of the current column of sub-pixels is close to the boundary of the next column of sub-pixels and the straight line where the first gate connection portion 32A is close to the boundary of the previous column of sub-pixels is less than the length of the first gate connection portion 32A along the first direction D1.

[0295] In an exemplary embodiment, the length of the first connecting segment 12A along the first direction D1 is greater than the length of the second connecting segment 22A along the first direction D1.

[0296] In an exemplary embodiment, the gate electrode 42 of the fourth transistor may include a third connecting segment 42A and two third branch segments 42B. The two third branch segments 42B are located on a side of the third connecting segment 42A close to the gate electrode 32 of the third transistor (also the first plate C1 of the capacitor) and are respectively connected to the third connecting segment 42A. One end of one third branch segment 42B is connected to an end of the third connecting segment 42A, and the other third branch segment 42B is connected to the middle of the third connecting segment 42A. The third connecting segment 42A may be strip-shaped and extend along the first direction D1. The third branch segments 42B extend along the second direction D2, and the two third branch segments 42B are arranged along the first direction D1.

[0297] In an exemplary embodiment, the length of the third branch segment 42A along the first direction D1 is less than the length of the first gate connection portion 32A along the first direction D1, and the distance between the straight line where the third branch segment 42A of the current column of sub-pixels is close to the boundary of the next column of sub-pixels and the straight line where the first gate connection portion 32A of the current column of sub-pixels is close to the boundary of the previous column of sub-pixels is less than the length of the first gate connection portion 32A along the first direction D1.

[0298] In an exemplary embodiment, the length of the third connecting segment 42A along the first direction D1 is greater than the length of the second connecting segment 22A along the first direction D1, and the length of the third branch segment 42B along the second direction D2 is greater than the length of the second branch segment 22B along the second direction D2.

[0299] In an exemplary embodiment, the area of ​​the gate electrode 42 of the fourth transistor is larger than the area of ​​the gate electrode 22 of the second transistor.

[0300] In example embodiments, the gate electrode 52 of the fifth transistor may be shaped like a bar and extend along the first direction D1 .

[0301] In an exemplary embodiment, the length of the gate electrode 52 of the fifth transistor along the first direction D1 is less than the length of the first gate connection portion 32A along the first direction D1, and the gate electrode 52 of the fifth transistor of the current column of sub-pixels near the boundary of the next column of sub-pixels is located between the boundary of the first gate connection portion 32A near the boundary of the previous column of sub-pixels and the boundary of the first gate connection portion 32A near the boundary of the next column of sub-pixels.

[0302] In an exemplary embodiment, the two first branch segments 12B of the gate electrode 12 of the first transistor are arranged across the active pattern of the first transistor, the two second branch segments 22B of the gate electrode 22 of the second transistor are arranged across the active pattern of the second transistor, the gate electrode 32 of the third transistor (which is also the first plate C1 of the capacitor) is arranged across the active pattern of the third transistor, the third branch segment 42B of the gate electrode 42 of the fourth transistor is arranged across the active pattern of the fourth transistor, and the gate electrode 52 of the fifth transistor is arranged across the active pattern of the fifth transistor. That is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0303] In an exemplary embodiment, the two first branch segments 12B of the gate electrode 12 of the first transistor are arranged across the active pattern of the first transistor, that is, the first transistor has a dual-gate structure, which is structurally equivalent to a sub-pixel including two first transistors connected in series.

[0304] In an exemplary embodiment, the two second branch segments 22B of the gate electrode 22 of the second transistor are arranged across the active pattern of the second transistor, that is, the second transistor has a dual-gate structure, which is structurally equivalent to a sub-pixel including two second transistors connected in series.

[0305] In an exemplary embodiment, the two third branch segments 42B of the gate electrode 42 of the fourth transistor are arranged across the active pattern of the fourth transistor, that is, the fourth transistor has a dual-gate structure, which is structurally equivalent to a sub-pixel including two fourth transistors connected in series.

[0306] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer pattern can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the fifth transistor T5, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the active pattern of the first transistor to the active pattern of the fifth transistor are both conductorized. After conductorization, the first area of ​​the active pattern of the third transistor (which is also the second area of ​​the active pattern of the fifth transistor) can serve as the first electrode 33 of the third transistor and the second electrode 54 of the fifth transistor.

[0307] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process to form a third insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the third insulating layer, as shown in Figures 15 and 16, where Figure 15 is a schematic diagram of the second conductive layer pattern in Figures 7A and 7B, and Figure 16 is a schematic diagram of Figures 7A and 7B after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0308] In an exemplary embodiment, as shown in FIG. 15 and FIG. 16 , the second conductive layer pattern may include at least a second plate C2 of a capacitor located in each sub-pixel.

[0309] In an exemplary embodiment, the main portion of the second plate C2 of the capacitor is rectangular in shape. The second plate C2 of the capacitor of at least one sub-pixel may further include at least one protrusion.

[0310] In an exemplary embodiment, an orthographic projection of the second plate C2 of the capacitor on the substrate at least partially overlaps an orthographic projection of the gate electrode of the third transistor (which is also the first plate of the capacitor) on the substrate.

[0311] In an exemplary embodiment, for any sub-pixel, the line where the second plate C2 of the capacitor of the current column of sub-pixels is close to the boundary of the next column of sub-pixels coincides with the line where the second gate connection portion is close to the boundary of the next column of sub-pixels.

[0312] In an exemplary embodiment, for any sub-pixel, a distance between an orthographic projection of the second plate C2 of the capacitor on the substrate and an orthographic projection of the active pattern of the first transistor on the substrate is smaller than a distance between an orthographic projection of the second gate connection portion on the substrate and an orthographic projection of the active pattern of the first transistor on the substrate.

[0313] In an exemplary embodiment, the second plates of the capacitors of sub-pixels in the same column have the same shape and area.

[0314] In an exemplary embodiment, the second plates C2 of the capacitors of the sub-pixels in the (3k + 1)-th column have the same shape and area, where 0 ≤ k < N / 3 and N is the total number of columns of the sub-pixels.

[0315] In an exemplary embodiment, the second plates C2 of the capacitors of the sub-pixels in the (3k + 2)-th column have the same shape and area.

[0316] In an exemplary embodiment, the second plates C2 of the capacitors of the sub-pixels in the (3k + 3)-th column have the same shape and area.

[0317] In an exemplary embodiment, the area of the second plate C2 of the capacitor of the sub-pixel in the (3k + 1)-th column is smaller than any one of the areas of the second plate C2 of the capacitor of the sub-pixel in the (3k + 2)-th column and the second plate C2 of the capacitor of the sub-pixel in the (3k + 3)-th column.

[0318] In an exemplary embodiment, the length of the second plate C2 of the capacitor of the sub-pixel in the (3k + 2)-th column along a direction D1 is smaller than the length of the second plate C2 of the capacitor of the sub-pixel in the (3k + 3)-th column along the first direction D1, and the length of the second plate C2 of the capacitor of the sub-pixel in the (3k + 2)-th column along a second direction D2 is greater than the length of the second plate C2 of the capacitor of the sub-pixel in the (3k + 3)-th column along the second direction D2.

[0319] In an exemplary embodiment, the area of the overlapping region between the second plate C2 of the capacitor of the sub-pixel in the (3k + 1)-th column and the first plate of the capacitor is smaller than the area of the overlapping region between the second plate C2 of the capacitor of the sub-pixel in the (3k + 2)-th column and the first plate of the capacitor, and the area of the overlapping region between the second plate C2 of the capacitor of the sub-pixel in the (3k + 2)-th column and the first plate of the capacitor is smaller than the area of the overlapping region between the second plate C2 of the capacitor of the sub-pixel in the (3k + 3)-th column and the first plate of the capacitor.

[0320] In an exemplary embodiment, the area of the overlapping region between the second plate C2 of the capacitor of the sub-pixel in the (3k + 1)-th column and the first gate connection portion is smaller than the area of the overlapping region between the second plate C2 of the capacitor of the sub-pixel in the (3k + 2)-th column and the first gate connection portion, and the area of the overlapping region between the second plate C2 of the capacitor of the sub-pixel in the (3k + 2)-th column and the first gate connection portion is smaller than the area of the overlapping region between the second plate C2 of the capacitor of the sub-pixel in the (3k + 3)-th column and the first gate connection portion.

[0321] In an exemplary embodiment, the area of ​​the overlapping region between the second plate C2 of the capacitor and the second gate connection portion of the sub-pixel in the 3k+1th column is smaller than the area of ​​the overlapping region between the second plate C2 of the capacitor and the second gate connection portion of the sub-pixel in the 3k+2th column, and the area of ​​the overlapping region between the second plate C2 of the capacitor and the second gate connection portion of the sub-pixel in the 3k+3th column is smaller than the area of ​​the overlapping region between the second plate C2 of the capacitor and the second gate connection portion of the sub-pixel in the 3k+2th column.

[0322] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer pattern covering the second conductive layer, wherein a plurality of vias are provided in the fourth insulating layer pattern, as shown in FIG17 , which is a schematic diagram of the fourth insulating layer pattern after FIG7A and FIG7B are formed.

[0323] In an exemplary embodiment, as shown in FIG. 17 , the fourth insulation layer pattern may include at least ninth to twenty-first via holes V9 to V21 located in each sub-pixel and a twenty-second via hole V22 located between at least two columns of adjacent sub-pixels.

[0324] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor on the substrate, the second insulating layer and the third insulating layer within the ninth via V9 are etched away to expose the surface of the first area of ​​the active pattern of the first transistor, and the ninth via V9 is configured to connect a subsequently formed initial signal line to the first area of ​​the active pattern of the first transistor through the via.

[0325] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor on the substrate, the second insulating layer and the third insulating layer within the tenth via V10 are etched away, exposing the surface of the second area of ​​the active pattern of the first transistor, and the tenth via V10 is configured to connect the second electrode of the subsequently formed first transistor to the second area of ​​the active pattern of the first transistor through the via.

[0326] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second transistor on the substrate, the second insulating layer and the third insulating layer within the eleventh via V11 are etched away, exposing the surface of the first area of ​​the active pattern of the second transistor, and the eleventh via V11 is configured to connect a subsequently formed reference signal line to the first area of ​​the active pattern of the second transistor through the via.

[0327] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the fourth transistor) on the substrate, the second insulating layer and the third insulating layer within the twelfth via V12 are etched away to expose the surface of the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the fourth transistor), and the twelfth via V12 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the fourth transistor and the third plate of the capacitor) to the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the fourth transistor) through the via.

[0328] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the third transistor on the substrate, the second insulating layer and the third insulating layer in the thirteenth via V13 are etched away, exposing the surface of the second area of ​​the active pattern of the third transistor, and the thirteenth via V13 is configured to connect the second electrode of the subsequently formed third transistor to the second area of ​​the active pattern of the third transistor through the via.

[0329] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the second insulating layer and the third insulating layer in the fourteenth via V14 are etched away to expose the surface of the first area of ​​the active pattern of the fourth transistor, and the fourteenth via V14 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via.

[0330] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor on the substrate, the second insulating layer and the third insulating layer in the fifteenth via V15 are etched away, exposing the surface of the first area of ​​the active pattern of the fifth transistor, and the fifteenth via V15 is configured to connect a subsequently formed light-emitting signal line to the first area of ​​the active pattern of the fifth transistor through the via.

[0331] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is within the range of the orthographic projection of the gate electrode of the first transistor on the substrate. The third insulating layer within the sixteenth via hole V16 is etched away, exposing the surface of the gate electrode of the first transistor. The sixteenth via hole V16 is configured to connect a subsequently formed third scan signal line to the gate electrode of the first transistor through the via hole. Exemplarily, the sixteenth via hole V16 exposes the surface of the first connecting segment of the gate electrode of the first transistor.

[0332] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the gate electrode of the second transistor on the substrate. The third insulating layer within the seventeenth via hole V17 is etched away, exposing the surface of the gate electrode of the second transistor. The seventeenth via hole V17 is configured to connect a subsequently formed second scan signal line to the gate electrode of the second transistor through the via hole. Exemplarily, the seventeenth via hole V17 exposes the surface of the second connecting segment of the gate electrode of the second transistor.

[0333] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the gate electrode of the third transistor (also the first plate of the capacitor) on the substrate, the third insulating layer in the eighteenth via V18 is etched away to expose the surface of the gate electrode of the third transistor (also the first plate of the capacitor), and the eighteenth via V18 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the fourth transistor) to the gate electrode of the third transistor (also the first plate of the capacitor) through the via.

[0334] In an exemplary embodiment, the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth transistor on the substrate. The third insulating layer within the nineteenth via hole V19 is etched away, exposing the surface of the gate electrode of the fourth transistor. The nineteenth via hole V19 is configured to connect a subsequently formed first scan signal line to the gate electrode of the fourth transistor through the via hole. Exemplarily, the nineteenth via hole V19 exposes the surface of the third connecting segment of the gate electrode of the fourth transistor.

[0335] In an exemplary embodiment, the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth transistor on the substrate, the third insulating layer in the twentieth via hole V20 is etched away to expose the surface of the gate electrode of the fifth transistor, and the twentieth via hole V20 is configured to connect a subsequently formed light-emitting signal line to the gate electrode of the fifth transistor through the via hole.

[0336] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the second plate of the capacitor on the substrate, the twenty-first via V21 exposes the surface of the second plate of the capacitor, and the twenty-first via V21 is configured to connect the second electrode of the subsequently formed third transistor and the second electrode of the first transistor to the second plate of the capacitor through the via.

[0337] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the initial connecting line on the substrate, the third insulating layer in the twenty-second via V22 is etched away to expose the surface of the initial connecting line, and the twenty-second via V22 is configured to connect the subsequently formed initial signal line to the initial connecting line through the via.

[0338] In an exemplary embodiment, a virtual straight line extending along the first direction D1 passes through the ninth via hole V9 and the twenty-second via hole V22. A virtual straight line extending along the first direction D1 passes through the thirteenth via hole V13 and another portion of the twenty-first via hole V21. A virtual straight line extending along the first direction D1 passes through the twelfth via hole V12 and the fourteenth via hole V14.

[0339] In an exemplary embodiment, a virtual straight line extending along the second direction D2 passes through the tenth via hole V10 and another portion of the twenty-first via hole V21. A virtual straight line extending along the second direction D2 passes through the twelfth via hole V12 and the eighteenth via hole V18. A virtual straight line extending along the second direction D2 passes through the eleventh via hole V11, the thirteenth via hole V13, and the fifteenth via hole V15.

[0340] In an exemplary embodiment, in each sub-pixel, the number of the ninth via hole V9 may be at least one. When the number of the ninth via hole V9 is plural, the plurality of ninth via holes V9 are arranged along the first direction D1.

[0341] In an exemplary embodiment, in each sub-pixel, the number of any one of the tenth via hole V10 , the eleventh via hole V11 , the twelfth via hole V12 , the thirteenth via hole V13 , the fourteenth via hole V14 , the fifteenth via hole V15 , and the eighteenth via hole V18 may be one.

[0342] In an exemplary embodiment, in each sub-pixel, the number of the sixteenth via hole V16 may be plural, and the plurality of sixteenth via holes V16 are arranged along the first direction D1.

[0343] In an exemplary embodiment, in each sub-pixel, the number of the seventeenth via hole V17 may be plural, and the plurality of seventeenth via holes V17 are arranged along the first direction D1.

[0344] In an exemplary embodiment, in each sub-pixel, the number of the nineteenth via hole V19 may be plural, and the plurality of nineteenth via holes V19 are arranged along the first direction D1.

[0345] In an exemplary embodiment, in each sub-pixel, the number of the twentieth via hole V20 may be plural, and the plurality of twentieth via holes V20 are arranged along the first direction D1.

[0346] In an exemplary embodiment, the number of the twenty-first vias V21 can be multiple, and at least part of the twenty-first vias V21 in the current row of sub-pixels are arranged along the first direction D1 and are located at the second plate of the capacitor close to the boundary of the previous row of sub-pixels, and another part of the twenty-first vias V21 in the current row of sub-pixels are located at the second plate of the capacitor close to the boundary of the next row of sub-pixels.

[0347] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process, and forming a third conductive layer pattern on the fourth insulating layer, as shown in Figures 18 and 19. Figure 18 is a schematic diagram of the third conductive layer pattern in Figures 7A and 7B, and Figure 19 is a schematic diagram of Figures 7A and 7B after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0348] In an exemplary embodiment, as shown in Figures 18 and 19, the third conductive layer pattern may include at least: the first electrode 13 and the second electrode 14 of the first transistor located in each sub-pixel, the second electrode 23 and the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, the first electrode 43 and the second electrode 44 of the fourth transistor, the first electrode 53 of the fifth transistor, the third plate C3 of the capacitor, the first scan signal line G1, the second scan signal line G2, the third scan signal line G3, the reference signal line REF, the light emitting signal line EM, the first power line VDD and the initial signal line INIT.

[0349] In an exemplary embodiment, the reference signal line REF may be in the shape of a line with a main portion extending along a first direction D1. The reference signal line REF connected to the sub-pixels in the current row may be located on the side of the third plate C3 of the capacitor of the current sub-pixel that is closest to the sub-pixels in the previous row. Each reference signal line REF is provided with a first connection block REF-1, the first end of which is connected to the reference signal line REF. The first connection block REF-1 is located on the side of the reference signal line REF that is closest to the third plate C3 of the capacitor and extends along the second direction D2. The orthographic projection of at least a portion of the first connection block REF-1 on the substrate is located between the orthographic projections of the two first signal lines on the substrate. The region where the reference signal line REF overlaps with the active pattern of the second transistor may serve as the first electrode 23 of the second transistor. The reference signal line REF is electrically connected to the first region of the active pattern of the second transistor via a third via.

[0350] In an exemplary embodiment, the second scan signal line G2 may be in the shape of a line with a main portion extending along the first direction D1. The second scan signal line G2 connected to the sub-pixels in the row may be located between the third plate C3 of the capacitor of the sub-pixel and the reference signal line REF connected to the sub-pixels in the row. The orthographic projection of the second scan signal line G2 on the substrate at least partially overlaps with the orthographic projection of the second connecting segment of the gate electrode of the second transistor on the substrate. The second scan signal line G2 is electrically connected to the gate electrode of the second transistor through a seventeenth via hole.

[0351] In an exemplary embodiment, the first scan signal line G1 may be in the shape of a line with a main portion extending along the first direction D1. The first scan signal line G1 connected to the sub-pixels in the row may be located between the third plate C3 of the capacitor of the sub-pixels and the second scan signal line G2 connected to the sub-pixels in the row. The orthographic projection of the first scan signal line G1 on the substrate at least partially overlaps with the orthographic projection of the third connecting segment of the gate electrode of the fourth transistor on the substrate. The first scan signal line G1 is electrically connected to the gate electrode of the fourth transistor through a nineteenth via.

[0352] In an exemplary embodiment, the light-emitting signal line EM may be in the shape of a line with a main portion extending along the first direction D1. The light-emitting signal line EM connected to the sub-pixels in the row may be located on a side of the third plate C3 of the capacitor of the sub-pixel away from the first scanning signal line G1 connected to the sub-pixels in the row. The orthographic projection of the light-emitting signal line EM on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the fifth transistor on the substrate, and the light-emitting signal line EM is electrically connected to the gate electrode of the fifth transistor through a twentieth via hole.

[0353] In an exemplary embodiment, the first power line VDD may be in the shape of a line with a main portion extending along a first direction D1. The first power line VDD connected to the sub-pixels in the row may be located on a side of the light-emitting signal line EM connected to the sub-pixels, away from the third plate C3 of the capacitor. Each first power line VDD is provided with a second connection block VDD-1, the first end of which is connected to the first power line VDD. The second connection block VDD-1 is located on a side of the first power line VDD away from the third plate C3 of the capacitor and extends along the second direction D2. The area where the first power line VDD overlaps with the active pattern of the fifth transistor may serve as the first electrode 53 of the fifth transistor. The first power line VDD is electrically connected to the first region of the active pattern of the fifth transistor via a fifteenth via.

[0354] In an exemplary embodiment, straight lines extending in the second direction D2 where the second connection blocks VDD- 1 are located are alternately arranged with straight lines extending in the second direction D2 where the first connection wires REF- 1 are located.

[0355] In an exemplary embodiment, the third scan signal line G3 may be in the shape of a line with a main portion extending along the first direction D1. The third scan signal line G3 connected to the sub-pixels in the row may be located on a side of the first power line VDD connected to the sub-pixels that is away from the third plate C3 of the capacitor of the sub-pixels in the row. The orthographic projection of the third scan signal line G3 on the substrate at least partially overlaps with the orthographic projection of the first connecting segment of the gate electrode of the first transistor on the substrate, and the third scan signal line G3 is electrically connected to the gate electrode of the first transistor through a sixteenth via hole.

[0356] In an exemplary embodiment, the initial signal line INIT may be in the shape of a line with a main portion extending along the first direction D1. The initial signal line INIT connected to the sub-pixels in the row may be located on a side of the third scanning signal line G3 connected to the sub-pixels in the row that is away from the first power line VDD connected to the sub-pixels in the row. The region where the initial signal line INIT overlaps with the active pattern of the first transistor may serve as the first electrode 13 of the first transistor. The initial signal line INIT is electrically connected to the first region of the active pattern of the first transistor via a ninth via hole and is connected to the first signal line via a twenty-second via hole.

[0357] In an exemplary embodiment, the second electrode 24 of the second transistor, the second electrode 44 of the fourth transistor and the third electrode plate C3 of the capacitor are an integrated structure connected to each other, and the second electrode 14 of the first transistor, the second electrode 34 of the third transistor and the first electrode 43 of the fourth transistor can be set separately.

[0358] In an exemplary embodiment, the orthographic projections of the integrated structure of the second electrode 24 of the second transistor, the second electrode 44 of the fourth transistor, and the third plate C3 of the capacitor on the substrate at least partially overlap with the orthographic projections of the first plate of the capacitor and the second plate of the capacitor on the substrate, respectively. The orthographic projections of the integrated structure of the second electrode 24 of the second transistor, the second electrode 44 of the fourth transistor, and the third plate C3 of the capacitor on the substrate do not overlap with the orthographic projections of the first plate of the capacitor on the substrate, and do not overlap with the orthographic projections of the second plate of the capacitor on the substrate.

[0359] In an exemplary embodiment, the integrated structure of the second electrode 24 of the second transistor, the second electrode 44 of the fourth transistor, and the third plate C3 of the capacitor includes a first electrode connection portion 24A and a second electrode connection portion 24B. The second electrode connection portion 24B is located on a side of the first electrode connection portion 24A closer to the first scan signal line G1 and is disposed at a right angle to the first electrode connection portion 24A. The second electrode connection portion 24B may be strip-shaped and extend along the second direction D2. The first electrode connection portion 24A may be shaped like a circle, wherein the width of the portion of the first electrode connection portion 24A extending along the second direction D2 is greater than the width of the portion of the first electrode connection portion 24A extending along the first direction D1. The second electrode 24 of the second transistor (also the second electrode 44 of the fourth transistor and the third plate C3 of the capacitor) is connected to the second region of the active pattern of the second transistor (also the second region of the active pattern of the fourth transistor) via a twelfth via hole, and is connected to the gate electrode of the third transistor (also the first plate of the capacitor) via an eighteenth via hole.

[0360] In an exemplary embodiment, the second electrode 14 of the first transistor is located on a side of the first electrode connection portion 24A close to the light-emitting signal line EM and is arranged along the second direction D2 with the second electrode connection portion 24B. The second electrode 14 of the first transistor can be strip-shaped and extend along the second direction D2. The second electrode 14 of the first transistor is connected to the second region of the active pattern of the first transistor through a tenth via hole and is electrically connected to the second plate of the capacitor through a twenty-first via hole.

[0361] In an exemplary embodiment, a length of the second electrode 14 of the first transistor along the first direction D1 is greater than a length of the second electrode connection portion 24B along the first direction D1.

[0362] In an exemplary embodiment, the second electrode 34 of the third transistor is located on a side of the first electrode connection portion 24A close to the first scan signal line G1, and the second electrode 34 of the third transistor in the current column of sub-pixels is located on a side of the second electrode connection portion 24B close to the sub-pixels in the previous column of sub-pixels. The second electrode 34 of the third transistor and the second electrode connection portion 24B are arranged along the first direction D1. The second electrode 34 of the third transistor may be shaped like a character "┘", and the width of the portion of the second electrode 34 of the third transistor extending along the second direction D2 is greater than the width of the portion of the second electrode 34 of the third transistor extending along the first direction D1. The second electrode 34 of the third transistor is connected to the second region of the active pattern of the third transistor via a thirteenth via hole, and is electrically connected to the second plate of the capacitor via a twenty-first via hole.

[0363] In an exemplary embodiment, the first electrode 43 of the fourth transistor is located between the second electrode 34 of the third transistor and the first scan signal line G1, and is located on a side of the second electrode 34 of the third transistor away from the second electrode connecting portion 24B. The first electrode 43 of the fourth transistor may be in a block shape. The first electrode 43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through a fourteenth via.

[0364] In an exemplary embodiment, the first scanning signal line G1, the second scanning signal line G2, the third scanning signal line G3, the reference signal line REF, the light-emitting signal line EM, the first power line VDD and the initial signal line INIT can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure is not limited here.

[0365] (6) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer pattern covering the third conductive layer pattern, wherein a plurality of vias are provided on the first planar layer pattern, as shown in FIG20 , which is a schematic diagram of FIG7A and FIG7B after the first planar layer pattern is formed.

[0366] In an exemplary embodiment, as shown in FIG. 20 , the plurality of via holes in the first planar layer pattern include at least a first via hole V1 and a second via hole V2 located in each sub-pixel, and a third via hole V3 and a fourth via hole V4 located between at least two columns of adjacent sub-pixels.

[0367] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the second electrode of the third transistor on the substrate, the first via V1 exposes the surface of the second electrode of the third transistor, and the first via V1 is configured to connect a subsequently formed anode connection electrode to the second electrode of the third transistor through the via.

[0368] In an exemplary embodiment, an orthographic projection of the first via hole V1 on the substrate does not overlap with orthographic projections of the fifth and thirteenth via holes on the substrate, and an area of ​​the first via hole V1 is greater than an area of ​​either the fifth and thirteenth via holes.

[0369] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the second via V2 exposes the surface of the first electrode of the fourth transistor, and the second via V2 is configured to connect the subsequently formed data signal line Data to the first electrode of the fourth transistor through the via.

[0370] In an exemplary embodiment, an orthographic projection of the second via hole V2 on the substrate at least partially overlaps with an orthographic projection of the sixth via hole V6 on the substrate.

[0371] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is within the range of the orthographic projection of the reference signal line on the substrate. The third via V3 exposes the surface of the reference signal line. The third via V3 is configured to connect a subsequently formed third connecting line to the reference signal line through the via. Exemplarily, the third via V3 exposes the first connecting block of the reference signal line.

[0372] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is within the range of the orthographic projection of the first power line on the substrate. The fourth via V4 exposes the surface of the first power line. The fourth via V4 is configured to connect a subsequently formed second connection line to the first power line through the via. Exemplarily, the fourth via V4 exposes the second connection block of the first power line.

[0373] In an exemplary embodiment, the area of ​​the seventeenth via hole may be equal to the area of ​​the eighteenth via hole, and the seventeenth via hole is located on a center line extending along the first direction D1 between two adjacent eighteenth via holes.

[0374] In an exemplary embodiment, the number of any one of the first to fourth via holes V1 to V4 may be one.

[0375] (7) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer pattern covering the first flat layer pattern, wherein a plurality of vias are provided on the fifth insulating layer, as shown in FIG21 and FIG22 , FIG21 is a schematic diagram of FIG7A after the fifth insulating layer pattern is formed, and FIG22 is a schematic diagram of FIG7B after the fifth insulating layer pattern is formed.

[0376] In an exemplary embodiment, as shown in FIG. 21 and FIG. 22 , the plurality of via holes in the fifth insulation layer pattern include at least fifth and sixth via holes V5 and V6 located in each sub-pixel, and seventh and eighth via holes V7 and V8 located between at least two columns of adjacent sub-pixels.

[0377] In an exemplary embodiment, as shown in FIG. 21 and FIG. 22 , the number of any one of the fifth via hole V5 and the sixth via hole V6 in each sub-pixel is one.

[0378] In an exemplary embodiment, as shown in Figures 21 and 22, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the second electrode of the third transistor on the substrate, the fifth via V5 exposes the surface of the second electrode of the third transistor, and the fifth via V5 is configured to connect the subsequently formed anode connection electrode to the second electrode of the third transistor through the via.

[0379] In an exemplary embodiment, as shown in FIG. 21 , the orthographic projection of the fifth via hole V5 on the substrate does not overlap with the orthographic projections of the fifth via hole and the twenty-first via hole on the substrate.

[0380] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of a portion of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first via on the substrate, and the orthographic projection of another portion of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first flat layer on the substrate, that is, the fifth via V5 exposes the second electrode of the third transistor and may also expose the first flat layer.

[0381] In an exemplary embodiment, as shown in FIG. 21 , the length of the fifth via hole V5 along the first direction D1 is smaller than that of the first via hole, and the length of the fifth via hole V5 along the second direction D2 is smaller than that of the first via hole.

[0382] In an exemplary embodiment, as shown in Figure 21, the boundaries of the via include: a first boundary, a second boundary, a third boundary and a fourth boundary, wherein the first boundary of the via is a boundary of the via close to the first signal line, the second boundary of the via is a boundary of the via away from the first signal line, the third boundary of the via is a boundary located on one side of the first center line, and the fourth boundary of the via is a boundary located on the other side of the first center line. The via includes: a first via and a fifth via, the first signal line is one of the light-emitting signal line, the first power line, the third scanning signal line and the initial signal line connected to the sub-pixel, the first center line is the center line of the first via extending along the second direction, the third boundary of the first via and the third boundary of the fifth via are located on the same side of the first center line, and the fourth boundary of the first via and the fourth boundary of the fifth via are located on the same side of the first center line. The distance between the orthographic projection of the first boundary of the first via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the fifth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the orthographic projection of the second boundary of the first via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the fifth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the third boundary of the first via and the first center line is greater than the distance between the orthographic projection of the third boundary of the fifth via on the substrate and the orthographic projection of the first center line on the substrate, and the distance between the fourth boundary of the first via and the first center line is greater than the distance between the orthographic projection of the fourth boundary of the fifth via on the substrate and the orthographic projection of the first center line on the substrate.

[0383] In an exemplary embodiment, as shown in FIG. 21 , within any sub-pixel, the distance between the orthographic projection of the first boundary of the first via hole on the substrate and the orthographic projection of the first boundary of the fifth via hole on the substrate is greater than the distance between the orthographic projection of the third boundary of the first via hole on the substrate and the orthographic projection of the third boundary of the fifth via hole on the substrate, and is less than the distance between the orthographic projection of the second boundary of the first via hole on the substrate and the orthographic projection of the second boundary of the fifth via hole on the substrate.

[0384] In an exemplary embodiment, as shown in FIG21 , the distance between the orthographic projection of the first boundary of the first via hole and the orthographic projection of the first boundary of the fifth via hole on the substrate is approximately 1 micron to 2 microns. Exemplarily, the distance between the orthographic projection of the first boundary of the first via hole and the orthographic projection of the first boundary of the fifth via hole on the substrate is approximately 1.5 microns.

[0385] In an exemplary embodiment, as shown in FIG. 22 , the orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the first via hole on the substrate.

[0386] In an exemplary embodiment, as shown in Figures 21 and 22, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the sixth via V6 exposes the surface of the first electrode of the fourth transistor, and the sixth via V6 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via.

[0387] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of a portion of the sixth via V6 on the substrate is located within the range of the orthographic projections of the sixth via and the second via on the substrate, and the orthographic projection of another portion of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first flat layer on the substrate, that is, the twentieth via exposes the first electrode of the fourth transistor and also exposes the first flat layer.

[0388] In an exemplary embodiment, as shown in FIG. 21 , the length of the sixth via hole V6 along the first direction D1 is smaller than that of the second via hole, and the length of the sixth via hole V6 along the second direction D2 is smaller than that of the second via hole.

[0389] In an exemplary embodiment, as shown in FIG21 , within any sub-pixel, the boundaries of the via hole include: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the first signal line, the second boundary of the via hole is a boundary of the via hole away from the first signal line, the third boundary of the via hole is a boundary located on one side of the second center line, and the fourth boundary of the via hole is a boundary located on the other side of the second center line. The via hole includes: a second via hole and a sixth via hole. The first signal line is one of the light emitting signal line, the first power line, the third scanning signal line, and the initial signal line connected to the sub-pixel. The second center line is the center line of the second via hole extending along the second direction. The third boundary of the second via hole and the third boundary of the sixth via hole are located on the same side of the second center line. The fourth boundary of the second via hole and the fourth side of the sixth via hole are located on the same side of the second center line. the orthographic projection of the first boundary of the second via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the sixth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the orthographic projection of the second boundary of the second via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the sixth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the third boundary of the second via and the second midline is greater than the distance between the orthographic projection of the third boundary of the sixth via on the substrate and the orthographic projection of the second midline on the substrate, and the distance between the fourth boundary of the second via and the second midline is greater than the distance between the orthographic projection of the fourth boundary of the sixth via on the substrate and the orthographic projection of the second midline on the substrate.

[0390] In an exemplary embodiment, as shown in FIG. 21 , within any sub-pixel, the distance between the orthographic projection of the first boundary of the second via hole on the substrate and the orthographic projection of the first boundary of the sixth via hole on the substrate is greater than the distance between the orthographic projection of the third boundary of the second via hole on the substrate and the orthographic projection of the third boundary of the sixth via hole on the substrate, and is less than the distance between the orthographic projection of the second boundary of the second via hole on the substrate and the orthographic projection of the second boundary of the sixth via hole on the substrate.

[0391] In an exemplary embodiment, as shown in FIG21 , the distance between the orthographic projection of the first boundary of the second via hole and the orthographic projection of the first boundary of the sixth via hole on the substrate is approximately 1 micron to 2 microns. For example, the distance between the orthographic projection of the first boundary of the second via hole and the orthographic projection of the first boundary of the sixth via hole on the substrate may be approximately 1.5 microns.

[0392] In an exemplary embodiment, as shown in FIG. 22 , the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the second via hole on the substrate.

[0393] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the reference signal line on the substrate, the seventh via V7 exposes the surface of the reference signal line, and the seventh via V7 is configured to connect a subsequently formed third signal line to the reference signal line through the via.

[0394] In an exemplary embodiment, as shown in FIG. 21 and FIG. 22 , the orthographic projection of the twentieth via hole V21 on the substrate does not overlap with the orthographic projection of the first signal line on the substrate.

[0395] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of a portion of the seventh via V7 on the substrate is located within the range of the orthographic projection of the third via on the substrate, and the orthographic projection of another portion of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first flat layer on the substrate, that is, the seventh via V7 exposes the reference signal line and also exposes the first flat layer.

[0396] In an exemplary embodiment, as shown in FIG. 21 , the length of the seventh via hole V7 along the first direction D1 is smaller than that of the third via hole, and the length of the seventh via hole V7 along the second direction D2 is smaller than that of the third via hole.

[0397] In an exemplary embodiment, as shown in FIG21 , the boundaries of the via include: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary of the via is a boundary of the via close to the second signal line, the second boundary of the via is a boundary of the via away from the second signal line, the third boundary of the via is a boundary located on one side of the third center line, and the fourth boundary of the via is a boundary located on the other side of the third center line. The via includes: a third via and a seventh via, the second signal line is one of a light-emitting signal line, a first power line, a first scan signal line, a second scan signal line, a third scan signal line, an initial signal line, and a light-emitting signal line connected to a sub-pixel connected to a reference signal line exposed by the third via, the third center line is a center line of the third via extending along the second direction, the third boundary of the third via and the third boundary of the seventh via are located on the same side of the third center line, and the third via is connected to the reference signal line exposed by the third via. The fourth boundary of the hole and the fourth boundary of the seventh via are located on the same side of the third center line; the distance between the orthographic projection of the first boundary of the third via on the substrate and the orthographic projection of the second signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the seventh via on the substrate and the orthographic projection of the second signal line on the substrate, the distance between the orthographic projection of the second boundary of the third via on the substrate and the orthographic projection of the second signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the seventh via on the substrate and the orthographic projection of the second signal line on the substrate, the distance between the third boundary of the third via and the third center line is greater than the distance between the orthographic projection of the third boundary of the seventh via on the substrate and the orthographic projection of the third center line on the substrate, and the distance between the fourth boundary of the third via and the third center line is greater than the distance between the orthographic projection of the fourth boundary of the seventh via on the substrate and the orthographic projection of the third center line on the substrate.

[0398] In an exemplary embodiment, as shown in FIG. 21 , the distance between the orthographic projection of the first boundary of the third via on the substrate and the orthographic projection of the first boundary of the seventh via on the substrate is greater than the distance between the orthographic projection of the third boundary of the third via on the substrate and the orthographic projection of the third boundary of the seventh via on the substrate, and is less than the distance between the orthographic projection of the second boundary of the third via on the substrate and the orthographic projection of the second boundary of the seventh via on the substrate.

[0399] In an exemplary embodiment, as shown in FIG21 , the distance between the orthographic projection of the first boundary of the third via hole and the orthographic projection of the first boundary of the seventh via hole on the substrate is approximately 1 micrometer to 2 micrometers. For example, the distance between the orthographic projection of the first boundary of the third via hole and the orthographic projection of the first boundary of the seventh via hole on the substrate may be approximately 1.5 micrometers.

[0400] In an exemplary embodiment, as shown in FIG. 22 , the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the third via hole on the substrate.

[0401] In an exemplary embodiment, as shown in Figures 21 and 22, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first power line on the substrate, the eighth via V8 exposes the surface of the first power line, and the eighth via V8 is configured to connect the subsequently formed second signal line to the first power line through the via.

[0402] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of a portion of the eighth via V8 on the substrate is within the range of the orthographic projection of the fourth via on the substrate, and the orthographic projection of another portion of the eighth via V8 on the substrate is within the range of the orthographic projection of the first planar layer on the substrate. The eighth via V8 exposes the first power line and may also expose the first planar layer.

[0403] In an exemplary embodiment, as shown in FIG. 21 , the length of the eighth via hole V8 along the first direction D1 is smaller than that of the fourth via hole, and the length of the eighth via hole V8 along the second direction D2 is smaller than that of the fourth via hole.

[0404] In an exemplary embodiment, as shown in FIG21 , the boundaries of the via include: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary of the via is a boundary of the via close to the third signal line, the second boundary of the via is a boundary of the via away from the third signal line, the third boundary of the via is a boundary located on one side of the fourth center line, and the fourth boundary of the via is a boundary located on the other side of the fourth center line. The via includes: a fourth via and an eighth via, the third signal line is any one of a third scanning signal line and an initial signal line connected to the sub-pixel connected to the first power line exposed by the fourth via, the fourth center line is a center line of the fourth via extending along the second direction, the third boundary of the fourth via and the third boundary of the eighth via are located on the same side of the fourth center line, and the fourth boundary of the fourth via and the fourth boundary of the eighth via are located on the same side of the fourth center line. on the same side of the fourth center line; the distance between the orthographic projection of the first boundary of the fourth via on the substrate and the orthographic projection of the third signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the eighth via on the substrate and the orthographic projection of the third signal line on the substrate, the distance between the orthographic projection of the second boundary of the fourth via on the substrate and the orthographic projection of the third signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the eighth via on the substrate and the orthographic projection of the third signal line on the substrate, the distance between the third boundary of the fourth via and the fourth center line is greater than the distance between the orthographic projection of the third boundary of the eighth via on the substrate and the orthographic projection of the fourth center line on the substrate, and the distance between the fourth boundary of the fourth via and the fourth center line is greater than the distance between the orthographic projection of the fourth boundary of the eighth via on the substrate and the orthographic projection of the fourth center line on the substrate.

[0405] In an exemplary embodiment, as shown in FIG. 21 , the distance between the orthographic projection of the first boundary of the fourth via on the substrate and the orthographic projection of the first boundary of the eighth via on the substrate is greater than the distance between the orthographic projection of the third boundary of the fourth via on the substrate and the orthographic projection of the third boundary of the eighth via on the substrate, and is less than the distance between the orthographic projection of the second boundary of the fourth via on the substrate and the orthographic projection of the second boundary of the eighth via on the substrate.

[0406] In an exemplary embodiment, as shown in FIG21 , the distance between the orthographic projection of the first boundary of the fourth via hole and the orthographic projection of the first boundary of the eighth via hole on the substrate is approximately 1 micron to 2 microns. Exemplarily, the distance between the orthographic projection of the first boundary of the fourth via hole and the orthographic projection of the first boundary of the eighth via hole on the substrate is approximately 1.5 microns.

[0407] In an exemplary embodiment, as shown in FIG. 22 , the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the fourth via hole on the substrate.

[0408] In an exemplary embodiment, as shown in FIG22 , the fifth insulating layer pattern in the display substrate provided in FIG8 may further include: first to third ventilation holes H1 to H3 located in at least one sub-pixel and fourth and fifth ventilation holes H4 and H5 located between at least two columns of adjacent sub-pixels.

[0409] In an exemplary embodiment, as shown in FIG22 , the orthographic projection of any one of the first to fifth ventilation holes H1 to H5 on the substrate partially overlaps with the orthographic projection of the first flat layer on the substrate, that is, any one of the first to fifth ventilation holes H1 to H5 exposes the first flat layer.

[0410] In an exemplary embodiment, as shown in FIG22 , the distance between the orthographic projection of the first vent hole H1 on the substrate and the orthographic projection of the fifth via hole on the substrate is smaller than the distance between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the fifth via hole on the substrate. That is, the first vent hole H1 is disposed on the periphery of the casing hole including the fifth via hole and the first via hole.

[0411] In an exemplary embodiment, as shown in Figure 22 , the cross-section of the first vent hole H1 may be in the shape of a broken line. The orthographic projection of the first vent hole H1 on the substrate at least surrounds at least one side of the orthographic projection of the first via hole on the substrate.

[0412] In an exemplary embodiment, as shown in Figure 22, the orthographic projection of the first air hole H1 on the substrate does not overlap with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor on the substrate, as well as the reference signal line, first scan signal line, second scan signal line, third scan signal line, initial signal line, first power line, light-emitting signal line and initial connection line.

[0413] In an exemplary embodiment, as shown in FIG22 , the length of the first air hole H1 along the first direction D1 may be greater than the length of the second electrode of the third transistor close to the boundary of the first scan signal line, and the length of the first air hole H1 along the second direction D2 may be greater than the length of the sixth via hole V6 along the second direction D2.

[0414] In an exemplary embodiment, as shown in FIG22 , the second ventilation holes H2 and the sixth via holes V6 are arranged along the second direction D2. The distance between the orthographic projection of the sixth via hole V6 on the substrate and the orthographic projection of the first scan signal line on the substrate is greater than the distance between the second ventilation holes H2 and the sixth via hole V6. That is, the second ventilation holes H2 are arranged on the periphery of the sleeve hole including the sixth via hole and the second via hole.

[0415] 22 , the length of the second ventilation hole H2 along the second direction D2 is greater than the length of the sixth via hole V6 along the second direction D2 , and the length of the second ventilation hole H2 along the first direction D1 is less than the length of the sixth via hole V6 along the first direction D1 .

[0416] In an exemplary embodiment, as shown in Figure 22, the orthographic projection of the second air hole H2 on the substrate does not overlap with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor on the substrate, as well as the reference signal line, first scan signal line, second scan signal line, third scan signal line, initial signal line, first power line, light-emitting signal line and initial connection line.

[0417] In an exemplary embodiment, as shown in FIG. 22 , the orthographic projection of the third vent hole H3 on the substrate is located between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the third plate of the capacitor on the substrate.

[0418] In an exemplary embodiment, as shown in Figure 22, the orthographic projection of the third air hole H3 on the substrate does not overlap with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor on the substrate, as well as the reference signal line, first scan signal line, second scan signal line, third scan signal line, initial signal line, first power line, light-emitting signal line and initial connection line.

[0419] In an exemplary embodiment, as shown in FIG. 22 , in any sub-pixel, the number of any one of the first to third ventilation holes H1 to H3 may be one.

[0420] In an exemplary embodiment, the display substrate includes a plurality of fourth ventilation holes H4 and a plurality of fifth ventilation holes H5.

[0421] In an exemplary embodiment, as shown in FIG22 , the fourth ventilation hole H4 and the seventh via hole V7 are arranged along the first direction D1. The distance between the orthographic projection of the fourth ventilation hole on the substrate and the orthographic projection of the gate electrode of the first transistor of the adjacent sub-pixel on the substrate is smaller than the distance between the orthographic projection of the seventh via hole on the substrate and the orthographic projection of the gate electrode of the first transistor of the adjacent sub-pixel on the substrate. That is, the fourth ventilation hole H4 is disposed on the periphery of the casing hole including the seventh via hole and the third via hole.

[0422] In an exemplary embodiment, as shown in Figure 22, the orthographic projection of the fourth air hole H4 on the substrate at least partially overlaps with the orthographic projections of the initial connection line and the reference signal line on the substrate, and there is no overlapping area with the orthographic projections of the active pattern, gate electrode, first pole and second pole of any transistor and the first scanning signal line, second scanning signal line, third scanning signal line, initial signal line, first power line and light-emitting signal line on the substrate.

[0423] In an exemplary embodiment, as shown in FIG. 22 , the length of the fourth ventilation hole H4 along the second direction D2 is greater than the length of the third via hole along the second direction D2 , and the length of the fourth ventilation hole H4 along the first direction D1 is less than the length of the third via hole along the first direction D1 .

[0424] In an exemplary embodiment, as shown in FIG22 , the fifth vent H5 and the eighth via V8 are arranged along the first direction D1. The distance between the orthographic projection of the fifth vent H5 on the substrate and the orthographic projection of the fourth via on the substrate is smaller than the distance between the orthographic projection of the fourth via on the substrate and the orthographic projection of the gate electrode of the first transistor on the substrate. That is, the fifth vent H5 is disposed on the periphery of the casing including the eighth via and the fourth via.

[0425] In an exemplary embodiment, as shown in FIG. 22 , the length of the fifth ventilation hole H5 along the second direction D2 is greater than the length of the fourth via hole along the second direction D2 , and the length of the fifth ventilation hole H5 along the first direction D1 is less than the length of the fourth via hole along the first direction D1 .

[0426] In an exemplary embodiment, as shown in FIG22 , the orthographic projections of some of the fifth vent holes H5 on the substrate do not overlap with the orthographic projections of any transistor's active pattern, gate electrode, first electrode, second electrode, reference signal line, first scan signal line, second scan signal line, third scan signal line, initial signal line, first power line, light-emitting signal line, and initial connection line on the substrate. The orthographic projections of another portion of the fifth vent holes H5 on the substrate at least partially overlap with the orthographic projections of the first power line on the substrate, and do not overlap with the orthographic projections of any transistor's active pattern, gate electrode, first electrode, second electrode, reference signal line, first scan signal line, second scan signal line, third scan signal line, initial signal line, light-emitting signal line, and initial connection line on the substrate.

[0427] In an exemplary embodiment, the cross-section of any of the second to fifth ventilation holes may be polygonal, for example, rectangular, square, pentagonal, or hexagonal. The present disclosure is described using a rectangle as an example.

[0428] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the fifth insulating layer, as shown in Figures 23, 24, and 25. Figure 23 is a schematic diagram of the fourth conductive layer pattern in Figures 7A and 7B, Figure 24 is a schematic diagram of Figure 7A after the fourth conductive layer pattern is formed, and Figure 25 is a schematic diagram of Figure 7B after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0429] In exemplary embodiments, as shown in FIG. 23 to FIG. 25 , the fourth conductive layer pattern may include at least an anode connection electrode AL located at each sub-pixel, and a data signal line Data, a power connection line L2 , and a reference connection line L3 .

[0430] In an exemplary embodiment, the data signal line Data may be in the shape of a line with a main portion extending along the second direction D2. The orthographic projection of the data signal line Data connected to the current column of sub-pixels may be located on the side of the substrate where the orthographic projection of the third plate of the capacitor is closer to the sub-pixels in the previous column. Each data signal line Data is provided with a third connection block Data-1. The first end of the third connection block Data-1 is connected to the data signal line Data. The third connection block Data-1 is located on the side of the data signal line Data closer to the third plate C3 of the capacitor and extends along the first direction D1. The orthographic projection of the third connection block Data-1 on the substrate at least partially overlaps with the orthographic projection of the first electrode of the fourth transistor on the substrate. The data signal line Data is electrically connected to the first electrode of the fourth transistor via a sixth via and a second via, respectively.

[0431] In an exemplary embodiment, the power connection line L2 may be shaped like a line with a main portion extending along the second direction D2, and an orthographic projection of the power connection line L2 on the substrate at least partially overlaps an orthographic projection of the second connection block on the first power line on the substrate. The power connection line L2 is electrically connected to the first power line through the eighth via and the fourth via, respectively.

[0432] In an exemplary embodiment, the plurality of power connection lines L2 and the plurality of first power lines may form a mesh structure, which may improve display uniformity of the display substrate.

[0433] In an exemplary embodiment, the reference connection line L3 may be in the shape of a line having a main portion extending along the second direction D2, and an orthographic projection of the reference connection line L3 on the substrate at least partially overlaps an orthographic projection of the first connection block on the reference signal line on the substrate. The reference connection line L3 is electrically connected to the reference signal line through the seventh via and the third via, respectively.

[0434] In an exemplary embodiment, an orthographic projection of at least a portion of the reference connection line L3 on the substrate is between orthographic projections of two initial connection lines located between two adjacent sub-pixels on the substrate.

[0435] In an exemplary embodiment, the plurality of reference connection lines L3 and the plurality of reference signal lines may form a mesh structure, which may improve display uniformity of the display substrate.

[0436] In an exemplary embodiment, the anode connection electrode AL may be block-shaped, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second electrode of the third transistor on the substrate. The anode connection electrode AL is sequentially connected to the second electrode of the third transistor through the fifth via and the first via.

[0437] In an exemplary embodiment, as shown in FIG25 , the orthographic projections of the first to fifth ventilation holes on the substrate do not overlap with the orthographic projections of the power connection line, the reference connection line, the data signal line, and the anode connection electrode on the substrate.

[0438] In an exemplary embodiment, the power connection line L2, the reference connection line L3 and the data signal line Data can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0439] (9) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer pattern covering the fourth conductive layer pattern, and providing a plurality of vias on the sixth insulating layer, as shown in Figures 26 and 27. Figure 26 is a schematic diagram of Figure 7A after the sixth insulating layer pattern is formed, and Figure 27 is a schematic diagram of Figure 7B after the sixth insulating layer pattern is formed.

[0440] In an exemplary embodiment, as shown in FIG. 26 and FIG. 27 , the plurality of via holes of the sixth insulation layer pattern includes at least a twenty-third via hole V23 located in each sub-pixel.

[0441] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate, the twenty-third via hole V23 exposes the surface of the anode connecting electrode, and the twenty-third via hole V23 is configured to connect the anode of the subsequently formed light-emitting device to the anode connecting electrode through the via hole.

[0442] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of the twenty-third via hole on the substrate does not overlap with orthographic projections of the fifteenth via hole and the nineteenth via hole on the substrate.

[0443] (10) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the sixth insulating layer pattern, wherein a plurality of vias are provided on the second planar layer, as shown in FIG28 and FIG29 . FIG28 is a schematic diagram of FIG7A after the second planar layer pattern is formed, and FIG29 is a schematic diagram of FIG7B after the second planar layer pattern is formed.

[0444] In an exemplary embodiment, as shown in FIG. 28 and FIG. 29 , the plurality of via holes of the second planarization layer pattern may include at least a twenty-fourth via hole V24 located at each sub-pixel.

[0445] In an exemplary embodiment, the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate, and the twenty-fourth via hole V24 exposes the surface of the anode connecting electrode. The twenty-fourth via hole V24 exposure is configured to connect the anode of the subsequently formed light-emitting device to the anode connecting electrode through the via hole.

[0446] In an exemplary embodiment, for any sub-pixel, the orthographic projection of the 23rd via hole on the substrate is within the orthographic projection of the 24th via hole V24 on the substrate, and partially overlaps with the orthographic projection of a portion of the sixth insulating layer on the substrate.

[0447] At this point, the drive structure layer is completed on the substrate. In a plane parallel to the display substrate, the drive structure layer can include multiple pixel drive circuits, which are connected to the first scan signal line, the second scan signal line, the third scan signal line, the light emitting signal line, the initial signal line, the reference signal line, the data signal line, and the first power supply line. In a plane perpendicular to the display substrate, the drive structure layer can be disposed on the substrate.

[0448] The driving structure layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, and a second planar layer, which are sequentially arranged on a substrate. The semiconductor layer may include at least active patterns of first to fifth transistors, the first conductive layer may include at least gate electrodes of the first to fifth transistors, a first plate of a capacitor, and an initial connection line, the second conductive layer may include at least a second plate of a capacitor, the third conductive layer may include at least a first scanning signal line, a second scanning signal line, a third scanning signal line, a reference signal line, a light-emitting signal line, an initial signal line, and a first power line, as well as first and second electrodes of a plurality of transistors, the initial signal lines being connected via initial connection lines, the fourth conductive layer may include at least a data signal line, a power connection line, a reference connection line, and an anode connection electrode, the power connection line being connected to the first power line via a via, and the reference connection line being connected to the reference signal line via a via.

[0449] In exemplary embodiments, the semiconductor layer may be made of various materials, such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, and polythiophene. This means that the present disclosure is applicable to transistors manufactured using oxide, silicon, and organic technologies. For example, the semiconductor layer may be made of polycrystalline silicon.

[0450] In an exemplary embodiment, the thickness of the semiconductor layer may be approximately 430 angstroms to 520 angstroms. For example, the thickness of the semiconductor layer may be approximately 470 angstroms.

[0451] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, or Ti / Al / Ti, etc.

[0452] In an exemplary embodiment, the resistivity of any of the third and fourth conductive layers is less than the resistivity of any of the first and second conductive layers. For example, the first and second conductive layers may be made of molybdenum, and the third and fourth conductive layers may be made of Ti / Al / Ti.

[0453] In an exemplary embodiment, the thickness of the first conductive layer may be approximately 2500 angstroms to 3000 angstroms. For example, the thickness of the first conductive layer may be approximately 2800 angstroms.

[0454] In an exemplary embodiment, the thickness of the second conductive layer may be approximately 2500 angstroms to 3000 angstroms. For example, the thickness of the second conductive layer may be approximately 2800 angstroms.

[0455] In an exemplary embodiment, the third conductive layer and the fourth conductive layer each include: a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer sequentially stacked on a substrate. The first sub-conductive layer and the third sub-conductive layer may be made of Ti, and the second sub-conductive layer may be made of Al. Exemplarily, the thickness of the first sub-conductive layer may be approximately 400 angstroms to 600 angstroms, and exemplary, approximately 500 angstroms. The thickness of the second sub-conductive layer may be approximately 6000 angstroms to 7000 angstroms, and exemplary, approximately 6500 angstroms. The thickness of the third sub-conductive layer may be approximately 200 angstroms to 400 angstroms, and exemplary, approximately 300 angstroms.

[0456] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer may be referred to as a buffer layer, the second insulating layer and the third insulating layer may be referred to as a gate insulating (GI) layer, the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer may be referred to as a passivation (PVX) layer. For example, the first insulating layer may be made of

[0457] In an exemplary embodiment, when the first insulating layer is made of silicon oxide (SiOx), the thickness of the first insulating layer may be approximately 2500 angstroms to 3500 angstroms, and exemplary, the thickness of the first insulating layer may be approximately 3000 angstroms. When the first insulating layer is made of silicon nitride (SiNx), the thickness of the first insulating layer may be approximately 500 angstroms to 1500 angstroms, and exemplary, the thickness of the first insulating layer may be approximately 1000 angstroms.

[0458] In an exemplary embodiment, when the second insulating layer is made of silicon oxide (SiOx), the thickness of the second insulating layer may be approximately 700 angstroms to 900 angstroms, and exemplary, the thickness of the second insulating layer may be approximately 800 angstroms. When the second insulating layer is made of silicon nitride (SiNx), the thickness of the second insulating layer may be approximately 350 angstroms to 450 angstroms, and exemplary, the thickness of the second insulating layer may be approximately 400 angstroms.

[0459] In an exemplary embodiment, the third insulating layer may be made of silicon nitride (SiNx), and the thickness of the third insulating layer may be approximately 2500 angstroms to 3000 angstroms. For example, the thickness of the third insulating layer may be approximately 2800 angstroms.

[0460] In an exemplary embodiment, when the fourth insulating layer is made of silicon oxide, the thickness of the fourth insulating layer may be approximately 1500 angstroms to 2500 angstroms, and exemplarily, the thickness of the fourth insulating layer may be approximately 2000 angstroms. When the fourth insulating layer is made of silicon nitride (SiNx), the thickness of the fourth insulating layer may be approximately 2500 angstroms to 3500 angstroms, and exemplarily, the thickness of the fourth insulating layer may be approximately 3000 angstroms.

[0461] In an exemplary embodiment, the fifth insulating layer may be made of silicon nitride (SiNx) and have a thickness of approximately 1200 angstroms to 1600 angstroms. For example, the fifth insulating layer may have a thickness of approximately 1400 angstroms.

[0462] In an exemplary embodiment, the sixth insulating layer may be made of silicon nitride (SiNx) and may have a thickness of approximately 1200 angstroms to 1600 angstroms. For example, the sixth insulating layer may have a thickness of approximately 1400 angstroms.

[0463] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of an organic material such as a resin, for example, polyimide.

[0464] In an exemplary embodiment, the thickness of the first planar layer may be approximately 18,000 angstroms to 22,000 angstroms. For example, the thickness of the first planar layer may be approximately 20,000 angstroms.

[0465] In an exemplary embodiment, the thickness of the second planar layer may be approximately 20,000 angstroms to 40,000 angstroms. For example, the thickness of the second planar layer may be approximately 20,000 angstroms.

[0466] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0467] (11) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the second flat layer, as shown in Figures 30 to 32, wherein Figure 30 is a schematic diagram of the fifth conductive layer pattern in Figures 7A and 7B, Figure 31 is a schematic diagram of Figure 7A after the fifth conductive layer pattern is formed, and Figure 32 is a schematic diagram of Figure 7B after the fifth conductive layer pattern is formed.

[0468] In an exemplary embodiment, the fifth conductive layer pattern includes at least the first electrode 20 located in each sub-pixel.

[0469] In an exemplary embodiment, the shape of the first electrode 20 may be rectangular, or may be other shapes, which is not limited in the present disclosure.

[0470] In an exemplary embodiment, for any sub-pixel, the anode 20 of the light emitting device is connected to the anode connection electrode through the twenty-fourth via hole and the twenty-third via hole in sequence.

[0471] In an exemplary embodiment, at least a portion of any one of the structures including the anode connection electrode, the first plate of the capacitor, the second plate of the capacitor, the third plate of the capacitor, the gate electrode of the fifth transistor, and the gate electrode of the first transistor is within the range of the orthographic projection of the anode on the substrate.

[0472] In an exemplary embodiment, the plurality of anodes may include a first anode of a red light-emitting device, a second anode of a blue light-emitting device, and a third anode of a green light-emitting device. The first anode may be located at a red sub-pixel that emits red light, the second anode may be located at a blue sub-pixel that emits blue light, and the third anode may be located at a green sub-pixel that emits green light.

[0473] (12) Forming a first pixel definition layer pattern. In an exemplary embodiment, forming the first pixel definition layer pattern may include: coating a first pixel definition film on the substrate on which the aforementioned pattern is formed, and patterning the first pixel definition film using a patterning process to form a first pixel definition layer pattern, wherein the first pixel definition layer pattern includes a plurality of vias, as shown in FIG33 and FIG34 , FIG33 is a schematic diagram of FIG7A after the first pixel definition layer pattern is formed, and FIG34 is a schematic diagram of FIG7B after the first pixel definition layer pattern is formed.

[0474] In an exemplary embodiment, as shown in FIG. 33 and FIG. 34 , the first pixel definition layer pattern may include a twenty-fifth via hole V25 located at each sub-pixel.

[0475] In an exemplary embodiment, the orthographic projections of the twenty-fifth via hole V25 on the substrate are respectively within the range of the orthographic projections of the anode and a portion of the second flat layer on the substrate, the twenty-fifth via hole V25 exposes the surface of the anode, and the twenty-fifth via hole V25 is configured to connect the subsequently formed organic light-emitting layer to the anode through the via hole.

[0476] In an exemplary embodiment, a distance between an orthographic projection of a boundary of the twenty-fifth via V25 close to the reference signal line on the substrate and the orthographic projection of the reference signal line on the substrate is smaller than a distance between an orthographic projection of the anode on the substrate and the orthographic projection of the reference signal line on the substrate.

[0477] In an exemplary embodiment, the length of the twenty-fifth via hole V25 in the first direction D1 may be greater than or equal to the length of the anode in the first direction D1. The length of the twenty-fifth via hole V25 in the second direction D2 may be less than or equal to the length of the anode in the second direction D2.

[0478] (13) Forming a second pixel definition layer pattern. In an exemplary embodiment, forming the second pixel definition layer pattern may include: coating a second pixel definition film on the substrate on which the aforementioned pattern is formed, and patterning the second pixel definition film using a patterning process to form a second pixel definition layer pattern, wherein the second pixel definition layer pattern includes a plurality of vias, as shown in FIG35 and FIG36 , FIG35 is a schematic diagram of FIG7 after the second pixel definition layer pattern is formed, and FIG36 is a schematic diagram of FIG8 after the second pixel definition layer pattern is formed.

[0479] In an exemplary embodiment, as shown in FIG. 35 and FIG. 36 , the second pixel definition layer pattern may include a twenty-sixth via hole V26 located at each sub-pixel.

[0480] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the substrate is respectively located within the range of the orthographic projection of the anode and a portion of the twenty-fifth via on the substrate, the twenty-sixth via V26 exposes the surface of the anode, and the twenty-sixth via V26 is configured to connect the subsequently formed organic light-emitting layer to the anode through the via.

[0481] In an exemplary embodiment, the distance between the orthographic projection of the boundary of the twenty-sixth via V26 close to the reference signal line on the substrate and the orthographic projection of the reference signal line on the substrate may be equal to the distance between the orthographic projection of the boundary of the twenty-fifth via close to the reference signal line on the substrate and the orthographic projection of the reference signal line on the substrate.

[0482] In an exemplary embodiment, the length of the twenty-sixth via hole V26 in the first direction D1 may be less than the length of the anode in the first direction D1. The length of the twenty-sixth via hole V26 in the second direction D2 may be greater than the length of the anode in the second direction D2.

[0483] In an exemplary embodiment, the fifth conductive layer may have a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0484] In an exemplary embodiment, the fifth conductive layer may include a first anode layer, a second anode layer, and a third anode layer sequentially stacked on the substrate. The first anode layer and the third anode layer may be made of ITO, and the second anode layer may be made of Ag. Exemplarily, the thickness of the first anode layer and the third anode layer may be approximately 50 angstroms to 100 angstroms. Exemplarily, the thickness of the first anode layer may be approximately 70 angstroms, the thickness of the second anode layer may be approximately 800 angstroms to 1200 angstroms, and the thickness of the second anode layer may be approximately 1000 angstroms.

[0485] In an exemplary embodiment, materials of the first pixel definition layer and the second pixel definition layer may include polyimide, acryl, polyethylene terephthalate, or the like.

[0486] In an exemplary embodiment, the transmittance of the first pixel definition layer is less than the transmittance of the second pixel definition layer.

[0487] In an exemplary embodiment, the thickness of the first pixel definition layer may be approximately 16,000 angstroms to 20,000 angstroms. For example, the thickness of the first pixel definition layer may be approximately 18,000 angstroms.

[0488] In an exemplary embodiment, the thickness of the second pixel definition layer may be approximately 13,000 angstroms to 17,000 angstroms. Exemplarily, the thickness of the second pixel definition layer may be approximately 15,000 angstroms.

[0489] In an exemplary embodiment, the subsequent preparation process may include: first using an evaporation or inkjet printing process to form a light-emitting material layer, wherein the light-emitting material layer may at least include: an organic light-emitting layer, the organic light-emitting layer located in the same sub-pixel may be connected to the anode through the twenty-sixth via and the twenty-fifth via in sequence, and then forming a sixth conductive layer pattern on the organic light-emitting layer, wherein the sixth conductive layer pattern may include at least a second electrode, and then forming an encapsulation structure layer, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0490] As can be seen from the structure and manufacturing process of the display substrate described above, the display substrate provided by the present disclosure, by providing vias in the fifth insulating layer that expose the first planar layer, forms a degassing channel. This allows for the release of residual moisture in the first planar layer during subsequent manufacturing processes, thereby improving the reliability of the display substrate and ensuring the display quality of the display product. The manufacturing process of the display substrate of the exemplary embodiment of the present disclosure is highly compatible with existing manufacturing processes, is simple to implement, and offers high production efficiency, low production costs, and a high yield rate.

[0491] The structure and fabrication process described above are merely exemplary. In exemplary embodiments, the corresponding structure may be modified and patterning processes may be added or removed as needed. For example, some overlapping vias may be located in sub-pixels away from the first centerline to increase the spacing between adjacent overlapping vias, reduce mutual interference, and ensure crosstalk-free display. This disclosure is not limited to these requirements.

[0492] In an exemplary embodiment, the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.

[0493] An embodiment of the present disclosure further provides a display device, which includes a display substrate.

[0494] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0495] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

[0496] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0497] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0498] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, provided with a plurality of sub-pixels arranged in an array, at least one sub-pixel comprising: The pixel driving circuit, the display substrate comprises: a substrate and a driving structure layer arranged on the substrate, the pixel driving circuit is arranged on the driving structure layer; The driving structure layer at least comprises: a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fifth insulating layer and a fourth conductive layer sequentially stacked on the substrate; The fifth insulating layer is provided with a plurality of via holes, and at least one via hole on the fifth insulating layer exposes the first planar layer; The thickness of the first planarizing layer is greater than the thickness of the fifth insulating layer.

2. The display substrate according to claim 1, wherein: The pixel driving circuit comprises: a first transistor to a fifth transistor, the driving structure layer further comprises: a first scanning signal line, a second scanning signal line, a third scanning signal line, an initial signal line, a data signal line, a light emitting signal line, a reference signal line and a first power line, the first transistor is electrically connected to the third scanning signal line and the initial signal line respectively, the second transistor is electrically connected to the second scanning signal line and the reference signal line respectively, the fourth transistor is electrically connected to the first scanning signal line and the data signal line respectively, and the fifth transistor is electrically connected to the light emitting signal line and the first power line respectively; Any one of the first scan signal line, the second scan signal line, the third scan signal line, the initial signal line, the light emitting signal line, the reference signal line and the first power line at least partially extends along a first direction, and the data signal line at least partially extends along a second direction, and the first direction intersects the second direction; The reference signal line, the second scanning signal line, the first scanning signal line, the light emitting signal line, the first power supply line, the third scanning signal line and the initial signal line connected to any sub-pixel are arranged in sequence along the second direction; The first flat layer is provided with first to fourth via holes, wherein the orthographic projection of the first via hole on the substrate is located within the range of the orthographic projection of the second electrode of the third transistor on the substrate, and the surface of the second electrode of the third transistor is exposed, the orthographic projection of the second via hole on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, and the surface of the first electrode of the fourth transistor is exposed, the orthographic projection of the third via hole on the substrate is located within the range of the orthographic projection of the reference signal line on the substrate, and the surface of the reference signal line is exposed, and the orthographic projection of the fourth via hole on the substrate is located within the range of the orthographic projection of the first power line on the substrate, and the surface of the first power line is exposed; The third via hole is located on a midline extending along the second direction between two adjacent fourth via holes.

3. The display substrate according to claim 2, wherein: The fifth insulating layer is provided with fifth to eighth via holes, wherein: The orthographic projection of the fifth via hole on the substrate is located within the range of the orthographic projection of the first via hole and the first flat layer on the substrate, the orthographic projection of the sixth via hole on the substrate is located within the range of the orthographic projection of the second via hole and the first flat layer on the substrate, the orthographic projection of the seventh via hole on the substrate is located within the range of the orthographic projection of the third via hole and the first flat layer on the substrate, and the orthographic projection of the eighth via hole on the substrate is located within the range of the orthographic projection of the fourth via hole and the first flat layer on the substrate.

4. The display substrate according to claim 3, wherein: The length of the fifth via hole along the first direction is smaller than the length of the first via hole along the first direction, and the length of the fifth via hole along the second direction is smaller than the length of the first via hole along the second direction; The length of the sixth via hole along the first direction is less than the length of the second via hole along the first direction, and the length of the sixth via hole along the second direction is less than the length of the second via hole along the second direction; The length of the seventh via hole along the first direction is less than the length of the third via hole along the first direction, and the length of the seventh via hole along the second direction is less than the length of the third via hole along the second direction; The length of the eighth via hole along the first direction is shorter than the length of the fourth via hole along the first direction, and the length of the eighth via hole along the second direction is shorter than the length along the second direction.

5. The display substrate according to claim 4, wherein: In any sub-pixel, the boundaries of the via hole include: a first boundary, a second boundary, a third boundary and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the first signal line, the second boundary of the via hole is a boundary of the via hole far from the first signal line, the third boundary of the via hole is a boundary located on one side of the first center line, and the fourth boundary of the via hole is a boundary located on the other side of the first center line, the via hole includes: a first via hole and a fifth via hole, the first signal line is one of the light emitting signal line, the first power line, the third scanning signal line and the initial signal line connected to the sub-pixel, the first center line is a center line of the first via hole extending along the second direction, the third boundary of the first via hole and the third boundary of the fifth via hole are located on the same side of the first center line, and the fourth boundary of the first via hole and the fourth boundary of the fifth via hole are located on the same side of the first center line; The distance between the orthographic projection of the first boundary of the first via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the fifth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the orthographic projection of the second boundary of the first via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the fifth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the third boundary of the first via and the first center line is greater than the distance between the orthographic projection of the third boundary of the fifth via on the substrate and the orthographic projection of the first center line on the substrate, and the distance between the fourth boundary of the first via and the first center line is greater than the distance between the orthographic projection of the fourth boundary of the fifth via on the substrate and the orthographic projection of the first center line on the substrate.

6. The display substrate according to claim 5, wherein: In any sub-pixel, a distance between an orthographic projection of a first boundary of the first via hole on the substrate and an orthographic projection of a first boundary of the fifth via hole on the substrate is greater than a distance between an orthographic projection of a third boundary of the first via hole on the substrate and an orthographic projection of a third boundary of the fifth via hole on the substrate, and is less than a distance between an orthographic projection of a second boundary of the first via hole on the substrate and an orthographic projection of a second boundary of the fifth via hole on the substrate; A distance between an orthographic projection of a first boundary of the first via hole on the substrate and an orthographic projection of a first boundary of the fifth via hole on the substrate is approximately 1 micrometer to 2 micrometers.

7. The display substrate according to claim 4, wherein: In any sub-pixel, the boundaries of the via hole include: a first boundary, a second boundary, a third boundary and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the first signal line, the second boundary of the via hole is a boundary of the via hole far from the first signal line, the third boundary of the via hole is a boundary located on one side of the second center line, and the fourth boundary of the via hole is a boundary located on the other side of the second center line, and the via hole includes: a second via hole and a sixth via hole, the first signal line is one of the light emitting signal line, the first power line, the third scanning signal line and the initial signal line connected to the sub-pixel, the second center line is a center line of the second via hole extending along the second direction, the third boundary of the second via hole and the third boundary of the sixth via hole are located on the same side of the second center line, and the fourth boundary of the second via hole and the fourth boundary of the sixth via hole are located on the same side of the second center line; The distance between the orthographic projection of the first boundary of the second via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the sixth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the orthographic projection of the second boundary of the second via on the substrate and the orthographic projection of the first signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the sixth via on the substrate and the orthographic projection of the first signal line on the substrate, the distance between the third boundary of the second via and the second center line is greater than the distance between the orthographic projection of the third boundary of the sixth via on the substrate and the orthographic projection of the second center line on the substrate, and the distance between the fourth boundary of the second via and the second center line is greater than the distance between the orthographic projection of the fourth boundary of the sixth via on the substrate and the orthographic projection of the second center line on the substrate.

8. The display substrate according to claim 7, wherein: In any sub-pixel, a distance between an orthographic projection of a first boundary of the second via hole on the substrate and an orthographic projection of a first boundary of the sixth via hole on the substrate is greater than a distance between an orthographic projection of a third boundary of the second via hole on the substrate and an orthographic projection of a third boundary of the sixth via hole on the substrate, and is less than a distance between an orthographic projection of a second boundary of the second via hole on the substrate and an orthographic projection of a second boundary of the sixth via hole on the substrate; A distance between an orthographic projection of a first boundary of the second via hole on the substrate and an orthographic projection of a first boundary of the sixth via hole on the substrate is approximately 1 micrometer to 2 micrometers.

9. The display substrate according to claim 4, wherein: The boundaries of the via hole include: a first boundary, a second boundary, a third boundary and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the second signal line, the second boundary of the via hole is a boundary of the via hole far from the second signal line, the third boundary of the via hole is a boundary located on one side of a third center line, and the fourth boundary of the via hole is a boundary located on the other side of the third center line, the via hole includes: a third via hole and a seventh via hole, the second signal line is a light emitting signal line connected to a sub-pixel connected to a reference signal line exposed by the third via hole, a first power line, a first scanning signal line, a second scanning signal line, a third scanning signal line, an initial signal line and a light emitting signal line, the third center line is a center line of the third via hole extending along the second direction, the third boundary of the third via hole and the third boundary of the seventh via hole are located on the same side of the third center line, and the fourth boundary of the third via hole and the fourth boundary of the seventh via hole are located on the same side of the third center line; The distance between the orthographic projection of the first boundary of the third via on the substrate and the orthographic projection of the second signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the seventh via on the substrate and the orthographic projection of the second signal line on the substrate, the distance between the orthographic projection of the second boundary of the third via on the substrate and the orthographic projection of the second signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the seventh via on the substrate and the orthographic projection of the second signal line on the substrate, the distance between the third boundary of the third via and the third center line is greater than the distance between the orthographic projection of the third boundary of the seventh via on the substrate and the orthographic projection of the third center line on the substrate, and the distance between the fourth boundary of the third via and the third center line is greater than the distance between the orthographic projection of the fourth boundary of the seventh via on the substrate and the orthographic projection of the third center line on the substrate.

10. The display substrate according to claim 9, wherein: The distance between the orthographic projection of the first boundary of the third via hole on the substrate and the orthographic projection of the first boundary of the seventh via hole on the substrate is greater than the distance between the orthographic projection of the third boundary of the third via hole on the substrate and the orthographic projection of the third boundary of the seventh via hole on the substrate, and is less than the distance between the orthographic projection of the second boundary of the third via hole on the substrate and the orthographic projection of the second boundary of the seventh via hole on the substrate; A distance between an orthographic projection of a first boundary of the third via hole on the substrate and an orthographic projection of a first boundary of the seventh via hole on the substrate is approximately 1 micrometer to 2 micrometers.

11. The display substrate according to claim 4, wherein: The boundaries of the via hole include: a first boundary, a second boundary, a third boundary and a fourth boundary, wherein the first boundary of the via hole is a boundary of the via hole close to the third signal line, the second boundary of the via hole is a boundary of the via hole far from the third signal line, the third boundary of the via hole is a boundary located on one side of a fourth center line, and the fourth boundary of the via hole is a boundary located on the other side of the fourth center line, the via hole includes: a fourth via hole and an eighth via hole, the third signal line is any one of a third scanning signal line and an initial signal line connected to a sub-pixel connected to a first power line exposed by the fourth via hole, the fourth center line is a center line of the fourth via hole extending along the second direction, the third boundary of the fourth via hole and the third boundary of the eighth via hole are located on the same side of the fourth center line, and the fourth boundary of the fourth via hole and the fourth boundary of the eighth via hole are located on the same side of the fourth center line; The distance between the orthographic projection of the first boundary of the fourth via hole on the substrate and the orthographic projection of the third signal line on the substrate is greater than the distance between the orthographic projection of the first boundary of the eighth via hole on the substrate and the orthographic projection of the third signal line on the substrate, the distance between the orthographic projection of the second boundary of the fourth via hole on the substrate and the orthographic projection of the third signal line on the substrate is greater than the distance between the orthographic projection of the second boundary of the eighth via hole on the substrate and the orthographic projection of the third signal line on the substrate, and the distance between the third boundary of the fourth via hole and the fourth midline is greater than the distance between the orthographic projection of the third boundary of the eighth via hole on the substrate and the orthographic projection of the third midline. The distance between the orthographic projections of the four center lines on the substrate and the distance between the fourth boundary of the fourth via and the fourth center line are greater than the distance between the orthographic projection of the fourth boundary of the eighth via and the orthographic projection of the fourth center line on the substrate.

12. The display substrate according to claim 11, wherein: A distance between an orthographic projection of a first boundary of the fourth via hole on the substrate and an orthographic projection of a first boundary of the eighth via hole on the substrate is greater than a distance between an orthographic projection of a third boundary of the fourth via hole on the substrate and an orthographic projection of a third boundary of the eighth via hole on the substrate, and is less than a distance between an orthographic projection of a second boundary of the fourth via hole on the substrate and an orthographic projection of a second boundary of the eighth via hole on the substrate; A distance between an orthographic projection of a first boundary of the fourth via hole on the substrate and an orthographic projection of a first boundary of the eighth via hole on the substrate is approximately 1 micrometer to 2 micrometers.

13. The display substrate according to claim 2, wherein: The fifth insulating layer is provided with fifth to eighth via holes, wherein: The orthographic projection of the fifth via on the substrate is within the range of the orthographic projection of the first via on the substrate, the orthographic projection of the sixth via on the substrate is within the range of the orthographic projection of the second via on the substrate, the orthographic projection of the seventh via on the substrate is within the range of the orthographic projection of the third via on the substrate, and the orthographic projection of the eighth via on the substrate is within the range of the orthographic projection of the fourth via on the substrate.

14. The display substrate according to claim 13, wherein: The fifth insulating layer is also provided with any one of the first and second ventilation holes; The orthographic projections of the first vent hole and the second vent hole on the substrate partially overlap with the orthographic projection of the first flat layer on the substrate, and the first flat layer is exposed; There is no overlapping area between the orthographic projections of the first air hole and the second air hole on the substrate and the orthographic projections of the active pattern, gate electrode, first pole and second pole of any transistor, as well as the reference signal line, first scanning signal line, second scanning signal line, third scanning signal line, initial signal line, first power supply line and light-emitting signal line on the substrate.

15. The display substrate according to claim 14, wherein: The length of the first ventilation hole along the first direction is greater than the length of the boundary of the second electrode of the third transistor close to the first scanning signal line, and the length of the first ventilation hole along the second direction is greater than the length of the fifth via hole along the second direction; The orthographic projection of the first vent hole on the substrate is at least arranged around at least one side of the orthographic projection of the first via hole on the substrate; The distance between the orthographic projection of the first vent hole on the substrate and the orthographic projection of the fifth via hole on the substrate is smaller than the distance between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the fifth via hole on the substrate.

16. The display substrate according to claim 14, wherein: The length of the second vent hole along the second direction is greater than the length of the sixth via hole along the second direction, and the length of the second vent hole along the first direction is less than the length of the sixth via hole along the first direction; The second ventilation holes and the sixth via holes are arranged along the second direction, and the distance between the orthographic projection of the sixth via hole on the substrate and the orthographic projection of the first scanning signal line on the substrate is greater than the distance between the second ventilation holes and the sixth via holes.

17. The display substrate according to claim 13 or 14, wherein: The fifth insulating layer is also provided with a third vent hole; The orthographic projection of the third vent hole on the substrate partially overlaps with the orthographic projection of the first flat layer on the substrate, and the first flat layer is exposed; The positive projection of the third vent hole on the substrate is located between the positive projection of the first scanning signal line on the substrate and the positive projection of the light emitting signal line on the substrate, and is in contact with the active pattern, the gate electrode, the first electrode and the second electrode of any transistor, and the reference signal line, the first scanning signal line, the second scanning signal line, the third scanning signal line, the initial signal line, the first electrode, the There is no overlapping area between the orthographic projections of the source line and the light emitting signal line on the substrate.

18. The display substrate according to any one of claims 13, 14 and 17, wherein: The fifth insulating layer is also provided with at least one of the fourth and fifth ventilation holes; The orthographic projections of the fourth vent hole and the fifth vent hole on the substrate partially overlap with the orthographic projection of the first flat layer on the substrate, and the first flat layer is exposed; The orthographic projection of the fourth vent hole on the substrate at least partially overlaps with the orthographic projection of the reference signal line on the substrate, and does not overlap with the orthographic projections of the active pattern, the gate electrode, the first electrode and the second electrode of any transistor, and the first scanning signal line, the second scanning signal line, the third scanning signal line, the initial signal line, the first power supply line and the light emitting signal line on the substrate; The orthographic projection of part of the fifth air holes on the substrate has no overlapping area with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor, as well as the reference signal line, first scanning signal line, second scanning signal line, third scanning signal line, initial signal line, first power line and light-emitting signal line on the substrate; the orthographic projection of another part of the fifth air holes on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate, and has no overlapping area with the orthographic projection of the active pattern, gate electrode, first pole and second pole of any transistor, as well as the reference signal line, first scanning signal line, second scanning signal line, third scanning signal line, initial signal line and light-emitting signal line on the substrate.

19. The display substrate according to claim 18, wherein: The length of the fourth vent hole along the second direction is greater than the length of the third via hole along the second direction, and the length of the fourth vent hole along the first direction is less than the length of the third via hole along the first direction; The fourth air hole and the seventh via hole are arranged along the first direction, and the distance between the orthographic projection on the substrate and the orthographic projection of the gate electrode of the first transistor of the adjacent sub-pixel on the substrate is smaller than the distance between the orthographic projection of the seventh via hole on the substrate and the orthographic projection of the gate electrode of the first transistor of the adjacent sub-pixel on the substrate.

20. The display substrate according to claim 18, wherein: The length of the fifth vent hole along the second direction is greater than the length of the fourth via hole along the second direction, and the length of the fifth vent hole along the first direction is less than the length of the fourth via hole along the first direction; The fifth vent hole and the eighth via hole are arranged along the first direction, and the distance between their orthographic projection on the substrate and the orthographic projection of the fourth via hole on the substrate is smaller than the distance between the orthographic projection of the fourth via hole on the substrate and the orthographic projection of the gate electrode of the first transistor on the substrate.

21. The display substrate according to claim 3 or 13, wherein: The pixel driving circuit further includes: a capacitor, the capacitor including: a first plate, a second plate and a third plate, the first plate being electrically connected to the third plate; The semiconductor layer includes at least: an active pattern of at least one transistor; The first conductive layer at least includes: a gate electrode of at least one transistor and a first plate of a capacitor; The second conductive layer at least includes: a second plate of the capacitor; The third conductive layer at least includes: a first electrode and a second electrode of at least one transistor, a first scanning signal line, a second scanning signal line, a third scanning signal line, a light emitting signal line, an initial signal line, a reference signal line, a first power supply line and a third electrode plate of a capacitor; The fourth conductive layer at least includes: a data signal line.

22. The display substrate according to claim 21, wherein: The first electrode plate of the capacitor includes: a first gate connection portion and a second gate connection portion, the second gate connection portion of the sub-pixel in the current column is located on a side of the first gate connection portion close to the sub-pixel in the next column, and a distance between a boundary of the first gate connection portion close to the gate electrode of the fifth transistor and the gate electrode of the fifth transistor is smaller than a distance between a boundary of the second gate connection portion close to the gate electrode of the fifth transistor and the gate electrode of the fifth transistor, and a distance between a boundary of the first gate connection portion far from the gate electrode of the fifth transistor and the gate electrode of the fifth transistor is smaller than a distance between a boundary of the second gate connection portion far from the gate electrode of the fifth transistor and the gate electrode of the fifth transistor; The length of the first gate connection portion along the first direction is greater than the length of the second gate connection portion along the first direction, and the length of the first gate connection portion along the second direction is greater than the length of the second gate connection portion along the second direction.

23. The display substrate according to claim 22, wherein: The orthographic projection of the second plate of the capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor on the substrate; The second plates of the capacitors of the sub-pixels in the same column have the same shape and area, and the area of ​​the second plates of the capacitors of the sub-pixels in the 3k+1th column is smaller than any one of the areas of the second plates of the capacitors of the sub-pixels in the 3k+2th column and the second plates of the capacitors of the sub-pixels in the 3k+3th column; The area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the 3k+1th column of sub-pixels is smaller than the area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the 3k+2th column of sub-pixels, and the area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the 3k+2th column of sub-pixels is smaller than the area of ​​the overlapping region between the second plate of the capacitor and the first plate of the capacitor of the 3k+3th column of sub-pixels; The area of ​​the overlapped region between the second electrode plate of the capacitor of the 3k+1th column of sub-pixels and the first gate connection portion is smaller than the area of ​​the overlapped region between the second electrode plate of the capacitor of the 3k+2th column of sub-pixels and the first gate connection portion, and the area of ​​the overlapped region between the second electrode plate of the capacitor of the 3k+2th column of sub-pixels and the first gate connection portion is smaller than the area of ​​the overlapped region between the second electrode plate of the capacitor of the 3k+3th column of sub-pixels and the first gate connection portion; The area of ​​the overlapping area between the second plate and the second gate connection portion of the capacitor of the 3k+1th column of sub-pixels is smaller than the area of ​​the overlapping area between the second plate and the second gate connection portion of the capacitor of the 3k+2th column of sub-pixels, and the area of ​​the overlapping area between the second plate and the second gate connection portion of the capacitor of the 3k+3th column of sub-pixels is smaller than the area of ​​the overlapping area between the second plate and the second gate connection portion of the capacitor of the 3k+2th column of sub-pixels.

24. The display substrate according to claim 22 or 23, wherein: The orthographic projection of the third plate of the capacitor on the substrate at least partially overlaps with the orthographic projections of the first plate of the capacitor and the second plate of the capacitor on the substrate, respectively, and the orthographic projection on the substrate has a non-overlapping area with the orthographic projection of the first plate of the capacitor on the substrate, and has a non-overlapping area with the orthographic projection of the second plate of the capacitor on the substrate.

25. The display substrate according to claim 21, further comprising: An initial connection line located in the first conductive layer, the initial connection line at least partially extending along the second direction, the initial connection line being electrically connected to the initial signal line; Two initial connection lines are arranged between at least two columns of sub-pixels, and the two initial connection lines between at least two adjacent sub-pixels are arranged symmetrically with respect to a midline extending along the second direction between the two adjacent sub-pixels; The orthographic projection of the sixth via hole on the substrate does not overlap with the orthographic projection of the initial connection line on the substrate.

26. The display substrate according to claim 25, further comprising: At least one of a power connection line and a reference connection line located in the fourth conductive layer, wherein at least a portion of the power connection line and the reference connection line extends along the second direction; The power connection line is electrically connected to the first power line, and the reference connection line is electrically connected to the reference signal line; The orthographic projection of at least part of the reference connection line on the substrate is between the orthographic projections of two initial connection lines located between two adjacent sub-pixels on the substrate, and the orthographic projection of the power connection line on the substrate and the orthographic projection of the initial connection line on the substrate are away from the side of the orthographic projection of the reference connection line on the substrate.

27. The display substrate according to claim 26, wherein: When the fifth insulating layer is provided with at least one of the first to fifth ventilation holes; There is no overlapping area between the orthographic projections of the first to fifth vent holes on the substrate and the orthographic projections of the power connection line, the reference connection line and the data signal line on the substrate; The orthographic projection of the fourth vent hole on the substrate partially overlaps with the orthographic projection of the initial connection line on the substrate.

28. The display substrate according to claim 1, further comprising: The light-emitting structure layer, the sub-pixel further includes: a light-emitting device, the light-emitting device includes: a first electrode, an organic light-emitting layer and a second electrode, the light-emitting structure layer includes a light-emitting device, and the light-emitting structure layer includes: a fifth conductive layer, a first pixel definition layer, a second pixel definition layer, a light-emitting material layer and a sixth conductive layer sequentially stacked on a side of the driving structure layer away from the substrate; The fifth conductive layer at least includes: a first electrode; The light-emitting material layer at least includes: an organic light-emitting layer; The sixth conductive layer at least includes: a second electrode; The light transmittance of the first pixel definition layer is less than the light transmittance of the second pixel definition layer.

29. The display substrate according to claim 1, wherein: The thickness of the fifth insulating layer is about 1200 angstroms to 1600 angstroms; The thickness of the first planar layer is about 18000 angstroms to 22000 angstroms, and the material used to make the first planar layer includes polyimide.

30. A display device comprising: A display substrate as claimed in any one of claims 1 to 29.

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