Amplifier device and radio-frequency circuit

Abstract

The invention relates to a circuit arrangement for frequency multiplication. The circuit arrangement comprises an operating-point device for an operating-point voltage on the drain or collector side, and a current source which can limit the maximum electric current and the voltages in the circuit arrangement for frequency multiplication.

Description

[0001] Description

[0002] title

[0003] Amplifier device and high-frequency circuit

[0004] Technical area

[0005] The present invention relates to an amplifier device, in particular for amplifying high-frequency signals. The present invention further relates to a high-frequency circuit comprising such an amplifier device.

[0006] background

[0007] Numerous high-frequency devices, such as those used in mobile communications or radar systems, require circuit components to amplify high-frequency signals. If the breakdown voltage of the individual switching elements, i.e., transistors, is below the required supply voltage, amplifier circuits with a stacked arrangement of switching elements can be used.

[0008] For example, document EP 1673858 A2 describes a technique for electrically isolated switching elements in a stacked high-frequency amplifier.

[0009] Disclosure of the invention

[0010] The present invention provides a device for multiplying a frequency, in particular for multiplying the frequency of a high-frequency signal, as well as a high-frequency circuit, having the features of the independent patent claims. Further advantageous embodiments are the subject of the dependent patent claims.

[0011] Accordingly, there is provided: a device for multiplying the frequency, in particular the frequency of a high-frequency signal, having a current source, a multiplier, and an operating point device. The multiplier comprises an input terminal with a positive input terminal and a negative input terminal. The multiplier further comprises an output terminal, a first transistor, and a second transistor. The input terminal of the multiplier is designed to receive an input signal between the positive input terminal and the negative input terminal. The first transistor of the multiplier is electrically coupled to the positive terminal of the input terminal at a control terminal. The second transistor of the multiplier is electrically coupled to the negative terminal of the input terminal at a control terminal.The first transistor and the second transistor of the multiplier are electrically connected to a reference potential at a first terminal. The first transistor and the second transistor are further electrically coupled to the output terminal of the multiplier at a second terminal. The first transistor and the second transistor of the

[0012] Furthermore, the multiplier device is electrically coupled to the current source at the second terminal of the multiplier device. In other words, the current source is coupled to the drain and collector terminals of the transistors, respectively. The operating point device is designed to provide an operating point voltage.

[0013] Furthermore, it is planned:

[0014] A high-frequency circuit with a frequency multiplication device according to the invention. For example, the high-frequency circuit can be a high-frequency circuit of a radar system or a high-frequency component for a mobile radio system.

[0015] Advantages of the invention

[0016] The present invention is based on the finding that, due to the progressive scaling of modern semiconductor technologies, the breakdown voltages between the terminals of individual transistors can decrease. At the same time, the maximum current is also limited due to, for example, electromigration and thermal conditions. On the other hand, the requirements regarding the required power in the signals for the underlying systems remain at least unchanged.

[0017] For maximum output power, the individual components should be operated as close as possible to their breakdown voltage and current limits without exceeding these limits. However, conventional approaches are increasingly reaching their limits.

[0018] It is therefore an idea of ​​the present invention to create an improved concept for an efficiently operated frequency multiplier. To this end, the present invention provides, on the one hand, for providing a drain- or collector-side operating point voltage (bias voltage) in the frequency multiplier circuit in order to operate the circuit at an operating point close to the optimal operating point, and, at the same time, for providing a controllable current source which limits the maximum current in the device for multiplying the frequency. In this way, a drain- or collector-side bias voltage can be provided.

[0019] A collector voltage can be set very close to the supply voltage without requiring negative feedback, especially to the source or emitter. Such a circuit configuration for a frequency multiplier thus enables reliable and efficient operation.

[0020] According to one embodiment, the multiplier device comprises a first matching network. This first matching network is designed to couple the output terminals of the first transistor and the second transistor to the current source. Furthermore, the first matching network is designed to couple the first transistor and the second transistor to the output terminal of the multiplier device. The matching network can, in particular, be a passive network, through which the necessary impedance matching and, if necessary, filtering is realized. According to one embodiment, the multiplier device comprises a second matching network and a third matching network. The second matching network is designed to couple the positive connection point of the input terminal to the control terminal of the second transistor.Similarly, the third matching network is designed to couple the negative terminal of the input terminal to the control terminal of the third transistor. The second matching network and the third matching network can also be implemented as passive matching circuits, which implement the required impedance matching or transformation, as well as filtering if necessary.

[0021] According to one embodiment, the power source is designed to limit a maximum electrical current to the multiplier. This ensures that, on the one hand, the components in the multiplier can be operated very close to the optimal operating point, while, on the other hand, the electrical current through the multiplier does not assume an unacceptably high value.

[0022] According to one embodiment, the current source comprises a transistor and a control device. The transistor is arranged between a voltage source and a terminal of the multiplier. The control device is connected to a control terminal of the transistor and implements the control or limitation of the electrical current through the multiplier.

[0023] According to one embodiment, the operating-point device is designed to provide the operating-point voltage between the output terminals and the control inputs of the first transistor and the second transistor of the multiplier device. Such drain- and collector-side operating-point voltages, respectively, enable the multiplier device to operate close to the optimal operating points.

[0024] According to one embodiment, the operating point device comprises a current mirror circuit. The current mirror circuit can be implemented in a simple manner, for example, using a transistor and an electrical resistor.

[0025] According to one embodiment, the first transistor and the second transistor of the multiplier each comprise a field-effect transistor. Alternatively, the first transistor and the second transistor can each comprise a bipolar transistor.

[0026] According to one embodiment, the frequency multiplication device is implemented as an integrated circuit. In particular, the device can be integrated into a system-on-chip or a monolithic microwave integrated circuit (MMIC).

[0027] The above embodiments and further developments can be combined with one another as desired, where appropriate. Further embodiments, further developments, and implementations of the invention also include combinations of features of the invention not explicitly mentioned above or described below with respect to the exemplary embodiments. In particular, those skilled in the art will also add individual aspects as improvements or additions to the respective basic forms of the invention.

[0028] Short description of the drawings

[0029] Further features and advantages of the invention are explained below with reference to the figures.

[0030] Fig. 1 : a schematic representation of a device for

[0031] Frequency multiplication according to one embodiment.

[0032] Description of embodiments

[0033] Figure 1 shows a schematic representation of a device 1 for

[0034] Frequency multiplication. In particular, the frequency multiplication device 1 can be used to multiply the frequency of a signal in a high-frequency circuit.

[0035] The device 1 for multiplying a frequency comprises a multiplier 10, a current source 20 and an operating point device 30.

[0036] The multiplier 10 comprises an input terminal with a positive input terminal 11 and a negative input terminal 12. An input signal whose frequency is to be multiplied can be provided between the positive terminal 11 and the negative terminal 12. The resulting signal with the multiplied frequency can be provided at an output terminal 13.

[0037] The multiplier 10 further comprises a first transistor T1 and a second transistor T2. The two transistors T1 and T2 can be field-effect transistors, for example. Alternatively, bipolar transistors are also possible. The following describes the frequency multiplication device 1 based on field-effect transistors, with the source terminal being referred to as the input terminal, the drain terminal as the output terminal, and the gate terminal as the control terminal. For bipolar transistors, these terminals are analogously equivalent to the collector, emitter, and base.

[0038] The first transistor T1 is arranged between a reference potential and a first node K1. The input terminal of the first transistor T1 can be electrically connected to the reference potential and the output terminal to the first node K1. In the same way, the second transistor T2 is arranged between the reference potential and the first node K1, wherein here too the input terminal is connected to the reference potential and the output terminal to the first node K1. The control terminal of the first transistor T1 is coupled to the positive input terminal 11. A matching network 14 can be provided between the positive input terminal 11 and the control terminal of the first transistor T1. This matching network 14 can be a passive network for impedance transformation, which can optionally also include filter components.

[0039] Similarly, the negative input terminal 12 can be coupled to the control terminal of the second transistor T2. In this case, a further matching network 15 can also be provided between the control terminal of the second transistor T2 and the negative input terminal 12.

[0040] The first node K1 is coupled to the power source 20. A further matching network 16 can be provided between a connection point 19 for the power source 20 and the first node K1. In this case, the output connection 13 can also be connected via this matching network 16.

[0041] If a signal with an input frequency is applied between the positive terminal 11 and the negative terminal 12, the first transistor T1 and the second transistor T2 are alternately activated. Accordingly, a signal with twice the input frequency is applied to the output terminal 13.

[0042] The operating point device 30 can provide a drain-side operating point voltage (bias voltage) between the connection point 19 for the current source 20 and the control terminals of the two transistors T1, T2, in particular at the two matching networks 14, 15 at the control terminals of the transistors T1, T2. In principle, any suitable circuit concepts designed to provide a suitable operating point voltage are possible for this purpose. For example, the operating point voltage can be realized by the illustrated current mirror comprising a transistor 31 and a resistor 32.

[0043] If necessary, a capacitor C1 can be provided in the multiplier device 10 between the reference potential and the connection point 19 for the current source 20. This can stabilize the supply voltage provided by the current source 20, if necessary.

[0044] The current source 20 provides the supply voltage required to power the multiplier 10 at the connection point 19 of the multiplier 10. The current source 20 is designed to adjust and, in particular, limit the electrical current for the multiplier 10. The current source 20 can, for example, limit the electrical current for the multiplier 10 to a predetermined maximum value.

[0045] The current source 20 can be implemented, for example, by a transistor 21 and a corresponding control unit 22. For example, the transistor 21 can be provided between a terminal for a supply voltage VDD and the connection point 19 of the multiplier. The control unit 22 can be connected to the control terminals of the transistor 21 and thus control or limit the electrical current for the multiplier 10.

[0046] For large signals at the input terminal of multiplier 10, transistor 21 of current source 20 saturates. This reduces the average electrical voltage at connection point 19 of multiplier 10 and thus also the electrical current through multiplier 10. In this way, device 1, and in particular multiplier 10, can be protected from overload.

[0047] In the embodiment shown in Figure 1, the first transistor T1 and the second transistor T2 are implemented as n-channel transistors, and the transistor 21 of the current source 20 is implemented as a p-channel transistor. In principle, however, a reverse topology is also possible, in which the first transistor T1 and the second transistor T2 are implemented as p-channel transistors, and the transistor 21 of the current source 20 is implemented as an n-channel transistor. The same applies to an implementation based on bipolar transistors. The circuit arrangement described can, for example, be implemented in an integrated circuit. In particular, implementation as a system-on-chip (SoC) or monolithic microwave integrated circuit (MMIC) is possible.

[0048] In addition to the frequency doubling described here, the circuit concept described can also be used for multi-stage arrangements for higher frequency multiplication. In particular, the circuit concept can be used for radar circuits or mobile communications applications, for example.

[0049] In summary, the present invention relates to a circuit arrangement for frequency multiplication. The circuit arrangement comprises an operating point device for a drain-side or collector-side operating point voltage, as well as a current source that can limit the maximum electrical current and the voltages in the circuit arrangement for frequency multiplication.

Claims

Claims 1. A device (1) for multiplying the frequency of a high-frequency signal, comprising: a current source (20); a multiplier (10); and an operating point device (30), wherein the multiplier (10) comprises an input terminal with a positive input terminal (11) and a negative input terminal (12), an output terminal (13), a first transistor (T1), and a second transistor (T2), wherein the input terminal of the multiplier (10) is designed to receive an input signal between the positive input terminal (11) and the negative input terminal (12), the first transistor (T1) of the multiplier (10) being electrically coupled at a control terminal to the positive input terminal (11) of the input terminal,the second transistor (T2) of the multiplier (10) is electrically coupled at a control terminal to the negative input terminal (12) of the input terminal, the first transistor (T1) and the second transistor (T2) of the multiplier (10) are electrically connected at a first terminal to a reference potential, the first transistor (T1) and the second transistor (T2) are each electrically coupled at a second terminal to the output terminal (13) of the multiplier (10), the first transistor (T1) and the second transistor (T2) of the multiplier device (10) are each electrically coupled to the current source (20) at the output terminal (13) of the multiplier device (10), and wherein the operating point device (30) is designed to provide an operating point voltage.

2. Device (1) according to claim 1, wherein the multiplier (10) comprises a first matching network (16) designed to couple the second terminals of the first transistor (T1) and the second transistor (T2) to the current source (20) and the output terminal (13) of the multiplier (10).

3. Device (1) according to claim 1 or 2, wherein the multiplier (10) comprises a second matching network (14) and a third matching network (15), wherein the second matching network (14) is designed to couple the positive input terminal (11) of the input terminal to the control terminal of the first transistor (T1) and wherein the third matching network (15) is designed to couple the negative input terminal (12) of the input terminal to the control terminal of the second transistor (T2).

4. Device (1) according to one of claims 1 to 3, wherein the power source (20) is designed to limit a maximum electrical current to the multiplier (10).

5. Device (1) according to claim 4, wherein the current source (20) comprises a transistor (21) and a control device (22), wherein the transistor (21) is arranged between a voltage source and a connection point (19) to the multiplier device (10), and wherein the control device (22) is connected to a control terminal of the transistor (21).

6. Device (1) according to one of claims 1 to 5, wherein the operating point device (30) is designed to determine the operating point voltage between the second terminals of the first transistor (T1) and the second transistor (T2) and the control terminals of the first transistor (T1) and the second transistor (T2) of the multiplier (10).

7. The device (1) according to claim 6, wherein the operating point device (30) comprises a current mirror circuit.

8. Device (1) according to one of claims 1 to 7, wherein the first transistor (T1) and the second transistor (T2) of the multiplier (10) each comprise field-effect transistors or bipolar transistors.

9. Device (1) according to one of claims 1 to 8, wherein the device (1) is integrated in an integrated circuit, in particular in a system-on-chip, an application-specific integrated circuit or a monolithic integrated microwave circuit.

10. High-frequency circuit comprising a frequency multiplying device (1) according to one of claims 1 to 9.

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