Memory device and operation method of memory device

Abstract

The present invention relates to a memory device and an operation method of the memory device. The memory device according to one embodiment of the present invention comprises: an upper electrode; a lower electrode; and a resistance change material layer which is interposed between the upper electrode and the lower electrode, and which is in resistance state that changes in response to a voltage applied through the upper electrode and the lower electrode and an incident optical signal.

Description

Memory devices and methods of operating memory devices

[0001] The present invention relates to a memory device and a method of operating the memory device.

[0002] Future societies will face a rapidly increasing amount of information, requiring technologies capable of efficiently storing and processing that information. Therefore, alternative technologies are needed that offer higher computational efficiency than the binary operations implemented in existing silicon-based devices, can store large amounts of information per unit area, and dramatically reduce the energy required for information processing while operating at high speeds.

[0003] Electronic circuits are represented by combinations of basic elements such as resistors, capacitors, and inductors. Since materials typically represent a single resistance or capacitance value, multiple basic elements are needed to express diverse information.

[0004] Therefore, if a material is developed that can stepwise control resistance and capacitance by voltage and store resistance and capacitance values, electronic circuits can be dramatically simplified and power consumption can also be greatly reduced.

[0005] Memristor devices can be applied to neuromorphic and mem-computing fields because they simultaneously implement a memory function that remembers the resistance state and a switching function in which the resistance is modulated by voltage.

[0006] Typical oxide-based memristors utilize sapphire or silicon substrates to form a metal-oxide-metal structure, resulting in a device configuration with a top-bottom structure. Oxide thin films typically exhibit insulating properties, resulting in a high-resistance state, with very low currents (less than nA) flowing when voltage is applied to the upper and lower electrodes.

[0007] However, when a certain voltage is applied, a conductive channel is formed between the upper and lower electrodes by the movement of oxygen vacancies and metal ions in the electrodes within the oxide thin film, which can exhibit a low resistance state (set process). Conversely, when voltage is applied, a high resistance state is exhibited again due to the collapse of the conductive channel formed by defects such as metal ions or oxygen vacancies (reset process). In this way, a resistive memory, i.e. a memristor, has been reported by utilizing the characteristic of changing between low and high resistance through the set and reset processes according to the applied voltage.

[0008] Conventional memristors can be used as semiconductors that use binary logic, with high and low resistance states as the logical states of '0' and '1', through electrical input. Optoelectronic synaptic devices also exhibit long-term memory characteristics using high and low photoexcitation currents, similar to conventional memristors, by maintaining photoexcitation current for a long time through a photoexcitation method. However, these binary-based semiconductors that utilize high and low resistance states have technical limitations in terms of power consumption, and technology for storing and processing data through memories with more logical states is needed.

[0009] The background technology described above is technology that the inventor possessed or acquired in the process of deriving the disclosure of the present invention, and cannot necessarily be said to be publicly known technology disclosed to the general public prior to the present application.

[0010] The present invention is intended to solve the above-described problems, and an object of the present invention is to provide a memory device having a double resistance state and an operating method of the memory device by reducing the resistance of the device through electrical stimulation and optical stimulation.

[0011] However, the problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0012] A memory device according to one embodiment of the present invention includes: an upper electrode; a lower electrode; and a resistance change material layer interposed between the upper electrode and the lower electrode, the resistance state of which changes in response to a voltage applied through the upper electrode and the lower electrode and an incident light signal.

[0013] In one embodiment, the resistance state may include a first resistance state to an nth resistance state (n≥3) in response to a voltage applied through the upper electrode and the lower electrode and an incident light signal.

[0014] In one embodiment, it may be possible to implement a first resistance state in which the voltage is not applied and the optical signal is not incident, a second resistance state in which the voltage is not applied and the optical signal is incident, a third resistance state in which the voltage is applied and the optical signal is not incident, and a fourth resistance state in which the voltage is applied and the optical signal is incident.

[0015] In one embodiment, the first resistance state may be a high resistance state, the second resistance state may be a state in which current flows by generating photogenerated electron-hole pairs by photogenerated carriers, the third resistance state may be a low resistance state, and the fourth resistance state may be a state in which current flows by generating photogenerated electron-hole pairs by photogenerated carriers.

[0016] In one embodiment, the optical signal may be converted from at least one light selected from the group consisting of an ultraviolet band, an infrared band, and a visible light band.

[0017] In one embodiment, the photoexcitation current may be proportional to the energy and light output of at least one light selected from the group consisting of the ultraviolet band, the infrared band, and the visible light band, so as to exhibit a first resistance state to an nth resistance state (n≥3).

[0018] In one embodiment, the upper electrode and the lower electrode may each include at least one selected from the group consisting of platinum (Pt), iridium (Ir), gold (Au), silver (Ag), aluminum (Al), ruthenium (Ru), tungsten (W), titanium (Ti), nickel (Ni), hafnium (Hf), iridium oxide (IrO2), ruthenium oxide (RuO2), titanium nitride (TiN), and tantalum nitride (TaN).

[0019] In one embodiment, the resistance-changing material layer may include a conductive channel formed of a metal ion, a point defect, or both, which is capable of electron mobility and is controllable according to voltage.

[0020] In one embodiment, the resistance change material layer may include at least one selected from the group consisting of metal oxide, metal nitride, metal sulfide, metal selenide, and metal telluride.

[0021] In one embodiment, the metal oxide may include at least one selected from the group consisting of CaO, CdO, Co3O5, CoO2, CuO2, MoO3, WO3, Ga2O3, MnO2, ZnO, RuO2, TiO2, SnO2, Nb2O5, NiO, CrO2, Fe3O4, ZrO2, HfO2, and V2O5.

[0022] In one embodiment, the metal nitride may include at least one selected from the group consisting of GaN, InN, AlN, Ti2N, Ti3N2, Ti4N3, Zr2N, V2N, and Cr2N.

[0023] In one embodiment, the metal sulfide may include at least one selected from the group consisting of MoS2, MoS2, WS2, ReS2, NbS2, ZrS2, TiS2, HfS2, and VS2.

[0024] In one embodiment, the metal selenide may include at least one selected from the group consisting of MoSe2, WSe2, ReSe2, NbSe2, ZrSe2, TiSe2, HfSe2, or VSe2.

[0025] In one embodiment, the metal telluride may include at least one selected from the group consisting of MoTe2, WTe2, ReTe2, NbTe2, ZrTe2, TiTe2, HfTe2, and VTe2.

[0026] In one embodiment, the memory element may be a memristor.

[0027] In one embodiment, the memristor may include at least one selected from the group consisting of Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PcRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FeRAM), and Conductive Bridging Random Access Memory (CBRAM).

[0028] According to another embodiment of the present invention, a method of operating a memory device includes an upper electrode; a lower electrode; and a resistance change material layer interposed between the upper electrode and the lower electrode, the method comprising: a step of selectively applying a voltage through the upper electrode and the lower electrode; a step of selectively incident an optical signal onto the resistance change material layer; and a step of changing a resistance state of the resistance change material layer in response to the voltage applied through the upper electrode and the lower electrode and the incident optical signal.

[0029] In one embodiment, the step of changing the resistance state of the resistance change material layer may be to implement a first resistance state to an nth resistance state (n≥3) in response to a voltage applied through the upper electrode and the lower electrode and an incident light signal.

[0030] In one embodiment, the step of changing the resistance state of the resistance change material layer may be a step of implementing the resistance state of the resistance change material layer into any one of a first resistance state in which the voltage is not applied and the optical signal is not incident, a second resistance state in which the voltage is not applied and the optical signal is incident, a third resistance state in which the voltage is applied and the optical signal is not incident, or a fourth resistance state in which the voltage is applied and the optical signal is incident.

[0031] In one embodiment, the first resistance state may be a high resistance state, the second resistance state may be a state in which current flows by generating photogenerated electron-hole pairs by photogenerated carriers, the third resistance state may be a low resistance state, and the fourth resistance state may be a state in which current flows by generating photogenerated electron-hole pairs by photogenerated carriers.

[0032] In one embodiment, the step of changing the resistance state of the resistance change material layer may be changing the resistance state of the resistance change material layer by an optical signal converted from at least one light selected from the group consisting of an ultraviolet band, an infrared band, and a visible light band.

[0033] In one embodiment, the photoexcitation current may be proportional to the energy and light output of at least one light selected from the group consisting of the ultraviolet band, the infrared band, and the visible light band, thereby changing the first resistance state to the nth resistance state (n≥3).

[0034] A memory device according to one embodiment of the present invention has three or more logical states and can be used in a multi-state system, and thus is more advantageous in power consumption and large-capacity information processing than conventional binary-based semiconductors that have reached their technological limits in terms of power consumption, and is expected to contribute to the speed, miniaturization, and power-saving of next-generation semiconductors. In addition, it can be used as a device capable of simultaneously performing image sensing and memory through electrical stimulation and optical stimulation. In addition, as a memristor-based synaptic device, it can be expanded into a high-speed, high-density, next-generation resistive memory device capable of multi-state processing beyond the conventional computer structure.

[0035] According to an operating method of a memory device according to one embodiment of the present invention, three or more logical states can be obtained by using light incident in high and low resistance states of the memory device, and this can be used in a multi-state method, and can be applied to multi-state memory device technology.

[0036] FIG. 1 is a schematic diagram showing a memory device according to one embodiment of the present invention.

[0037] FIG. 2 is a flowchart for explaining an operating method of a memory device using a memory device according to one embodiment of the present invention.

[0038] FIG. 3 shows (a) a resistance state change mechanism of a Pt / Ga2O3 / Pt structure memristor according to Example 1 of the present invention, (b) a current-voltage graph according to the resistance state of the memristor, (c) a photocurrent according to the resistance state of the memristor, and (d) a current-voltage graph before and after application of ultraviolet light.

[0039] FIG. 4 is a graph showing long-term memory characteristics according to the formation of photocurrent according to the photoexcitation time, excitation light intensity, excitation light frequency, and excitation light cycle in (a) high resistance and (b) low resistance states of a Pt / Ga2O3 / Pt structure memristor according to Example 1 of the present invention.

[0040] FIG. 5 is a graph showing the results of (a) continuous measurement of a memristor and (b) measurement of retention time of a memristor according to Example 1 of the present invention.

[0041] FIG. 6 is a diagram showing a learning-experience simulation of a Pt / Ga2O3 / Pt memristor in (a) high resistance and (b) low resistance states according to Example 1 of the present invention.

[0042] FIG. 7 is a diagram showing a visual memory simulation in (a) high resistance and (b) low resistance states of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention.

[0043] FIG. 8 is a graph showing (a) the structure of an artificial neural network of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention and (b) the pattern recognition accuracy of high-resistance and low-resistance states through artificial neural network simulation.

[0044] FIG. 9 is a schematic diagram of a quaternary memory element using (a) a light-emitting diode of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention and (b) a schematic diagram of a quaternary implementation through electrical / optical signals over time in high-resistance and low-resistance states.

[0045] FIG. 10 is a schematic diagram of a resistance change mechanism in the '0, 1, 2, 3' states corresponding to four resistance components of high resistance, high resistance + photocurrent, low resistance, and low resistance + photocurrent of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention.

[0046] FIG. 11 is a diagram showing the results of a visual memory simulation using the quaternary system of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention.

[0047] FIG. 12 is a diagram showing a Pavlovian puppy simulation using a four-stage resistance state from a high resistance (0,1 state) to a low resistance (2,3) state of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention.

[0048] Figure 13 shows the results of an actual simulation using a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention.

[0049] FIG. 14 is a diagram showing (a) resistive switching behavior and current-voltage curves according to injection of various excitation lights of a bipolar memristor having an Ag / Ga2O3 / Pt structure according to Example 2 of the present invention, and (b) photocurrent according to application of ultraviolet, blue, green, and red light.

[0050] Hereinafter, embodiments are described in detail with reference to the attached drawings. However, the embodiments may be modified in various ways, and the scope of the patent application is not limited or restricted by these embodiments. It should be understood that all modifications, equivalents, or alternatives to the embodiments are included within the scope of the patent application.

[0051] The terms used in the examples are for illustrative purposes only and should not be construed as limiting. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "have" are intended to indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood to not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0052] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the embodiments pertain. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0053]

[0054] In addition, when describing with reference to the attached drawings, identical components will be assigned the same reference numerals regardless of the drawing numbers, and redundant descriptions thereof will be omitted. When describing embodiments, if a detailed description of a related known technology is judged to unnecessarily obscure the gist of the embodiment, the detailed description will be omitted.

[0055] Additionally, in describing components of an embodiment, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms.

[0056] Components included in one embodiment and components with common functions will be described using the same names in other embodiments. Unless otherwise stated, the descriptions given in one embodiment may also apply to other embodiments, and detailed descriptions will be omitted to the extent of overlap.

[0057]

[0058] Hereinafter, the memory device and the operating method of the memory device of the present invention will be described in detail with reference to examples and drawings. However, the present invention is not limited to these examples and drawings.

[0059]

[0060] A memory device according to one embodiment of the present invention includes: an upper electrode; a lower electrode; and a resistance change material layer interposed between the upper electrode and the lower electrode, the resistance state of which changes in response to a voltage applied through the upper electrode and the lower electrode and an incident light signal.

[0061] In one embodiment, the resistance state may include a first resistance state to an nth resistance state (n≥3) in response to a voltage applied through the upper electrode and the lower electrode and an incident light signal.

[0062] Accordingly, a memory device according to one embodiment of the present invention may have a polynomial logic state capable of expressing three or more resistance states.

[0063] According to one embodiment of the present invention, a voltage is applied to a memory device to control high resistance and low resistance states, and in each of the high resistance and low resistance states, the resistance state can be controlled through high resistance, high resistance + photoexcitation, low resistance, and low resistance + photoexcitation conditions through photoexcitation.

[0064] FIG. 1 is a schematic diagram showing a memory device according to one embodiment of the present invention.

[0065] Referring to FIG. 1, a memory device (100) according to one embodiment of the present invention includes a substrate (110), a lower electrode (120), a resistance change material layer (130), and an upper electrode (140).

[0066] The substrate (110) may be, for example, a sapphire substrate; a semiconductor substrate such as a silicon substrate or germanium; or an SOI substrate (silicon on insulator).

[0067] Preferably, the substrate (110) may be sapphire.

[0068] In one embodiment, the upper electrode (140) and the lower electrode (120) may each include at least one selected from the group consisting of platinum (Pt), silver (Ag), aluminum (Al), iridium (Ir), gold (Au), ruthenium (Ru), tungsten (W), titanium (Ti), nickel (Ni), hafnium (Hf), iridium oxide (IrO2), ruthenium oxide (RuO2), titanium nitride (TiN), and tantalum nitride (TaN).

[0069] The upper electrode (140) and the lower electrode (120) may be made of the same material or different materials, respectively.

[0070] Preferably, the upper electrode (140) and the lower electrode (120) may each be made of platinum (Pt).

[0071] In one embodiment, the resistance change material layer (130) may include a conductive channel formed of a metal ion, a point defect, or both, which allows electron movement and is controllable according to voltage.

[0072] The resistance change material layer (130) can reversibly change its structure between a low-resistance crystalline state and a high-resistance amorphous state depending on the application of an external voltage or current. Even if the applied external voltage or current is removed, the resistance change material layer (130) can non-volatilely store the changed crystalline or amorphous state.

[0073] For example, the point defect may include oxygen vacancies.

[0074] The above oxygen vacancies can electrically connect the upper electrode (140) and the lower electrode (120), and can perform a function of changing the resistance state of the element to exhibit switching characteristics.

[0075] For example, the metal ion may be a metal cation having a positive charge or a metal anion having a negative charge.

[0076] In one embodiment, the resistance change material layer (130) may include at least one selected from the group consisting of metal oxide, metal nitride, metal sulfide, metal selenide, and metal telluride.

[0077] In one embodiment, the metal oxide may include at least one selected from the group consisting of CaO, CdO, Co3O5, CoO2, CuO2, MoO3, WO3, Ga2O3, MnO2, ZnO, RuO2, TiO2, SnO2, Nb2O5, NiO, CrO2, Fe3O4, ZrO2, HfO2, and V2O5.

[0078] In one embodiment, the metal nitride may include at least one selected from the group consisting of GaN, InN, AlN, Ti2N, Ti3N2, Ti4N3, Zr2N, V2N, and Cr2N.

[0079] In one embodiment, the metal sulfide may include at least one selected from the group consisting of MoS2, MoS2, WS2, ReS2, NbS2, ZrS2, TiS2, HfS2, and VS2.

[0080] In one embodiment, the metal selenide may include at least one selected from the group consisting of MoSe2, WSe2, ReSe2, NbSe2, ZrSe2, TiSe2, HfSe2, or VSe2.

[0081] In one embodiment, the metal telluride may include at least one selected from the group consisting of MoTe2, WTe2, ReTe2, NbTe2, ZrTe2, TiTe2, HfTe2, and VTe2.

[0082] Preferably, the resistance change material layer (130) may be a metal oxide, and more preferably, may be Ga2O3.

[0083] In one embodiment, the memory element (100) may implement a first resistance state in which the voltage is not applied and the optical signal is not incident, a second resistance state in which the voltage is not applied and the optical signal is incident, a third resistance state in which the voltage is applied and the optical signal is not incident, and a fourth resistance state in which the voltage is applied and the optical signal is incident.

[0084] In one embodiment, the first resistance state may be a high resistance state, the second resistance state may be a state in which current flows by generating photogenerated electron-hole pairs by photogenerated carriers, the third resistance state may be a low resistance state, and the fourth resistance state may be a state in which current flows by generating photogenerated electron-hole pairs by photogenerated carriers.

[0085] That is, the first resistance state may be a high resistance condition, the second resistance state may be a high resistance + photoexcitation condition, the third resistance state may be a low resistance condition, and the fourth resistance state may be a low resistance + photoexcitation condition.

[0086] The first resistance state, the second resistance state, the third resistance state and the fourth resistance state can each represent a signal of the '0, 1, 2, 3' stages, and the logical states of '0, 1, 2, 3' can be used in quaternary and applied to a quaternary memory element.

[0087] When a light signal is incident, a higher current flows in the high resistance state due to the photocurrent, and a set appears in the lower voltage range due to the movement of photogenerated carriers and ionized oxygen defects. This memory device undergoes a set process in which the resistance changes from high to low when a positive voltage is applied. After the set process, if a positive voltage is applied again, the resistance changes from low to high through a reset process, which can exhibit the behavior of a memristor with unipolar characteristics.

[0088] Accordingly, by incident a light signal and applying the same voltage, two additional states can be created: a lower resistance component than the high resistance component and a lower resistance state than the low resistance state after the set process. When a light signal is applied, photogenerated electron-hole pairs are generated, lowering the resistance, thereby creating states in which current flows better in the high resistance and low resistance states, respectively. This photoreaction can be utilized as an optoelectronic synapse element.

[0089] Additionally, if a set process is performed at a positive voltage and then a reset process is performed at a negative voltage, it may have bipolar characteristics.

[0090] For example, when the structure of the upper electrode / resistance change material layer / lower electrode is Pt / Ga2O3 / Pt, unipolar characteristics may appear, and when the structure is Ag / Ga2O3 / Pt, bipolar characteristics may appear.

[0091] In both structures, set and reset formations are possible, and four resistance states can appear depending on the light excitation.

[0092] In one embodiment, the optical signal may be converted from at least one light selected from the group consisting of an ultraviolet band, an infrared band, and a visible light band.

[0093] In one embodiment, the photoexcitation current may be proportional to the energy and light output of at least one light selected from the group consisting of the ultraviolet band, the infrared band, and the visible light band, so as to exhibit a first resistance state to an nth resistance state (n≥3).

[0094] For example, high and low resistance states may be affected by different wavelengths of ultraviolet, blue, green and red light, each of which may exhibit five resistance states.

[0095] In addition, it is possible to implement a multiple-digit system such as the decimal system by exciting light of various energies.

[0096] In one embodiment, the memory element (100) may be a memristor.

[0097] In one embodiment, the memristor may include at least one selected from the group consisting of Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PcRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FeRAM), and Conductive Bridging Random Access Memory (CBRAM).

[0098] Preferably, the memory element (100) may be a memristor.

[0099] A memory device according to one embodiment of the present invention has three or more logical states and can be used in a multi-state system, and thus is more advantageous in power consumption and large-capacity information processing than conventional binary-based semiconductors that have reached their technological limits in terms of power consumption, and is expected to contribute to the speed, miniaturization, and power-saving of next-generation semiconductors. In addition, it can be used as a device capable of simultaneously performing image sensing and memory through electrical stimulation and optical stimulation. In addition, as a memristor-based synaptic device, it can be expanded into a high-speed, high-density, next-generation resistive memory device capable of multi-state processing beyond the conventional computer structure.

[0100]

[0101] According to another embodiment of the present invention, a method of operating a memory device includes an upper electrode; a lower electrode; and a resistance change material layer interposed between the upper electrode and the lower electrode, the method comprising: a step of selectively applying a voltage through the upper electrode and the lower electrode; a step of selectively incident an optical signal onto the resistance change material layer; and a step of changing a resistance state of the resistance change material layer in response to the voltage applied through the upper electrode and the lower electrode and the incident optical signal.

[0102] Figure 2 is a flowchart showing an operating method of a memory device according to one embodiment of the present invention.

[0103] Referring to FIG. 2, a method of operating a memory device according to one embodiment of the present invention includes a step (210) of selectively applying a voltage through an upper electrode and a lower electrode, a step (220) of selectively incident an optical signal onto a resistance change material layer, and a step (230) of changing a resistance state of the resistance change material layer in response to the voltage applied and the optical signal incident through the upper electrode and the lower electrode.

[0104] Step (210) can selectively apply voltage through the upper electrode and the lower electrode.

[0105] At this time, in step (210), the memory element may undergo a set process in which a high resistance state changes to a low resistance state when a positive voltage is applied to the upper electrode. After the set process at a positive voltage, a voltage of 0 V is applied, and then a positive voltage is applied again to change from a low resistance state to a high resistance state, thereby having a unipolar characteristic.

[0106] Additionally, if a set process is performed at a positive voltage and then a reset process is performed at a negative voltage, it may have bipolar characteristics.

[0107] For example, when the structure of the upper electrode / resistance change material layer / lower electrode is Pt / Ga2O3 / Pt, unipolar characteristics may appear, and when the structure is Ag / Ga2O3 / Pt, bipolar characteristics may appear.

[0108] In both structures, set and reset formations are possible, and four resistance states can appear depending on the light excitation.

[0109] Depending on the voltage applied, it can be divided into two logical states: high resistance state '0' and low resistance state '1'.

[0110] Step (220) can selectively cause an optical signal to be incident on the resistance change material layer of the memory element.

[0111] In this specification, an optical signal can be interpreted as an electromagnetic wave of any frequency band. That is, the light in this specification may be an electromagnetic wave of the visible light band (VL), an electromagnetic wave of the ultraviolet band (UV), or an electromagnetic wave of the infrared band (InfraRed light (IR). Alternatively, the light in this specification may be an electromagnetic wave having a wavelength band other than the frequency bands described above.

[0112] By applying the same voltage while incident on a light signal, two additional states can be created: one with a lower resistance component than the high resistance component and another with a lower resistance state than the low resistance state after the set process. Incident on a light signal generates photogenerated electron-hole pairs, which lowers the resistance, creating states in which current flows better in both the high and low resistance states.

[0113] Depending on the light incident, four resistance states can be obtained, which can be used as a quaternary number of '0, 1, 2, 3'.

[0114] In one embodiment, the step (230) of changing the resistance state of the resistance change material layer may be to implement a first resistance state to an nth resistance state (n≥3) in response to a voltage applied through the upper electrode and the lower electrode and an incident light signal.

[0115] Accordingly, it can be operated as a memory element having a polynomial logic state capable of expressing three or more resistance states.

[0116] In one embodiment, the step (230) of changing the resistance state of the resistance change material layer may be a step of implementing the resistance state of the resistance change material layer in any one of a first resistance state in which the voltage is not applied and the optical signal is not incident, a second resistance state in which the voltage is not applied and the optical signal is incident, a third resistance state in which the voltage is applied and the optical signal is not incident, or a fourth resistance state in which the voltage is applied and the optical signal is incident.

[0117] In one embodiment, the first resistance state may be a high resistance state, the second resistance state may be a state in which current flows better by generating photogenerated electron-hole pairs by photogenerated carriers in the first resistance state, the third resistance state may be a low resistance state, and the fourth resistance state may be a state in which current flows better by generating photogenerated electron-hole pairs by photogenerated carriers in the third resistance state.

[0118] That is, the first resistance state may be a high resistance condition, the second resistance state may be a high resistance + photoexcitation condition, the third resistance state may be a low resistance condition, and the fourth resistance state may be a low resistance + photoexcitation condition.

[0119] The first resistance state, the second resistance state, the third resistance state, and the fourth resistance state can each represent a signal of '0, 1, 2, 3' stages.

[0120] '0' represents the basic high resistance state of the device, '1' represents the state in which photogenerated carriers are generated by applying light to the '0' state, allowing better current flow. '2' represents the low resistance state in which conductive filaments are formed by applying voltage to the '0' state, and '3' represents the state in which photogenerated carriers are generated by applying light to the '2' state, allowing better current flow.

[0121] In one embodiment, the step of changing the resistance state of the resistance change material layer may be changing the resistance state of the resistance change material layer by an optical signal converted from at least one light selected from the group consisting of an ultraviolet band, an infrared band, and a visible light band.

[0122] In one embodiment, the photoexcitation current may be proportional to the energy and light output of at least one light selected from the group consisting of the ultraviolet band, the infrared band, and the visible light band, thereby changing the first resistance state to the nth resistance state (n≥3).

[0123] For example, high and low resistance states may be affected by different wavelengths of ultraviolet, blue, green and red light, each of which may exhibit five resistance states.

[0124] In addition, it is possible to implement a multiple-digit system such as the decimal system by exciting light of various energies.

[0125] According to an operating method of a memory device according to one embodiment of the present invention, three or more logical states can be obtained by using light incident in high and low resistance states of the memory device, and this can be used in a multi-state method, and can be applied to multi-state memory device technology.

[0126]

[0127] Hereinafter, the present invention will be described in detail with reference to the following examples and comparative examples. However, the technical concept of the present invention is not limited or restricted thereby.

[0128]

[0129] [Example 1]

[0130] Fabrication of Pt / Ga2O3 / Pt structure memristor

[0131] Pt was deposited as a lower electrode on a sapphire substrate, a Ga2O3 thin film was formed thereon, and then a Pt upper electrode was deposited again. To deposit the upper electrode, a photomask or shadow mask was used to form a cylindrical upper electrode, thereby manufacturing a Pt / Ga2O3 / Pt structure memristor.

[0132]

[0133] Experimental Example 1-1

[0134] FIG. 3 is a current-voltage graph showing (a) a resistance state change mechanism of a Pt / Ga2O3 / Pt structure memristor according to Example 1 of the present invention, (b) a current-voltage graph according to the resistance state of the memristor, (c) a photocurrent according to the resistance state of the memristor, and (d) a resistive switching phenomenon before and after application of ultraviolet light.

[0135] Figure 3 (a) illustrates the principle of forming a conductive channel to implement a memristor with a metal-oxide-metal structure. First, by applying a (+) voltage to the upper electrode, conductive filaments based on oxygen vacancies in the oxide are formed, and the device enters a low-resistance state (set process). When voltage is applied again to the electrode of the device in a low-resistance state, a high current flows, and oxygen ions are absorbed into the weak part of the filament, causing the conductive filament to decompose and return to a high-resistance state (reset process). In this way, the high-resistance state and the low-resistance state have logic states of '0' and '1', respectively.

[0136] Figure 3 (b) is a current-voltage graph in high-resistance and low-resistance states, showing that the memristor of the Ga2O3 oxide structure proposed in the present invention can be controlled into high-resistance and low-resistance states depending on the applied voltage.

[0137] Figure 3(c) shows the photocurrent of this Pt / Ga2O3 / Pt memristor in high-resistance and low-resistance states. The photocurrent at 1 V was obtained by applying 365 nm UV light for 1 minute and using the difference between the UV current and the dark current. It was 84.41 μA in the high-resistance state and 11.02 μA in the low-resistance state.

[0138] Figure 3(d) shows the photocurrent when UV is irradiated under the same voltage applied as the voltage-current when a positive voltage is applied from 0 V to 0 V, and then back to a positive voltage. When UV is applied, a higher current flows in the high resistance state due to the photocurrent, and a set appears in the lower voltage range due to the movement of photogenerated carriers and ionized oxygen defects. This memristor underwent a set process in which the resistance changed from a high to a low state when a positive voltage was applied, and after the set process, a reset process in which the resistance changed from low to high by applying a positive voltage again after applying 0 V was performed, demonstrating the behavior of a memristor with unipolar characteristics. In addition, by applying UV and the same voltage, two other states can be additionally created, one of which is a resistance component lower than the high resistance component and the other is a low resistance state lower than the low resistance state after the set process. Applying ultraviolet light generates photogenerated electron-hole pairs, lowering the resistance and enabling better current flow in both high- and low-resistance states. Furthermore, the photoreaction can be utilized as an optoelectronic synaptic device.

[0139]

[0140] Experimental Example 1-2

[0141] A memristor according to an embodiment of the present invention, rather than a typical oxide memristor having two logical states of '0' and '1', utilizes optical stimulation to generate photogenerated electron-hole pairs, thereby reducing resistance and creating a state in which higher current flows in each state. Utilizing this optical response, the memristor can be used as an artificial synaptic element.

[0142] FIG. 4 is a graph showing long-term memory characteristics according to the formation of photocurrent according to the photoexcitation time, excitation light intensity, excitation light frequency, and excitation light cycle in (a) high resistance and (b) low resistance states of a Pt / Ga2O3 / Pt structure memristor according to Example 1 of the present invention.

[0143] Figures 4(a) and (b) are time-dependent excitatory postsynaptic current graphs measuring the photoelectric synapse characteristics by changing the conditions of UV stimulation in high-resistance and low-resistance states, respectively. The measurements were performed by controlling the light duration, light intensity, frequency, and number of spikes. The longer the duration and the higher the light intensity in the single-pulse light duration and light intensity, the longer the long-term memory characteristics were exhibited. In addition, the higher the frequency and the higher the number of spikes in the multiple-pulse frequency and spike count, the longer the long-term memory characteristics were exhibited. Therefore, by applying light to the existing state, a state in which current flows better can be created and used by adding another state. This indicates that the Pt / Ga2O3 / Pt memristor not only controls the resistance state through the set and reset processes, but also can store a higher photoexcited current for a long time in the high-resistance and low-resistance states depending on the photoexcited synaptic characteristics. Accordingly, by applying light, the photoresponse can be used in the high and low resistance states of each memristor to obtain four resistance states, and this can be applied to the technology of a quaternary memristor that can be used in the quaternary system of '0, 1, 2, 3' and to an optoelectronic synaptic device using this.

[0144]

[0145] Experimental Example 1-3

[0146] In a Pt / Ga2O3 / Pt-based memristor according to an embodiment of the present invention, stability for high and low resistance over time is one of the very important characteristics.

[0147] FIG. 5 is a graph showing the results of (a) continuous measurement of a memristor and (b) measurement of retention time of a memristor according to Example 1 of the present invention.

[0148] As shown in Fig. 5, the resistance change was confirmed at a reading voltage of 0.2 V by performing continuous measurement for 100 cycles, and the low resistance was 10 to 10 2 It represents a resistance value of Ω, and in a high resistance state, it is about 10 5 ~10 7 It represents the value of Ω and has an average of about 10 3 It shows a resistance ratio of Ω or more. In addition, as a result of confirming the retention time characteristics of the memristor, it was 10 4 It was confirmed that the device has a stable retention time in which the resistance does not change for a period of 10 seconds. In summary, this demonstrates that the device stably maintains high and low resistance states, demonstrating stability and non-volatility.

[0149]

[0150] Experimental Example 1-4

[0151] Using a Pt / Ga2O3 / Pt memristor that increases current through light stimulation, we verified three learning-experience simulations in high- and low-resistance states. One learning session was conducted by applying 100 light pulses. The current obtained after 100 applications was assumed to be a 100% memory level, and the memory stage was set to be 70% of the maximum current, and the forgetting stage was assumed to be less than 70%.

[0152] FIG. 6 is a diagram showing a learning-experience simulation of a Pt / Ga2O3 / Pt memristor in (a) high resistance and (b) low resistance states according to Example 1 of the present invention.

[0153] Referring to Figure 6, in the high-resistance state, 55 light pulses were required for the current to increase from 140 μA to 170 μA for the first learning to be remembered. After that, the number of light pulses required decreased to 27 and 18 for the second and third learning, respectively. This shows that as learning progresses, the number of pulses required for memory decreases, indicating that learning is progressing. In addition, since the amount of current remaining during the same period increases, it can be seen that previously learned memories remain. In comparison, in the low-resistance state, the number of required light pulses decreases to 61, 28, and 21. Even in the low-resistance state, as learning progresses, the number of pulses required for memory decreases, and the amount of current decreases decreases, indicating that higher memory is achieved. These memristors demonstrate that effective learning-experience simulation is possible due to their photoresponsiveness and long-term memory characteristics.

[0154]

[0155] Experimental Example 1-5

[0156] Using the memristor proposed in the present invention that increases current through light stimulation, data stored for 1 second and data forgotten for 30 seconds were encoded with excitatory postsynaptic currents by encoding ultraviolet rays of different light intensities in a 4X4 square array in high and low resistance states, simulating the process of visual recognition. The light intensity was used to control the visual memory effect, which is expressed as color contrast. The longer the light is applied, the stronger the color contrast becomes, resulting in a more stable memory. Afterwards, it was confirmed that the color contrast gradually decreased during the 30-second forgetting process, and only a part of the image remained. This shows that forgetting is a gradual process, and the memory effect can be controlled depending on the input intensity.

[0157] FIG. 7 is a diagram showing a visual memory simulation in (a) high resistance and (b) low resistance states of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention.

[0158] Referring to Figures 7 (a) and (b), it can be seen that when storing memories with the same input light intensity, the remaining excitatory current after 1 second exhibits a higher memory current in the high-resistance state than in the low-resistance state. Furthermore, it was confirmed that the remaining excitatory current after 30 seconds of removing the input light also exhibited a greater amount of current in the high-resistance state. This indicates that while memory is possible in both high-resistance and low-resistance states, the high-resistance state exhibits slightly higher long-term memory characteristics.

[0159]

[0160] Experimental Example 1-6

[0161] The present invention confirmed the accuracy of image recognition through artificial neural network simulation using the current change when ultraviolet rays were applied in the high-resistance and low-resistance states of a Pt / Ga2O3 / Pt memristor.

[0162] FIG. 8 is a graph showing (a) the structure of an artificial neural network of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention and (b) the pattern recognition accuracy of high-resistance and low-resistance states through artificial neural network simulation.

[0163] Referring to Fig. 8, the pattern recognition accuracy of the device was confirmed to be high at over 90% in each resistance state.

[0164]

[0165] Experimental Example 1-7

[0166] FIG. 9 is a schematic diagram of a quaternary memory element using (a) a light-emitting diode of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention and (b) a schematic diagram of a quaternary implementation through electrical / optical signals over time in high-resistance and low-resistance states.

[0167] Conventional Pt / Ga2O3 / Pt memristors can be distinguished into two logical states, high resistance state '0' and low resistance state '1', depending on the voltage applied. However, the newly proposed memristor can exhibit four states through electrical and optical stimulation. Fig. 9 (a) shows a circuit diagram of a light-emitting diode and a memristor. The state can be changed by applying light from the light-emitting diode to the memristor. A graph showing the state change through such electrical and optical signals is shown in Fig. 9 (b).

[0168]

[0169] Experimental Example 1-8

[0170] FIG. 10 is a schematic diagram of a resistance change mechanism in the '0, 1, 2, 3' states corresponding to four resistance components of high resistance, high resistance + photocurrent, low resistance, and low resistance + photocurrent of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention.

[0171] As illustrated in Fig. 10, '0' represents the basic high resistance state of the device, '1' represents the state in which photogenerated carriers are generated by applying light to the '0' state, allowing better current flow, '2' represents the low resistance state in which conductive filaments are formed by applying voltage to the '0' state, and '3' represents the state in which photogenerated carriers are generated by applying light to the '2' state, allowing better current flow.

[0172] Based on these four resistance states, signals of levels 0, 1, 2, and 3 can be represented, which can be applied to quaternary semiconductors.

[0173]

[0174] Experimental Example 1-9

[0175] FIG. 11 is a diagram showing the results of a visual memory simulation using the quaternary system of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention.

[0176] In Fig. 11, the state of each cell in the 4X4 array is changed by applying light or voltage to each cell, thereby simulating the simulation of human visual memory. The high resistance state of '0' is indicated in white, and '1' is indicated in red. The low resistance state of the device, '2', is indicated in green, and the state of '3', where light is applied to the state of '2', is indicated in blue.

[0177]

[0178] Experimental Example 1-10

[0179] Pavlov's dog simulation was performed using the quaternary system of Pt / Ga2O3 / Pt memristors.

[0180] FIG. 12 is a diagram showing a Pavlovian puppy simulation using a four-stage resistance state from a high resistance (0,1 state) to a low resistance (2,3) state of a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention.

[0181] When a dog is played music (photoexcitation stimulus) in the conventional high resistance state '0' state with a current of about 70 μA flowing, it switches to the '1' state and a current of about 150 μA (high resistance + photocurrent) flows, causing the dog to sit. In addition, when a whistle (electrical stimulus, set process) is played to a dog in the high resistance state '0' state, it switches to the low resistance state with a current of about 12.5 mA flowing, causing it to switch to the '2' state and drool. When a bell sound (photoexcitation stimulus) is given in this low resistance state, it switches to an even lower low resistance state of about 12.61 mA or more, causing a higher current to flow, causing it to switch to the '3' state and eat.

[0182]

[0183] Experimental Example 1-11

[0184] Figure 13 shows the results of an actual simulation using a Pt / Ga2O3 / Pt memristor according to Example 1 of the present invention.

[0185] In the conventional high resistance state of '0', with a current of about 70 μA flowing, a voltage is applied and the set process switches to the low resistance state of '2', with a current of about 12.5 mA flowing. Afterwards, through the reset process and light stimulation, the high resistance state changes to the state of '1' with additional photocurrent, with a current of about 150 μA flowing. This photocurrent goes through a decay process and returns to the state of '0' again. In this state, through voltage application and light stimulation, it changes to the state of '3' with low resistance and additional photocurrent, with a current of about 12.6 mA or more flowing. In this state, it goes through the reset and decay processes to return to the '0' state again, and actual measurements were performed on the memristor that can express four states over time.

[0186]

[0187] [Example 2]

[0188] Fabrication of bipolar memristors with Ag / Ga2O3 / Pt structures

[0189] Pt was deposited as a lower electrode on a sapphire substrate, and a Ga2O3 thin film was formed thereon, followed by deposition of an Ag upper electrode. To deposit the upper electrode, a photomask or shadow mask was used to form a cylindrical upper electrode, thereby fabricating a bipolar memristor with an Ag / Ga2O3 / Pt structure.

[0190]

[0191] Experimental Example 2-1

[0192] FIG. 14 is a diagram showing (a) resistive switching behavior and current-voltage curves according to injection of various excitation lights of a bipolar memristor having an Ag / Ga2O3 / Pt structure according to Example 2 of the present invention, and (b) photocurrent according to application of ultraviolet, blue, green, and red light.

[0193] Referring to (a) of Fig. 14, when a positive voltage of 0 V is applied to a bipolar memristor of an Ag / Ga2O3 / Pt structure, a set process in which the resistance changes from a high resistance state to a low resistance state, and a reset process in which the resistance changes from a low resistance state to a high resistance state by applying a negative voltage thereafter are shown, and the current-voltage curves according to the injection of various excitation lights are shown.

[0194] When ultraviolet, blue, green, and red light were applied in the resistive switching behavior indicating high resistance and low resistance states, it was confirmed that the photocurrent was formed differently according to the wavelength of each excitation light in the high resistance state and low resistance state, as shown in Fig. 14(b). This result shows that the higher the energy of the excitation light, the more photoexcited carriers are generated, showing a characteristic of showing a high current. This can be expressed as a '0' state when there is no excitation light in the high resistance state, a '1' state which is a higher current state than the '0' state when excited with red light, a '2' state which is a higher current state than the '1' state when excited with green light, a '3' state which is a higher current state than the '2' state when excited with blue light, and a '4' state which is a higher current state than the '3' state when excited with ultraviolet light.

[0195] In addition, through the set process, it shows the '5' state which is a higher current state than the '4' state, and when red light is excited from the '5' state, the '6' state which is a higher current state than the '5' state, when green light is excited, the '7' state which is a higher current state than the '6' state, when blue light is excited, the '8' state which is a higher current state than the '7' state, and when ultraviolet light is excited, the '9' state which is a higher current state than the '8' state can be formed.

[0196] This demonstrates that the photoexcitation current can be controlled by adjusting the energy of the excitation light in the high and low resistance states of the memristor, thereby forming a decimal digit. Furthermore, it implies that various resistance states can be exhibited by controlling the energy and magnitude of the excitation light in the high and low resistance states of the memristor.

[0197]

[0198] Although the embodiments described above have been described with limited drawings, those skilled in the art will appreciate that various technical modifications and variations can be applied based on the above. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0199] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Upper electrode; lower electrode; and A resistance change material layer interposed between the upper electrode and the lower electrode, the resistance state of which changes in response to a voltage applied through the upper electrode and the lower electrode and an incident light signal; including, Memory device.

2. In paragraph 1, The above resistance state is, In response to a voltage applied through the upper electrode and the lower electrode and an incident light signal, the first resistance state to the nth resistance state (n≥3) are included. Memory device.

3. In paragraph 1, It implements a first resistance state by which the voltage is not applied and the optical signal is not incident, a second resistance state by which the voltage is not applied and the optical signal is incident, a third resistance state by which the voltage is applied and the optical signal is not incident, and a fourth resistance state by which the voltage is applied and the optical signal is incident. Memory device.

4. In paragraph 3, The above first resistance state is a high resistance state, The above second resistance state is a state in which current flows by generating photogenerated electron-hole pairs by photogenerated carriers, The above third resistance state is a low resistance state, The above fourth resistance state is a state in which current flows by generating photogenerated electron-hole pairs by photogenerated carriers. Memory device.

5. In paragraph 1, The above optical signal is converted from at least one light selected from the group consisting of an ultraviolet band, an infrared band, and a visible light band. Memory device.

6. In paragraph 5, The photoexcitation current is proportional to the energy and light output of at least one light selected from the group consisting of the ultraviolet band, the infrared band and the visible light band, and exhibits a first resistance state to an nth resistance state (n≥3). Memory device.

7. In paragraph 1, The upper electrode and the lower electrode are, respectively, Containing at least one selected from the group consisting of platinum (Pt), silver (Ag), aluminum (Al), iridium (Ir), gold (Au), ruthenium (Ru), tungsten (W), titanium (Ti), nickel (Ni), hafnium (Hf), iridium oxide (IrO2), ruthenium oxide (RuO2), titanium nitride (TiN), and tantalum nitride (TaN). Memory device.

8. In paragraph 1, The above resistance change material layer is, A conductive channel formed by a metal ion, a point defect, or both, which is capable of electron mobility and is controllable by voltage. Memory device.

9. In paragraph 1, The above resistance change material layer is, Containing at least one selected from the group consisting of metal oxides, metal nitrides, metal sulfides, metal selenides and metal tellurides, Memory device.

10. In paragraph 9, The metal oxide includes at least one selected from the group consisting of CaO, CdO, Co3O5, CoO2, CuO2, MoO3, WO3, Ga2O3, MnO2, ZnO, RuO2, TiO2, SnO2, Nb2O5, NiO, CrO2, Fe3O4, ZrO2, HfO2 and V2O5, The above metal nitride comprises at least one selected from the group consisting of GaN, InN, AlN, Ti2N, Ti3N2, Ti4N3, Zr2N, V2N and Cr2N, The above metal sulfide comprises at least one selected from the group consisting of MoS2, MoS2, WS2, ReS2, NbS2, ZrS2, TiS2, HfS2 and VS2, The above metal selenide comprises at least one selected from the group consisting of MoSe2, WSe2, ReSe2, NbSe2, ZrSe2, TiSe2, HfSe2 or VSe2, The above metal telluride comprises at least one selected from the group consisting of MoTe2, WTe2, ReTe2, NbTe2, ZrTe2, TiTe2, HfTe2 and VTe2. Memory device.

11. In paragraph 1, The above memory element is a memristor, The memristor includes at least one selected from the group consisting of RRAM (Resistive Random Access Memory), PcRAM (Phase change Random Access Memory), MRAM (Magnetic Random Access Memory), FeRAM (Ferroelectric Random Access Memory), and CBRAM (Conductive Bridging Random Access Memory). Memory device.

12. In a method of operating a memory device including an upper electrode; a lower electrode; and a resistance change material layer interposed between the upper electrode and the lower electrode, A step of selectively applying voltage through the upper electrode and the lower electrode; A step of selectively incident an optical signal onto the resistance change material layer; and A step of changing the resistance state of the resistance change material layer in response to a voltage applied through the upper electrode and the lower electrode and an incident light signal. including, How memory devices work.

13. In paragraph 12, The step of changing the resistance state of the above resistance change material layer is: In response to a voltage applied through the upper electrode and the lower electrode and an incident light signal, a first resistance state to an nth resistance state (n≥3) are implemented. How memory devices work.

14. In paragraph 12, The step of changing the resistance state of the above resistance change material layer is: A step of implementing the resistance state of the resistance change material layer in any one of a first resistance state in which the voltage is not applied and the optical signal is not incident, a second resistance state in which the voltage is not applied and the optical signal is incident, a third resistance state in which the voltage is applied and the optical signal is not incident, or a fourth resistance state in which the voltage is applied and the optical signal is incident. How memory devices work.

15. In paragraph 14, The above first resistance state is a high resistance state, The above second resistance state is a state in which current flows by generating photogenerated electron-hole pairs by photogenerated carriers, The above third resistance state is a low resistance state, The above fourth resistance state is a state in which current flows by generating photogenerated electron-hole pairs by photogenerated carriers. How memory devices work.

16. In paragraph 12, The step of changing the resistance state of the above resistance change material layer is: A method of changing the resistance state of a resistance change material layer by an optical signal converted from at least one light selected from the group consisting of an ultraviolet band, an infrared band, and a visible light band. How memory devices work.

17. In paragraph 16, The photoexcitation current is proportional to the energy and light output of at least one light selected from the group consisting of the ultraviolet band, the infrared band and the visible light band, and changes from the first resistance state to the nth resistance state (n≥3). How memory devices work.

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