Systems and methods to improve the jitter and time walk of integrated constant fraction discriminators

Abstract

Disclosed herein is an analog front-end (AFE) integrated circuit (IC) developed for interfacing with solid state ionizing radiation detectors, providing accurate amplitude and time-of-arrival measurements. The analogue front-end integrated circuit, capable of operating as a low-noise high-gain amplifier or a high-linearity low-gain amplifier allowing accurate time of arrival measurements. The circuit includes an array of one or more channels, wherein each channel includes: a low noise trans-impedance amplifier, a capacitor attenuator, a variable gain differential amplifier, a differential constant fraction discriminator, and output drivers.

Description

SYSTEMS AND METHODS TO IMPROVE THE JITTER AND TIME WALK OF INTEGRATED CONSTANT FRACTION DISCRIMINATORSGOVERNMENT SUPPORT STATEMENT

[0001] This invention was made with government support under grant number DE-AC02- 98CH10886 awarded by the Department of Energy. The government has certain rights in the invention.CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to, and benefit of, U.S. Provisional Patent Application No. 63 / 519,400, filed August 14, 2023, entitled “System and Methods to Improve the Jitter and Time Walk of Integrated Constant Fraction Discriminators,” which is incorporated by reference herein in its entirety.BACKGROUND

[0003] Accurate measurements of the energy and time-of-arrival of photons, particles, or ionizing radiation are important to either help identify individual particles or to enhance spatial and temporal resolution in many systems. Applications such as Light Detection and Ranging (LiDAR), positron emission tomography (PET), high energy particle colliders and X-ray imaging constantly push for improved energy and timing resolution [1-4], In the field of radiation transducers, many detector types (e.g., gas-filled detectors, scintillators or solid-state detectors) are used to sense ionizing radiation [5-7], In general, radiation detectors convert ionizing radiation into electric charge, electric current, or light signals that can then be conditioned and measured using readout electronics. Solid state detectors, in contrast to gas and scintillator detectors, have small form-factors that enable high packing density and large channel counts, while also reducing overall readout system power consumption. Notably, solid state detectors rely on electron-hole pair production resulting from the interaction between transiting ionizing particles and the detector material. Hence, the resulting charge drifts, due to the applied electric field across the detector electrodes and gets collected by the readout analog front-end (AFE) electronics. The readout circuits commonly incorporate a front-end configuration consisting of a low noise pre-amplifier followed by a pulse shaping filter and timing discriminator.SUMMARY

[0004] Disclosed herein is a radiation-hardened analog front-end (AFE) integrated circuit (IC) developed for interfacing with solid state ionizing radiation detectors, providing accurate amplitude and time-of-arrival measurements.

[0005] In some aspects, an analogue front-end integrated circuit, capable of operating as a low- noise high-gain amplifier or a high-linearity low-gain amplifier allowing accurate time of arrival measurements, is disclosed. The circuit includes an array of one or more channels, wherein each channel includes: a low noise trans-impedance amplifier, a capacitor attenuator, a variable gain differential amplifier, a differential constant fraction discriminator, and output drivers.

[0006] In some aspects, the low noise trans-impedance amplifier is optimized for minimal jitter and amplitude noise.

[0007] In some aspects, each channel can be configured to use either the low noise trans- impedance amplifier to measure low range radiation, or the capacitor attenuator to measure high range radiation.

[0008] In some aspects, each channel includes a first variable gain differential amplifier following the low noise trans-impedance amplifier and a second variable gain differential amplifier following the capacitor attenuator.

[0009] In some aspects, the differential constant fraction discriminator and output drivers follow the first and the second variable gain differential amplifier.

[0010] In some aspects, the low noise trans-impedance amplifier accepts both positive and negative input charge signals.

[0011] In some aspects, the variable gain differential amplifier is configured to rectify an output signal polarity according to a programable set of switches.

[0012] In some aspects, the differential constant fraction discriminator includes fully differential signaling schemes.

[0013] In some aspects, the differential constant fraction discriminator includes an all-pass filter circuit to provide delay and pulse shaping and a zero-crossing detector to minimize time walk.

[0014] In some aspects, the zero-crossing detector (ZCD) includes a cascade of at least three amplifiers, wherein all amplifiers except a final amplifier are low gain and high bandwidth amplifiers and the final amplifier is a high gain rail-to-rail amplifier.

[0015] In some aspects, the at least three amplifiers of the ZCD include digitally controlled capacitors to finely tune both bandwidth and slew-rate to achieve balance at which phase lead due to compression cancel out phase lag due to limited slew rate to attain a minimal time walk.

[0016] In some aspects, the cascade of at least three amplifiers includes five amplifiers.

[0017] In some aspects, the differential constant fraction discriminator further includes a hysteretic differential difference amplifier based arming comparator, wherein the hysteretic differential difference amplifier based arming comparator is used to propagate a ZCD output only if an input pulse is greater than a preset programmable reference level.

[0018] In some aspects, the circuit includes an array of four channels.

[0019] In some aspects, the output drivers are analogue and digital output drivers.

[0020] In some aspects, the circuit is preceded by a diamond detector.

[0021] In some aspects, the circuit described herein relates to a photon detector including the circuit.

[0022] In some aspects, the circuit described herein relates to a high-energy particle detector including the circuit.

[0023] In some aspects, the circuit described herein relates to a radiation detector including the circuit.BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Fig. 1 shows typical radiation detector readout electronic signal chain.

[0025] Figs. 2A-2B shows baseline recovery in radiation detector front end electronics for (Fig. 2A) complete baseline recovery and (Fig. 2B) charge pile up in slow amplifier-sharper front-end.

[0026] Figs. 3A-3C show two sources of time pick-off errors: jitter (Fig. 3A) and time-walk (Fig. 3B); and the CFD concept employed to mitigate time-walk (Fig. 3C)

[0027] Fig. 4 shows the location of the right half of the BCM detector with close radial proximity to the LHC beam pipe and separation from the collision point of the ATLAS detector showing the relationship in time between the analog output pulse for both background (beam leakage) and collision radiation.

[0028] Fig. 5 show a 5 mm x 5mm pCVD diamond pad detector segmented into four pad elements of varying areas, and related AFE architecture highlighting the eight channels of LUMI / ABORT, biasing, control circuits, and power segmentation with each supply domain represented by a separate red rectangle.

[0029] Fig. 6 shows a block diagram of the complete LUMI / ABORT readout channel, showing the amplifiers, CFD, and output drivers.

[0030] Fig. 7 shows a block diagram outlining the major time pick-off error contributors in a conventional radiation detector system.

[0031] Figs. 8A-8B show schematics of front-end amplifier (preamplifier) core (Fig. 8A) and second-stage differential VGA (Fig. 8B), indicating transistors’ W / L in pm.

[0032] Figs. 9A-9D show extracted simulation results for LUMI amplifiers showing: the voltage gain (Fig. 9A) and the input referred noise of the LN-TIA (Fig. 9B). Additionally shown are transient waveforms at the output of the LN-TIA with swept input charge (Fig. 9C) and the corresponding rectified voltage at the output of the VGA (Fig. 9D).

[0033] Figs. 10A-10D show the transfer function of the three candidates for the analog delay implementations: buffered cascade RC (Fig. 10A); 2ndorder butterworth LPF (Fig. 10B); and cascade first-order all-pass filter (Fig 10C). Additionally shown are the comparison criteria using the slope and noise degradation (Fig. 10D).

[0034] Fig. 11 shows the simulated normalization CFD jitter for different filters typologies vs the filter’s time constant.

[0035] Figs. 12A-12B show a schematic of the proposed OpAmp-RC all-pass filter unit (Fig. 12A) and the simulated waveforms for two cascaded units with delay programmability (Fig. 12B).

[0036] Figs. 13A-13D show the ZCD top level showing the five stages and the offset cancellation loop (Fig. 13 A); the first stage amplifier with calibration inputs (Fig. 13B); subsequent amplifiers 2-4 (Fig. 13C); and the fifth stage rail-to-rail output amplifier (Fig. 13D).

[0037] Figs. 14A-14B show transient simulation results for ZCD circuit showin: the differential input bipolar pulse with 6 ps time-walk (Fig. 14A) and the output digital signal with 10.4 ps time-walk (Fig. 14B).

[0038] Fig. 15 shows Multiple overlaid waveforms for the simulated ZCD input and output with transient noise.

[0039] Figs. 16A-16C show the hysteretic differential difference amplifier used in the arming comparator, indicating transistors’ W / L in pm (Fig. 16A); the 8-bit segmented reference DAC (Fig. 16B); and the output logic used to combine ZCD and arming outputs, showing a problematic marginal input being gated by the flip-flop (Fig. 16C).

[0040] Figs. 17A-17D show chip top level layouts for the first (Fig. 17A) and the second (Fig. 17B) tapeouts showing the major system components and the corresponding chip micrographs for the first (Fig. 17C) and the second (Fig.17D) tapeouts.

[0041] Figs. 18A-18B show persistence plot for the measured pulse response with 1 fC input charge (Fig. 18 A) and measured output noise waveform and histogram (Fig. 18B).

[0042] Fig. 19 shows gain and ENC variations across 43 measured channels.

[0043] Fig. 20 shows simulated and measured jitter versus input charge amplitude with no sensor capacitance.

[0044] Fig. 21 shows Measured relative time-of-arrival versus input charge amplitude with no sensor capacitance, showing ±6 ps of time-walk for 30 dB input range ( 2p \p-p).

[0045] Fig. 22 shows AFE gain across eight channels measured up to 225 Mrad TID.

[0046] Fig. 23 shows AFE noise across eight channels measured up to 225 Mrad TID.

[0047] Fig. 24 shows pulse height distribution of the AFE amplifier output when combined with a 1.8 pF pCVD diamond detector, operated at +700V, subjected to 120 GeV pions at the CERN SPS providing a SNR > 15: 1.DETAILED DESCRIPTION

[0048] Listing of nomenclature:Beam Condition Monitor (BCM)LHC beam luminosity (LUMI)LHC beam abort (ABORT)Large Hadron Collider (LHC) variable gain amplifier (VGA)analog front-end (AFE) trans-impedance amplifier (TIA) low-noise trans-impedance amplifier (LN-TIA) constant fraction discriminator (CFD) zero-crossing detector (ZCD) operational transconductance amplifier (OTA)Complementary Metal-Oxide-Semiconductor (CMOS) equivalent noise charge (ENC) charge sensitive preamplifier (CSA)Time to Digital Converter (TCD) amplifier-shaper-discriminator (ASD) application specific integrated circuit (ASIC) radiation hardening by design (RHBD) single event transient (SET) single event upsets (SEU)Minimum Ionizing Particles (MIP) digital-to-analog converter DAC common mode feedback circuits (CMFB) differential difference amplifier (DDA) current mode logic (CML) operational amplifiers (opamps)

[0049] A typical solid state amplifier-shaper-discriminator (ASD) readout electronic chain is shown in Fig. 1. The signal chain begins with a detector, such as diamond or silicon, which produces nanosecond scale current pulses resulting from interaction between the ionization radiation and the detector. Following the detector, a low noise charge sensitive preamplifier (CSA) is commonly used. The CSA, utilizing a feedback capacitor, integrates the electrical current impulse, generated by the detector, to produce a voltage step. This voltagestep is subsequently converted, by the pulse shaper, to a voltage pulse Vpuise, as illustrated in Fig. 1. The pulse shaping block can also provide noise filtration to minimize the equivalent noise charge (ENC) [8, 9], thus improving the amplitude measurement precision. However, this filtration may degrade the rise time of the signal, and hence, the time-of- arrival measurement precision. Furthermore, if the repetition rate of the incident radiation is faster than the baseline restoration time-constant, the shaper may introduce charge accumulation, or pile-up, as shown in Fig 2. In this situation, the readout system will be unable to accurately characterize the sequence of events over time. Therefore, the design of the amplifier and shaper response time is of upmost importance in the AFE and must be carefully optimized for each application. For systems that require an infrequent or averaged update of the incident radiation, an accurate amplitude measurement is of primary concern. In these scenarios, a high-precision, low- noise measurement of the charge collected by the detector is required, regardless of the pulse rise time [4, 9, 10], Hence, pulse rise times can be slow, and shaping times are chosen to achieve optimal amplitude resolution. In contrast, for highspeed applications that require simultaneous amplitude and time-of-arrival measurement, a high bandwidth readout amplifier is needed to minimize the timing measurement error and to ensure a fast retum-to-baseline. In this case, the feedback network in the pre-amplifier can be adjusted from the purely capacitive CSA to a resistive trans-impedance amplifier (TIA) configuration. Assuming a reasonably small feedback resistor, the TIA configuration provides a shaped fast baseline restoration capable of meeting system charge- to-voltage conversion and noise goals. Furthermore, a TIA maximizes the achievable bandwidth and hence minimizes timing jitter at the expense of less than optimal ENC [11, 12],

[0050] After amplifying and shaping the detected signal, a discriminator is needed to provide a timing trigger signal. There- after, the relative timing between this trigger signal and a synchronous system clock is measured using a Time to Digital Converter (TDC). Commonly, a leading edge discriminator is used due to its simplicity, as it provides the trigger signal when the received signal voltage crosses a fixed threshold, Vth

[0013] , Note that, depending on the detector material, thickness, and biasing voltage, it may take up to a few nanoseconds to completely deplete the charge resulting from the incident radiation. Hence, it is useful in this context to define the time- of-arrival as the instance of time that the ionizing particle traverse through the detector material and produces the initial current ramp that crosses the threshold. Figs. 3 A-3B highlight two potential sources of timing errors. First, pulses with fixed amplitude and fixed relative timing encounter random jitter due to circuit noise, as illustrated in Fig.3 A. Second, signals with different amplitudes have different Vth crossing instances, hence misleading the trigger time, as shown in Fig. 3B. This phenomenon, known as time-walk, is used to describe the amplitude influenced timing error

[0014] , To mitigate time-walk error, a constant fraction discriminator (CFD) is utilized

[0015] , Here, a CFD is able to provide an accurate timing signal based on a fixed percentage of the pulse peak amplitude rather than a fixed absolute threshold level.

[0051] A block diagram illustrating the operation of a CFD is shown in Fig. 3C. The received input signal is split into an attenuated version and a delayed version. Subtracting the former from the latter produces a bipolar signal that has an undershoot and overshoot, with the solid red lines indicating the delayed and attenuated signals, and the dotted blue line indicating the resulting bipolar signal. Note the independence of the zero crossing time of the bipolar signal to the input signal amplitude, indicating, ideally, the absence of any time-walk. Subsequently, a zero-crossing detector (ZCD) is used to detect the zero crossing of the bipolar signal and provide an accurate trigger. Note that the output signal from the ZCD is gated by the output of a fixed threshold comparator, also known as the arming comparator. This gating scheme is used to prevent the CFD from false triggering due to random noise and to provide control over the minimum permissible pulse amplitude. Both the analog delay and the ZCD are essential components that influence both the time-jitter and time-walk of the CFD. When the CFD was first introduced

[0015] , a transmission line cable or printable circuit board trace were used to realize the analog delay function. In recent integrated CFD iterations, however, the delay line is replaced by either passive or active delay elements [16, 17], while the ZCD is typically realized by a fast comparator with particular emphasis upon the offset voltage, as it can introduce a large time-walk component

[0018] ,

[0052] Described herein is an analysis and design of a multi-channel, amplitude, and time pick-off AFE that is slated for use in the next generation ATLAS Beam Condition Monitor (BCM’). The AFE is designed to interface with either segmented diamond or silicon detectors having a wide range of segment sizes to extend the total system dynamic range, the proposed fully-differential CFD, detailing a new all-pass filter as an analog delay line circuit, a ZCD with a proposed scheme that provides a minimal time-walk, and a fully differential arming comparator.

[0053] In an exemplary aspect, an analogue front-end integrated circuit, configured to operate as a low-noise high-gain amplifier or a high-linearity low-gain amplifier allowing accurate time ofarrival measurements is disclosed. The circuit includes an array of one or more channels, wherein each channel includes a low noise trans-impedance amplifier, a capacitor attenuator, a variable gain differential amplifier, a differential constant fraction discriminator, and output drivers.

[0054] In some aspects, the low noise trans-impedance amplifier is optimized for minimal jitter and amplitude noise.

[0055] In some aspects, each channel includes a first variable gain differential amplifier following the low noise trans-impedance amplifier and a second variable gain differential amplifier following the capacitor attenuator. In some aspects, the differential constant fraction discriminator and output drivers follow the first and the second variable gain differential amplifier.

[0056] In some aspects, the low noise trans-impedance amplifier accepts both positive and negative input charge signals.

[0057] In some aspects, the variable gain differential amplifier is configured to rectify an output signal polarity according to a programable set of switches.

[0058] In some aspects, the differential constant fraction discriminator includes fully differential signaling schemes. In some aspects, the differential constant fraction discriminator includes an all-pass filter circuit to provide delay and pulse shaping and a zero-crossing detector to minimize time walk.

[0059] In some aspects, the zero-crossing detector (ZCD) includes a cascade of at least three amplifiers, wherein all amplifiers except a final amplifier are low gain and high bandwidth amplifiers and the final amplifier is a high gain rail-to-rail amplifier. In some aspects, the at least three amplifiers of the ZCD include digitally controlled capacitors to finely tune both bandwidth and slew-rate to achieve balance at which phase lead due to compression cancel out phase lag due to limited slew rate to attain a minimal time walk. For example, the cascade of at least three amplifiers includes three, four, five, six, or seven amplifiers

[0060] In some aspects, the differential constant fraction discriminator further includes a hysteretic differential difference amplifier based arming comparator, wherein the hysteretic differential difference amplifier based arming comparator is used to propagate a ZCD output only if an input pulse is greater than a preset programmable reference level.

[0061] In some aspects, the output drivers are analogue and digital output drivers.

[0062] In some aspects, the circuit is preceded by a diamond detector.

[0063] In some aspects, the circuit includes an array of four channels.

[0064] It is contemplated that the circuit may be used in a photon detector, in a high-energy particle detector, or in a radiation detector.EXAMPLE

[0065] In this section, the implemented AFE circuit architecture and its planned application environment are detailed. Additionally, a discussion of the individual noise sources that limit the accuracy of the amplitude and time-of-arrival measurements are discussed.ATLAS BEAM CONDITION MONITOR

[0066] Targeting high energy physics (HEP) experiments, the Large Hadron Collider (LHC) is a particle accelerator that accelerates proton bunches to nearly the speed of light and creates controlled collisions of these bunches, at the rate of 40 MHz

[0019] , The ATLAS detector is constructed to analyze the outcome of the aforementioned collisions

[0020] , Provided that the LHC has over 320 MJ of total energy stored in its circulating beams, an immediate detection of any unexpected beam trajectory deviation is crucial to protect the system electronics. To mitigate proton beam trajectory deviation, the BCM system raises an abort flag prompting the LHC to dump the circulating protons into safe external absorbers in order to protect the delicate detector components from severe radiation damage.

[0067] The current BCM uses polycrystalline Chemical Vapor Deposition (pCVD) diamond radiation detectors to continuously monitor the losses from the proton beam as well as the products of the collisions. Diamond detectors, with their intrinsic radiation tolerance, low electric permittivity, low electric conductivity, and high thermal conductivity

[0021] , are ideal for use in this application. Specifically, radiation tolerance and thermal conductivity improve the life span of the detector, while low electric permittivity and conductivity minimize both the capacitance and leakage current to enable fast real-time non-integrating monitoring of collisions

[0022] ,

[0068] In the LHC, the colliding proton packets are separated by a 25 ns interval. To distinguish between background radiation leaked directly from the proton beam and radiation detected from collisions, an equal number of BCM modules are positioned symmetrically on both sides of the collision point, as discussed in

[0023] , Placement of each half of the BCMdetector, at a distance of 1.84 m from the collision point, ensures a 12.5 ns separation between the background and collision signals, as illustrated in Fig. 4. This arrangement imposes a constraint on the BCM front-end electronic baseline recovery time to be less than 12.5 ns. While the original BCM modules are satisfying the recovery time criteria

[0024] , they suffer from two significant limitations. First, the output signal of each BCM module, which is transmitted through 14 m coaxial cables for post-processing, requires a high-mass and spatial occupancy that prohibits high channel counts. Second, the discrete radiation intolerant commercial components of the BCM module amplifier mandate placement of the circuitry within a shielded enclosure, creating a physical separation from the diamond sensor. This separation increases the interface parasitic capacitance and consequently limits the system’s achievable ENC. To address these limitations, the upgraded BCM module, also known as BCM prime (BCM’), utilizes the AFE named "Calypso" (detailed in this study) to deliver digital outputs of both the signal amplitude and time pick- off. Unlike the current generation BCM module amplifier, the Calypso is radiation-tolerant, possesses an improved amplitude and timing resolution with a -50% reduction in ENC, and has multi-channel per chip integration capability. To address the high-mass readout cabling of the existing BCM, the amplitude and time pick-off from Calypso are digitized and transmitted serially through the ATLAS readout chain using another application specific integrated circuit (ASIC) developed at CERN

[0025] , Moreover, Calypso is intentionally over- designed for a finer time-of-arrival precision than required by the BCM, enabling it to be used in potential future applications that demand sub- 100 picosecond time accuracy.SYSTEM ARCHITECTURE

[0069] Figure 5B illustrates the AFE architecture comprising eight readout channels, of which four high gain, 130 mV / fC, channels are used for monitoring the LHC beam luminosity (LUMI). The other four channels have reduced gain, 3 / / V / fC, and are used to capture very high radiation intensities in order to signal a potential LHC beam abort (ABORT). Both channel types are also equipped with accurate time-of-arrival measurement capability. Each channel of the AFE can be configured for either the LUMI or ABORT functionality providing a total of four active channels at a time. The AFE also contains common biasing circuitry and an / 2C interface which uses radiation hardening by design (RHBD) techniques to reduce the impact of single event transient (SET) events and single event upsets (SEU).

[0070] Figure 6 illustrates the block diagram of the readout channel. The readout circuit employs a single-ended low-noise TIA (LN-TIA), followed by a second stage variable gain amplifier(VGA) with differential outputs. To accommodate positive or negative biasing for the bottom electrode of the diamond detector, the LN-TIA accepts both positive and negative input charge signals. This is an important feature in this application since some diamond detectors exhibit superior performance for one polarity over the other. This dual polarity, in turn, imposes constraints on the linear range of the amplifier chain. The Calypso AFE, however, circumvents these constraints by converting the balance of the signal chain after the VGA to fully differential. This also results in increasing the common mode rejection and reducing the amount of pick-up noise. To permit a direct measurement of the analog signal from the VGA, a buffer is included and used to transmit the VGA signal to an auxiliary output optimized to drive a 50 Q load.

[0071] A bipartite strategy between the detector and AFE is adopted to enable the detection of the widest possible dynamic range of radiation intensities. First, the diamond pad detector is segmented into separate pad regions with different areas, as shown in Fig. 5. Note that the large area pads are used to detect low radiation intensities, while the small pads are used to detect high radiation intensities. Since the probability of radiation interaction is proportional to the detector area, in the small area pads for example, there will be less of a chance for saturating the amplifier during periods of high radiation intensity. The second strategy leverages circuit techniques to improve the linearity of the amplifier chain, thus ensuring that amplifiers connected to larger area pads do not saturate until an adequately large signal is collected by amplifiers connected to smaller area pads. Hence, a sufficient overlap of linear detection range is achieved by selecting an appropriate range of pad sizes.

[0072] The constant fraction discriminator, shown in the red dotted box in Fig. 6, follows the differential VGA and is comprised of three major blocks: a pulse shaper, a zero-crossing detector, and an arming comparator. The pulse shaping element, which is implemented using the analog delay and the subtracting resistors Ri and Rz, subtracts a fraction of the VGA input signal from a delayed version of the VGA signal, producing an output pulse with a bipolar shape, as shown in Fig. ID. The zero crossing of this bipolar waveform is monitored by the subsequent zero-crossing detector, which produces a corresponding rising edge after each time the zero level is crossed. In this work, the zero-crossing detector features an offset cancellation loop to minimize offset induced time-walk. Finally, the arming comparator evaluates the input signal amplitude continuously against a voltage reference threshold set using a programmable 8- bit digital-to-analog converter (DAC). Below this threshold, the gated CFD output is disabled,effectively rejecting events, or noise, with an input charge lower than the arming comparator threshold.

[0073] Under the nominal operating conditions in ATLAS, the BCM’ is expected to sense radiation levels of 10’s to 100’s of Minimum Ionizing Particles (MIP) / cm2

[0026] , Should the beam trajectory deviates, the levels of radiation, for the beam to be aborted, has an estimate between 25,000 and 7,500,000 MIP / cm2, which is six orders of magnitude larger than radiation under nominal conditions. Hence, it is not feasible to cover the entire range with the same frontend amplifier circuit. Therefore, the AFE ABORT channel is designed to tolerate these high signal levels and alert the LHC operators in the event a beam leakage is detected. To tolerate and capture the high signal levels present during a concerning beam leakage scenario, the AFE ABORT channel incorporates a calibrated capacitor attenuator, in place of the LN-TIA. Following this attenuator, the balance of the signal chain is identical to the LUMI readout channels.

[0074] The first version of Calypso employed a single supply domain for the entire AFE. This scheme resulted in an immense inter-channel coupling, and sporadic instability due to intrachannel feedback from output driver to the LN-TIA. To address these issues in the following versions, dedicated front end analog supply pads were provided for the LN-TIA of each channel. This separated powering structure mitigates inter-channel coupling and feedback by employing the supply bond wires as filters. A second analog supply rail is shared among the four channels to power the VGAs and CFDs. This common analog supply rail is connected through pads on opposing sides of the AFE die to minimize the resistance of the power distribution network. Finally, a third dedicated series of supply pads for each channel is provided to the digital and analog output drivers to isolate activity on these high current drivers from the more sensitive AFE circuitry. Figure 5B illustrates the described supply domain segmentation with each domain represented in a separate red rectangle.SOURCES OF TIMING ERRORS

[0075] In addition to both jitter and time-walk, discussed in Section I, other sources of error can impact the precision of the time pick-off measurements in radiation detector systems, as shown in Fig. 7. Assuming the error sources are all independent, the overall root mean square error (RMS) of the measured time can be calculated as

[0027] :^total0)

[0076] where atotai is the RMS error in the measured time of signal arrival, oiandau is the RMS error due to fluctuations in the detector charge collected for each radiation event, GTDC and odock are RMS errors caused by the backend electronics, i.e. the TDC and the clock generation and distribution circuits. Note that GTDC and Odock are typically small compared to errors originating from the radiation detector and front- end electronic sources

[0028] , The remaining two components, ajuter and c vaik, are timing errors introduced by the frontend electronics. Whereas cjitter is the fixed amplitude random jitter associated with the pre-amplifier and shaping circuit noise, <7waik is the time-walk induced by the time pick-off circuitry assuming an ideal input signal that scales linearly with radiation amplitude . It is important to note that the CFD design has a maj or impact on (Jjitter and Owalk. A detailed analysis of the CFD impact, along with other aspects of timing accuracy, is presented in Section IV. While the previous discussion assumes that the detector receives particles with a unique time-of-arrival, which is the most common scenario, it is worth noting that the detector may occasionally receive multiple ionizing particles with a temporal separation shorter than the AFE rise and return to baseline, leading to pile-up.READOUT AMPLIFIER DESIGN

[0077] The proposed front-end preamplifier, depicted in Fig. 8A, is realized with a single ended input, as imposed by the single- ended diamond detector. As a feedback capacitor will always limit the achievable bandwidth, a resistor-feedback TIA, rather than a CSA with a feedback capacitor, is used to achieve the widest possible gain bandwidth and improve the jitter performance. The amplifier topology utilizes a common source amplifier (Ml) with cascade (M2) and a current bleeding branch (M5 and M6) to increase the impedance of the output branch (M3 and M4), and hence enhance the gain. Given a diamond pixel capacitance range from 0.25 pF to 4 pF, the common source device (Ml) is optimized for a 2 pF median sensor capacitance using the method in [9, 29], To ensure a fast and sharp rise time, Ml is biased at a nominal current of 14 mA. Note that in order to meet the speed requirement without overpowering the input gate capacitance, Ml is implemented with minimum length and incurs a total gate capacitance of 0.39 pF. To reduce the devices’ noise contribution, the transconductance of M5 and M6 is minimized by biasing them at the highest possible overdrive voltage allowed by the voltage supply. Transistors M3 and M4, however, are biased at a moderate overdrive voltage for a compromise between noise and output swing. Such a large swing is necessary to cover the wide dynamic range of the segmented diamond sensor.Additionally, a symmetric output swing is targeted covering both positive and negative inputcharges. The feedback resistor RFB, which is a core constituent of the TIA topology, also provides the proper DC biasing for the input transistor Ml through the negative feedback.

[0078] The TIA is followed by a single-ended to differential VGA, as shown in Fig. 8B. This second-stage amplifier is based on a current mirror operational transconductance amplifier (OTA) topology, providing a large output swing with a degenerated input pair (Ml and M2) used to enhance the input linearity. The tail current source is evenly divided between M9 and MIO such that the degeneration resistor, Rdegdoes not drop the DC voltage, allowing for low input common mode voltage. To achieve gain control, a programmable differential load resistor, Rioad, is used. Switches S1-S4, are programmatically configured to maintain the output pulse polarity regardless of the input charge polarity, by either conducting the branch current to the current mirrors M3 / M4 (blue connections) or to flip their polarity (red connections).

[0079] The VGA provides 10-13 dB gain programmable with 1 dB granularity, and its differential output compresses by 1 dB at 750 mV output pulse-peak voltage. Additionally, the input differential pair biasing current (M9 / 10) is 1 mA, while the output branch (M8 / M7) uses 2 mA, with an additional 0.5 mA consumed in the common mode feedback circuits (CMFB) for a total of 3.5 mA. Figure 9 shows the AC and transient, parasitic extracted, simulation results for both the LN-TIA and the VGA. In this simulation, a rectangular current pulse of 500 ps width is used to model the input signal, with the pulse height adjusted according to the total integrated test charge.CONSTANT FRACTION DISCRIMINATOR

[0080] The CFD was introduced to reduce the owaik component in equation (1), which is an amplitude-dependent error impacting the overall timing measurement uncertainty a total

[0015] , Design considerations for the three circuit components used to implement the integrated CFD are discussed in the following subsections.ANALOG DELAY AND PULSE SHAPING CIRCUIT

[0081] An integrated analog delay commonly employs a filter to mimic the functionality of an ideal transmission line delay. In the proposed design, it is plausible, given the available power and area, to incorporate two operational amplifiers (opamps) in addition to their associated passive components to implement this filter. Accordingly, three alternative filters, with similar complexity that could be implemented using two opamps, were considered for the delay. The first is two cascaded F'-order passive RC filters with buffers inserted after each section, as proposed in

[0017] , This topology showed an improved jitter performance compared to unbuffered RCsections. The second alternative is a 2""'-order butterworth low-pass filter, while the third option is a cascade of two identical P' order all-pass filters. Note that the use of an all-pass filter was proposed in

[0030] , yet the author settled to use a passive Gaussian low pass filter for simplicity. For benchmarking, a fourth implementation using four cascaded passive RC sections is included in the comparison given its relative simplicity.

[0082] Figures 10A-10C describe the transfer function of the active alternatives, while Fig. 10D shows the comparison criteria by looking at the deterioration in signal slope and noise at the output, since this can provide a good estimate for the jitter impact. Here, simulations were undertaken using ideal filters to compare jitter performance of these alternatives. It is noted that the input to each filter is driven from the LN-TIA / VGA.

[0083] Figure 11A shows the simulated output jitter, normalized by the minimum input jitter, of the shaped pulse, with the x-axis denoting the filters’ time constant r normalized to the rise time of the input pulse. Here, the use of a butter- worth filter showed an improved jitter performance compared to both buffered and passive RC sections delay realization. Nonetheless, the all-pass filter implementation showed the best performance as far as the jitter is concerned, with a remarkable 20% jitter reduction over the butterworth low pass filter.

[0084] Based on the aforementioned results, a first order all-pass filter using an opamp-RC configuration (Fig. 12A) is adopted in this work. Notably, the absence of large swings at the input nodes of the opamp in this topology ensures an improved linearity. The complete delay line circuit consists of two cascaded units with re-configurable fifteen different delay settings achieved through programmable capacitors for flexibility. The filter’s opamp, shown in Fig. 12A, is implemented using a modified version of the same circuit used for the VGA (Fig. 8B), with omitted Rioad and Rdeg. Figure 12B depicts the transient simulation results, across different delay settings, for the all-pass filter, achieving delays with fine resolution between 0.7 and 1.7 ns.

[0085] Finally, the CFD bipolar pulse shape is derived by the resistor interpolation of the pulse and its delayed version, as in Fig. 6. The cross coupled signal is a substitution for the negative sign, capitalizing the differential implementation of the CFD, while the attenuation is determined by the ratio of ^l / ?2 . This bipolar waveform is subsequently passed to a zero-crossing detector to accurately set the CFD timing flag.ZERO-C ROSSING DETECTOR (ZCD)

[0086] As discussed previously, the ZCD converts the input bipolar waveform to a rail-to-rail digital signal. Ideally, the rising edge of this digital signal has a fixed timing association with the crossing instant of the input that is independent of the pulse amplitude. To achieve this behavior, a large gain and bandwidth in the ZCD is required. A cascade of low gain amplifiers can be used to simultaneously achieve a large gain and bandwidth, thus managing the trade-off between gain and bandwidth in a single stage amplifier. The top-level schematic of the ZCD is shown in Fig. 13 A, comprising four CML amplifiers followed by a high gain comparator. Figure 13B depicts the schematic of the first stage amplifier with the auxiliary calibration inputs M3 / M4, while the following three identical stages are shown in Fig. 13C. Finally, the laststage comparator is shown in Fig. 13D, which is based on a current mirror OTA with two rail-to- rail outputs and uses Rz and Cz to improve the output speed by introducing a peaking in its frequency response.

[0087] Offset cancellation is implemented with a low frequency negative feedback loop. Here, the positive and negative outputs from the ZCD are separately averaged by Real and Ccai, as shown in Fig. 13 A, then subtracted from the input based on the feedback factor, as determined by the ratio of M5:M0 in Fig. 13C. This scheme ensures an offset free balanced steady state. Note that the cut- off frequency of the Rcat / Ccai filter is set a few orders of magnitude lower than the bandwidth of the amplifiers to ensure a stable operation. Ultimately, consecutive bipolar CFD pulses, with their non-zero average, may cause a drift for the balanced calibration voltages. To prevent such a drift, the feedback loop is opened during the presence of an active signal, indicated by the arming comparator output, thus maintaining the proper calibration voltages on the capacitors.

[0088] Finally, the simulation results for the ZCD are presented in Figs. 14A-14B. The input signal, depicted in Fig. 14A, exhibits a time-walk of approximately 6 ps, due to nonidealities in preceding circuits. In Fig. 14B, the differential digital output waveform is shown, indicating minimal time-walk degradation compared to the input.ARMING COMPARATOR

[0089] The purpose of the arming comparator is to limit undesirable random ZCD switching caused by input noise. As shown in Fig. 15, the undesirable ZCD behavior is evident in the presence of a noisy signal, resulting in many false output transitions. To prevent this from happening, the arming comparator is designed to propagate the ZCD output only if the input pulse is greater than a preset reference level, thus ensuring that the output triggers correspond toan actual detected pulse. An eight-bit segmented resistor string Digital to Analog Converter (DAC) (Fig. 16B) generates the arming comparator differential threshold reference. Note that the DAC output range is divided into sub 1 mV increments, corresponding to a marginal increase of the sensor input charge of less than 100 electrons per step.

[0090] The arming amplifier is designed as a hysteretic differential difference amplifier (DDA) to compare the differential input pulse, from the VGA, with the differential reference, from the DAC, as shown in the channel block diagram in Fig. 6. The schematic of the DDA is shown in Fig. 16A, where the input and the reference voltages are converted to current signals and then subtracted from one another by the matched M3 / M4 and M5 / M6 differential pairs. The resulting current difference is then converted back to voltage at the output stage. The hysteresis function is implemented by effectively lowering the reference level when the output toggles high by opening the So switch that normally shorts out the degeneration resistor Rhyst.

[0091] Ultimately, a flip-flop is used to combine the ZCD and arming comparator outputs. Figure 16C shows an abstracted schematic for the output logic. This scheme prevents late arming, due to inputs that are marginally above the threshold, from propagating to the output and misleading the measured timing, as illustrated in Fig 16C. In an earlier version of the Calypso, a single ended CMOS circuit was used to implement the output logic. Here, the jitter performance degraded due to current glitches from the CMOS switching that affected supply integrity. As such, a fully differential current mode logic (CML) was used in the subsequent revisions, replacing the CMOS logic, to reduce the current glitches and supply induced jitter.EXPERIMENTAL SETUP AND MEASUREMENT RESULTS

[0092] In this section, efforts to characterize the performance of the AFE in bench-top, irradiation, and beam-line testing are detailed. An initial fabrication run of a chip that included only the amplifier and analog drivers was undertaken, followed by a second run including the CFD and amplifiers. This chip succeeded by a third and fourth iteration to address miscellaneous issues, increasing the reliability of the AFE. The chip micrograph and layout details of the first and second test chips are detailed in Figs. 17A-17D, with the third and fourth iterations essentially being the same at this magnification view. Given the interdisciplinary nature of the AFE and diamond detector integrated performance evaluation, independent bench testing for the AFE alone was undertaken to verify and characterize the circuit prior to the combined analysis with detectors and radiation.BENCH TESTING

[0093] Absent of the radiation detector, an input charge is injected into the amplifier using a fast step function applied to a series on-chip calibration capacitor [8], The input charge resulting from the step voltage is calculated as:Qtest=^test- ^test (2) where Wtest is the voltage step from the pulse generator and Ctest is the small series capacitor. A high-speed time domain digital oscilloscope is then used to analyze the characteristics of the AFE output pulse.Table I. Simulated Current Consumption Breakdown (Drawn from 1.2V Supply)

[0094] Figure 18A shows a persistence plot for the measured transient response at the analog 50 Q driver from Fig. 6, with 1 fC input charge. Note that the charge to voltage gain, rise and fall times are all annotated in the graph. Figure 18B shows the transient noise, noise histogram and RMS noise om the measurements. Absent of any sensor capacitance, the measured rise time was 1.12 ns, with a charge to voltage gain of 133 mV / fC, and an RMS noise of 2.59 mV. The ENC was calculated at 120 electrons using the equation below:where Ne is the number of electrons in one femtocoulomb, which is approximately 6241 electrons. The spread of Gain and ENC for 43 measured channels are shown in Fig. 19, while Fig. 20 shows the simulated and measured jitter performance at the output due to the amplifier chain and the CFD. Note that almost identical jitter characteristics were observed for both positive and negative input charges using the polarity control (Fig. 8B).

[0095] The measured time-walk is depicted in Fig. 21, where the relative time-of-arrival is plotted versus the input charge. The combined amplifiers and CFD were characterized by less than ±6 ps of time-walk for over a 30 dB signal range. Table I shows the simulated current consumption for each sub-circuit shown in Fig. 6, which accurately matched the measured channel power consumption of 57 mW from 1.2V supply. Finally, Table II summarizes the standalone AFE measurement highlights along with comparison to published benchmarks from similar systems. Note that, for comparison purposes, the gain of the TIA and the rest of the chain was expressed as equivalent charge gain, in V / C unit, by measuring the peak output voltage for a fast (<500 ps) input current pulse.IRRADIATION AND BEAM TESTING

[0096] In preparation for deployment in the ATLAS’ upgraded BCM’ detector, the AFE was subjected to TID irradiation experiments using an X-RAY source at CERN. During this irradiation, the AFEs were measured after discrete increments of dose. As can be seen in Fig. 22 and Fig. 23, the measured gain and noise, over eight channels, was mostly unchanged and meets the BCM’ system goal specifications after a total dose of 225 Mrad. In field characterization of the AFE performance while connected to pCVD diamond radiation detectors was also performed on multiple occasions at the CERN Super Proton Synchrotron (SPS) 120 GeV test beam. A representative result from these studies is illustrated in Fig. 24, highlighting that the AFE and diamond detector combination was capable of delivering a signal to noise ratio (SNR) greater than 15:1 when detecting relativistic particles, representative of what will be seen in the ATLAS environment.

[0097] It should be understood that the various techniques described herein may be implemented in connection with hardware components or software components or, where appropriate, with a combination of both. Illustrative types of hardware components that can be used include Field- programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), etc. The methods and apparatus of the presently disclosed subject matter, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium where, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the presently disclosed subject matter.

[0098] As used herein, the singular form "a," "an," and "the" include plural references unless the context clearly dictates otherwise. As used herein, the terms "can," "may," "optionally," "can optionally," and "may optionally" are used interchangeably and are meant to include cases in which the condition occurs as well as cases in which the condition does not occur.

[0099] Ranges can be expressed herein as from "about" one particular value, and / or to "about" another particular value. When such a range is expressed, another embodiment includes from the one particular value and / or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another embodiment. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. It is also understood that there are a number of values disclosed herein, and that each value is also herein disclosed as "about" that particular value in addition to the value itself. For example, if the value "10" is disclosed, then "about 10" is also disclosed.

[0100] Although exemplary implementations may refer to utilizing aspects of the presently disclosed subject matter in the context of one or more stand-alone computer systems, the subject matter is not so limited, but rather may be implemented in connection with any computing environment, such as a network or distributed computing environment. Still further, aspects of the presently disclosed subject matter may be implemented in or across a plurality of processing chips or devices, and storage may similarly be effected across a plurality of devices. Such devices might include personal computers, network servers, and handheld devices, for example.

[0101] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0102] Exemplary aspect 1. An analogue front-end integrated circuit capable of operating as a low-noise high-gain amplifier or a high-linearity low-gain amplifier allowing accurate time of arrival measurements.

[0103] Exemplary aspect 2. The circuit of exemplary aspect 1, used in an array of two or more channels.

[0104] Exemplary aspect 3. The circuit of exemplary aspect 2, wherein each channel comprises a low noise trans-impedance amplifier.

[0105] Exemplary aspect 4. The circuit of exemplary aspect 3, wherein the low noise trans- impedance amplifier is optimized for minimal jitter and amplitude noise.

[0106] Exemplary aspect 5. The circuit of exemplary aspect 2, wherein each channel comprises a second stage variable gain differential amplifier.

[0107] Exemplary aspect 6. The circuit of exemplary aspect 2, wherein each channel further comprises a fully differential constant fraction discriminator.

[0108] Exemplary aspect 7. The circuit of exemplary aspect 6, wherein the constant fraction discriminator comprises a all-pass filter circuit to provide delay and pulse shaping and a zerocrossing detector to minimize time walk.

[0109] Exemplary aspect 8. The circuit of exemplary aspect 6, wherein the zero-crossing detector (ZCD) includes digitally controlled capacitors to finely tune the bandwidth to achieve a minimal time walk at an intermediate bandwidth.

[0110] Exemplary aspect 9. The circuit of exemplary aspect 6, wherein a hysteretic differential difference amplifier based arming comparator is used to propagate the ZCD output only if the input pulse is greater than a preset programmable reference level.Exemplary Aspects:

[0111] Exemplary aspect 1. An analogue front-end integrated circuit as described herein and capable of operating as a low-noise high-gain amplifier or a high-linearity low-gain amplifier allowing accurate time of arrival measurements.

[0112] Exemplary aspect 2. The circuit of exemplary aspect 1, wherein the circuit is used in an array of two or more channels.

[0113] Exemplary aspect 3. The circuit of exemplary aspect 2, wherein each channel comprises a low noise trans-impedance amplifier.

[0114] Exemplary aspect 4. The circuit of exemplary aspect 3, wherein the low noise trans- impedance amplifier is optimized for minimal jitter and amplitude noise.

[0115] Exemplary aspect 5. The circuit of exemplary aspect 2, wherein each channel comprises a second stage variable gain differential amplifier.

[0116] Exemplary aspect 6. The circuit of exemplary aspect 2, wherein each channel further comprises a fully differential constant fraction discriminator.

[0117] Exemplary aspect 7. The circuit of exemplary aspect 6, wherein the constant fraction discriminator comprises an all-pass filter circuit to provide delay and pulse shaping and a zerocrossing detector to minimize time walk.

[0118] Exemplary aspect 8. The circuit of exemplary aspect 6, wherein the zero-crossing detector (ZCD) includes digitally controlled capacitors to finely tune the bandwidth to achieve a minimal time-walk at an intermediate bandwidth.

[0119] Exemplary aspect 9. The circuit of exemplary aspect 6, wherein a hysteretic differential difference amplifier based arming comparator is used to propagate the ZCD output only if the input pulse is greater than a preset programmable reference level.REFERENCES CITED[1] D. L. Snyder, L. J. Thomas, and M. M. Ter-Pogossian, “A mathematical model for Positron-Emission Tomography systems having time-of-flight measurements,” IEEE Transactions on Nuclear Science, vol. 28, no. 3, pp. 3575-3583, 1981.[2] M. Simpson, C. Britton, A. Wintenberg, and G. Young, “An integrated, CMOS, constant-fraction timing discriminator for multichannel detector systems,” IEEE transactions on nuclear science, vol. 42, no. 4, pp. 762-766, 1995.[3] C. Fiorini, M. Porro, and T. Frizzi, “An 8-channel DRAGO readout circuit for silicon detectors with inte- grated front-end JFET,” IEEE transactions on nuclear science, vol. 53, no. 5, pp. 2998-3003, 2006.[4] S. Adachi, A. Nishimura, T. Yoshimuta, K. Tanabe, and S. Okamura, “A 128-channel CMOS charge readout ASIC for flat-panel X-ray detectors,” IEEE Transactions on Nuclear Science, vol. 55, no. 6, pp. 3673-3683, 2008.[5] F. Sauli, Gaseous radiation detectors: fundamentals and applications. Cambridge University Press, 2014, no. 36.[6] R. Hofstadter, “Alkali halide scintillation counters,” Physical Review, vol. 74, no. 1, p. 100, 1948.[7] I. Lee, M. Deleplanque, and K. Vetter, “Developments in large gamma-ray detector arrays,” Reports on Progress in Physics, vol. 66, no. 7, p. 1095, 2003.[8] H. Spieler, Semiconductor Detector Systems, ser. Semi- conductor Science and Technology. Oxford: Oxford University Press, 2005, vol. v.12.[9] W. M. C. Sansen and Z. Y. Chang, “Limits of low noise performance of detector readout front ends in CMOS technology,” IEEE Transactions on Circuits and Systems, vol. 37, no. 11, pp. 1375-1382, Nov 1990.

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Claims

CLAIMSWhat is claimed is:

1. An analogue front-end integrated circuit, wherein the circuit is capable of operating as a low-noise high-gain amplifier or a high-linearity low-gain amplifier allowing accurate time of arrival measurements, the circuit comprising: an array of one or more channels, wherein each channel comprises: a low noise trans-impedance amplifier, a capacitor attenuator, a variable gain differential amplifier, a differential constant fraction discriminator, and output drivers.

2. The circuit of claim 1, wherein the low noise trans-impedance amplifier is optimized for minimal jitter and amplitude noise.

3. The circuit of claim 1, wherein each channel can be configured to use either the low noise trans-impedance amplifier to measure low range radiation, or the capacitor attenuator to measure high range radiation.

4. The circuit of claim 3, wherein each channel comprises a first variable gain differential amplifier following the low noise trans-impedance amplifier and a second variable gain differential amplifier following the capacitor attenuator.

5. The circuit of claim 4, wherein the differential constant fraction discriminator and output drivers follow the first and the second variable gain differential amplifier.

6. The circuit of claim 1, wherein the low noise trans-impedance amplifier accepts both positive and negative input charge signals.

7. The circuit of claim 1, wherein the variable gain differential amplifier is configured to rectify an output signal polarity according to a programable set of switches.

8. The circuit of claim 1, wherein the differential constant fraction discriminator comprises fully differential signaling schemes.

9. The circuit of claim 1, wherein the differential constant fraction discriminator comprises an all-pass filter circuit to provide delay and pulse shaping and a zero-crossing detector to minimize time walk.

10. The circuit of claim 9, wherein the zero-crossing detector (ZCD) comprises a cascade of at least three amplifiers, wherein all amplifiers except a final amplifier are low gain and high bandwidth amplifiers and the final amplifier is a high gain rail-to-rail amplifier.

11. The circuit of claim 10, wherein the at least three amplifiers of the ZCD comprise digitally controlled capacitors to finely tune both bandwidth and slew-rate to achieve balance at which phase lead due to compression cancel out phase lag due to limited slew rate to attain a minimal time walk.

12. The circuit of claim 10, wherein the cascade of at least three amplifiers comprises five amplifiers.

13. The circuit of claim 1, wherein the differential constant fraction discriminator further comprises a hysteretic differential difference amplifier based arming comparator, wherein the hysteretic differential difference amplifier based arming comparator is used to propagate a ZCD output only if an input pulse is greater than a preset programmable reference level.

14. The circuit of claim 1, wherein the circuit comprises an array of four channels.

15. The circuit of claim 1, wherein the output drivers are analogue and digital output drivers.

16. The circuit of claim 1, wherein the circuit is preceded by a diamond detector.

17. A photon detector comprising the circuit of any one of claims 1-16.

18. A high-energy particle detector comprising the circuit of any one of claims 1-16.

19. A radiation detector comprising the circuit of any one of claims 1-16.

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