Semiconductor memory cell, array and device, and manufacturing method therefor

Abstract

The present invention provides a semiconductor memory cell, comprising: a magnetic material stack, comprising a first magnetic layer, a tunneling barrier layer, and a second magnetic layer stacked in sequence from bottom to top; a first contact member connected to the first magnetic layer; a third magnetic layer stacked on the magnetic material stack; and a second contact member in direct contact with the third magnetic layer. The spin directions of the first magnetic layer, the second magnetic layer and the third magnetic layer are collinear; and the third magnetic layer has non-uniform material distribution in a vertical direction and has a continuous sidewall topography at least at a contact interface between the third magnetic layer and the magnetic material stack. In the present invention, by providing a third magnetic layer on a magnetic material stack, the magnetic material stack is always effectively protected, stable electrical contact is provided between the magnetic material stack and contact members, and the magnetization direction of the magnetic layer below the third magnetic layer is also fixed, thereby improving, taken as a whole, the reliability of the semiconductor memory cell and device performance.

Description

Semiconductor storage unit, array, device and preparation method thereof Technical Field

[0001] The present invention belongs to the field of integrated circuits and relates to semiconductor storage units, arrays, devices and preparation methods thereof, and in particular to a magnetic semiconductor storage unit, array, device and preparation method thereof. Background Art

[0002] In the integrated circuit field, semiconductor memory devices, used for storing information, have always been a crucial component. In recent years, with the advent of the data age and the increasing amount of data being generated and utilized, the industry's requirements for key memory device specifications, such as storage capacity, power consumption, read speed, and device size, have gradually increased. As miniaturization significantly impacts many key performance indicators of MOSFET-based memory, increasing research and industry exploration are focusing on magnetic semiconductor memory fabricated using magnetic materials.

[0003] The further reduction in the size of arrayed magnetic semiconductor memory cells poses a challenge to the patterning process of magnetic semiconductor memory cells. Patterning processes based on silicon-based materials typically place a hard mask structure on the material to be processed, such as insulating silicon oxide and / or silicon nitride, or highly conductive titanium nitride, tantalum carbide, or tantalum. After the patterning process is completed, the hard mask structure is removed, such as by wet or dry etching. However, in order to fully remove the hard mask, a certain amount of overetching is usually performed, which in turn damages the exposed surface of the material to be processed. Such damage caused by such processes can pose a risk of failure to the reliability of the core structure of the magnetic semiconductor memory cell.

[0004] Summary of the Invention

[0005] To solve the technical problem in the prior art of difficulty in reducing the core size of magnetic semiconductor memory cells while maintaining reliability, the present invention provides the following technical solutions:

[0006] A semiconductor memory cell comprising:

[0007] a magnetic material stack, the magnetic material stack comprising a first magnetic layer, a tunneling barrier layer, and a second magnetic layer stacked sequentially from bottom to top; and a first contact connected to the first magnetic layer;

[0008] a third magnetic layer, the third magnetic layer being stacked on the magnetic material stack;

[0009] a second contact member, the second contact member being in direct contact with the third magnetic layer;

[0010] wherein the spin directions of the first magnetic layer, the second magnetic layer, and the third magnetic layer are collinear;

[0011] The third magnetic layer has a non-uniform material distribution in the vertical direction and a continuous sidewall morphology at least at the contact interface between the third magnetic layer and the magnetic material stack, so that the third magnetic layer always protects the magnetic material stack and fixes the magnetization direction of the second magnetic layer while providing a stable electrical contact;

[0012] The third magnetic layer includes a stacked third magnetic inner layer and a third magnetic cover layer, and the third magnetic cover layer continuously covers at least the top surface and a portion of the sidewall of the third magnetic inner layer.

[0013] Furthermore, a portion of the third magnetic layer that is in direct contact with the second contact piece is different from a portion of the third magnetic layer located at the contact interface.

[0014] Furthermore, the third magnetic layer is made of ferromagnetic material, antiferromagnetic material or ferrimagnetic material.

[0015] A semiconductor memory cell comprising:

[0016] a magnetic material stack, the magnetic material stack comprising a first magnetic layer, a tunneling barrier layer, a second magnetic layer, and a fourth magnetic layer stacked sequentially from bottom to top; and a first contact member connected to the first magnetic layer; wherein the fourth magnetic layer has a different polarization characteristic from the second magnetic layer;

[0017] a third magnetic layer, the third magnetic layer being stacked on the magnetic material stack;

[0018] a second contact member, the second contact member being in direct contact with the third magnetic layer;

[0019] Wherein, the spin directions of the first magnetic layer and the second magnetic layer are collinear, and the spin directions of the third magnetic layer and the fourth magnetic layer are collinear;

[0020] The third magnetic layer has a non-uniform material distribution in the vertical direction and a continuous sidewall morphology at least at the contact interface between the third magnetic layer and the magnetic material stack, so that the third magnetic layer always protects the magnetic material stack and fixes the magnetization direction of the fourth magnetic layer while providing a stable electrical contact;

[0021] The third magnetic layer includes a stacked third magnetic inner layer and a third magnetic cover layer, wherein the third magnetic cover layer continuously covers at least the top surface and a portion of the sidewall of the third magnetic inner layer.

[0022] Furthermore, a portion of the third magnetic layer that is in direct contact with the second contact piece is different from a portion of the third magnetic layer located at the contact interface.

[0023] Furthermore, the first magnetic layer or the second magnetic layer comprises a plurality of stacked magnetic material layers, wherein at least two magnetic material layers have opposite polarization directions in the plurality of magnetic material layers, and the plurality of magnetic material layers have a fixed polarization direction.

[0024] Furthermore, the third magnetic layer is made of ferromagnetic material, antiferromagnetic material or ferrimagnetic material.

[0025] A method for preparing a semiconductor memory cell, comprising:

[0026] Providing a magnetic material stack, the magnetic material stack including a first magnetic layer, a tunneling barrier layer, and a second magnetic layer stacked sequentially from bottom to top; and forming a first contact, the first contact being connected to the first magnetic layer;

[0027] forming a third magnetic layer, the third magnetic layer being stacked on the magnetic material stack; wherein the spin directions of the first magnetic layer, the second magnetic layer, and the third magnetic layer are collinear;

[0028] The patterning step includes directly performing a first patterning process on the third magnetic layer; and directly performing a second patterning process on the magnetic material stack using the patterned third magnetic layer;

[0029] forming a second contact member, wherein the second contact member is directly formed on the third magnetic layer to form a contact connection;

[0030] The third magnetic layer has a non-uniform material distribution in the vertical direction and a continuous sidewall morphology at least at the contact interface between the third magnetic layer and the magnetic material stack, so that the third magnetic layer always protects the magnetic material stack and fixes the magnetization direction of the second magnetic layer while providing a stable electrical contact;

[0031] The third magnetic layer includes a stacked third magnetic inner layer and a third magnetic cover layer, and the third magnetic cover layer continuously covers at least the top surface and a portion of the sidewall of the third magnetic inner layer.

[0032] A method for preparing a semiconductor memory cell, comprising:

[0033] Providing a magnetic material stack, the magnetic material stack comprising a first magnetic layer, a tunneling barrier layer, a second magnetic layer, and a fourth magnetic layer stacked sequentially from bottom to top; wherein the fourth magnetic layer has a different polarization characteristic from the second magnetic layer;

[0034] and forming a first contact, the first contact being connected to the first magnetic layer;

[0035] forming a third magnetic layer, the third magnetic layer being stacked on the magnetic material stack; wherein the spin directions of the first magnetic layer and the second magnetic layer are collinear, and the spin directions of the third magnetic layer and the fourth magnetic layer are collinear;

[0036] The patterning step includes directly performing a first patterning process on the third magnetic layer; and directly performing a second patterning process on the magnetic material stack using the patterned third magnetic layer;

[0037] forming a second contact member, wherein the second contact member is directly formed on the third magnetic layer to form a contact connection;

[0038] The third magnetic layer has a non-uniform material distribution in the vertical direction and a continuous sidewall morphology at least at the contact interface between the third magnetic layer and the magnetic material stack, so that the third magnetic layer always protects the magnetic material stack and fixes the magnetization direction of the fourth magnetic layer while providing a stable electrical contact;

[0039] The third magnetic layer includes a stacked third magnetic inner layer and a third magnetic cover layer, and the third magnetic cover layer continuously covers at least the top surface and a portion of the sidewall of the third magnetic inner layer.

[0040] A semiconductor storage array comprises a plurality of any of the aforementioned semiconductor storage units; a switch component for selecting addresses for individual semiconductor storage devices; and a connection component for connecting the switch component with the semiconductor storage unit.

[0041] A semiconductor memory device comprises the aforementioned semiconductor memory array; and a controller for controlling a switch component.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] The present invention introduces a third magnetic layer into a magnetic semiconductor memory device. The third magnetic layer is arranged between a magnetic material stack and a second contact piece, which can help the magnetic material stack achieve a stable electrical connection. At the same time, the third magnetic layer is stacked on the magnetic material stack to complete the patterning process until a final device form is formed. The third magnetic layer can always provide stable protection for the magnetic material stack. The third magnetic layer is arranged between the magnetic material stack and the contact piece to provide a stable electrical contact, and at the same time, helps to fix the magnetization direction of the magnetic material located therebelow, thereby greatly improving the reliability and device performance of the magnetic semiconductor memory unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] FIG1 is a semiconductor memory unit provided by the present invention;

[0046] FIG2 is a semiconductor memory cell provided by the present invention, wherein a partial enlarged view is shown in a circular frame;

[0047] FIG3 is a semiconductor memory unit provided by the present invention;

[0048] FIG4 is a semiconductor memory unit provided by the present invention;

[0049] FIG5 is a semiconductor memory array provided by the present invention;

[0050] FIG6 is a flow chart of a method for preparing a semiconductor memory cell provided by the present invention;

[0051] FIG. 7 is a schematic diagram of a method for manufacturing a semiconductor memory unit provided by the present invention.

[0052] Among them, 1-second contact member; 2-magnetic material stack; 3-first contact member;

[0053] 21-second magnetic layer; 211-second magnetic inner layer; 212-second magnetic cover layer;

[0054] 22- tunneling barrier layer;

[0055] 23-first magnetic layer; 231-first magnetic inner layer; 232-first magnetic cover layer;

[0056] 24- fourth magnetic layer;

[0057] 4-third magnetic layer; 41-third magnetic inner layer; 42-third magnetic cover layer;

[0058] 51……5 n - the 1st ... nth semiconductor memory unit;

[0059] 61 - first dielectric layer, 62 - inorganic underlayer, 63 - second dielectric layer, 64 - third dielectric layer. DETAILED DESCRIPTION

[0060] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0061] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0062] In semiconductor devices, the patterning process determines the size and morphology of the device. Magnetic semiconductor memory cells are core storage structures formed by stacking magnetic materials. If patterned using the hard mask structure used in traditional silicon-based devices, magnetic materials are more difficult to etch than traditional silicon-based materials. Furthermore, to etch thicker magnetic material stacks, the hard mask must be thickened. These conditions can lead to impurity redeposition, shadowing, or micro-masking effects, significantly impacting the process efficiency and reliability of magnetic semiconductor memory cells.

[0063] The present invention provides a semiconductor memory cell, array, device, and method for manufacturing the same. The semiconductor memory cell, array, device, and method for manufacturing the same are described in detail below with reference to the accompanying drawings. The features of the following embodiments and implementations may be combined unless otherwise specified.

[0064] 1 , which shows a semiconductor storage unit provided by the present invention, including a magnetic material stack 2, the magnetic material stack 2 including a first magnetic layer 23, a tunneling barrier layer 22, and a second magnetic layer 21 stacked in sequence from bottom to top; and a first contact 3, the first contact 3 being connected to the first magnetic layer 23; a third magnetic layer 4, the third magnetic layer 4 being stacked on the magnetic material stack 2; a second contact 1, the second contact 1 being in direct contact with the third magnetic layer 4; wherein the spin directions of the first magnetic layer 23, the second magnetic layer 21, and the third magnetic layer 4 are collinear; the third magnetic layer has a non-uniform material distribution in the vertical direction and has a continuous sidewall morphology at least at the contact interface between the third magnetic layer and the magnetic material stack, so that the third magnetic layer always protects the magnetic material stack and fixes the magnetization direction of the second magnetic layer while providing a stable electrical contact.

[0065] Specifically, the core structure of the semiconductor memory cell provided by the present invention is a magnetic material stack 2, which is composed of a first magnetic layer 23, a tunneling barrier layer 22, and a second magnetic layer 21 stacked in sequence. This stack forms a basic magnetic tunnel junction (MTJ). Electrical connections are established at both ends of the MTJ to form a basic memory cell. One of the first magnetic layer 23 and the second magnetic layer 21 maintains a fixed magnetization direction, while the other flips its magnetization direction under the influence of an electric current, a spin-polarized current, or an electric field, thereby completing the write operation. Reading is achieved by measuring the magnetic resistance of the magnetic tunnel junction through which current passes. The present invention does not limit the specific type of magnetic memory. As long as it uses a magnetic tunnel junction (MTJ) as the basic structure, a typical application is magnetic random access memory (MRAM), which can be a magnetic field write-type MRAM, a spin transfer torque write-type MRAM (STT-MRAM), a spin orbit torque write-type MRAM (SOT-MRAM), a voltage-controlled magnetic anisotropy MRAM (VCMA-MRAM), or a composite MRAM cell combining multiple of the aforementioned write methods. The memory structure formed by the memory cell array can be a structure composed of multiple memory cells with a single write principle, or a hybrid structure integrating at least two of the aforementioned memory cells with different write principles.

[0066] In the present invention, a third magnetic layer 4 is stacked on top of the magnetic material stack 2, and a second contact 1 is directly disposed on the third magnetic layer 4. The third magnetic layer 4 is disposed between the magnetic material stack 2 and the second contact 1 and has good electrical conductivity, generally requiring a resistivity of less than 100 μΩ·cm.

[0067] In the present invention, the spin direction of the third magnetic layer 4 remains collinear with the first magnetic layer 23 and the second magnetic layer 21. For example, the first, second, and third magnetic layers can all be in-plane polarized or out-of-plane polarized. It is important to note that although the spin directions of the first, second, and third magnetic layers remain collinear, their specific polarization directions can be different.

[0068] In addition, the present invention has a continuous sidewall morphology at the interface where the third magnetic layer 4 contacts the magnetic material stack 2. The continuous sidewall morphology can extend to a certain extent in the direction of the third magnetic layer 4 and / or the magnetic material stack 2 at the interface. The continuous sidewall morphology reflects the process continuity and structural stability between the third magnetic layer 4 and the magnetic material stack 2. A typical implementation method is to stack the third magnetic layer on the magnetic material layer, directly pattern the magnetic material layer 2 through the third magnetic layer 4, and the third magnetic layer 4 is completely retained after the patterning without being removed. The third magnetic layer 4 can effectively protect the magnetic material stack 2 during and after the patterning process, so that the entire magnetic material stack 2, especially the top surface of the magnetic material stack 2 that can contact the outside world, can maintain the initial surface state after the stacking preparation. That is, the third magnetic layer always protects the magnetic material stack.

[0069] In addition to providing stable protection for the magnetic material stack, the third magnetic layer, located between the magnetic material stack and the contact, also exhibits good electrical conductivity, at least in the portion adjacent to the contact, to help achieve a stable electrical connection between the magnetic material stack 2. Furthermore, the third magnetic layer 4 utilizes its magnetic properties to fix the spin orientation of underlying magnetic material layers, such as the second magnetic layer 21.

[0070] It can be seen that the third magnetic layer has multiple superimposed functions, which can enhance the contact performance, improve the magnetic properties of the magnetic tunnel junction MTJ, and at the same time provide stable protection for the structure of the magnetic tunnel junction MTJ, thereby enhancing the reliability of the device.

[0071] The third magnetic layer 4 can be made of an antiferromagnetic material with good electrical conductivity, including collinear antiferromagnetic and non-collinear antiferromagnetic materials. In actual use, the third magnetic layer 4 can be made of a collinear antiferromagnetic material with good electrical conductivity, such as nickel-manganese-copper alloy, iron-aluminum alloy, iron-rhodium alloy, iron-ruthenium alloy, manganese nitride, iron-manganese alloy, manganese-platinum alloy, manganese-iridium alloy, iron-manganese-rhodium alloy, rhodium-manganese alloy, palladium-platinum-manganese alloy, nickel-manganese alloy, chromium-platinum-manganese alloy, etc.; in addition, the third magnetic layer 4 can be made of a non-collinear antiferromagnetic material with good electrical conductivity, such as manganese-tin alloy, manganese-gallium alloy, manganese-germanium alloy, etc.

[0072] In particular, the third magnetic layer 4 is also more often selected from copper-chromium alloy, iron-chromium-aluminum alloy, chromium dioxide, nickel-molybdenum alloy, iron-aluminum alloy, manganese nitride, iron-manganese alloy, manganese-platinum alloy, manganese-iridium alloy, etc.

[0073] The third magnetic layer 4 may also be made of a ferromagnetic material, usually a material with good conductivity, such as an alloy material composed of one or more of iron (Fe), nickel (Ni), and cobalt (Co); or a Whistler alloy, such as FeSiAl alloy.

[0074] In addition, the third magnetic layer 4 may also be made of ferrimagnetic materials with good electrical conductivity, such as iron-aluminum alloy, iron-niobium alloy, iron-silicon alloy, etc.

[0075] In practical applications, since the lower surface of the third magnetic layer 4 is connected to the magnetic material stack 2 and the upper surface is connected to the second contact 1 , at least the upper and lower surfaces of the third magnetic layer 4 can be made of different materials.

[0076] Optionally, the third magnetic layer 4 is formed of an alloy material, and the composition of the alloy changes in the direction from the second contact 1 to the magnetic material stack 2. Specifically, a multi-layer stack of alloy magnetic material layers can be provided, or a gradient alloy magnetic material layer can be obtained by continuously changing the composition. Taking the antiferromagnetic material manganese-iridium alloy as an example, manganese-iridium alloys of different compositions can be stacked or a manganese-iridium alloy with continuously changing composition can be provided, and the portion close to the second contact 1 has a higher manganese content. Alternatively, the third magnetic layer 4 can be formed of a manganese-copper alloy, and the portion of the third magnetic layer 4 close to the second contact 1 has a higher manganese content.

[0077] Another approach is to improve a portion of the third magnetic layer 4 by introducing other impurities, such as selectively injecting or doping the third magnetic layer 4. Specifically, the portion close to the second contact 1 is implanted or doped with impurities that enhance the conductivity, and / or the portion close to the magnetic material stack 2 is implanted or doped with impurities that enhance its magnetism, and / or the portion close to the magnetic material stack 2, especially the sidewall portion, is implanted or doped with impurities that enhance its etching resistance.

[0078] In actual use, when manganese-copper alloy is selected as the material of the third magnetic layer 4, gold (Au) can be selected as an impurity to enhance the conductivity; when manganese-platinum alloy is selected as the material of the third magnetic layer 4, ruthenium (Ru) or chromium (Cr) impurities can be introduced therein to improve the exchange bias of the third magnetic layer; and nitrogen (N), ruthenium (Ru), copper (Cu), manganese (Mn) or chromium (Cr) impurities can be introduced into the third magnetic layer 4 to improve the etching resistance of the magnetic material in the subsequent IBE etching process.

[0079] Next, referring to Figure 2, another magnetic storage cell is shown. The small box diagrams in both figures each magnify a portion of the sidewall area of ​​the magnetic storage cell. Figure 2(a) differs from Figure 1 in that the third magnetic layer is divided into a third magnetic inner layer 41 and a third magnetic cover layer 42, which are stacked in sequence. The third magnetic cover layer 42 continuously covers at least the central area of ​​the third magnetic inner layer 41 and at least the area where the second contact 1 is to be formed. The third magnetic cover layer 42 is made of a material with excellent electrical conductivity, which allows for a wider range of material choices for the third magnetic inner layer 41 in terms of electrical conductivity.

[0080] It is particularly important to note that, structurally, the third magnetic inner layer 41 is stacked on top of the magnetic material stack 2, and the contact interface has a continuous sidewall morphology. This continuous sidewall morphology can extend somewhat toward the third magnetic layer 41 and / or the magnetic material stack 2 at the interface. Specifically, the third magnetic inner layer 41 is selected to perform a patterning process on the magnetic material stack 2. After the overall patterning of the magnetic material stack 2 is completed, the third magnetic cover layer 42 is grown. This third magnetic cover layer 42 can, to a certain extent, cover the surface damage of the third magnetic inner layer 41 caused by the patterning process, thereby largely preventing circuit failure caused by direct contact between the damaged surface and the second contact member 1.

[0081] Optionally, the third magnetic cover layer 42 can also be arranged as shown in (b) of FIG2 , where the third magnetic cover layer 42 continuously covers the entire top surface of the third magnetic inner layer 41 and includes at least a portion extending from the top surface to the side wall. That is, the third magnetic cover layer 42 forms a complete covering on the entire top surface of the third magnetic inner layer 41 and extends outward and downward from the four sides of the top surface to the side wall of the third magnetic inner layer 41. Since the edges of the third magnetic inner layer 41 are more susceptible to the patterning process, the degree of damage is further increased, which increases the difficulty of preparing subsequent external contacts. In the present invention, the edges of the third magnetic inner layer 41 are all covered by the third magnetic cover layer 42, avoiding direct connection of the damaged edges of the third magnetic inner layer 41 to the external contacts. Optionally, the third magnetic cover layer 42 expands the area of ​​the magnetic memory unit where external contacts can be set to a certain extent, reduces the contact resistance, and increases the process tolerance space of the external contacts.

[0082] Optionally, the third magnetic cover layer 42 does not extend to the interface between the third magnetic inner layer 41 and the magnetic material stack 2 to avoid affecting the performance of the magnetic material stack 2 .

[0083] Next, referring to Figure 3, another magnetic semiconductor memory cell is provided. This differs from the magnetic semiconductor memory cell in Figure 1 in that the magnetic material stack 2 further includes a fourth magnetic layer 24, which is stacked above the second magnetic layer 21. The fourth magnetic layer 24 has different polarization characteristics from the second magnetic layer 21. Optionally, when the second magnetic layer 21 is in-plane polarized, the fourth magnetic layer 24 can be made of a magnetic material with out-of-plane polarization. Alternatively, when the second magnetic layer 21 is out-of-plane polarized, the fourth magnetic layer 24 can be made of a magnetic material with in-plane polarization. Providing the fourth magnetic layer 24 on top of the magnetic material stack 2, with a polarization different from that of the MTJ, provides additional magnetic coupling under magnetic field conditions, thereby reducing the magnetic field, current, or electric field required to magnetize the free layer and improving the device's thermal stability and data retention. Furthermore, the MTJ's tunnel resistance can be increased, thereby improving read speed and reliability.

[0084] In this embodiment, the spin directions of the first magnetic layer 23 and the second magnetic layer 21 are collinear, while the spin directions of the third magnetic layer and the fourth magnetic layer are collinear. The third magnetic layer has a non-uniform material distribution in the vertical direction and a continuous sidewall morphology at least at the interface between the third magnetic layer and the magnetic material stack. This allows the third magnetic layer to consistently protect the magnetic material stack and fix the magnetization direction of the fourth magnetic layer while providing a stable electrical contact.

[0085] It should be noted that, in addition to forming a basic MTJ structure, the magnetic material stack may also be stacked with multiple magnetic material layers. Although it is defined in the embodiment corresponding to FIG3 that the polarization characteristics of the fourth magnetic layer are different from those of the magnetic layer in the MTJ, the present invention is not limited thereto. In the magnetic material stack, there may be more than one layer of magnetic material located above the MTJ structure, and their polarization characteristics may be the same or different. The third magnetic layer is stacked on the magnetic material stack. When it has a collinear spin direction with the magnetic material directly below it, the magnetization characteristics may be enhanced by impurity doping near the contact interface, and the magnetic field direction of the magnetic material below it may be fixed. In this embodiment, the magnetization direction of the fourth magnetic layer is fixed by the third magnetic layer 4.

[0086] In the structure shown in FIG3 , the material selection of the third magnetic layer, the composite structure of the inner layer and the cover layer, etc. can all be referred to the above description and will not be repeated here.

[0087] FIG4 provides another magnetic semiconductor memory cell, which further provides the first magnetic layer 23 or the second magnetic layer 21 as a multilayer based on the example of FIG3 . Although FIG4 only illustrates the case where the first or second magnetic layer is a double layer, the present invention is not limited to this. FIG4 (a) shows that the second magnetic layer is divided into a second magnetic inner layer 211 and a second magnetic cover layer 212, and the polarization directions of the two are fixed and opposite. In this case, the polarization direction of the first magnetic layer 23 is variable. FIG4 (b) shows that the first magnetic layer is divided into a first magnetic inner layer 231 and a first magnetic cover layer 232, and the polarization directions of the two are fixed and opposite. In this case, the polarization direction of the second magnetic layer 21 is variable.

[0088] It should be noted that, in this embodiment, the third magnetic layer 4 can be further selected to be a diamagnetic material to form an exchange bias layer, so that the entire MTJ is more stable and reliable under the action of an external magnetic field.

[0089] FIG. 5 provides a circuit diagram of a plurality of semiconductor memory cells, such as the first semiconductor memory cell 51 . . . the nth semiconductor memory cell 5 nThe magnetic semiconductor memory array further comprises a switch component for selecting addresses for individual semiconductor memory devices and a connection component for connecting the switch component to the semiconductor memory cells. The individual semiconductor memory cells may be from the aforementioned embodiments or a combination of related embodiments.

[0090] Furthermore, a semiconductor memory device can be constructed using the semiconductor memory array, which also includes a controller to control the switch components in the memory array.

[0091] The foregoing is a detailed introduction to the semiconductor memory cells, arrays, and devices provided in this application, corresponding to the aforementioned semiconductor memory cell, array, and device embodiments. The following will focus on the preparation methods of the semiconductor memory cells, arrays, and devices provided in this application.

[0092] The present invention also provides a method for preparing a semiconductor memory cell, specifically referring to FIG6 , which comprises the following steps:

[0093] S100: providing a magnetic material stack, the magnetic material stack comprising a first magnetic layer, a tunneling barrier layer, and a second magnetic layer stacked sequentially from bottom to top; and forming a first contact, the first contact being connected to the first magnetic layer;

[0094] S200: forming a third magnetic layer, the third magnetic layer being stacked on the magnetic material stack; wherein the spin directions of the first magnetic layer, the second magnetic layer, and the third magnetic layer are collinear;

[0095] S300: a patterning step, comprising directly performing a first patterning process on the third magnetic layer; and directly performing a second patterning process on the magnetic material stack using the patterned third magnetic layer;

[0096] S400: a step of forming a second contact member, wherein the second contact member is directly prepared above the third magnetic layer to form a contact connection.

[0097] Specifically, referring to the process steps shown in FIG7 , the method for preparing a semiconductor memory cell includes:

[0098] As shown in (a) of FIG7 , step S100 includes:

[0099] Step S101: Providing a magnetic material stack 2; and Step S102: Forming a first contact. After step S100, the magnetic material stack 2 is stacked on the first contact 3. The order of steps S101 and S102 is not limited in the process.

[0100] In a specific implementation of step S100, step S102 is first performed. A typical implementation method is to form a through groove in the bulk material of the first dielectric layer 61 and fill it with the first contact metal material; then a planarization process is performed to remove the metal material filled outside the bulk material.

[0101] In particular, there is another metal structure under the first contact piece. The first contact piece is formed by forming a block material of the first dielectric layer 61 on the patterned other metal structure, and forming a through groove in the block material of the first dielectric layer 61. The groove can form a certain amount of over-etching to penetrate into the other metal structure. When the first contact piece metal is filled in the groove, a stable contact can be formed with the other metal structure.

[0102] Subsequently, a magnetic material stacking process is performed on the plane from which the first contact 3 is obtained, i.e., step S101 is performed. A typical method for performing step S101 is to use the bulk material from which the first contact 3 is obtained as a growth substrate, directly placing it in a growth chamber, and then growing each magnetic material separately. The magnetic material can be grown using an appropriate process such as deposition. The necessary cleaning and material growth inspection steps involved in the above process are not further described here.

[0103] In another specific embodiment of step S100, steps S101 and S102 are performed separately. If another metal structure is included below the first contact, the step of forming the other metal structure, step S101, and step S102 are all performed independently. After the three are prepared separately, they are sequentially combined using a bonding process or other processes. In this embodiment, by selecting the most suitable substrate for growing the magnetic material for step S101 and removing the substrate after the growth of the magnetic material stack 2 is completed, this embodiment can improve the reliability of the growth of the magnetic material stack.

[0104] Optionally, when step S102 is implemented independently, a groove can be formed in the bulk material of the first dielectric layer 61, and the groove does not need to be through; then a suitable metal is filled therein to form a first contact metal; and then a double-sided planarization process is performed to expose the first contact metal on both sides and form a flat surface on both sides.

[0105] In practical applications, as shown in FIG7 , the magnetic material stack 2 includes a first magnetic layer 23, a tunneling barrier layer 22, and a second magnetic layer 21, with the spin directions of the first and second magnetic layers collinear. Those skilled in the art will appreciate that the structure of the magnetic material stack 2 can be modified and implemented in accordance with the various device embodiments described earlier in this specification.

[0106] FIG7( a ) also illustrates step S200, specifically the step of forming a third magnetic layer 4. The third magnetic layer is stacked on the magnetic material stack, wherein the spin directions of the first magnetic layer 23, the second magnetic layer 21, and the third magnetic layer 4 are collinear. The third magnetic layer 4 is formed after the magnetic material stack 2 is prepared. In the process, the third magnetic layer 4 can be directly prepared in the chamber where the magnetic material stack 2 is grown without breaking the vacuum. The preparation method is selected based on the specific material, and can be sputtering, deposition, etc.

[0107] After the preparation process of the third magnetic layer 4 is completed, the patterning step S300 is performed, including a first patterning process S3O1, that is, a patterning process directly performed on the third magnetic layer; and a second patterning process S3O2, that is, a patterning process directly performed on the magnetic material stack using the patterned third magnetic layer.

[0108] Figure 7(b) illustrates the structure of the patterned third magnetic layer obtained after step S301. The patterned third magnetic layer 4 can be formed by spin-coating a mask layer, an anti-reflective layer, and a photoresist on the stacked third magnetic layer 4, followed by a photolithography process, or by a patterning process such as laser direct writing.

[0109] Optionally, the first patterning process may be performed by using the patterned first contact 3 as a mask to perform back exposure to obtain the pattern of the third magnetic layer.

[0110] Subsequently, the S3O2 step is directly performed, and the pattern of the third magnetic layer 4 is used to pattern the magnetic material stack 2. (c) in Figure 7 illustrates the morphology of the patterned magnetic material stack 2, and an inorganic underlayer 62 and a second dielectric material 63 are formed between each magnetic material stack structure, and the morphology after flattening is performed. Among them, the etching of the magnetic material stack 2 can be achieved by chemical reaction etching (RIE) and / or ion beam etching (IBE). The inorganic underlayer 62 can be selected from SiOx, SiN, AlO, etc.

[0111] Specifically, when forming a structure having a third magnetic inner layer 41 and a third magnetic cover layer 42 as shown in FIG2 , it is necessary to first form the third magnetic inner layer 41 in step S200 , then pattern the third magnetic inner layer 41 in step S301 , and then pattern the magnetic material stack 2 using the patterned third magnetic inner layer 41 in step S302 . The third magnetic cover layer 42 is then prepared using methods such as sputtering and deposition. Finally, the inorganic underlayer 62 and the second dielectric material 63 are grown and planarized.

[0112] Finally, step S400 is performed on the surface of the third magnetic layer 4. That is, the second contact 1 is fabricated directly on the exposed surface of the third magnetic layer 4 in the structure shown in FIG7(c). The second contact can be fabricated by first forming the third dielectric layer 64, then forming an opening, and then filling it with metal, thereby completing the steps of fabricating a complete memory cell.

[0113] The present invention also provides another method for preparing a memory cell, comprising providing a magnetic material stack, the magnetic material stack comprising a first magnetic layer, a tunneling barrier layer, a second magnetic layer, and a fourth magnetic layer stacked in sequence from bottom to top; wherein the fourth magnetic layer has different polarization characteristics from the first and second magnetic layers; and forming a first contact member connected to the first magnetic layer; forming a third magnetic layer stacked on the magnetic material stack; wherein the spin directions of the first magnetic layer and the second magnetic layer are collinear, and the spin directions of the third magnetic layer and the fourth magnetic layer are collinear; patterning steps comprising directly performing a first patterning process on the third magnetic layer; and directly performing a second patterning process on the magnetic material stack using the patterned third magnetic layer; and forming a second contact member directly formed above the third magnetic layer to form a contact connection; wherein the third magnetic layer has a non-uniform material distribution in a vertical direction and a continuous sidewall morphology at least at a contact interface between the third magnetic layer and the magnetic material stack, so that the third magnetic layer always protects the magnetic material stack and fixes the magnetization direction of the fourth magnetic layer while providing a stable electrical contact.

[0114] Those skilled in the art should know that the details of the preparation method of the memory cell described in FIG. 6 and FIG. 7 and the aforementioned paragraphs can supplement the preparation method in this embodiment and will not be repeated here.

[0115] On the basis of the preparation of the semiconductor memory unit provided by the present invention, the logic structure of the switch can be prepared through an independent process, and the semiconductor memory unit can be connected to the switch structure through vertical interconnection, bonding, etc. to complete the preparation of the semiconductor memory array.

[0116] Based on the preparation of the semiconductor storage array provided by the present invention, controller functional blocks, chips or modules and other structures can be prepared through independent processes, and the semiconductor storage array can be connected to the control structure through an additional wiring substrate to complete the preparation of the semiconductor storage device.

[0117] It should be understood that, in the description of the present invention, the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0118] The applicant declares that the above content is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention fall within the protection scope and disclosure scope of the present invention.

Claims

1. A semiconductor storage unit, characterized in that: The semiconductor storage unit comprises: A magnetic material stack, wherein the magnetic material stack comprises a first magnetic layer, a tunnel barrier layer, and a second magnetic layer stacked in sequence from bottom to top; and a first contact member connected to the first magnetic layer; a third magnetic layer, the third magnetic layer being stacked on the magnetic material stack; a second contact member, the second contact member being in direct contact with the third magnetic layer; Wherein, the spin directions of the first magnetic layer, the second magnetic layer and the third magnetic layer are collinear; The third magnetic layer has a non-uniform material distribution in the vertical direction and has a continuous sidewall morphology at least at the contact interface between the third magnetic layer and the magnetic material stack, so that the third magnetic layer always protects the magnetic material stack and fixes the magnetization direction of the second magnetic layer while providing a stable electrical contact; The third magnetic layer includes a stacked third magnetic inner layer and a third magnetic cover layer, and the third magnetic cover layer at least continuously covers the top surface and a portion of the side wall of the third magnetic inner layer.

2. The semiconductor memory cell according to claim 1, wherein: A portion of the third magnetic layer that is in direct contact with the second contact is different from a portion of the third magnetic layer located at the contact interface.

3. The semiconductor memory cell according to claim 1, wherein: The third magnetic layer is a ferromagnetic material, an antiferromagnetic material or a ferrimagnetic material.

4. A semiconductor storage unit, characterized in that: The semiconductor storage unit comprises: A magnetic material stack, wherein the magnetic material stack comprises a first magnetic layer, a tunnel barrier layer, a second magnetic layer and a fourth magnetic layer stacked in sequence from bottom to top; and a first contact member, the first contact member being connected to the first magnetic layer; wherein the fourth magnetic layer and the second magnetic layer have different polarization characteristics; a third magnetic layer, the third magnetic layer being stacked on the magnetic material stack; a second contact member, the second contact member being in direct contact with the third magnetic layer; Wherein, the spin directions of the first magnetic layer and the second magnetic layer are collinear, and the spin directions of the third magnetic layer and the fourth magnetic layer are collinear; The third magnetic layer has a non-uniform material distribution in the vertical direction and has a continuous sidewall morphology at least at the contact interface between the third magnetic layer and the magnetic material stack, so that the third magnetic layer always protects the magnetic material stack and fixes the magnetization direction of the fourth magnetic layer while providing a stable electrical contact; The third magnetic layer includes a stacked third magnetic inner layer and a third magnetic cover layer, and the third magnetic cover layer at least continuously covers the top surface and a portion of the side wall of the third magnetic inner layer.

5. The semiconductor memory cell according to claim 4, wherein: A portion of the third magnetic layer that is in direct contact with the second contact is different from a portion of the third magnetic layer located at the contact interface.

6. The semiconductor memory cell according to claim 4, wherein: The first magnetic layer or the second magnetic layer comprises a plurality of stacked magnetic material layers, wherein at least two magnetic material layers have opposite polarization directions among the plurality of magnetic material layers, and the plurality of magnetic material layers have a fixed polarization direction.

7. The semiconductor memory cell according to claim 4, wherein: The third magnetic layer is a ferromagnetic material, an antiferromagnetic material or a ferrimagnetic material.

8. A method for preparing a semiconductor memory cell, characterized in that: The preparation method comprises: Providing a magnetic material stack, the magnetic material stack comprising a first magnetic layer, a tunnel barrier layer, and a second magnetic layer stacked sequentially from bottom to top; and forming a first contact, the first contact being connected to the first magnetic layer; A step of forming a third magnetic layer, wherein the third magnetic layer is stacked on the magnetic material stack; wherein the spin directions of the first magnetic layer, the second magnetic layer and the third magnetic layer are collinear; The patterning step includes directly performing a first patterning process on the third magnetic layer; and directly performing a second patterning process on the magnetic material stack using the patterned third magnetic layer; The step of forming a second contact, wherein the second contact is directly prepared to form a contact connection above the third magnetic layer; The third magnetic layer has a non-uniform material distribution in the vertical direction and has a continuous sidewall morphology at least at the contact interface between the third magnetic layer and the magnetic material stack, so that the ... non-uniform material distribution in the vertical direction. The material stack is always protected and the magnetization direction of the second magnetic layer is fixed while providing a stable electrical contact; The third magnetic layer includes a stacked third magnetic inner layer and a third magnetic cover layer, and the third magnetic cover layer at least continuously covers the top surface and a portion of the side wall of the third magnetic inner layer.

9. A method for preparing a semiconductor memory cell, characterized in that: The preparation method comprises: Providing a magnetic material stack, the magnetic material stack comprising a first magnetic layer, a tunnel barrier layer, a second magnetic layer and a fourth magnetic layer stacked in sequence from bottom to top; wherein the fourth magnetic layer has a different polarization characteristic from the second magnetic layer; and forming a first contact, the first contact being connected to the first magnetic layer; A step of forming a third magnetic layer, wherein the third magnetic layer is stacked on the magnetic material stack; wherein the spin directions of the first magnetic layer and the second magnetic layer are collinear, and the spin directions of the third magnetic layer and the fourth magnetic layer are collinear; The patterning step includes directly performing a first patterning process on the third magnetic layer; and directly performing a second patterning process on the magnetic material stack using the patterned third magnetic layer; The step of forming a second contact, wherein the second contact is directly prepared to form a contact connection above the third magnetic layer; The third magnetic layer has a non-uniform material distribution in the vertical direction and has a continuous sidewall morphology at least at the contact interface between the third magnetic layer and the magnetic material stack, so that the third magnetic layer always protects the magnetic material stack and fixes the magnetization direction of the fourth magnetic layer while providing a stable electrical contact; The third magnetic layer includes a stacked third magnetic inner layer and a third magnetic cover layer, and the third magnetic cover layer at least continuously covers the top surface and a portion of the side wall of the third magnetic inner layer.

10. A semiconductor storage array, characterized in that: It comprises a plurality of semiconductor memory cells as claimed in any one of claims 1 to 7; a switch component for addressing a single semiconductor memory cell, and a connection component for connecting the switch component to the semiconductor memory cell.

11. A semiconductor memory device, characterized in that: The method comprises the semiconductor memory array as claimed in claim 10; and a controller, wherein the controller controls the switch component.

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