Semiconductor device

Abstract

Provided is a semiconductor device capable of suppressing the occurrence of destruction. This semiconductor device is provided with a first electrode, a semiconductor layer, a second electrode, a gate electrode, and a third electrode. The semiconductor layer includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of the first conductivity type, and contains silicon carbide. The gate electrode faces the second semiconductor region across a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The gate electrode includes a first portion additionally facing the third semiconductor region, a second portion located at an end portion of the gate electrode in a third direction perpendicular to the first direction and the second direction, and a third portion located between the first portion and the second portion in the third direction. The impurity concentration of the second portion is lower than the impurity concentration of the third portion. The third electrode is electrically connected to the gate electrode and is spaced apart from the second electrode.

Description

Semiconductor Devices

[0001] FIELD An embodiment of the present invention relates to a semiconductor device.

[0002] There are semiconductor devices that use silicon carbide, and there is a demand for technology that can prevent the occurrence of breakdown in semiconductor devices.

[0003] Patent No. 7176206

[0004] The problem to be solved by the present invention is to provide a semiconductor device that can suppress the occurrence of breakdown.

[0005] The semiconductor device according to the embodiment includes a first electrode, a semiconductor layer, a second electrode, a gate electrode, and a third electrode. The semiconductor layer includes a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region. The semiconductor layer contains silicon carbide. The second electrode is provided on the second semiconductor region and the third semiconductor region. The gate electrode faces the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The gate electrode includes a first portion, a second portion, and a third portion. The first portion also faces the third semiconductor region. The second portion is located at an end of the gate electrode in a third direction perpendicular to the first and second directions. The third portion is located between the first and second portions in the third direction. The impurity concentration of the second portion is lower than the impurity concentration of the third portion. The third electrode includes a wiring portion provided on the third portion, and is electrically connected to the gate electrode and spaced apart from the second electrode.

[0006] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is an enlarged plan view of a portion II in FIG. 1. FIG. 3 is a cross-sectional view taken along III-III in FIG. 2. FIG. 4 is a cross-sectional view taken along IV-IV in FIG. 2. FIG. 5 is a cross-sectional view taken along V-V in FIG. 2. FIGS. 6(a) and 6(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. FIGS. 7(a) and 7(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. FIGS. 8(a) and 8(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. FIGS. 9(a) and 9(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. FIGS. 10(a) and 10(b) are plan views showing a second portion of a gate electrode. FIG. 11 is a plan view showing a portion of a semiconductor device according to a first modified example of the embodiment. FIG. 12 is a cross-sectional view taken along XII-XII in FIG. 11. FIG. 13 is a plan view showing a portion of a semiconductor device according to a second modified example of the embodiment. FIG. 14 is a cross-sectional view taken along XIV-XIV in FIG. 13.

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals, and detailed explanations will be omitted as appropriate. In the following description, n ＋ , n －－ and p ＋ , p, p － The notation indicates the relative level of the impurity concentration in each conductivity type. In other words, the impurity concentration indicated by a "+" sign is higher than the impurity concentration indicated by a notation without either a "+" or a "-" sign. The impurity concentration indicated by a notation without either a "+" or a "-" sign is lower than the impurity concentration indicated by a notation without either a "+" or a "-" sign. The impurity concentration indicated by a notation with a "- -" sign is lower than the impurity concentration indicated by a notation with a "-" sign. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is an enlarged plan view of a portion II in FIG. 1. FIGS. 3 to 5 are cross-sectional views taken along lines III-III, IV-IV, and V-V in FIG. 2, respectively. The semiconductor device according to the embodiment is a metal oxide semiconductor field effect transistor (MOSFET). As shown in FIGS. 1 to 5, the semiconductor device 1 according to the embodiment includes a semiconductor layer 10, a gate electrode 20, a first electrode 31, a second electrode 32, a third electrode 33, and an insulating layer 35.

[0009] In the description of the embodiment, an XYZ Cartesian coordinate system is used. The direction from the first portion 21 toward the semiconductor layer 10 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (third direction) and the Y direction (second direction). For the sake of explanation, the direction from the first portion 21 toward the semiconductor layer 10 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the first portion 21 and the semiconductor layer 10 and are unrelated to the direction of gravity.

[0010] 1, a second electrode 32 and a third electrode 33 are provided on the top surface of the semiconductor device 1. The second electrode 32 and the third electrode 33 are spaced apart and electrically isolated from each other. The third electrode 33 includes a wiring portion 33a extending in one direction and a pad portion 33b extending along the XY plane. The wiring portion 33a is electrically connected to the pad portion 33b. A bonding wire or the like is connected to the pad portion 33b. The outer periphery of the semiconductor device 1 is covered with an insulating layer 35.

[0011] 2, the semiconductor layer 10, the gate electrode 20, etc. are provided below the second electrode 32 and the third electrode 33. In FIG. 2, the insulating layer 35 is omitted, and the second electrode 32 and the wiring portion 33a are indicated by dashed lines.

[0012] 3 to 5, a first electrode 31 is provided on the lower surface of the semiconductor device 1. The semiconductor layer 10 is provided on the first electrode 31.

[0013] The semiconductor layer 10 is －－type (first conductivity type) drift region 11 (first semiconductor region), p － type (second conductivity type) base region 12 (second semiconductor region), n ＋ a p-type source region 13 (third semiconductor region), a p-type shield region 14 (fourth semiconductor region), and ＋ Contact regions 15a, p ＋ contact region 15b, and ＋ The semiconductor substrate 10 includes a drain region 16 .

[0014] n ＋ The drain region 16 is provided on the first electrode 31 and is electrically connected to the first electrode 31. －－ The drift region 11 is ＋ The n-type drain region 16 is provided on the n-type drain region 16. －－ The n-type impurity concentration of the n-type drift region 11 is ＋ The n-type impurity concentration of the n-type drain region 16 is lower than that of the n-type impurity of the n-type drain region 16 .

[0015] p － The base region 12 is n －－ The n-type semiconductor layer 11 is provided on the n-type drift region 11. ＋ The source region 13 and p ＋ The contact region 15a is p － The conductive layer 14 is selectively provided on the base region 12. ＋ The p-type impurity concentration of the p-type contact region 15a is － The p-type impurity concentration is higher than that of the p-type base region 12 .

[0016] As shown in FIGS. 2 to 4, the gate electrode 20 is formed in a p － The gate electrode 20 faces the n-type base region 12. The gate electrode 20 includes a first portion 21, a second portion 22, and a third portion 23. As shown in FIGS. 2 and 3, the first portion 21 is connected to the n-type base region 12 via a gate insulating layer 25. ＋ 2 and 5 , the second portion 22 is located at an end of the gate electrode 20 in the X direction and is spaced apart from the first portion 21. The third portion 23 is located between the first portion 21 and the second portion 22 in the X direction.

[0017] The gate electrode 20 is conductive and contains polysilicon and impurities. The impurities contained in the gate electrode 20 may be n-type or p-type. In the gate electrode 20, the impurity concentration of the second portion 22 is lower than the impurity concentration of the first portion 21 and lower than the impurity concentration of the third portion 23.

[0018] The length of the first portion 21 in the X direction is longer than the lengths of the second portion 22 and the third portion 23 in the X direction. For example, the length of the third portion 23 in the Z direction is longer than the lengths of the first portion 21 and the second portion 22 in the Z direction.

[0019] 2, 4, and 5, the wiring portion 33a is located on the third portion 23. The wiring portion 33a is in contact with the third portion 23, whereby the third electrode 33 is electrically connected to the gate electrode 20.

[0020] The p-type shield region 14 is n-type in the Z direction. －－ The p-type shield region 14 is provided between the p-type drift region 11 and the gate electrode 20 and is in contact with the gate insulating layer 25. The p-type impurity concentration of the p-type shield region 14 is － 2 and 5, a part of the p-type shield region 14 faces the second portion 22 in the X direction, and the p-type impurity concentration is higher than that of the p-type base region 12. － It is connected to the shape base area 12 .

[0021] As shown in FIG. 3, the second electrode 32 has n ＋ The source region 13 and p ＋ Located on the contact region 15a, － Shape base region 12,n ＋ shaped source region 13, and p ＋ The gate electrode 20 is electrically connected to the contact region 15a. An insulating layer 35 is provided between the gate electrode 20 and the second electrode 32, and the gate electrode 20 and the second electrode 32 are electrically isolated from each other.

[0022] As shown in FIG. － Shape base region 12,n ＋ Shape source region 13, p ＋A plurality of the contact regions 15a and gate electrodes 20 are provided in the Y direction. － Shape base region 12, each n ＋ Shape source region 13, each p ＋ The contact region 15a and each gate electrode 20 extend in the X direction. The wiring portion 33a extends in the Y direction over the third portions 23.

[0023] p ＋ The contact region 15b is p － A plurality of p ＋ Each p ＋ The end of the contact region 15a in the X direction is p ＋ It is connected to the contact region 15b. ＋ A part of the second electrode 32 is provided on the contact region 15b. ＋ The contact region 15 b is electrically connected to the second electrode 32 .

[0024] An example of the material of each component will be described. The semiconductor layer 10 contains silicon carbide. Arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The gate electrode 20 is conductive and contains polysilicon and impurities. The gate insulating layer 25 and the insulating layer 35 contain an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The first electrode 31, the second electrode 32, and the third electrode 33 contain a metal such as aluminum.

[0025] The operation of the semiconductor device 1 will be described. With a positive voltage applied to the first electrode 31 relative to the second electrode 32, a voltage equal to or higher than the threshold is applied to the gate electrode 20. － A channel (inversion layer) is formed in the base region 12, and the semiconductor device 1 is turned on. Electrons pass through the channel from the second electrode 32 to the n-type inverted layer. －－ The electrons flow into the drift region 11 and move toward the first electrode 31. This causes a current to flow through the semiconductor device 1. When the voltage applied to the gate electrode 20 becomes lower than the threshold voltage, －The channel in the base region 12 disappears, and the semiconductor device 1 is turned off.

[0026] 6(a) to 9(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. 6(a) to 9(b) show the manufacturing steps in the VV cross section of FIG. 2. First, n ＋ The semiconductor layers 16x and n －－ A semiconductor substrate including a semiconductor layer 11x is prepared. －－ The semiconductor layer 11x is ＋ The semiconductor layer 16x is provided on the semiconductor layer 16x. －－ As shown in FIG. 6A, p-type impurities are ion-implanted into a predetermined region on the p-type semiconductor layer 11x. － type semiconductor region 12x, p-type semiconductor region 14x, and p-type semiconductor region 12x, ＋ 2 and 3, n-type impurities and p-type impurities are ion-implanted sequentially into regions not shown in the figure, thereby forming n-type semiconductor regions 15x. ＋ The source region 13 and p ＋ A contact region 15a is formed. ＋ The contact region 15a is p ＋ The insulating layer 15 may be formed simultaneously with the semiconductor region 15x.

[0027] n －－ A part of the semiconductor layer 11x and p － A portion of the p-type semiconductor region 12x is removed to form an opening OP. A p-type semiconductor region 14x is located at the bottom of the opening OP. A plurality of openings OP are formed in the Y direction, and each opening OP extends in the X direction. P-type impurities are ion-implanted into the side surface of the opening OP in the X direction to form a p-type semiconductor region 14y, as shown in FIG. 6(b).

[0028] Thereafter, post-processing of the opening OP is performed. In the post-processing, annealing or chemical dry etching (CDE) is performed in a hydrogen atmosphere. By the post-processing, the corners at the bottom of the opening OP are smoothed and the curvature of the corners is reduced. Then, the implanted impurities are activated by heat treatment.

[0029] By chemical vapor deposition (CVD), －An insulating layer 35x is formed on the outer periphery of the semiconductor region 12x. An insulating layer 25x is formed by CVD along the inner surface of the opening OP and the surface of the insulating layer 35x. Polysilicon is deposited by CVD on the insulating layer 25x to form a conductive layer 20x. As shown in FIG. 7A, the opening OP is filled with the conductive layer 20x.

[0030] As shown in FIG. 7A, the conductive layer 20x includes a central portion p1, an end portion p2, an intermediate portion p3, and an outer peripheral portion p4. The central portion p1, the end portion p2, and the intermediate portion p3 are located inside the opening OP. The end portion p2 is located at the end of the opening OP in the X direction. The intermediate portion p3 is located between the central portion p1 and the intermediate portion p3. The outer peripheral portion p4 is located above the central portion p1, the end portion p2, and the intermediate portion p3, and － The semiconductor region 12x is located on the outer periphery of the semiconductor region 12x.

[0031] 7B, a protective film 36 is formed to cover the end portion p2 and the outer peripheral portion p4. The central portion p1 and the intermediate portion p3 are exposed and not covered by the protective film 36. Any material may be used for the protective film 36, and for example, silicon oxide or silicon nitride may be used.

[0032] With the end portion p2 and the outer peripheral portion p4 covered, the impurities are diffused into the central portion p1 and the intermediate portion p3. As a specific example, the impurities are diffused into the central portion p1 and the intermediate portion p3 of the conductive layer 20x by performing a heat treatment in a gas atmosphere containing impurities. For example, a gas containing POC13 (phosphorus chloride) is used. After depositing an impurity-containing layer on the conductive layer 20x and the protective film 36, the impurities may be diffused from the impurity-containing layer into the conductive layer 20x by performing a heat treatment.

[0033] Impurities diffuse into the end portion p2 and the outer peripheral portion p4 through the central portion p1 and the intermediate portion p3. Therefore, the impurity concentrations of the end portion p2 and the outer peripheral portion p4 are lower than the impurity concentration of the central portion p1 and lower than the impurity concentration of the intermediate portion p3. An impurity concentration gradient is formed in the end portion p2 in the direction from the central portion p1 to the end portion p2.

[0034] The protective film 36 is removed. The outer peripheral portion p4 is removed, and the upper surfaces of the central portion p1 and the end portion p2 are recessed. As a result, as shown in FIG. 8A, the upper surface of the intermediate portion p3 is positioned higher than the upper surfaces of the central portion p1 and the end portion p2.

[0035] An insulating layer 35y is formed by CVD to cover the conductive layer 20x and the insulating layer 25x. By removing a part of the insulating layer 35y, intermediate portions p3 and p4 are formed as shown in FIG. ＋ The semiconductor region 15x is exposed.

[0036] A metal layer is formed on the insulating layer 35y by sputtering. The metal layer is patterned to form the second electrode 32 and the third electrode 33, as shown in FIG. 9(a). ＋ The n-type semiconductor layer 16x is then grown to a predetermined thickness. ＋ 9B, the first electrode 31 is formed on the ground back surface by sputtering. Through the above steps, the semiconductor device 1 according to the embodiment is manufactured.

[0037] The advantages of the embodiment will be described. When the semiconductor device 1 is used, a voltage is applied to the gate electrode 20. For example, a negative voltage may be applied to the gate electrode 20 with respect to the first portion 21 and the second portion 22. At this time, n －－ The potential difference between the drift region 11 and the gate electrode 20 increases, and the electric field strength near the gate electrode 20 increases. In particular, the electric field strength tends to be higher near the second portion 22 located at the end of the gate electrode 20 than in other portions. When the electric field concentrates near the second portion 22, dielectric breakdown occurs in the gate insulating layer 25. The first electrode 31 and the third electrode 33 become conductive, and the semiconductor device 1 is destroyed.

[0038] 10(a) and 10(b) are plan views showing the second portion of the gate electrode. In particular, when the semiconductor layer 10 contains silicon carbide, breakdown is more likely to occur near the second portion 22 for the following reasons. As described in the manufacturing method, after the opening OP is formed, post-processing of the opening OP is performed. The post-processing reduces the curvature of the corner at the bottom of the opening OP. This reduces the curvature of the corner at the bottom of the gate electrode 20 to be formed later. As a result, when a voltage is applied to the gate electrode 20, electric field concentration at the corner at the bottom of the gate electrode 20 can be suppressed.

[0039] On the other hand, when the semiconductor layer 10 contains silicon carbide, a surface parallel to the plane orientation of the silicon carbide appears at the X-direction end of the opening OP due to post-processing. As a result, the gate electrode 20 and the gate insulating layer 25 also have surfaces parallel to the plane orientation of the silicon carbide. In the example of FIG. 10( a), the gate insulating layer 25 has a side surface S1, a side surface S2, an end surface E1, and an end surface E2. The side surfaces S1 and S2 are parallel to the X-Z plane. The end surfaces E1 and E2 are inclined with respect to the X-Z plane. In the example of FIG. 10( b), the gate insulating layer 25 has a side surface S1, a side surface S2, and end surfaces E3 to E5. The end surfaces E3 and E5 are inclined with respect to the X-Z plane. The end surface E4 is parallel to the Y-Z plane. The end surfaces E1 to E5 are substantially parallel to the crystal plane of the silicon carbide. The appearance of the end surfaces E1 to E5 increases the curvature of the corners between the surfaces. This makes it easier for electric field concentration to occur in the vicinity of the second portion 22 .

[0040] In the semiconductor device 1 according to the embodiment, the impurity concentration of the second portion 22 is lower than the impurity concentration of the third portion 23. Therefore, the electrical resistivity of the second portion 22 is higher than the electrical resistivity of the third portion 23. When a voltage is applied to the gate electrode 20, a current flows less easily through the second portion 22 than through the first portion 21 and the third portion 23. The voltage of the second portion 22 can be made lower than the voltages of the first portion 21 and the third portion 23, respectively. This reduces the electric field strength near the second portion 22. As a result, the gate insulating layer 25 is less susceptible to dielectric breakdown, and breakdown of the semiconductor device 1 can be suppressed.

[0041] Furthermore, the wiring portion 33a is connected to a third portion 23 that is separate from the second portion 22. The impurity concentration of the third portion 23 is higher than the impurity concentration of the second portion 22. Therefore, even if the impurity concentration of the second portion 22 is reduced, an increase in the electrical resistance between the gate electrode 20 and the wiring portion 33a can be suppressed.

[0042] According to the embodiment, it is possible to suppress an increase in the electrical resistance of the gate electrode 20 and also to suppress the occurrence of breakdown of the semiconductor device 1 .

[0043] The impurity concentration of the second portion 22 is preferably less than 0.5 times the impurity concentration of the third portion 23. This effectively suppresses an increase in voltage in the second portion 22 compared to the first portion 21 and the third portion 23, and sufficiently reduces the electric field strength near the second portion 22. More preferably, the impurity concentration of the second portion 22 is greater than 0.001 times and less than 0.1 times the impurity concentration of the third portion 23.

[0044] The gate electrode 20 preferably contains phosphorus. By using phosphorus, the electrical resistance of the gate electrode 20 can be reduced and the threshold voltage can be lowered compared to when other impurities are used.

[0045] The semiconductor layer 10 preferably includes a p-type shield region 14. The p-type shield region 14 is an n －－ The p-type shield region 14 is provided between the p-type drift region 11 and the gate electrode 20. The provision of the p-type shield region 14 can reduce the electric field strength near the bottom of the gate electrode 20, thereby further suppressing the occurrence of dielectric breakdown in the gate insulating layer 25. In particular, the p-type shield region 14 faces at least a part of the second portion 22 via the gate insulating layer 25, thereby further reducing the electric field strength near the second portion 22.

[0046] (First Modification) Fig. 11 is a plan view showing a portion of a semiconductor device according to a first modification of the embodiment. Fig. 12 is a cross-sectional view taken along the line XII-XII of Fig. 11. Note that in Fig. 11, the insulating layer 35 is omitted, and the second electrode 32 and the wiring portion 33a are indicated by dashed lines. In the semiconductor device 2 according to the first modification, as shown in Figs. 11 and 12, a portion of the p-type shield region 14 faces the second portion 22 in the Y direction via the gate insulating layer 25. This portion of the p-type shield region 14 is p － The p-type shield region 14 is connected to the p-type base region 12. A part of the p-type shield region 14 may further face the third portion 23.

[0047] In the illustrated example, the p-type shield region 14 is provided on both sides of the second portion 22 in the Y direction. The p-type shield region 14 may be provided only on one side of the second portion 22 in the Y direction. － The arrangement of the part connected to the shape base region 12 can be changed as appropriate.

[0048] (Second Modification) Fig. 13 is a plan view showing a portion of a semiconductor device according to a second modification of the embodiment. Fig. 14 is a cross-sectional view taken along line XIV-XIV of Fig. 13. Note that in Fig. 13, the insulating layer 35 is omitted, and the second electrode 32 and the wiring portion 33a are indicated by dashed lines. In the semiconductor device 3 according to the second modification, as shown in Figs. 13 and 14, the gate insulating layer 25 includes a first insulating region 25a and a second insulating region 25b.

[0049] The first insulating region 25a is provided between the semiconductor layer 10 and the gate electrode 20 in the Y direction. The first insulating region 25a contacts the first portion 21, the second portion 22, and the third portion 23 in the Y direction. The second insulating region 25b is provided between the semiconductor layer 10 and the gate electrode 20 in the X direction. The second insulating region 25b contacts the second portion 22 in the X direction.

[0050] The thickness of the second insulating region 25b is greater than the thickness of the first insulating region 25a. The thickness of the first insulating region 25a corresponds to the distance between the semiconductor layer 10 and the gate electrode 20 in the Y direction. The thickness of the second insulating region 25b corresponds to the distance between the semiconductor layer 10 and the gate electrode 20 in the X direction.

[0051] After forming the opening OP as shown in Fig. 6B, an insulating layer is formed only on the end portion of the opening OP in the Y direction. Thereafter, the same method as that shown in Fig. 7A and subsequent steps is carried out. This forms the gate insulating layer 25 including the second insulating region 25b that is thicker than the other portions.

[0052] The gate insulating layer 25 includes the second insulating region 25b, which further reduces the electric field strength in the vicinity of the second portion 22. According to the second modification, the occurrence of breakdown in the semiconductor device 3 can be further suppressed compared to the semiconductor device 1.

[0053] Embodiments of the present invention may include the following configurations: (Configuration 1) A semiconductor device comprising: a first electrode; a semiconductor layer containing silicon carbide, the semiconductor layer including: a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, the gate electrode including: a first portion further facing the third semiconductor region, a second portion located at an end of the gate electrode in a third direction perpendicular to the first direction and the second direction, and a third portion located between the first portion and the second portion in the third direction, the second portion having an impurity concentration lower than an impurity concentration of the third portion; and a third electrode including a wiring portion provided on the third portion, electrically connected to the gate electrode and separated from the second electrode. (Structure 2) The semiconductor device according to Structure 1, wherein the semiconductor layer further includes a fourth semiconductor region of the second conductivity type provided between the first semiconductor region and the gate electrode, and the fourth semiconductor region is connected to the second semiconductor region. (Structure 3) The semiconductor device according to Structure 2, wherein a part of the fourth semiconductor region faces the third portion via the gate insulating layer in the second direction or the third direction. (Structure 4) The semiconductor device according to any one of Structures 1 to 3, wherein the impurity concentration of the second portion is less than 0.5 times the impurity concentration of the third portion. (Structure 5) The semiconductor device according to any one of Structures 1 to 4, wherein a plurality of the gate electrodes are provided in the second direction, and the wiring portion is located on a plurality of the third portions. (Structure 6) The semiconductor device according to any one of Structures 1 to 5, wherein the gate insulating layer includes a first insulating region provided between the gate electrode and the semiconductor layer in the second direction and a second insulating region provided between the gate electrode and the semiconductor layer in the third direction, and wherein a thickness of the second insulating region is greater than a thickness of the first insulating region.(Structure 7) The semiconductor device according to any one of structures 1 to 6, wherein the length of the third portion in the first direction is longer than the length of the first portion in the second direction and longer than the length of the second portion in the second direction.

[0054] According to the embodiment described above, it is possible to suppress an increase in the electrical resistance of the gate electrode and also to suppress the occurrence of breakdown of the semiconductor device.

[0055] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS).

[0056] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other.

[0057] 1 to 3: semiconductor device, 10: semiconductor layer, 11: n －－ Shape drift region, 11x:n －－ Semiconductor layer, 12:p － Shape base area, 12x:p － Semiconductor region, 13:n ＋ p-type source region, 14: p-type shield region, 14x, 14y: p-type semiconductor region, 15a, 15b: p ＋ Shape contact area, 15x:p ＋ Semiconductor region, 16:n＋ shaped drain region, 16x:n ＋ Semiconductor layer, 20: gate electrode, 20x: conductive layer, 21: first portion, 22: second portion, 23: third portion, 25: gate insulating layer, 25a: first insulating region, 25b: second insulating region, 25x: insulating layer, 31: first electrode, 32: second electrode, 33: third electrode, 33a: wiring portion, 33b: pad portion, 35, 35x, 35y: insulating layer, 36: protective film, 100: semiconductor device, E1 to E5: end face, OP: opening, S1, S2: side face, p1: central portion, p2: end portion, p3: intermediate portion, p4: outer periphery

Claims

a semiconductor layer containing silicon carbide, the semiconductor layer including a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode to the first semiconductor region, the gate electrode including a first portion further facing the third semiconductor region, a second portion located at an end of the gate electrode in a third direction perpendicular to the first direction and the second direction, and a third portion located between the first portion and the second portion in the third direction, the gate electrode having an impurity concentration of the second portion lower than an impurity concentration of the third portion; and a third electrode including a wiring portion provided on the third portion, electrically connected to the gate electrode and separated from the second electrode.

2. The semiconductor device according to claim 1, wherein the semiconductor layer further includes a fourth semiconductor region of a second conductivity type provided between the first semiconductor region and the gate electrode, and the fourth semiconductor region is connected to the second semiconductor region.

3. The semiconductor device according to claim 2, wherein a portion of said fourth semiconductor region faces said third portion in said second direction or said third direction via said gate insulating layer.

4. The semiconductor device according to claim 1, wherein the impurity concentration of the second portion is less than 0.5 times the impurity concentration of the third portion.

5. The semiconductor device according to claim 1, wherein a plurality of the gate electrodes are provided in the second direction, and the wiring portion is located above a plurality of the third portions.

6. The semiconductor device described in any one of claims 1 to 3, wherein the gate insulating layer includes a first insulating region provided between the gate electrode and the semiconductor layer in the second direction, and a second insulating region provided between the gate electrode and the semiconductor layer in the third direction, and a thickness of the second insulating region is greater than a thickness of the first insulating region.

7. A semiconductor device according to any one of claims 1 to 3, wherein the length of the third portion in the first direction is longer than the length of the first portion in the second direction and longer than the length of the second portion in the second direction.

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