Semiconductor package

Abstract

The present disclosure relates to a semiconductor package. The semiconductor package comprises: a first semiconductor chip; at least one second semiconductor chip; and a switch protection circuit, wherein the switch protection circuit has a first end connected to the first semiconductor chip, and a second end connected to each of the second semiconductor chips, and is in an off state when charged-device model (CDM) discharge of the semiconductor package is implemented, so as to disconnect the connection between the first semiconductor chip and the second semiconductor chips. Thus, the probability that electrostatic discharge causes a semiconductor package to be burned out when CDM discharge of the semiconductor package is implemented is reduced.

Description

A semiconductor package Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a semiconductor package. Background Art

[0002] Integrated circuit (IC) chips are susceptible to destructive electrostatic discharge (ESD) during manufacturing, assembly, and testing, as well as in final applications. Currently, ESD protection for IC chips still needs to be further optimized to meet demand.

[0003] Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor chip and a semiconductor package.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor package, comprising:

[0006] a first semiconductor chip;

[0007] at least one second semiconductor chip; and

[0008] A switch protection circuit, wherein a first end of the switch protection circuit is connected to the first semiconductor chip, a second end of the switch protection circuit is connected to each of the second semiconductor chips, and when the semiconductor package performs a charge device model (CDM) discharge, the switch protection circuit is in an off state to disconnect the first semiconductor chip from the second semiconductor chip.

[0009] In the above solution, when the semiconductor package operates normally, the switch protection circuit is in an on state to connect the first semiconductor chip and the second semiconductor chip.

[0010] In the above solution, the switch protection circuit is provided in the first semiconductor chip and includes: a first sub-circuit;

[0011] A first end of the first sub-circuit is connected to a first node in the first semiconductor chip, a second end of the first sub-circuit is connected to a second node in the first semiconductor chip, a control end of the first sub-circuit receives a first control signal, and when the first control signal is in a first state, the first sub-circuit is in a disconnected state, or when the first control signal is in a second state, the first sub-circuit is in a connected state;

[0012] When the first sub-circuit is in an off state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the first sub-circuit is in an on state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

[0013] In the above solution, the switch protection circuit further includes: a second sub-circuit; wherein the second sub-circuit includes a first capacitive element, a first end of the first capacitive element is connected between the second end of the first sub-circuit and a second node in the first semiconductor chip, and a second end of the first capacitive element is connected to a third node in the first semiconductor chip;

[0014] The control terminal of the first sub-circuit is connected between the second terminal of the first capacitive element and the third node.

[0015] In the above solution, the switch protection circuit further includes: a second sub-circuit; wherein the second sub-circuit includes a second capacitive element, a first end of the second capacitive element is connected between the second end of the first sub-circuit and the second node of the first semiconductor chip; and a second end of the second capacitive element is connected to a first node in a second semiconductor chip;

[0016] The control terminal of the first sub-circuit is connected between the second terminal of the second capacitive element and a first node in the second semiconductor chip.

[0017] In the above solution, the second sub-circuit further includes: a first resistive element, a first end of the first resistive element being connected to the third node in the first semiconductor chip; a second end of the first resistive element being connected to the second end of the first capacitive element;

[0018] The control terminal of the first sub-circuit is connected between the second terminal of the first capacitive element and the second terminal of the first resistive element.

[0019] In the above solution, the second sub-circuit further includes: a second resistive element, wherein a first end of the second resistive element is connected to a first node in the second semiconductor chip; a second end of the second resistive element is connected to a second end of the second capacitive element;

[0020] The control terminal of the first sub-circuit is connected between the second terminal of the second capacitive element and the second terminal of the second resistive element.

[0021] In the above solution, the first sub-circuit includes: a first N-type metal oxide semiconductor (NMOS) transistor.

[0022] In the above solution, wherein the first resistive element comprises at least one resistor connected in series; the first capacitive element comprises at least one capacitor connected in series;

[0023] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value ranging from 1 nanosecond to 1 microsecond.

[0024] In the above solution, the second resistive element includes at least one resistor connected in series; the second capacitive element includes at least one capacitor connected in series;

[0025] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value ranging from 1 nanosecond to 1 microsecond.

[0026] In the above scheme, the first node in the first semiconductor chip is connected to the ground pad (PAD) in the first semiconductor chip; the second node in the first semiconductor chip is connected to the ground pin of the first semiconductor chip; and the third node in the first semiconductor chip is connected to the power PAD in the first semiconductor chip.

[0027] In the above scheme, the first node in the first semiconductor chip is connected to the ground pad (PAD) in the first semiconductor chip; the second node in the first semiconductor chip is connected to the ground pin of the first semiconductor chip; and the first node in a certain second semiconductor chip is connected to the power PAD in a certain second semiconductor chip.

[0028] In the above solution, the switch protection circuit is provided in each second semiconductor chip and includes: a third sub-circuit; wherein,

[0029] A first end of the third sub-circuit is connected to a second node in the second semiconductor chip, a second end of the third sub-circuit is connected to a third node in the second semiconductor chip, a control end of the third sub-circuit receives a second control signal, and when the second control signal is in a first state, the third sub-circuit is in an off state, or when the second control signal is in a second state, the third sub-circuit is in an on state;

[0030] When the third sub-circuit is in an off state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the third sub-circuit is in an on state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

[0031] In the above solution, the switch protection circuit further includes: a fourth sub-circuit; wherein the fourth sub-circuit includes a third capacitive element, a first end of the third capacitive element is connected between the second end of the third sub-circuit and a third node in the second semiconductor chip, and a second end of the third capacitive element is connected to the first node in the second semiconductor chip;

[0032] The control terminal of the third sub-circuit is connected between the second terminal of the third capacitive element and a first node in the second semiconductor chip.

[0033] In the above solution, the switch protection circuit further includes: a fourth sub-circuit; wherein the fourth sub-circuit includes a fourth capacitive element, a first end of the fourth capacitive element is connected between the second end of the third sub-circuit and a third node in the second semiconductor chip; and a second end of the fourth capacitive element is connected to the third node in the first semiconductor chip;

[0034] The control terminal of the third sub-circuit is connected between the second terminal of the fourth capacitive element and a third node in the first semiconductor chip.

[0035] In the above solution, the fourth sub-circuit further includes a third resistive element; wherein a first end of the third resistive element is connected to a first node in the second semiconductor chip; and a second end of the third resistive element is connected to a second end of the third capacitive element;

[0036] The control terminal of the third sub-circuit is connected between the second terminal of the third capacitive element and the second terminal of the third resistive element.

[0037] In the above solution, the fourth sub-circuit further includes a fourth resistive element; wherein a first end of the fourth resistive element is connected to a third node in the first semiconductor chip; and a second end of the fourth resistive element is connected to a second end of the fourth capacitive element;

[0038] The control terminal of the third sub-circuit is connected between the second terminal of the fourth capacitive element and the second terminal of the fourth resistive element.

[0039] In the above solution, the third sub-circuit includes a second N-type metal oxide semiconductor (NMOS) transistor.

[0040] In the above solution, the third resistive element includes at least one resistor connected in series; the third capacitive element includes at least one capacitor connected in series;

[0041] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value ranging from 1 nanosecond to 1 microsecond.

[0042] In the above solution, the fourth resistive element includes at least one resistor connected in series; the fourth capacitive element includes at least one capacitor connected in series;

[0043] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value ranging from 1 nanosecond to 1 microsecond.

[0044] In the above solution, the substrate of the first NMOS transistor and the substrate of the first semiconductor chip are isolated by a deep N well (DNW).

[0045] In the above solution, the substrate of the second NMOS transistor and the substrate of the second semiconductor chip are isolated by a deep N well (DNW).

[0046] In the above solution, the first semiconductor chip includes an interface chip; the second semiconductor chip includes a NAND flash memory chip.

[0047] In a second aspect, the present disclosure also provides another semiconductor package, including:

[0048] A packaging shell; the packaging shell is provided with a first pin capable of performing charge device model (CDM) discharge;

[0049] A first semiconductor chip is located in the packaging shell; and

[0050] at least one second semiconductor chip located in the package shell and each second semiconductor chip connected to the first semiconductor chip via an N-type metal oxide semiconductor (NMOS) transistor;

[0051] The NMOS transistor is arranged in the first semiconductor chip or each of the second semiconductor chips; and the control terminal of the NMOS transistor is connected to a control signal; the state of the control signal is controlled by whether the first pin performs charge device model (CDM) discharge control.

[0052] In the above solution, wherein the NMOS transistor is provided in the first semiconductor chip;

[0053] The first end of the NMOS transistor is connected to the first node in the first semiconductor chip, the second end of the NMOS transistor is connected to the second node in the first semiconductor chip, and the control end of the NMOS transistor is connected to the control signal; wherein, the second node in the first semiconductor chip is connected to the first pin of the first semiconductor chip; the first semiconductor chip is also connected to each of the second semiconductor chips through the first pin of the first semiconductor chip.

[0054] In the above solution, a first capacitive element is further provided in the first semiconductor chip, a first end of the first capacitive element is connected between the second end of the NMOS transistor and the first pin of the first semiconductor chip; a second end of the first capacitive element is connected to a third node in the first semiconductor chip;

[0055] The control terminal of the NMOS transistor is connected between the second terminal of the first capacitive element and a third node in the first semiconductor chip;

[0056] When the first pin of the semiconductor package performs CDM discharge, the third node in the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the first capacitive element; when the first pin of the semiconductor package performs normal operation, the third node in the first semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the first capacitive element.

[0057] In the above solution, a second capacitive element is further provided in the first semiconductor chip, wherein a first end of the second capacitive element is connected between the second end of the NMOS transistor and the first pin of the first semiconductor chip; a second end of the second capacitive element is connected to the first pin of the second semiconductor chip via the second pin of the first semiconductor chip;

[0058] The control terminal of the NMOS transistor is connected between the second terminal of the second capacitive element and the first pin of the second semiconductor chip;

[0059] When the first pin of the semiconductor package performs CDM discharge, the first pin of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the second capacitive element; when the first pin of the semiconductor package performs normal operation, the first pin of the second semiconductor chip is connected to a power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the second capacitive element.

[0060] In the above solution, a first resistive element is further provided in the first semiconductor chip;

[0061] The first end of the first resistive element is connected to a third node in the first semiconductor chip; the second end of the first resistive element is connected to the second end of the first capacitive element;

[0062] The control terminal of the NMOS transistor is connected between the second terminal of the first capacitive element and the second terminal of the first resistive element.

[0063] In the above solution, a second resistive element is also provided in the first semiconductor chip;

[0064] The first end of the second resistive element is connected to the first pin of the second semiconductor chip via the second pin of the first semiconductor chip; the second end of the second resistive element is connected to the second end of the second capacitive element;

[0065] The control terminal of the NMOS transistor is connected between the second terminal of the second capacitive element and the second terminal of the second resistive element.

[0066] In the above scheme, the NMOS transistor is arranged in each second semiconductor chip; in a certain second semiconductor chip, the first end of the NMOS transistor is connected to the second node in the second semiconductor chip, the second end of the NMOS transistor is connected to the third node in the second semiconductor chip, and the control end of the NMOS transistor is connected to the control signal; wherein the third node in the second semiconductor chip is connected to the second pin of the second semiconductor chip, and the second semiconductor chip is also connected to the first semiconductor chip through the second pin in the second semiconductor chip.

[0067] In the above solution, a third capacitive element is provided in the second semiconductor chip, a first end of the third capacitive element is connected between the second end of the NMOS transistor and the second pin of the second semiconductor chip, and a second end of the third capacitive element is connected to a first node in the second semiconductor chip;

[0068] The control terminal of the NMOS transistor is connected between the second terminal of the third capacitive element and a first node in the second semiconductor chip;

[0069] When the first pin of the semiconductor package performs CDM discharge, the first node of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the first node of the second semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element.

[0070] In the above solution, the first semiconductor chip is further provided with a fourth capacitive element, a first end of the fourth capacitive element is connected between the second end of the NMOS transistor and the second pin of the second semiconductor chip, and a second end of the fourth capacitive element is connected to the third pin of the first semiconductor chip via the third pin of the second semiconductor chip;

[0071] When the first pin of the semiconductor package performs CDM discharge, the third pin of the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the third pin of the first semiconductor chip is connected to a power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element.

[0072] In the above solution, wherein the second semiconductor chip is further provided with a third resistive element, wherein;

[0073] A first end of the third resistive element is connected to a first node in the second semiconductor chip, and a second end of the third resistive element is connected to a second end of the third capacitive element;

[0074] The control terminal of the NMOS transistor is connected between the second terminal of the third resistive element and the second terminal of the third capacitive element.

[0075] In the above solution, a fourth resistive element is further provided in the second semiconductor chip, wherein;

[0076] The first end of the fourth resistive element is connected to the third pin of the first semiconductor chip via the third pin of the second semiconductor chip, and the second end of the fourth resistive element is connected to the second end of the fourth capacitive element;

[0077] The control terminal of the NMOS transistor is connected between the second terminal of the fourth resistive element and the second terminal of the fourth capacitive element.

[0078] In the above solution, the first pin of the semiconductor package includes an input pin or an output pin.

[0079] In the above solution, the first pin of the first semiconductor chip includes a ground pin; the second pin of the first semiconductor chip and the first pin of the second semiconductor chip include power pins.

[0080] In the above solution, the second pin of the second semiconductor chip includes a ground pin; the third pin of the first semiconductor chip and the third pin of the first semiconductor chip include power pins.

[0081] In the above solution, the first semiconductor chip is an interface chip; the second semiconductor chip is a NAND flash memory chip.

[0082] An embodiment of the present disclosure provides a semiconductor package, comprising: a first semiconductor chip; at least one second semiconductor chip; and a switch protection circuit, wherein a first end of the switch protection circuit is connected to the first semiconductor chip, and a second end of the switch protection circuit is connected to each of the second semiconductor chips. The switch protection circuit is in an off state during a Charged Device Model (CDM) discharge, thereby disconnecting the first and second semiconductor chips. The semiconductor package provided by the embodiment of the present disclosure can disconnect the switch protection circuit during CDM discharge, thereby disconnecting the first and second semiconductor chips, thereby preventing a breakdown failure of the semiconductor chip caused by a large amount of static charge carried by the first or second semiconductor chip being connected to ground through a pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] In the accompanying drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0084] FIG1 is an exemplary system block diagram of an electronic device having a memory system according to some aspects of the present disclosure;

[0085] FIG2 is a schematic diagram of an exemplary memory card having a memory according to some aspects of the present disclosure;

[0086] FIG3 is a schematic diagram of an exemplary SSD having a memory according to some aspects of the present disclosure;

[0087] FIG4 is a first structural diagram of a semiconductor package provided according to some aspects of the present disclosure;

[0088] FIG5 is a first structural diagram of a NAND package provided according to some aspects of the present disclosure;

[0089] FIG6 is a second structural diagram of a NAND package provided according to some aspects of the present disclosure;

[0090] FIG7 is a schematic diagram of CMD discharge of a NAND package according to some aspects of the present disclosure;

[0091] FIG8 is a schematic diagram of a CMD discharge path of a NAND package according to some aspects of the present disclosure;

[0092] FIG9 is a second structural diagram of a semiconductor package provided according to some aspects of the present disclosure;

[0093] FIG10 is a schematic diagram of the position structure of a first NMOS transistor provided according to some aspects of the present disclosure;

[0094] 11 to 22 are some exemplary structural diagrams of the structure of a semiconductor package provided according to some aspects of the present disclosure;

[0095] FIG23 is a schematic diagram of an exemplary structure of the semiconductor package shown in FIG12 according to some aspects of the present disclosure;

[0096] FIG. 24 is another exemplary structural diagram of the semiconductor package shown in FIG. 13 according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0097] The following describes various embodiments of the present disclosure in more detail with reference to the accompanying drawings. Other embodiments that can be used as variations of any disclosed embodiment can be formed by configuring or arranging the elements and features in the embodiments of the present disclosure in different ways. Therefore, the embodiments of the present disclosure are not limited to the embodiments set forth herein. On the contrary, the described embodiments are provided so that the embodiments of the present disclosure are thorough and complete, and the scope of the embodiments of the present disclosure is fully conveyed to those skilled in the art of the technical field to which the embodiments of the present disclosure belong. It should be noted that references to "embodiment", "another embodiment" and the like do not necessarily represent only one embodiment, and different references to any such phrases are not necessarily for the same embodiment. It should be understood that although the terms "first", "second", "third" and the like may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element with the same or similar name. Therefore, without departing from the spirit and scope of the embodiments of the present disclosure, the first element in one embodiment may also be referred to as the second or third element in another embodiment.

[0098] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former may be directly connected or coupled to the latter, or may be electrically connected or coupled to the latter via one or more intermediate elements therebetween. In addition, it should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may be present.

[0099] The terms used in this article are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise. Unless otherwise specified or can be clearly understood from the context to be singular, the articles "one" and / or "an" used in the embodiments of the present disclosure and the appended claims should be collectively interpreted as meaning "one or more". It should be further understood that the terms "include", "include", "include" and "include" used in the embodiments of the present disclosure specify the presence of the elements and do not exclude the presence or addition of one or more other elements. The term "and / or" used in the embodiments of the present disclosure includes any and all combinations of one or more associated listed items. Unless otherwise defined, all terms including technology and science used in the embodiments of the present disclosure have the same meaning as those of ordinary skill in the art to which the present disclosure belongs in view of the embodiments of the present disclosure. It should be further understood that, unless the embodiments of the present disclosure are clearly defined, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the embodiments of the present disclosure and the related art, and should not be interpreted in an idealized or overly formal manner.

[0100] In the following description, many specific details are set forth to provide a thorough understanding of the present disclosure, and the present disclosure can be practiced without some or all of these specific details. In other cases, well-known processing structures and / or processes are not described in detail to avoid unnecessarily obscuring the present disclosure. It should also be understood that in some cases, unless otherwise specified, it will be apparent to those skilled in the relevant art that features or elements described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment. Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The following description focuses on details to facilitate understanding of the embodiments of the present disclosure. Well-known technical details may be omitted to avoid obscuring the features and aspects of the embodiments of the present disclosure.

[0101] An embodiment of the present disclosure provides a semiconductor package (including an IC chip), which includes a protection switch circuit that can prevent a large amount of static charge carried by the semiconductor chip in the package from flowing into a certain semiconductor chip during CDM discharge, thereby causing the semiconductor chip and the semiconductor package to fail through breakdown.

[0102] FIG1 shows a block diagram of an exemplary system with a memory device provided by an embodiment of the present disclosure. In FIG1 , system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC), wherein the system on chip may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory device 104. Specifically, the memory device 104 may be any memory disclosed in this application. For example, Phase Change Random Access Memory (PCRAM), three-dimensional NAND flash memory, etc.

[0103] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal computers, digital cameras, and mobile phones. In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded Multi Media Card (eMMC), where the SSD or eMMC is used as data storage for mobile devices with high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) on data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnection (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc.

[0104] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end-use electronic products. In one example, as shown in FIG2 , the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. Memory cards can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CompactFlash cards, SmartMedia (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a memory card connector 204 that couples the memory card to a host (e.g., the host 108 in FIG1 ). In another example, as shown in FIG3 , the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 302. The SSD can also include an SSD connector 304 that couples the SSD to a host (e.g., the host 108 in FIG1 ). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of the memory card. In addition, the memory controller 106 can also be configured to control erase, read, and write operations of the memory device 104 .

[0105] The memory device and memory system provided above include a large number of IC chips (such as the interface chip or NAND flash memory chip described later). These large numbers of IC chips are more susceptible to destructive ESD during their manufacture, assembly, testing and final use. Among them, ESD is generated due to the static electricity of the IC chip itself. This type of ESD can be generated by a single pin of the IC chip, and this type of ESD can be used to create a Charged Device Model (CDM) protection circuit for ESD protection. When the IC chip undergoes CDM discharge, the external circuit connected to the IC chip will also carry static charge. Then, the static charge carried by the external circuit will also flow to the IC chip and discharge through the pins of the IC chip. At this time, the static charge passing through the pins of the IC is bound to increase, and therefore, it is very easy to cause the IC chip pins to break down and fail. That is, at present, the protection capability of the CDM protection circuit of the semiconductor chip (or package) containing the IC chip is affected by other semiconductor chips (or circuits) that are connected and carry static charge, and the effect is poor, which is very easy to cause the IC chip pins to break down and fail.

[0106] To solve one or more of the above problems, as shown in FIG4 , an embodiment of the present disclosure provides a semiconductor package 400, comprising:

[0107] a first semiconductor chip 401;

[0108] at least one second semiconductor chip 402 ; and

[0109] A switch protection circuit 403; a first end 4031 of the switch protection circuit 403 is connected to the first semiconductor chip 401, and a second end 4032 of the switch protection circuit 403 is connected to each of the second semiconductor chips 402, and is in an off state when the semiconductor package 400 performs a charge device model (CDM) discharge to disconnect the connection between the first semiconductor chip 401 and the second semiconductor chip 402.

[0110] It should be noted that the switch protection circuit 403 further includes a third terminal 4033 , which can be connected to a control signal to control the on or off state of the switch protection circuit 403 . This will be described in detail later and will not be repeated here.

[0111] Here, the first semiconductor chip 401 may include an interface chip; the second semiconductor chip 402 may include a memory chip. The interface chip may refer to a chip having an internal interface circuit. Specifically, the internal interface circuit may have at least one of the following functions: a) setting data storage and buffering logic to accommodate the speed difference between the memory controller and the memory device; b) information format conversion, such as serial to parallel conversion; c) coordinating the type and level differences between the memory controller and the memory device in the information, such as level conversion drive, digital-to-analog or analog-to-digital conversion, etc. The memory chip may refer to the specific application of the concept of embedded system chip in the storage industry. For example, the aforementioned NAND flash memory chip having a NAND memory array may be a type of memory chip.

[0112] Here, the semiconductor package 400 may refer to a structure formed by encapsulating multiple semiconductor chips on a package board (or package structure). For example, in the present disclosure, a semiconductor package is formed by encapsulating a first semiconductor chip and at least one second semiconductor chip on a package board. In actual use, with the development of integrated circuits, package packaging modes are also constantly evolving, and the number of chips packaged in a package is increasing. Among them, the packaging modes may include: DDP (two-die package), QDP (four-die package), ODP (eight-die package), and HDP (16-die package), etc. As more and more memory chips are integrated into a package, the load on the external signal (DQ) pins of the package structure increases, which limits the operating speed of the DQ. For example, as more and more NAND chips are integrated into a package, the load on the external signal (DQ) pins of the package structure increases, which limits the operating speed of the DQ. In some embodiments, multiple NAND chips are packaged using a Combo-NAND packaging method. Combo-NAND packaging involves integrating one or more interface (or buffer) chips in addition to the conventional NAND chip. These chips handle signal processing and transmission within and outside the package, optimizing the timing of each NAND chip and enabling high-speed operation of the package's signal pins. This is a development trend in high-capacity, high-speed NAND products, as shown in Figures 5 and 6.

[0113] Figure 5 is a schematic diagram of the structure of a NAND package according to some aspects of the present disclosure. Figure 5 illustrates the global VSS solution for the Combo-NAND package. Specifically, this global VSS solution connects the VSS pins of each NAND chip together via bonding wires, which are then connected to the package's VSS pin. Furthermore, the VSS pin of the interface chip is also connected to the package's VSS pin via bonding wires. Therefore, the VSS pins of all NAND chips and interface chips are connected together, and thus the substrates of all chips are also connected together.

[0114] Figure 6 is a second schematic diagram of the NAND package structure provided according to some aspects of the present disclosure. Figure 6 illustrates the Combo-NAND signaling scheme. Within the package, the signal pins (i.e., signal pins) of each NAND chip are first connected to the interface chip. After interface processing and timing optimization, they are then connected to the package's signal pins via the interface chip's signal pins. In other words, the NAND chip is not directly connected to the package's signal pins; only the interface chip's signal pins are connected to the package's signal pins.

[0115] For semiconductor packages using the Combo-NAND packaging method described in Figures 5 and 6, the technical problem raised by the above-mentioned disclosure (IC chip undergoes CDM discharge, causing IC chip pin breakdown failure) also exists and is more serious. Specifically, as shown in Figures 7 and 8, they are schematic diagrams of CMD discharge of NAND packages provided according to some aspects of the present disclosure. Based on Figures 7 and 8. Before a certain signal pin of the package undergoes CDM ESD discharge, all chips in the package (NAND chip and interface chip) will be filled with static charge. When the package pin undergoes CDM discharge, the static charge accumulated on the substrate of each chip will be quickly discharged to the outside of the chip through the package pin. Since the CDM current is very large (several amperes to tens of amperes), a high voltage difference will be generated across the input gate, causing the input gate to breakdown and fail. The CDM of the external pins in the combo-NAND package is protected by the interface chip's ESD pins. Since the NAND chip and interface chip substrates are connected, the static charge of all NAND chip substrates is also discharged through the interface chip pin ESD. Within the package, the static charge of 17 chips is discharged through a single interface chip pin ESD. This far exceeds the protection capability of the interface chip pin ESD and will cause the package pin ESD breakdown failure. One solution to this problem is to increase the interface chip's ESD size by 17 times, but this may not be effective. Even if it were, it would result in excessive pin parasitic capacitance, severely affecting signal transmission speed, thus losing the timing optimization advantage of the combo-NAND and is unacceptable. Furthermore, combo-NAND CDM failures can also occur within the NAND itself or at the interface between the NAND and buffer chip. Conventional post-ESD IV testing of the package pins cannot detect such failures, making them easily overlooked and potentially a hidden danger in product use. It should be noted that Figure 8 illustrates the principle structure of CDM discharge in the package structure shown in Figures 5 to 7. For a specific understanding, please refer to the relevant technology, which will not be elaborated here.

[0116] Based on this, the present disclosure adds a switch protection circuit 403 to the semiconductor package. When the semiconductor package 400 is performing a charge device model (CDM) discharge, the switch protection circuit 403 is in the off state to disconnect the connection between the first semiconductor chip 401 and the second semiconductor chip 402, thereby blocking the static charge carried by the second semiconductor chip from flowing to the first semiconductor chip, and then blocking the static charge from flowing through the pins of the first semiconductor chip to the pins of the semiconductor package, thereby avoiding the breakdown failure of the first semiconductor chip and the pins of the semiconductor package. It should be noted that the static charge carried by the second semiconductor chip (such as a NAND chip) and the first semiconductor chip (such as an interface chip) can be accumulated during the normal operation of the semiconductor package, or can be charged during the CDM test of the semiconductor package before leaving the factory to test the ability of the pins to withstand ESD.

[0117] In some embodiments, when the semiconductor package operates normally, the switch protection circuit is in a conducting state to enable connection between the first semiconductor chip and the second semiconductor chip.

[0118] It should be noted that the semiconductor package's CDM discharge is only one operating state of its ESD protection. The semiconductor package operates normally most of the time, such as during read, write, and erase operations. During normal operation, the switch protection circuit must not affect normal operation. Specifically, the switch protection circuit is in a conductive state during normal operation, connecting the first semiconductor chip to the second semiconductor chip to ensure normal operation of the semiconductor package.

[0119] That is, the semiconductor package performs CDM discharge or normal operation, wherein CDM discharge and normal operation are two independent operation modes of the semiconductor package, and only one of the modes can be operated at the same time. That is, when the semiconductor package performs CDM discharge, the semiconductor package is not in the normal operation mode at this time; furthermore, when the semiconductor package is in normal operation, the semiconductor package will not perform CDM discharge.

[0120] There are several options for the setting and structure of the switch protection circuit:

[0121] Specifically, in some embodiments, as shown in FIG9 , the switch protection circuit 403 is provided in the first semiconductor chip 401 and includes: a first sub-circuit 900 ; wherein,

[0122] The first terminal 900-1 of the first sub-circuit is connected to a first node 901 in the first semiconductor chip, the second terminal 900-2 of the first sub-circuit is connected to a second node 902 in the first semiconductor chip, and the control terminal 900-3 of the first sub-circuit receives the first control signal. When the first control signal is in a first state, the first sub-circuit is in an off state, or when the first control signal is in a second state, the first sub-circuit is in an on state.

[0123] When the first sub-circuit is in an off state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the first sub-circuit is in an on state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

[0124] Here, the first node 901 of the first semiconductor chip can be connected to the ground pad (PAD) within the first semiconductor chip; the second node 902 within the first semiconductor chip can be connected to the ground pin of the first semiconductor chip; and the third node within the first semiconductor chip can be connected to the power PAD within the first semiconductor chip.

[0125] The ground pad (PAD) described herein may specifically refer to a pad for grounding (GND). The ground pin of the first semiconductor chip may refer to a pin (or pin) exposed on the outside of the first semiconductor chip after packaging for connecting to GND. The power pad (PAD) may specifically refer to a pad for receiving a power signal (e.g., a voltage signal).

[0126] Here, the first sub-circuit may include: a first N-type Metal Oxide Semiconductor (NMOS) transistor, wherein a substrate of the first NMOS transistor is isolated from a substrate of the first semiconductor chip by a deep N-well (DNW).

[0127] Specifically, as shown in Figure 10, which illustrates a schematic diagram of an NMOS transistor disposed in a DNW according to some aspects of the present disclosure, in Figure 10, a DNW is present on the substrate of the first semiconductor chip, and a first NMOS transistor is disposed between adjacent DNWs. This isolates the substrate of the first NMOS transistor from the substrate of the first semiconductor chip through the DNW, preventing parasitic P / N junction conduction.

[0128] Here, the first subcircuit has two states: an off state and an on state. Therefore, to achieve the switching between these two states, two control signals of different states are required for control, namely the control signal of the first state and the control signal of the second state. That is: under the control of the control signal of the first state, the first subcircuit is in the off state; under the control of the control signal of the second state, the first subcircuit is in the on state. For example, the first control signal of the first state may refer to a control signal at a low level (such as 0 volts (V)); correspondingly, the first control signal of the second state may refer to a control signal at a high level (such as VDD, such as 3.3V). Or, for example, the diyi control signal of the first state may refer to a control signal at a high level; correspondingly, the first control signal of the second state may refer to a control signal at a low level.

[0129] Furthermore, in the present disclosure, when the first sub-circuit is in an off state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the first sub-circuit is in an on state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

[0130] In some embodiments, as shown in FIG11 , the switch protection circuit 403 includes: a second sub-circuit 1100; wherein the second sub-circuit 1100 includes a first capacitive element 1101, wherein a first end 1101-1 of the first capacitive element is connected between the second end 900-2 of the first sub-circuit and a second node 902 within the first semiconductor chip, and a second end 1101-2 of the first capacitive element is connected to a third node 903 within the first semiconductor chip;

[0131] The control terminal 900 - 3 of the first sub-circuit is connected between the second terminal 1101 - 2 of the first capacitive element and a third node 903 in the first semiconductor chip.

[0132] It should be noted that the control terminal of the first sub-circuit described above requires access to the first control signal. In practice, the first control signal can also be generated by a related circuit. For example, a first capacitive element and its connections constitute the related circuit to generate the first control signal. Specifically, the first terminal of the first capacitive element is connected between the second terminal of the first sub-circuit and the second node within the first semiconductor chip, and its second terminal is connected to the third node within the first semiconductor chip. In this case, the control terminal of the first sub-circuit is connected between the second terminal of the first capacitive element and the third node within the first semiconductor chip. When the semiconductor package performs CDM discharge, the third node within the first semiconductor chip is placed in a floating state, and the control terminal of the first sub-circuit is connected to the first control signal in the first state via the first capacitive element. When the semiconductor package is operating normally, the third node within the first semiconductor chip is connected to a power signal, and the control terminal of the first sub-circuit is connected to the first control signal in the second state via the first capacitive element. Here, the power signal can refer to a voltage signal, that is, the third node within the first semiconductor chip is connected to the voltage signal to enable the semiconductor package to operate normally.

[0133] In some other embodiments, to protect the safety of the first capacitive element, as shown in FIG12 , the second sub-circuit further includes: a first resistive element 1102, wherein a first end 1102-1 of the first resistive element is connected to the third node 903 in the first semiconductor chip; a second end 1102-2 of the first resistive element is connected to a second end 1101-2 of the first capacitive element;

[0134] The control terminal 900 - 3 of the first sub-circuit is connected between the second terminal of the first capacitive element and the second terminal of the first resistive element.

[0135] It should be noted that if the two ends of the first capacitive element are directly connected to the power signal, when the voltage of the power signal is relatively large, the first capacitive element will be broken down, thereby causing the first capacitive element to fail and the control signal cannot be connected to the first sub-circuit. Therefore, in order to ensure the safety of the first capacitive element, the second sub-circuit may further include a first resistive element to reduce the voltage across the first capacitive element to a range that it can withstand in a voltage-dividing or current-limiting manner. When the second sub-circuit also includes a first resistive element, the control end of the first sub-circuit is connected between the second end of the first capacitive element and the second end of the first resistive element, and when the semiconductor package performs CDM discharge, the third node in the first semiconductor chip is in a floating state, and the control end of the first sub-circuit is connected to the first control signal in the first state through the first capacitive element and the first resistive element; when the semiconductor package performs normal operation, the third node in the first semiconductor chip is connected to the power signal, and the control end of the first sub-circuit is connected to the first control signal in the second state through the first capacitive element and the first resistive element.

[0136] In some embodiments, the first resistive element may include at least one resistor connected in series; the first capacitive element may include at least one capacitor connected in series;

[0137] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value ranging from 1 nanosecond to 1 microsecond.

[0138] Here, the relationship between the first capacitive element and the first resistive element is described, that is, the product of the capacitance value of at least one capacitor included in the first capacitive element and the resistance value of at least one resistor included in the first resistive element has a value range of 1 nanosecond to 1 microsecond. After the above conditions are met, the second sub-circuit can enable the first sub-circuit to timely access the control signal of the first state when the semiconductor package is performing CDM discharge, so as to disconnect the connection between the first semiconductor chip and each second semiconductor chip, so as to block the static charge carried by the second semiconductor chip from flowing into the first semiconductor chip, and then connecting to the ground through the semiconductor package to cause breakdown failure of the semiconductor package pins and the pins of the first semiconductor chip. In addition, the second sub-circuit can also enable the first sub-circuit to timely access the control signal of the second state when the semiconductor package is performing normal operation, so as to connect the connection between the first semiconductor chip and the second semiconductor chip to ensure normal operation.

[0139] In some other embodiments, as shown in FIG13 , the switch protection circuit 403 may further include: a second sub-circuit 1300; wherein the second sub-circuit includes a second capacitive element 1301, wherein a first end 1301-1 of the second capacitive element is connected between the second end 900-2 of the first sub-circuit and the second node 902 of the first semiconductor chip; and a second end 1301-2 of the second capacitive element is connected to a first node 1302 within a second semiconductor chip;

[0140] The control terminal 900 - 3 of the first sub-circuit is connected between the second terminal 1301 - 2 of the second capacitive element and the first node 1302 in the second semiconductor chip.

[0141] It should be noted that the structure and connection relationship of a second sub-circuit are described above. The second sub-circuit shown in Figure 13 is another possible structure and connection relationship of the second sub-circuit. Here, the second sub-circuit includes a second capacitive element 1301, and the first end 1301-1 of the second capacitive element is connected in the same manner as the first end of the first capacitive element, that is, connected between the second end of the first sub-circuit and the second node of the first semiconductor chip. The second end 1301-2 of the second capacitive element is connected differently from the second end of the first capacitive element, that is, the second end 1301-2 of the second capacitive element is connected to the first node 1302 of a second semiconductor chip; and the second end of the first capacitive element is connected to the third node 903 of the first semiconductor chip. In this connection relationship, the control terminal of the first sub-circuit can be connected between the second terminal of the second capacitive element and the first node within a second semiconductor chip. When the semiconductor package is performing CDM discharge, the first node within the second semiconductor chip is placed in a floating state, and the first sub-circuit is connected to the first control signal of the first state via the second capacitive element. When the semiconductor package is operating normally, the first node within the second semiconductor chip is connected to the power signal, and the first sub-circuit is connected to the first control signal of the second state via the second capacitive element. It should be noted that the second terminal 1301-2 of the second capacitive element is connected to the first node 1302 of the second semiconductor chip 402 via pin 1304 on the second semiconductor chip 402.

[0142] Here, the first node in the first semiconductor chip can be connected to the ground pad (PAD) in the first semiconductor chip; the second node in the first semiconductor chip is connected to the ground pin of the first semiconductor chip; and the first node in a certain second semiconductor chip is connected to the power PAD in a certain second semiconductor chip.

[0143] It should be noted that the first and second nodes within the first semiconductor chip are the same as those described above and will not be further described here. The first node within a second semiconductor chip is now connected to the power supply PAD within that second semiconductor chip. This arrangement has the advantage of preventing interference with the switch protection circuit caused by the power supply PAD connected to the third node within the first semiconductor chip and reducing power consumption of the power supply PAD.

[0144] In some embodiments, as shown in FIG13 , the second sub-circuit further includes: a second resistive element 1303 , wherein a first end 1303 - 1 of the second resistive element is connected to a first node 1302 in the second semiconductor chip; a second end 1303 - 2 of the second resistive element is connected to a second end 1301 - 2 of the second capacitive element;

[0145] The control terminal 900 - 3 of the first sub-circuit is connected between the second terminal of the second capacitive element and the second terminal of the second resistor.

[0146] In some embodiments, the second resistive element comprises at least one resistor connected in series; the second capacitive element comprises at least one capacitor connected in series;

[0147] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value ranging from 1 nanosecond to 1 microsecond.

[0148] It should be noted that the second resistive element here has the same function as the aforementioned first resistive element, which can be understood by referring to the previous description and will not be repeated here.

[0149] The first sub-circuit and the second sub-circuit included in the switch protection circuit described above are both disposed in the first semiconductor chip. In other embodiments, the switch protection circuit can also be disposed in each second semiconductor chip to achieve the above functions.

[0150] Specifically, as shown in FIG14 , the switch protection circuit 403 is provided in each second semiconductor chip 402 and includes: a third sub-circuit 1400; wherein,

[0151] The first terminal 1400-1 of the third sub-circuit is connected to the second node 1401 in the second semiconductor chip, the second terminal 1400-2 of the third sub-circuit is connected to the third node 1402 in the second semiconductor chip, and the control terminal 1400-3 of the third sub-circuit receives a second control signal. When the second control signal is in a first state, the third sub-circuit is turned off, or when the second control signal is in a second state, the third sub-circuit is turned on.

[0152] When the third sub-circuit is in an off state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the third sub-circuit is in an on state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

[0153] In some embodiments, as shown in FIG15 , the switch protection circuit 403 may further include: a fourth sub-circuit 1500; wherein the fourth sub-circuit includes a third capacitive element 1501, wherein a first end 1501-1 of the third capacitive element is connected between a second end 1400-2 of the third sub-circuit and a third node 1402 in the second semiconductor chip, and a second end 1501-2 of the third capacitive element is connected to a first node 1302 in the second semiconductor chip;

[0154] The control terminal 1400 - 3 of the third sub-circuit is connected between the second terminal of the third capacitive element and the first node in the second semiconductor chip.

[0155] In some embodiments, as shown in FIG15 , the fourth sub-circuit further includes a third resistive element 1502 ; wherein a first end 1502 - 1 of the third resistive element is connected to a first node in the second semiconductor chip; and a second end 1502 - 2 of the third resistive element is connected to a second end of the third capacitive element.

[0156] The control terminal 1400 - 3 of the third sub-circuit is connected between the second terminal of the third capacitive element and the second terminal of the third resistive element.

[0157] In some embodiments, the third resistive element comprises at least one resistor connected in series; the third capacitive element comprises at least one capacitor connected in series;

[0158] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value ranging from 1 nanosecond to 1 microsecond.

[0159] In some other embodiments, as shown in FIG16 , the switch protection circuit 403 further includes: a fourth sub-circuit 1600; wherein the fourth sub-circuit includes a fourth capacitive element 1601, wherein a first end 1601-1 of the fourth capacitive element is connected between the second end 1400-2 of the third sub-circuit and a third node 1402 in the second semiconductor chip; and a second end 1601-2 of the fourth capacitive element is connected to a third node 903 in the first semiconductor chip;

[0160] The control terminal 1400 - 3 of the third sub-circuit is connected between the second terminal of the fourth capacitive element and the third node 903 in the first semiconductor chip.

[0161] Here, the second end 1601-2 of the fourth capacitive element is connected to the third node 903 of the first semiconductor chip via the pin 1602. This situation is not shown in Figure 16. Figure 16 shows an example diagram including a fourth resistive element.

[0162] In some embodiments, as shown in FIG16 , the fourth sub-circuit further includes a fourth resistive element 1603 ; wherein a first end 1603 - 1 of the fourth resistive element is connected to the third node 903 in the first semiconductor chip; and a second end 1603 - 2 of the fourth resistive element is connected to a second end of the fourth capacitive element.

[0163] The control terminal 1400 - 3 of the third sub-circuit is connected between the second terminal of the fourth capacitive element and the second terminal of the fourth resistive element.

[0164] Here, the first end 1603 - 1 of the fourth resistive element is connected to the third node 903 of the first semiconductor chip via the pin 1602 .

[0165] In some embodiments, the fourth resistive element comprises at least one resistor connected in series; the fourth capacitive element comprises at least one capacitor connected in series;

[0166] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value ranging from 1 nanosecond to 1 microsecond.

[0167] In some embodiments, the third sub-circuit includes a second N-type metal oxide semiconductor (NMOS) transistor. Here, the substrate of the second NMOS transistor is isolated from the substrate of the second semiconductor chip by a deep N-well (DNW). It should be noted that the principle of DNW isolation has been described above and will not be repeated here.

[0168] It should be noted that the structure and connection method of the switch protection circuit described in Figures 14 to 16 are different from the structure and connection method of the switch protection circuit described in Figures 4 to 13 above. This is because they are arranged in different semiconductor chips, but their working principles and the functions of each component are similar. The functions of each component in the switch protection circuit in Figures 4 and 13 have been described in detail above. The functions of each component in the switch protection circuit in Figures 14 to 16 are similar to those mentioned above, which can be used as a reference for understanding and will not be described in detail here.

[0169] Based on the same inventive concept, the present disclosure further provides another embodiment. As shown in FIG17 , the present disclosure further provides another semiconductor package 1700, including:

[0170] The packaging shell 1701 is provided with a first pin 1701-1 capable of performing charge device model (CDM) discharge;

[0171] A first semiconductor chip 1702 is located in the package shell; and

[0172] At least one second semiconductor chip 1703 is located in the package shell and each second semiconductor chip is connected to the first semiconductor chip via an N-type metal oxide semiconductor (NMOS) transistor 1704;

[0173] The NMOS transistor is arranged in the first semiconductor chip or each of the second semiconductor chips; and the control terminal of the NMOS transistor is connected to a control signal; the state of the control signal is controlled by whether the first pin performs charge device model (CDM) discharge control.

[0174] Here, the first pin of the semiconductor package may include an input pin or an output pin, that is, the signal pin of the semiconductor package shown in FIG. 7 to FIG. 9 .

[0175] In some embodiments, as shown in FIG18 , the NMOS transistor is disposed in the first semiconductor chip;

[0176] The first end 1704-1 of the NMOS transistor is connected to the first node 1801 in the first semiconductor chip, the second end 1704-2 of the NMOS transistor is connected to the second node 1802 in the first semiconductor chip, and the control end 1704-3 of the NMOS transistor is connected to the control signal; wherein, the second node 1802 in the first semiconductor chip is connected to the first pin 1803 of the first semiconductor chip; the first semiconductor chip is also connected to each of the second semiconductor chips through the first pin of the first semiconductor chip.

[0177] In some embodiments, as shown in FIG18 , a first capacitive element 1804 is further provided in the first semiconductor chip. A first end 1804-1 of the first capacitive element 1804 is connected between the second end of the NMOS transistor and the first pin 1803 of the first semiconductor chip. A second end 2403-2 of the first capacitive element is connected to a third node 1805 in the first semiconductor chip.

[0178] The control terminal 1704-3 of the NMOS transistor is connected between the second terminal of the first capacitive element and a third node in the first semiconductor chip;

[0179] When the first pin of the semiconductor package performs CDM discharge, the third node in the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the first capacitive element; when the first pin of the semiconductor package performs normal operation, the third node in the first semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the first capacitive element.

[0180] Here, first pin 1803 is connected to second node 1802 within the first semiconductor chip. The first end of first capacitive element 1804, connected between second end 1704-2 of the NMOS transistor and first pin 1803 of the first semiconductor chip, can refer to any accessible location between second end 1704-2 and first pin 1803, or can be at second node 1802. The connections between external pins and internal nodes in the remaining figures are understood in this manner and are not further explained.

[0181] In some embodiments, as shown in FIG19 , a first resistive element 1806 is further provided in the first semiconductor chip;

[0182] The first end 1806-1 of the first resistive element is connected to the third node 1805 in the first semiconductor chip; the second end 1806-2 of the first resistive element is connected to the second end of the first capacitive element;

[0183] The control terminal 1704 - 3 of the NMOS transistor is connected between the second terminal of the first capacitive element and the second terminal of the first resistive element.

[0184] In some embodiments, as shown in FIG20 , a second capacitive element 2001 is further provided in the first semiconductor chip. A first end 2001-1 of the second capacitive element 2001 is connected between the second end of the NMOS transistor and the first pin of the first semiconductor chip. A second end 2001-2 of the second capacitive element is connected to a first pin 2003 of the second semiconductor chip via a second pin 2002 of the first semiconductor chip.

[0185] The control terminal 1704 of the NMOS transistor is connected between the second terminal of the second capacitive element and the first pin 2003 of the second semiconductor chip;

[0186] When the first pin of the semiconductor package performs CDM discharge, the first pin of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the second capacitive element; when the first pin of the semiconductor package performs normal operation, the first pin of the second semiconductor chip is connected to a power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the second capacitive element.

[0187] In some embodiments, as shown in FIG20 , a second resistive element 2004 is also provided in the first semiconductor chip; wherein,

[0188] The first end 2004-1 of the second resistive element is connected to the first pin 2003 of the second semiconductor chip via the second pin 2002 of the first semiconductor chip; the second end 2004-2 of the second resistive element is connected to the second end 2001-2 of the second capacitive element;

[0189] The control terminal 1704 - 3 of the NMOS transistor is connected between the second terminal of the second capacitive element and the second terminal of the second resistive element.

[0190] In some embodiments, the first pin 1803 of the first semiconductor chip includes a ground pin; the second pin 2002 of the first semiconductor chip and the first pin 2003 of the second semiconductor chip include power pins.

[0191] In some embodiments, as shown in Figure 21, the NMOS transistor is arranged in each second semiconductor chip; in a certain second semiconductor chip, the first end 1704-1 of the NMOS transistor is connected to the second node 2101 in the second semiconductor chip, the second end 1704-2 of the NMOS transistor is connected to the third node 2102 in the second semiconductor chip, and the control end 1704-3 of the NMOS transistor is connected to the control signal; wherein, the third node 2102 in the second semiconductor chip is connected to the second pin 2103 of the second semiconductor chip, and the second semiconductor chip is also connected to the first semiconductor chip through the second pin 2103 in the second semiconductor chip.

[0192] In some embodiments, as shown in FIG21 , a third capacitive element 2104 is provided in the second semiconductor chip, a first end 2104-1 of the third capacitive element is connected between the second end of the NMOS transistor and the second pin 2103 of the second semiconductor chip, and a second end 2104-2 of the third capacitive element is connected to a first node 2105 in the second semiconductor chip;

[0193] The control terminal 1704-3 of the NMOS transistor is connected between the second terminal of the third capacitive element and the first node 2105 in the second semiconductor chip;

[0194] When the first pin of the semiconductor package performs CDM discharge, the first node of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the first node of the second semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element.

[0195] In some embodiments, as shown in FIG21 , the second semiconductor chip is further provided with a third resistive element 2106 , wherein;

[0196] The first end 2106-1 of the third resistive element is connected to the first node 2105 in the second semiconductor chip, and the second end 2106-2 of the third resistive element is connected to the second end 2104-1 of the third capacitive element;

[0197] The control terminal 1704 - 3 of the NMOS transistor is connected between the second terminal of the third resistive element and the second terminal of the third capacitive element.

[0198] In some embodiments, as shown in FIG22 , the second semiconductor chip is further provided with a fourth capacitive element 2201, wherein a first end 2201-1 of the fourth capacitive element is connected between the second end 1704-2 of the NMOS transistor and the second pin 2103 of the second semiconductor chip, and a second end 2202-2 of the fourth capacitive element is connected to the third pin 2203 of the first semiconductor chip via the third pin 2202 of the second semiconductor chip;

[0199] When the first pin of the semiconductor package performs CDM discharge, the third pin of the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the third pin of the first semiconductor chip is connected to a power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element.

[0200] In some embodiments, a fourth resistive element 2204 is further provided in the second semiconductor chip, wherein;

[0201] The first end 2204-1 of the fourth resistive element is connected to the third pin 2203 of the first semiconductor chip via the third pin 2202 of the second semiconductor chip, and the second end 2204-2 of the fourth resistive element is connected to the second end 2201-2 of the fourth capacitive element;

[0202] The control terminal of the NMOS transistor is connected between the second terminal of the fourth resistive element and the second terminal of the fourth capacitive element.

[0203] In some embodiments, the second pin 2103 of the second semiconductor chip comprises a ground pin; and the third pin 2202 of the first half-cell chip and the third pin 2203 of the first semiconductor chip comprise power pins.

[0204] In some embodiments, the first semiconductor chip may be an interface chip; and the second semiconductor chip may be a NAND flash memory chip.

[0205] To facilitate understanding of the above-mentioned semiconductor package, as shown in FIG23 , it shows an exemplary structural schematic diagram of the semiconductor package shown in FIG12 provided according to some aspects of the present disclosure.

[0206] In FIG23 , the structure of the semiconductor package is simplified, and the present disclosure is illustrated only by taking a semiconductor package including a NAND chip and an interface chip as an example. Here, the switch protection circuit is disposed within the interface chip, and the first end of the NMOS transistor contained therein is connected to the ground pad VSS2 inside the interface chip, the second end is connected to the ground pin of the interface chip, and its control end is connected between the series-connected resistor R1 and capacitor C1. In addition, the ground pin of the NAND chip is connected to the ground pin of the interface chip via a DuPont wire. VCC1 in FIG23 is the sub-power pin or sub-power pad of the NAND chip; VCC2 is the power pin or power pad of the interface chip, which can be connected to the third node in the aforementioned first semiconductor chip. In this structure, when CDM discharge is performed on the semiconductor package's signal pins, VCC1 and VCC2 are floating, and the control terminal of the NMOS transistor is pulled to the low potential of VSS1 by C1. Consequently, the NMOS transistor is turned off, and VSS1 and VSS2 are electrically disconnected. Therefore, static charge in the NAND chip is not conducted to the interface chip. Therefore, the interface chip only needs to discharge its own CDM charge, without having to bear the large CDM charge from the NAND chip, thus preventing the interface chip pin from CDM breakdown and failure. During normal operation of the semiconductor package, VCC2 is high, and the control terminal (gate) of the NMOS transistor is pulled to the high potential of VCC2 by R1. Therefore, the second NMOS transistor remains on, and VSS1 and VSS2 are electrically connected, without affecting the normal operation of the entire Combo-NAND.

[0207] In other embodiments, as shown in FIG24 , which illustrates another exemplary structure of the semiconductor package shown in FIG13 according to some aspects of the present disclosure, the difference between FIG23 and FIG24 is that resistor R1 is connected to VCC1. That is, when the semiconductor package is operating normally, the control terminal (gate) of the NMOS transistor is pulled to the high potential of VCC1 by R1. Therefore, the NMOS transistor remains on, and VSS1 and VSS2 are electrically connected, without affecting the normal operation of the entire Combo-NAND.

[0208] A semiconductor package provided by an embodiment of the present disclosure adds a CDM discharge switch protection circuit (e.g., an NMOS circuit) to the VSS2 bus of an interface chip to control the connection and disconnection between the NAND chip's VSS1 and the interface chip's VSS2. During CDM discharge, under transient conditions, the gate of the switch NMOS is pulled to the VSS1 potential by C1, turning off the switch NMOS, thereby disconnecting VSS1 and VSS2. This cuts off the path for the NAND chip's CDM charge to flow to the interface chip, preventing the NAND chip's large static charge from causing electrostatic failure on the interface chip's signal pins. When the chip is operating normally, the gate of the switch NMOS is pulled up to VCC2 by R1, fully conducting, connecting VSS1 and VSS2. Furthermore, the NMOS can be placed in a DNW in the interface chip's substrate, so that the NMOS substrate and the interface chip substrate are isolated by the DNW, preventing VSS1 and VSS2 from conducting through a parasitic P / N junction. Furthermore, the resistor R1 of the switch circuit may also be connected to VCC1 via a bonding wire to prevent interference of VCC2 on the switch circuit and reduce power consumption of VCC2, thereby achieving the same effect.

[0209] It should be noted that the semiconductor package provided by the embodiment of the present disclosure can also set the switch protection circuit in the memory chip (such as a NAND flash memory chip). Based on this, the connection method of the switch protection circuit in the memory chip is also slightly different. Its function and structure are the same as the aforementioned switch protection circuit. For a specific understanding, please refer to the above description and will not be repeated here. Among them, setting the switch protection circuit in the memory chip can avoid the interference of the interface chip on the switch circuit, reduce the power consumption of the interface chip, and reduce the area of ​​the interface chip, which can achieve the same effect. However, it is necessary to integrate the switch circuit in each NAND chip to cut off the CDM current of all NAND chips.

[0210] It should be noted that in the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0211] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0212] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0213] Those skilled in the art will appreciate that all or part of the steps of the above-mentioned method embodiments may be implemented by hardware associated with program instructions, and the aforementioned program may be stored in a computer-readable storage medium. When the program is executed, the program executes the steps of the above-mentioned method embodiments. The aforementioned storage medium includes various media that can store program codes, such as mobile storage devices, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0214] Alternatively, if the above-mentioned integrated unit of the present disclosure is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present disclosure is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

[0215] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor package, comprising: a first semiconductor chip; at least one second semiconductor chip; as well as A switch protection circuit, wherein a first end of the switch protection circuit is connected to the first semiconductor chip, a second end of the switch protection circuit is connected to each of the second semiconductor chips, and when the semiconductor package performs a charged device model (CDM) discharge, the switch protection circuit is in an off state to disconnect the connection between the first semiconductor chip and the second semiconductor chip.

2. The semiconductor package according to claim 1, wherein When the semiconductor package operates normally, the switch protection circuit is in a conducting state to connect the first semiconductor chip and the second semiconductor chip.

3. The semiconductor package according to claim 1 or 2, wherein: The switch protection circuit is arranged in the first semiconductor chip and comprises: a first sub-circuit; wherein, A first end of the first subcircuit is connected to a first node in the first semiconductor chip, a second end of the first subcircuit is connected to a second node in the first semiconductor chip, a control end of the first subcircuit is connected to a first control signal, and when the first control signal is connected to a first state, the first subcircuit is in a disconnected state, or when the first control signal is connected to a second state, the first subcircuit is in a conducting state; When the first sub-circuit is in a disconnected state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the first sub-circuit is in a connected state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

4. The semiconductor package according to claim 3, wherein: The switch protection circuit further includes: a second sub-circuit; wherein the second sub-circuit includes a first capacitive element, a first end of the first capacitive element is connected between the second end of the first sub-circuit and a second node in the first semiconductor chip, and a second end of the first capacitive element is connected to a third node in the first semiconductor chip; The control terminal of the first sub-circuit is connected between the second terminal of the first capacitive element and the third node.

5. The semiconductor package according to claim 3, wherein: The switch protection circuit further comprises: a second sub-circuit; wherein the second sub-circuit comprises a second capacitive element, a first end of the second capacitive element is connected between the second end of the first sub-circuit and the second node of the first semiconductor chip; a second end of the second capacitive element is connected to a first node in a second semiconductor chip; The control terminal of the first sub-circuit is connected between the second terminal of the second capacitive element and a first node in the second semiconductor chip.

6. The semiconductor package according to claim 4, wherein: The second sub-circuit further includes: a first resistive element, a first end of the first resistive element connected to the third node in the first semiconductor chip; a second end of the first resistive element connected to a second end of the first capacitive element; The control terminal of the first sub-circuit is connected between the second terminal of the first capacitive element and the second terminal of the first resistive element.

7. The semiconductor package according to claim 5, wherein: The second sub-circuit further includes: a second resistive element, wherein a first end of the second resistive element is connected to a first node in the second semiconductor chip; a second end of the second resistive element is connected to a second end of the second capacitive element; The control terminal of the first sub-circuit is connected between the second terminal of the second capacitive element and the second terminal of the second resistor.

8. The semiconductor package according to claim 3, wherein: The first sub-circuit includes: a first N-type metal oxide semiconductor (NMOS) transistor.

9. The semiconductor package according to claim 6, wherein: The first resistive element comprises at least one resistor connected in series; the first capacitive element comprises at least one capacitor connected in series; The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

10. The semiconductor package according to claim 7, wherein: The second resistive element comprises at least one resistor connected in series; the second capacitive element comprises at least one capacitor connected in series; The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

11. The semiconductor package according to claim 6, wherein: The first node in the first semiconductor chip is connected to a ground pad (PAD) in the first semiconductor chip; the second node in the first semiconductor chip is connected to a ground pin of the first semiconductor chip; and the third node in the first semiconductor chip is connected to a power supply PAD in the first semiconductor chip.

12. The semiconductor package according to claim 7, wherein: The first node in the first semiconductor chip is connected to a ground pad (PAD) in the first semiconductor chip; the second node in the first semiconductor chip is connected to a ground pin of the first semiconductor chip; and the first node in a second semiconductor chip is connected to a power supply PAD in a second semiconductor chip.

13. The semiconductor package according to claim 1 or 2, wherein: The switch protection circuit is arranged in each second semiconductor chip and comprises: a third sub-circuit; wherein, The first end of the third subcircuit is connected to the second node in the second semiconductor chip, the second end of the third subcircuit is connected to the third node in the second semiconductor chip, the control end of the third subcircuit is connected to the second control signal, and when the second control signal in the first state is connected, the third subcircuit is in the disconnected state, or, when the second control signal in the second state is connected, the third subcircuit is in the on state; When the third sub-circuit is in a disconnected state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the third sub-circuit is in a conductive state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

14. The semiconductor package according to claim 13, wherein: The switch protection circuit further includes: a fourth subcircuit; wherein the fourth subcircuit includes a third capacitive element, a first end of the third capacitive element is connected between the second end of the third subcircuit and a third node in the second semiconductor chip, and a second end of the third capacitive element is connected to the first node in the second semiconductor chip; The control terminal of the third sub-circuit is connected between the second terminal of the third capacitive element and a first node in the second semiconductor chip.

15. The semiconductor package according to claim 13, wherein: The switch protection circuit further includes: a fourth subcircuit; wherein the fourth subcircuit includes a fourth capacitive element, a first end of the fourth capacitive element is connected between the second end of the third subcircuit and a third node in the second semiconductor chip; a second end of the fourth capacitive element is connected to the third node in the first semiconductor chip; The control terminal of the third sub-circuit is connected between the second terminal of the fourth capacitive element and a third node in the first semiconductor chip.

16. The semiconductor package according to claim 14, wherein: The fourth sub-circuit further comprises a third resistive element; wherein a first end of the third resistive element is connected to a first node in the second semiconductor chip; a second end of the third resistive element is connected to a second end of the third capacitive element; The control terminal of the third sub-circuit is connected between the second terminal of the third capacitive element and the second terminal of the third resistive element.

17. The semiconductor package according to claim 15, wherein: The fourth sub-circuit further includes a fourth resistive element; wherein a first end of the fourth resistive element is connected to a third node in the first semiconductor chip; a second end of the fourth resistive element is connected to a second end of the fourth capacitive element; The control terminal of the third sub-circuit is connected between the second terminal of the fourth capacitive element and the second terminal of the fourth resistive element.

18. The semiconductor package according to claim 13, wherein: The third sub-circuit includes a second N-type metal oxide semiconductor (NMOS) transistor.

19. The semiconductor package according to claim 16, wherein: The third resistive element comprises at least one resistor connected in series; the third capacitive element comprises at least one capacitor connected in series; The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

20. The semiconductor package according to claim 17, wherein The fourth resistive element comprises at least one resistor connected in series; the fourth capacitive element comprises at least one capacitor connected in series; The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

21. The semiconductor package according to claim 8, wherein The substrate of the first NMOS transistor and the substrate of the first semiconductor chip are isolated by a deep N well (DNW).

22. The semiconductor package according to claim 18, wherein A substrate of the second NMOS transistor and a substrate of the second semiconductor chip are isolated by a deep N well (DNW).

23. The semiconductor package according to claim 1, wherein The first semiconductor chip includes an interface chip; the second semiconductor chip includes a NAND flash memory chip.

24. A semiconductor package, comprising: Encapsulation shell; The packaging shell is provided with a first pin capable of performing charge device model (CDM) discharge; A first semiconductor chip is located in the packaging shell; as well as at least one second semiconductor chip, located in the package shell and each second semiconductor chip is connected to the first semiconductor chip via an N-type metal oxide semiconductor (NMOS) transistor; The NMOS transistor is arranged in the first semiconductor chip or each of the second semiconductor chips; and the control end of the NMOS transistor is connected to a control signal; and the state of the control signal is controlled by whether the first pin performs charge device model (CDM) discharge control.

25. The semiconductor package according to claim 24, wherein: The NMOS transistor is disposed in the first semiconductor chip; The first end of the NMOS transistor is connected to the first node in the first semiconductor chip, the second end of the NMOS transistor is connected to the second node in the first semiconductor chip, and the control end of the NMOS transistor is connected to the control signal; wherein, the second node in the first semiconductor chip is connected to the first pin of the first semiconductor chip; the first semiconductor chip is also connected to each of the second semiconductor chips through the first pin of the first semiconductor chip.

26. The semiconductor package according to claim 25, wherein A first capacitive element is also provided in the first semiconductor chip, a first end of the first capacitive element is connected between the second end of the NMOS transistor and the first pin of the first semiconductor chip; a second end of the first capacitive element is connected to a third node in the first semiconductor chip; The control terminal of the NMOS transistor is connected between the second terminal of the first capacitive element and a third node in the first semiconductor chip; When the first pin of the semiconductor package performs CDM discharge, the third node in the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the first capacitive element; when the first pin of the semiconductor package performs normal operation, the third node in the first semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the first capacitive element.

27. The semiconductor package according to claim 25, wherein: A second capacitive element is also provided in the first semiconductor chip, wherein a first end of the second capacitive element is connected between the second end of the NMOS transistor and the first pin of the first semiconductor chip; a second end of the second capacitive element is connected to the first pin of the second semiconductor chip via the second pin of the first semiconductor chip; The control end of the NMOS transistor is connected between the second end of the second capacitive element and the first pin of the second semiconductor chip; When the first pin of the semiconductor package is subjected to CDM discharge, the first pin of the second semiconductor chip is placed in a floating state, and the NMOS The control end of the transistor is connected to the control signal in the first state; when the first pin of the semiconductor package is working normally, the first pin of the second semiconductor chip is connected to the power signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the second capacitive element.

28. The semiconductor package according to claim 26, wherein The first semiconductor chip is also provided with a first resistive element; wherein, The first end of the first resistive element is connected to a third node in the first semiconductor chip; the second end of the first resistive element is connected to the second end of the first capacitive element; The control terminal of the NMOS transistor is connected between the second terminal of the first capacitive element and the second terminal of the first resistive element.

29. The semiconductor package according to claim 27, wherein: The first semiconductor chip is also provided with a second resistive element; wherein, The first end of the second resistive element is connected to the first pin of the second semiconductor chip via the second pin of the first semiconductor chip; the second end of the second resistive element is connected to the second end of the second capacitive element; The control terminal of the NMOS transistor is connected between the second terminal of the second capacitive element and the second terminal of the second resistive element.

30. The semiconductor package according to claim 24, wherein The NMOS transistor is arranged in each second semiconductor chip; in a second semiconductor chip, the first end of the NMOS transistor is connected to the second node in the second semiconductor chip, the second end of the NMOS transistor is connected to the third node in the second semiconductor chip, and the control end of the NMOS transistor is connected to the control signal; wherein the third node in the second semiconductor chip is connected to the second pin of the second semiconductor chip, and the second semiconductor chip is also connected to the first semiconductor chip through the second pin in the second semiconductor chip.

31. The semiconductor package according to claim 30, wherein: A third capacitive element is provided in the second semiconductor chip, a first end of the third capacitive element is connected between the second end of the NMOS transistor and the second pin of the second semiconductor chip, and a second end of the third capacitive element is connected to a first node in the second semiconductor chip; The control of the NMOS transistor is connected between the second end of the third capacitive element and the first node in the second semiconductor chip; When the first pin of the semiconductor package performs CDM discharge, the first node of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the first node of the second semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element.

32. The semiconductor package according to claim 30, wherein: The first semiconductor chip is further provided with a fourth capacitive element, a first end of the fourth capacitive element is connected between the second end of the NMOS transistor and the second pin of the second semiconductor chip, and a second end of the fourth capacitive element is connected to the third pin of the first semiconductor chip via the third pin of the second semiconductor chip; When the first pin of the semiconductor package performs CDM discharge, the third pin of the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the third pin of the first semiconductor chip is connected to a power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element.

33. The semiconductor package according to claim 31, wherein The second semiconductor chip is further provided with a third resistive element, wherein; A first end of the third resistive element is connected to a first node in the second semiconductor chip, and a second end of the third resistive element is connected to a second end of the third capacitive element; The control terminal of the NMOS transistor is connected to the second terminal of the third resistive element and the between the second ends of the third capacitive element.

34. The semiconductor package according to claim 32, wherein: A fourth resistive element is also provided in the second semiconductor chip, wherein; The first end of the fourth resistive element is connected to the third pin of the first semiconductor chip via the third pin of the second semiconductor chip, and the second end of the fourth resistive element is connected to the second end of the fourth capacitive element; The control terminal of the NMOS transistor is connected between the second terminal of the fourth resistive element and the second terminal of the fourth capacitive element.

35. The semiconductor package according to claim 25 or 30, wherein: The first pin of the semiconductor package includes an input pin or an output pin.

36. The semiconductor package according to claim 27, wherein: The first pin of the first semiconductor chip includes a ground pin; the second pin of the first semiconductor chip and the first pin of the second semiconductor chip include power pins.

37. The semiconductor package according to claim 32, wherein: The second pin of the second semiconductor chip comprises a ground pin; the third pin of the first semiconductor chip and the third pin of the first semiconductor chip comprise a power pin.

38. The semiconductor package according to claim 24, wherein: The first semiconductor chip is an interface chip; the second semiconductor chip is a NAND flash memory chip.

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