Super-junction silicon carbide NPN type triode and preparation method therefor

Abstract

A super-junction silicon carbide (SiC) NPN type triode and a preparation method therefor. The preparation method comprises: S100, selecting a SiC substrate (1) and performing N-type doping; S200, depositing and growing an N-drift region (2) on the SiC substrate (1); S300, etching a deep trench in the N-drift region (2), and depositing P-type SiC pillars (3); S400, sequentially depositing a P-type SiC layer (4) and an N-type SiC layer (5) on the upper surface in step S300; S500, etching an emitter mesa and performing surface implantation on a base region; S600, performing carbon film (6) protection and ion implantation, and then performing high-temperature annealing and activation; and S700, performing an ohmic contact process, and manufacturing a surface passivation layer. When the prepared triode is under withstand voltage, a super-junction structure formed by the P-type SiC pillars (3) and the N-drift region (2) between the P-type SiC pillars (3) can be fully exhausted to form an intrinsic layer, so that the reverse withstand voltage of the device is improved. Additionally, when an emitter junction is positively biased and a collector junction is reversely biased, the current emitted by an emitter can pass through the base region to a collector region, and the P-type SiC pillars (3) at two ends also move a few electrons therein to the collector region due to the reverse bias of the collector junction, so that the gain coefficient can be increased.

Description

A superjunction silicon carbide NPN transistor and its preparation method Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a super junction silicon carbide NPN type triode and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor with superior physical and electrical properties, making it a foundational material for future high-voltage, low-loss power electronics applications. As a representative of third-generation semiconductors, SiC offers significant advantages over other commonly used semiconductor materials. In terms of bandgap, SiC's bandgap is two to three times wider than that of Si and twice that of GaAs. A wider bandgap translates to lower intrinsic carrier concentration, resulting in lower reverse leakage current and making the device more suitable for switching circuits. In terms of thermal conductivity, SiC's thermal conductivity is over three times that of Si and over nine times that of GaAs at room temperature. This higher thermal conductivity allows for faster dissipation of heat generated during device operation, preventing device failure due to excessive temperatures and reducing the operating costs of circuit cooling systems. SiC devices can operate at temperatures exceeding 600°C without failure, while traditional Si devices often fail at around 200°C. In terms of critical breakdown electric field, SiC has approximately 10 times that of Si. Therefore, while achieving the same reverse withstand voltage, the drift region thickness of a SiC device is approximately 1 / 10 that of Si. This significantly reduces the device's forward on-resistance and minimizes unnecessary switching losses in the circuit. In terms of saturation electron velocity, SiC has twice that of Si, enabling SiC devices to operate at higher frequencies. Due to these excellent electrical properties, SiC is considered an ideal material for manufacturing next-generation high-performance power devices.

[0003] Bipolar transistors are current-driven, normally-off, three-terminal devices. In early integrated circuit chips, bipolar transistors were core components of digital and analog ICs. With the rapid development of CMOS and SOI technologies, bipolar processes have gradually been replaced. Today, bipolar transistors are primarily used in RF power amplifiers, signal amplification, and power switching, with discrete devices being the predominant form factor. Si power bipolar transistors can achieve forward currents of hundreds of amperes and reverse breakdown voltages of nearly 2000V. However, their low current gain has led to their gradual replacement by IGBTs. The superiority of silicon carbide (SiC) power BJTs has led to a renewed research boom. At the same operating voltage and current, SiC BJTs exhibit lower conduction and switching losses than Si IGBTs, demonstrating significant potential for power applications.

[0004] For SiC BJTs, since the mobility of electrons in SiC materials is greater than the mobility of holes, NPN BJTs have greater carrier transport capabilities than PNP BJTs, resulting in higher current gain. On the other hand, the commonly used SiC substrate doping type is N-type, and P-type substrates are more difficult to obtain. High-voltage BJTs are generally designed as vertical structures to maximize the reverse breakdown voltage. Considering the above two aspects, NPN-type BJTs are preferred in actual designs. It is worth noting that traditional BJTs mainly work in the forward active region for amplification of electrical signals, while power BJTs, as electrical switches, mainly work in the saturation region and cutoff region. Conventional transistors consist of three regions: emitter region, base region, and collector region. The collector region of a power BJT has a lower doping concentration and a thicker width than traditional BJTs. This region that withstands the reverse voltage of the device is called the drift region. From a structural point of view, the NPN bipolar transistor can be considered to be composed of an NP junction and a PN junction back to back, respectively called the emitter junction and the collector junction. Depending on the difference in the bias applied to these two junctions, the bipolar transistor mainly has two modes when used as a power switch: forward conduction and reverse cutoff, as shown below.

[0005] (1) Forward conduction mode: emitter junction is forward biased (VBE>0), collector junction is reverse biased (VBC<0);

[0006] (2) Reverse cutoff mode: the emitter junction is reverse biased (VBE < 0), and the collector junction is reverse biased (VBC < 0).

[0007] After more than a decade of continuous development, SiC BJT manufacturing processes have been continuously refined, and key processes that control device characteristics (such as dry etching, ion implantation, and ohmic contacts) have been successfully developed. As a result, the electrical performance of SiC BJTs has been greatly improved. However, before SiC BJTs can be fully commercialized, some issues still need to be resolved. The power device sector, in particular, has higher requirements for device breakdown characteristics and current gain. Summary of the Invention

[0008] In response to the above problems, the present invention provides a super-junction silicon carbide NPN transistor and a preparation method thereof, which improves the withstand voltage of the BJT collector junction and increases the current gain of the device.

[0009] The technical solution of the present invention is:

[0010] A method for preparing a superjunction silicon carbide NPN transistor comprises the following steps:

[0011] S100, selecting a SiC substrate and performing N-type doping;

[0012] S200, depositing and growing an N-drift region on a SiC substrate;

[0013] S300, deep trench etching in the N-drift region and deposition of P-type SiC pillars;

[0014] S400 , sequentially depositing a P-type SiC layer and an N-type SiC layer on the upper surface in step S300 ;

[0015] S500, emitter mesa etching and base region surface implantation;

[0016] S600, carbon film protection, high temperature annealing activation after ion implantation;

[0017] S700: Ohmic contact process and surface passivation layer production.

[0018] Specifically, step S100 includes:

[0019] Nitrogen was diffused on a 1 mm thick 4H-SiC substrate to achieve a nitrogen doping concentration of 5e18 cm -3 , becoming an N-type SiC substrate.

[0020] Specifically, step S200 includes:

[0021] The N-drift region is grown on the SiC substrate by chemical vapor deposition. The thickness of the drift region is 18 μm, the doping element is nitrogen, and the doping concentration is 5e15 cm -3 .

[0022] Specifically, step S300 includes:

[0023] S310, etching grooves with a width of 4 μm and a depth of 10 μm at both ends of the cell;

[0024] S320, using chemical vapor deposition to grow 10μm P-type SiC pillars in the groove, doped with aluminum at a concentration of 7.5e15cm -3 .

[0025] Specifically, step S400 includes:

[0026] S410 uses chemical vapor deposition to grow a 0.9 μm P-type SiC layer doped with aluminum at a concentration of 3e 17 ;

[0027] S420, using chemical vapor deposition to grow a 1.1um N-type SiC layer, the layer is doped with nitrogen and the doping concentration is 2e 19 .

[0028] Specifically, step S500 includes:

[0029] S510, using a dry etching process, etches the N-type SiC layer above the P column by 1.2 μm to prepare for the next step of ion implantation in the ohmic contact area of ​​the base region;

[0030] S520: High-concentration Al ions are implanted on the surface of the upper area of ​​the P column with an injection energy of 10 KeV and a dose of 8e14 cm -2 .

[0031] Specifically, step S600 includes:

[0032] A 1 μm carbon film is coated on the upper surface of the device, and then high-temperature annealing is performed after ion implantation. The annealing temperature is 1700°C and the annealing time is 30 minutes. After annealing, the carbon film is removed using RCA standard cleaning.

[0033] Specifically, step S700 includes:

[0034] S710: Ohmic metal is deposited on the collector using magnetron sputtering technology. The metal types are Ti and Ni, with thicknesses of 50nm and 200nm respectively, as shown in Figure 10.

[0035] S720 uses magnetron sputtering technology to make ohmic metal on the base and emitter. The metals include 50nm Ti, 200nm Al, and 50nm Ti respectively.

[0036] Specifically, step S700 includes:

[0037] S710 uses the PECVD process to first deposit a 500nm layer of SiO2 on the device surface, and then deposit a 500nm layer of Si3N4 to protect the device surface and smooth the electric field.

[0038] A superjunction silicon carbide NPN transistor includes a collector metal, a SiC substrate, an N-drift region, and a P-type SiC layer arranged in sequence from bottom to top;

[0039] A P-type SiC column extending to the P-type SiC layer is provided on the upper side of the N-drift region near the outer side;

[0040] An N-type SiC layer extending into the silicon dioxide protective layer is provided in the middle of the top surface of the P-type SiC layer, and an emitter metal is provided on the N-type SiC layer;

[0041] On the P-type SiC layer, a base metal extending into the silicon dioxide protective layer is provided on the outer side of the N-type SiC layer.

[0042] Beneficial effects of the present invention:

[0043] Compared with traditional SiC BJTs, the gain coefficient of the present invention is increased from 150 to 160 @ Ic = 100mA, Vce = 10V; and the withstand voltage BVcbo is increased from 1200V to 2200V @ Ic = 100mA. This is because when the device withstands the withstand voltage, the P-pillars and the N-drift region between the P-pillars can be fully depleted. After the entire drift region is completely depleted, it becomes equivalent to an intrinsic layer. Therefore, when the device withstands the reverse withstand voltage, both longitudinal and transverse electric fields exist within the drift region. When the applied drain voltage reaches the critical breakdown electric field strength of silicon carbide, the device will undergo avalanche breakdown. Under the condition that the two pillar regions meet the charge balance, the breakdown voltage that the superjunction can withstand is proportional to the thickness of the pillar region. In addition, when the emitter junction is forward biased and the collector junction is reverse biased, the current emitted by the emitter can not only pass through the base region to the collector region, but also the P-pillars at both ends also move a small number of electrons in the P-pillars to the collector region due to the reverse bias of the electrode junction, which has the effect of improving the gain coefficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a schematic diagram of SiC substrate growth and N-type substrate structure.

[0045] Figure 2 is a schematic diagram of the structure of the growing N-layer drift region.

[0046] Figure 3 is a schematic diagram of the structure of the drift region etched deep groove,

[0047] FIG4 is a schematic diagram of the structure of depositing P-type SiC pillars and planarizing them.

[0048] FIG5 is a schematic diagram of the structure of depositing a P-type SiC layer.

[0049] FIG6 is a schematic diagram of the structure of depositing an N-type SiC layer.

[0050] FIG7 is a schematic diagram of the structure of the emitter mesa etching,

[0051] FIG8 is a schematic diagram of the structure of the surface injection of the base region,

[0052] Figure 9 is a schematic diagram of the structure of depositing a 1um carbon film for protection and high temperature annealing to activate the implanted ions.

[0053] FIG10 is a schematic diagram of the structure of the collector ohmic contact process,

[0054] Figure 11 is a schematic diagram of the structure of the emitter region and the base region as ohmic contact metals.

[0055] Figure 12 is a schematic diagram of the structure of the protective layer deposition (500nmSiO2, 500nmSi3N4),

[0056] FIG13 is a schematic diagram of the structure of coating PI glue;

[0057] In the figure, 1 is the SiC substrate, 2 is the N-drift region, 3 is the P-type SiC column, 4 is the P-type SiC layer, 5 is the N-type SiC layer, 6 is the carbon film, 7 is the collector metal, 8 is the base metal, 9 is the emitter metal, 10 is the silicon dioxide protective layer, and 11 is the silicon nitride protective layer. Implementation Method

[0058] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0059] In the description of the present invention, it should be understood that terms such as "upper," "lower," "left," "right," "vertical," and "horizontal" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are used solely to facilitate and simplify the description of the present invention and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0060] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0061] The present invention is shown in Figures 1-3;

[0062] A method for preparing a superjunction silicon carbide NPN transistor comprises the following steps:

[0063] S100, selecting a SiC substrate 1 and performing N-type doping, as shown in FIG1 ;

[0064] S200, an N-drift region 2 is deposited and grown on the SiC substrate 1, as shown in FIG2 ;

[0065] S300, deep trenches are etched in the N-drift region 2, and P-type SiC pillars 3 are deposited, as shown in FIG3-4;

[0066] S400 , sequentially depositing a P-type SiC layer 4 and an N-type SiC layer 5 on the upper surface in step S300 ; as shown in FIG5-6 ;

[0067] S500: Etching the emitter mesa and performing surface implantation of the base region, as shown in FIG7-8 ;

[0068] S600, carbon film 6 protection, ion implantation and high temperature annealing activation; as shown in FIG9;

[0069] S700: Ohmic contact process and surface passivation layer production.

[0070] Further defined, step S100 includes:

[0071] Nitrogen was diffused on a 1 mm thick 4H-SiC substrate to achieve a nitrogen doping concentration of 5e18 cm -3 , becoming an N-type SiC substrate.

[0072] Further defined, step S200 includes:

[0073] The N-drift region 2 is grown on the SiC substrate 1 by chemical vapor deposition. The thickness of the drift region is 18 μm, the doping element is nitrogen, and the doping concentration is 5e15 cm -3 The drift zone is the main area responsible for withstand voltage.

[0074] Further defined, step S300 includes:

[0075] S310, using a dry etching process, etches a groove with a width of 4 μm and a depth of 10 μm at both ends of the SiC BJT cell (the total cell width is 20 μm). The deep groove is etched to prepare the P-type SiC column 3 in the next step; as shown in Figure 3;

[0076] S320, using chemical vapor deposition to grow 10μm P-type SiC column 3 in the groove, doped with aluminum, with a doping concentration of 7.5e15cm -3 , and a planarization process is used to make the surface height of the P column and the surface height of the N-drift region 2 the same. The width of the P column * the doping concentration of the P column must be equal to the width of the N-drift region 2 * the doping concentration of the N-drift region 2. This ensures that when the withstand voltage is applied, the interlaced P and N regions are fully depleted and the longitudinal electric field is reduced, as shown in Figure 4.

[0077] Further defined, step S400 includes:

[0078] S410, using chemical vapor deposition to grow a 0.9 μm P-type SiC layer 4, the layer is doped with aluminum, and the doping concentration is 3e 17 ; This layer serves as the base region of the transistor and is connected to the base electrode; as shown in Figure 5;

[0079] S420, using chemical vapor deposition to grow a 1.1 μm N-type SiC layer 5, the layer is doped with nitrogen at a doping concentration of 2e19 ; This layer serves as the emitter region of the transistor and is connected to the emitter region electrode; when the transistor amplifies, it relies on the emitter current to be quickly transported through the base region and then collected by the collector, as shown in Figure 6.

[0080] Further defined, step S500 includes:

[0081] S510, etching the N-type SiC layer 5 above the P column by 1.2 μm through a dry etching process to prepare for the next step of ion implantation in the ohmic contact region of the base region; as shown in FIG7;

[0082] S520: High-concentration Al ions are implanted on the surface of the upper area of ​​the P column with an injection energy of 10 KeV and a dose of 8e14 cm -2 ; The purpose of heavy surface doping is to utilize the tunneling effect caused by heavy surface doping to replace the role of ohmic contact, as shown in Figure 8.

[0083] Further defined, step S600 includes:

[0084] A 1 μm carbon film 6 is coated on the upper surface of the device, and then high-temperature annealing is performed after ion implantation. The annealing temperature is 1700° C. and the annealing time is 30 minutes. After annealing, the carbon film 6 is removed using RCA standard cleaning.

[0085] Further defined, step S700 includes:

[0086] S710, using magnetron sputtering technology to make ohmic metal on the collector, the metal types are Ti and Ni, with thicknesses of 50nm and 200nm respectively. The temperature of the ohmic contact is 1000℃, and the time is 4 minutes, as shown in Figure 10;

[0087] In step S720, ohmic metal is deposited on the base and emitter using magnetron sputtering technology. The metals include 50 nm of Ti, 200 nm of Al, and 50 nm of Ti, respectively. The rapid thermal annealing temperature for ohmic contact is 1000°C for 4 minutes, as shown in FIG11 .

[0088] S800, using the PECVD process, first deposit a 500nm layer of SiO2 on the device surface, and then deposit a 500nm layer of Si3N4 to protect the device surface and smooth the electric field; as shown in Figure 12.

[0089] S900: PI glue coating on the front side, as shown in FIG13 ;

[0090] Apply 3um PI glue (polyimide), model Toray PW-1500S, with a curing temperature of 350°C to prevent air sparks and electrostatic breakdown.

[0091] Further optimization, step S700 includes:

[0092] S710 uses the PECVD process to first deposit a 500nm layer of SiO2 on the device surface, and then deposit a 500nm layer of Si3N4 to protect the device surface and smooth the electric field.

[0093] A superjunction silicon carbide NPN transistor is characterized by comprising a collector metal 7, a SiC substrate 1, an N-drift region 2 and a P-type SiC layer 4 arranged in sequence from bottom to top;

[0094] A P-type SiC column 3 extending to the P-type SiC layer 4 is provided on the upper side of the N-drift region 2 and close to the outer side;

[0095] An N-type SiC layer 5 extending into the silicon dioxide protective layer 10 is provided in the middle of the top surface of the P-type SiC layer 4, and an emitter metal 9 is provided on the N-type SiC layer 5;

[0096] On the P-type SiC layer 4 , a base metal 8 extending into the silicon dioxide protective layer 10 is provided on the outer side of the N-type SiC layer 5 .

[0097] Further optimized, a silicon nitride protection layer 11 is provided on the top surface of the silicon dioxide protection layer 10 .

[0098] The amplification effect of the transistor is mainly achieved by its emitter current being able to transmit through the base region and then reach the collector. The two conditions for achieving this transmission process are:

[0099] 1. Internal conditions: The impurity concentration in the emitter region is much greater than that in the base region, and the base region is very thin;

[0100] 2. External conditions: The emitter junction is forward biased and the collector junction is reverse biased.

[0101] The withstand voltage of a transistor depends primarily on the width of the depletion region at the N-P junction and the distribution of the electric field. A key aspect of superjunction design is ensuring charge balance between the P and N pillars. If the charge in the pillars is unbalanced, the superjunction's breakdown voltage will decrease.

[0102] Compared to the existing SiC BJT (model YJSIC1200SB50A), the gain factor of this invention is increased from 150 to 160 @ Ic = 100mA, Vce = 10V; and the withstand voltage (BVcbo) is increased from 1200V to 2200V @ Ic = 100mA. This is because the P-pillars and the N-drift region 2 between them are fully depleted during withstand voltage. Once the entire drift region is fully depleted, it becomes equivalent to an intrinsic layer. Therefore, when the device withstands reverse voltage, both longitudinal and transverse electric fields exist within the drift region. When the applied drain voltage reaches the critical breakdown field strength of silicon carbide, the device undergoes avalanche breakdown. Assuming charge balance between the two pillars, the breakdown voltage that the superjunction can withstand is proportional to the thickness of the pillars. In addition, when the emitter junction is forward biased and the collector junction is reverse biased, the current emitted by the emitter can not only pass through the base region to reach the collector region, but the P columns at both ends also move a small number of electrons in the P columns to the collector region due to the reverse bias of the emitter junction, thereby increasing the gain coefficient.

[0103] Regarding the content disclosed in this case, the following points need to be explained:

[0104] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;

[0105] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to form new embodiments;

[0106] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a superjunction silicon carbide NPN transistor, characterized in that: The following steps are involved: S100, selecting a SiC substrate (1) and performing N-type doping; S200, depositing and growing an N-drift region (2) on the SiC substrate (1); S300, etching a deep groove in the N-drift region (2) and depositing a P-type SiC column (3); S400, depositing a P-type SiC layer (4) and an N-type SiC layer (5) in sequence on the upper surface in step S300; S500, etching the emitter mesa and performing surface implantation of the base region; S600, carbon film (6) protection, high temperature annealing activation after ion implantation; S700, ohmic contact process and surface passivation layer production.

2. The method for preparing a super junction silicon carbide NPN type triode according to claim 1, characterized in that: Step S100 includes: The nitrogen doping concentration was 5e18cm-1 by diffusing nitrogen on a 1mm thick 4H-SiC substrate. -3 , becoming an N-type SiC substrate.

3. The method for preparing a super junction silicon carbide NPN type triode according to claim 1, characterized in that: Step S200 includes: An N-drift region (2) is grown on a SiC substrate (1) by chemical vapor deposition. The drift region has a thickness of 18 μm, a doping element of nitrogen, and a doping concentration of 5 e 15 cm -3 .

4. The method for preparing a super junction silicon carbide NPN type triode according to claim 1, characterized in that: Step S300 includes: S310, etching grooves with a width of 4 μm and a depth of 10 μm at both ends of the cell; S320, using chemical vapor deposition to deposit and grow a 10um P-type SiC column (3) in the groove, with aluminum as the doping element and a doping concentration of 7.5e 15 cm -3 .

5. The method for preparing a super junction silicon carbide NPN type triode according to claim 1, characterized in that: Step S400 includes: S410, using chemical vapor deposition to deposit and grow a 0.9um P-type SiC layer (4), the layer is doped with aluminum and the doping concentration is 3e 17 ; S420, using chemical vapor deposition to deposit and grow a 1.1 um N-type SiC layer (5), the layer is doped with nitrogen and the doping concentration is 2e 19 .

6. The method for preparing a super junction silicon carbide NPN type triode according to claim 1, characterized in that: Step S500 includes: S510, etching the N-type SiC layer (5) above the P column by 1.2 μm through a dry etching process, in preparation for the next step of ion implantation in the ohmic contact region of the base region; S520: High concentration of Al ions are implanted on the surface of the upper area of ​​the P column with an implantation energy of 10 KeV and a dose of 8e14 cm -2 .

7. The method for preparing a super junction silicon carbide NPN type triode according to claim 1, characterized in that: Step S600 includes: A 1 um carbon film (6) is coated on the upper surface of the device, and then high-temperature annealing is performed after ion implantation. The annealing temperature is 1700° C. and the annealing time is 30 minutes. After annealing, the carbon film (6) is removed by RCA standard cleaning.

8. The method for preparing a super junction silicon carbide NPN type triode according to claim 1, characterized in that: Step S700 includes: S710, using magnetron sputtering technology to make ohmic metal on the collector, the metal types are Ti and Ni, and the thicknesses are 50nm and 200nm respectively; as shown in Figure 10; S720 uses magnetron sputtering technology to make ohmic metal on the base and emitter. The metals include 50nm Ti, 200nm Al, and 50nm Ti respectively.

9. The method for preparing a super junction silicon carbide NPN type triode according to claim 1, characterized in that: Step S700 includes: S710, using the PECVD process, first deposited a 500nm layer of SiO2 on the device surface, and then deposited a 500nm layer of Si3N4 to protect the device surface and smooth the electric field.

10. The super junction silicon carbide NPN type transistor prepared by the method for preparing a super junction silicon carbide NPN type transistor according to claim 1, characterized in that: It comprises a collector metal (7), a SiC substrate (1), an N-drift region (2) and a P-type SiC layer (4) which are arranged in sequence from bottom to top; A P-type SiC column (3) extending to the P-type SiC layer (4) is provided on the upper side of the N-drift region (2) and close to the outer side; An N-type SiC layer (5) extending into the silicon dioxide protective layer (10) is provided in the middle of the top surface of the P-type SiC layer (4), and an emitter metal (9) is provided on the N-type SiC layer (5); On the P-type SiC layer (4), a base metal (8) extending into the silicon dioxide protective layer (10) is provided on the outer side of the N-type SiC layer (5).

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