Semiconductor device and fabrication method therefor, and electronic apparatus

Abstract

A semiconductor device and a fabrication method therefor, and an electronic apparatus, which relate to the technical field of semiconductors and aim to solve the problem of how to avoid surface oxidation of source / drain electrodes. The fabrication method for a semiconductor device comprises: forming a through hole (T) in a stacked structure, wherein the through hole (T) runs through a second source / drain electrode (2) and an interlayer dielectric layer (5) in a direction perpendicular to a substrate (10), and extends to at least a first source / drain electrode (1); exposing at least the interlayer dielectric layer (5) to a side wall of the through hole (T), and forming on the side wall a self-assembled monolayer (6) having an adsorption relationship with the interlayer dielectric layer (5), so that the first source / drain electrode (1) and the second source / drain electrode (2), which are not covered by the self-assembled monolayer (6), are exposed in the through hole (T); by using the self-assembled monolayer (6) as a mask, forming contact layers (3) on the first source / drain electrode (1) and the second source / drain electrode (2); removing the self-assembled monolayer (6); isolating the contact layer (3) on the first source / drain electrode (1) from the contact layer (3) on the second source / drain electrode (2) by means of the interlayer dielectric layer (5); and forming a semiconductor layer (4) on the side wall in the through hole (T), wherein the semiconductor layer (4) is connected to the contact layers (3) on the first source / drain electrode (1) and the second source / drain electrode (2).

Description

Semiconductor device and manufacturing method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on August 31, 2023, with application number 202311109031.6 and invention name “Semiconductor device, method for manufacturing the same, and electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0005] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0006] Summary of the Invention

[0007] Embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and an electronic device.

[0008] According to some embodiments, the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0009] Providing a stacked structure comprising at least a first source / drain, an interlayer dielectric layer, and a second source / drain, which are sequentially formed in a direction perpendicular to the substrate;

[0010] forming a through hole in the stacked structure, wherein the through hole penetrates the second source / drain and the interlayer dielectric layer in a direction perpendicular to the substrate and extends at least to the first source / drain;

[0011] At least where the interlayer dielectric layer is exposed to the sidewall of the through hole, a self-assembled monolayer is formed on the sidewall in an adsorption relationship with the interlayer dielectric layer, so that the first source / drain and the second source / drain not covered by the self-assembled monolayer are exposed in the through hole;

[0012] forming a contact layer on the first source / drain and the second source / drain using the self-assembled monolayer as a mask;

[0013] removing the self-assembled monolayer; isolating the contact layer on the first source / drain electrode and the contact layer on the second source / drain electrode by the interlayer dielectric layer;

[0014] A semiconductor layer is formed on the sidewall of the through hole, and the semiconductor layer is connected to the contact layer on the first source / drain and the second source / drain.

[0015] According to some embodiments, the contact layer is an anti-oxidation conductive layer and / or a film layer for reducing Schottky barrier.

[0016] According to some embodiments, the self-assembled monolayer includes long-chain organic molecules; the long-chain organic molecules are combined with molecules of the interlayer dielectric layer through chemical adsorption.

[0017] According to some embodiments, the long-chain organic molecule contains at least a fluoroalkyl group, which is a tail group of the long-chain organic molecule. The method for preparing a semiconductor device further includes forming the contact layer using an atomic layer deposition process. The interlayer dielectric layer includes a non-metallic oxide layer.

[0018] According to some embodiments, the surface of the interlayer dielectric layer has at least hydroxyl groups; the fluoroalkyl groups in the long-chain organic molecules are combined with the hydroxyl groups on the surface of the interlayer dielectric layer through chemical adsorption.

[0019] According to some embodiments, the interlayer dielectric layer includes a silicon oxide film layer having hydroxyl groups on its surface.

[0020] According to some embodiments, the self-assembled monolayer comprises 1H,1H,2H,2H-perfluorooctyltrichlorosilane and / or (heptadecafluoro-1,1,2,2-tetrahydrodecyl)triethoxysilane. During the formation of the self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer, the first reaction gas comprises at least ammonia.

[0021] According to some embodiments, in the process of forming the contact layer in the through hole using the self-assembled monolayer as a mask, the reaction precursor includes at least pentamethyldiamine tantalum complex, the second reaction gas includes at least ammonia, and the reaction temperature is 225°C to 300°C.

[0022] According to some embodiments, the method for preparing a semiconductor device further includes: removing the self-assembled monolayer using a steam hydrolysis process or a silane thermal decomposition process.

[0023] According to some embodiments, the contact layer includes a tantalum metal nitride layer.

[0024] According to some embodiments, another aspect of the present disclosure provides a semiconductor device manufactured by the manufacturing method described in any of the above embodiments.

[0025] According to some embodiments, each region of the semiconductor layer has the same thickness.

[0026] According to some embodiments, a pattern of the contact layer on the first source / drain overlaps with a pattern of the first source / drain; and a pattern of the contact layer on the second source / drain overlaps with a pattern of the second source / drain.

[0027] According to some embodiments, the contact layer includes a tantalum metal nitride layer.

[0028] According to some embodiments, the interlayer dielectric layer includes a silicon oxide film layer.

[0029] According to some embodiments, another aspect of the present disclosure provides an electronic device comprising the semiconductor device described in any of the above embodiments.

[0030] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0032] FIG1 is a schematic diagram of the cross-sectional structure of a semiconductor device provided in some embodiments of the present disclosure; FIG1 is also a schematic diagram of the cross-sectional structure of a structure obtained after forming an anti-oxidation conductive layer in a method for preparing a semiconductor device provided in some embodiments of the present disclosure;

[0033] FIG2 is a schematic diagram of a cross-sectional structure of a semiconductor device provided in some other embodiments of the present disclosure;

[0034] FIG3 is a schematic diagram of a cross-sectional structure of a semiconductor device provided in some other embodiments of the present disclosure;

[0035] FIG4 is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0036] 5 is a schematic cross-sectional view of a structure obtained after forming an insulating dielectric layer and a first source / drain electrode in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0037] 6 is a schematic cross-sectional view of a structure obtained after forming an interlayer dielectric layer in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0038] FIG7 is a schematic cross-sectional view of a structure obtained after forming a second source / drain in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0039] FIG8 is a schematic cross-sectional view of a structure obtained after forming a through hole in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0040] FIG9 is a schematic cross-sectional view of a structure obtained after forming a self-assembled monolayer in a method for preparing a semiconductor device according to some embodiments of the present disclosure;

[0041] FIG10( a ) is a chemical scale model diagram of FOTS; FIG10( b ) is a chemical scale model diagram of HDFTEOS;

[0042] FIG11 is a schematic cross-sectional view of a structure obtained after forming an anti-oxidation conductive layer in a method for preparing a semiconductor device according to some embodiments of the present disclosure;

[0043] FIG. 12 (a) shows a TaN structure in a method for preparing a semiconductor device according to some embodiments of the present disclosure. x TaN during atomic layer deposition on self-assembled monolayers x The relationship curve between the number of atomic layer deposition cycles and the initial growth rate; Figure 12 (b) is a graph showing the TaN structure in the method for preparing a semiconductor device provided in some embodiments of the present disclosure. x TaN on copper layer during atomic layer deposition x The relationship between the number of atomic layer deposition cycles and the initial growth rate;

[0044] FIG. 13 (a) shows a TaN structure in a method for preparing a semiconductor device according to some embodiments of the present disclosure. x TaN during atomic layer deposition on self-assembled monolayers x The relationship curve between the thickness of the atomic layer deposition and the content of the Ta element; FIG13 (b) is a diagram of TaN in the method for preparing the semiconductor device provided in some embodiments of the present disclosure. x TaN on copper layer during atomic layer deposition x The relationship curve between atomic layer deposition thickness and Ta element content. DETAILED DESCRIPTION

[0045] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0047] It should be understood that when an element or layer is referred to as being "located on...", "on top of...", or "on the surface of...", it can be directly on, on top of, or on the surface of another element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on..." another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0048] It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures; the device may be included in alternative orientations (e.g., rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

[0049] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.

[0051] The present disclosure provides a semiconductor device and a method for manufacturing the same, as well as a semiconductor device. When forming a contact layer between a semiconductor layer and a source or drain electrode, the contact layer on both the source and drain electrodes is formed in a single process, resulting in a simple process and low manufacturing cost. Details will be described in subsequent examples.

[0052] In one aspect, the present disclosure provides a semiconductor device according to some embodiments.

[0053] Referring to FIG. 1 , in some embodiments, the semiconductor device may specifically include: a first source / drain 1 , a second source / drain 2 , a through hole T, a contact layer 3 , a semiconductor layer 4 , and an interlayer dielectric layer 5 .

[0054] Among them, the first source / drain 1, the interlayer dielectric layer 5 and the second source / drain 2 are stacked in sequence in a direction perpendicular to the substrate; the through hole T penetrates the second source / drain 2 and the interlayer dielectric layer 5 in a direction perpendicular to the substrate and extends to the first source / drain 1; the contact layer 3 is located on the side walls of the first source / drain 1 and the second source / drain 2 exposed to the through hole T; and the semiconductor layer 4 is located on the surfaces of the contact layer 3 and the interlayer dielectric layer 5 exposed to the through hole T.

[0055] The above-mentioned device is formed by the following method, providing a stacking structure comprising at least a first source / drain, an interlayer dielectric layer and a second source / drain formed in sequence in a direction perpendicular to a substrate; forming a through hole in the stacking structure, the through hole penetrating the second source / drain and the interlayer dielectric layer in a direction perpendicular to the substrate and extending at least to the first source / drain; forming a self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer at least on the sidewall of the interlayer dielectric layer exposed to the through hole, so that the first source / drain and the second source / drain not covered by the self-assembled monolayer are exposed in the through hole; using the self-assembled monolayer as a mask, forming a contact layer on the first source / drain and the second source / drain exposed in the through hole; removing the self-assembled monolayer; isolating the contact layer on the first source / drain and the contact layer on the second source / drain by the interlayer dielectric layer; forming a semiconductor layer on the sidewall in the through hole, the semiconductor layer being connected to the contact layer on the first source / drain and the second source / drain.

[0056] In the semiconductor device and method provided in the above embodiments, the contact layer 3 is selectively formed only on the first source / drain electrode 1 and the second source / drain electrode 2 exposed on the inner sidewalls of the through-hole, while a self-assembled monolayer is formed in other areas. The self-assembled monolayer serves as a mask for forming the contact layer 3 on the first source / drain electrode 1 and the second source / drain electrode 2. The contact layer 3 can be provided only on the first source / drain electrode 1 or the second source / drain electrode 2 to contact the semiconductor layer. This process does not require complex steps to simultaneously form a contact layer with the same pattern as the first source / drain electrode 1 or the second source / drain electrode 2.

[0057] It should be noted that in the embodiments of the present disclosure, one of the first source / drain 1 and the second source / drain 2 is a source, and the other is a drain. Specifically, the following situations may be included: if the first source / drain 1 is a source, then the second source / drain 2 is a drain; or if the first source / drain 1 is a drain, then the second source / drain 2 is a source.

[0058] The present disclosure does not specifically limit the materials constituting the first source / drain electrode 1 and the second source / drain electrode 2. The materials constituting the first source / drain electrode 1 and the second source / drain electrode 2 can be the same or different. The first source / drain electrode 1 and the second source / drain electrode 2 can be a single layer or a stacked multilayer structure, and the materials of each layer can be the same or different.

[0059] As an example, the first source / drain electrode 1 and the second source / drain electrode 2 may be formed of a metal, a metal alloy, a conductive metal oxide, or a conductive metal nitride. Specifically, the metal material may be, for example, tungsten (W), molybdenum (Mo), nickel (Ni), copper (Cu), tantalum (Ta), titanium (Ti), or aluminum (Al); the metal alloy material may be an alloy comprising two or more of the above metals, such as TiAl, an alloy material composed of titanium and aluminum; the conductive metal oxide may be, for example, indium tin oxide (ITO); and the conductive metal nitride may be, for example, titanium nitride (TiN).

[0060] As an example, the contact layer 3 is an anti-oxidation conductive layer and / or a film layer for reducing the Schottky barrier.

[0061] As an example, the contact layer 3 can be a double layer or a single layer. If it is a double layer, the second layer is formed immediately after the first layer is formed, and then the semiconductor layer 4 is formed after the self-assembled monolayer is removed.

[0062] For example, the single-layer contact layer may only play the function of anti-oxidation and electrical conductivity, or may simultaneously play the functions of anti-oxidation and electrical conductivity and reducing the Schottky barrier between the source or drain electrode and the semiconductor layer.

[0063] For example, the double-layer contact layer may have only the function of anti-oxidation and electrical conductivity or only the function of reducing the Schottky barrier, or may have both the function of anti-oxidation and electrical conductivity and the function of reducing the Schottky barrier.

[0064] In the above embodiment, there is no protective layer on the upper surface of the second source / drain 2 , and the upper surface and sidewalls are exposed at the same time. At this time, the contact layer 3 is formed in the exposed areas.

[0065] The present disclosure is not limited to the above-described embodiments. For example, a stacked structure includes a first source / drain electrode 1 and a second source / drain electrode 2, with a dielectric layer disposed on the second source / drain electrode 2. A through hole penetrates the dielectric layer, the second source / drain electrode 2, and the interlayer dielectric layer 5, exposing the first source / drain electrode 1. A self-assembled monolayer is disposed on any dielectric layer or insulating layer exposed within the hole, and the remaining area contains the first source / drain electrode 1 and the second source / drain electrode 2 with a pattern complementary to that of the dielectric layer or insulating layer.

[0066] Furthermore, there are different embodiments for extending the through hole T. The through hole T can extend to the upper surface of the first source / drain electrode 1, or extend into the first source / drain electrode 1 while exposing the sidewall, or penetrate the first source / drain electrode 1 to expose the dielectric layer or substrate below the first source / drain electrode 1. Any exposed non-conductive layer can form a self-assembled monolayer that serves as a mask for forming contact layers on the first source / drain electrode 1 and the second source / drain electrode 2.

[0067] For ease of understanding and explanation, please refer to Figure 1 . The surface of the contact layer 3 in contact with the first source / drain electrode 1 is defined as the first contact surface, and the surface connected to the first contact surface is defined as the first end surface. Simultaneously, the surface of the contact layer 3 in contact with the second source / drain electrode 2 is defined as the second contact surface, and the surface connected to the second contact surface is defined as the second end surface. As an example, the contact layer 3 may be a conductive film that extends along the sidewalls of the through hole T and may have two opposing end surfaces in the direction of extension; that is, the first end surface and the second end surface are opposing end surfaces.

[0068] Continuing with FIG1 , in some embodiments, a first end surface of the contact layer 3 may be flush with a surface of the first source / drain electrode 1 near the second source / drain electrode 2. In some embodiments, a second end surface of the contact layer 3 may be flush with a surface of the second source / drain electrode 2 near the first source / drain electrode 1. One end or the other end of the contact layer is an end surface between the major surfaces of the contact film layer.

[0069] As an example, the first end surface of the contact layer 3 can be flush with the surface of the first source / drain electrode 1 near the second source / drain electrode 2; at the same time, the second end surface of the contact layer 3 is also flush with the surface of the second source / drain electrode 2 near the first source / drain electrode 1. In this case, as shown in FIG1 , the pattern of the contact layer 3 overlaps with the patterns of the first source / drain electrode 1 and the second source / drain electrode 2, and is complementary to the pattern of the interlayer dielectric layer 5 exposed to the through hole T.

[0070] It can be understood that the contact layer between the first source / drain 1 and the semiconductor layer overlaps with the pattern of the first source / drain 1 exposed in the through hole. The contact layer between the second source / drain 2 and the semiconductor layer overlaps with the pattern of the second source / drain 2 exposed in the through hole.

[0071] The embodiment of the present disclosure does not specifically limit the constituent material of the contact layer 3. As an example, in the embodiment of the present disclosure, the contact layer 3 can be composed of a conductive material with high oxidation resistance; wherein the conductive material with high oxidation resistance refers to a conductive material with higher oxidation resistance than the first source / drain 1 and the second source / drain. Exemplarily, the conductive material with high oxidation resistance may include a conductive transition metal nitride material. The conductive transition metal nitride material may be, for example, tantalum metal nitride (TaN x ), vanadium (V) metal nitride, chromium (Cr) metal nitride, manganese (Mn) metal nitride, iron (Fe) metal nitride, cobalt (Co) metal nitride, nickel (Ni) metal nitride, etc.

[0072] For example, the conductive material with high oxidation resistance may also include tantalum metal oxide (TaO x The bond energy of tantalum oxide is greater than that of tantalum nitride, so it has more stable chemical properties than tantalum nitride. In addition, tantalum oxide is a high dielectric constant material (high-k material), which is also beneficial for improving the electrical performance of semiconductor devices.

[0073] 1 , in some embodiments, the thickness of the semiconductor layer 4 formed by ALD on the surface of the interlayer dielectric layer 5 exposed to the through hole T is equal to the thickness of the semiconductor layer 4 on the surface of the contact layer 3 .

[0074] Please refer to FIG2 . In some embodiments, the semiconductor device may further include a gate dielectric layer 7 and a gate electrode 8 . The gate dielectric layer 7 conformally covers the semiconductor layer 4 ; the gate electrode 8 is located on the gate dielectric layer 7 and fills the hole.

[0075] As shown in FIG. 2 , in some embodiments, the channel direction between the first source / drain 1 and the second source / drain 2 generally extends in a direction perpendicular to the substrate.

[0076] It should be noted that when the channel direction between the first source / drain 1 and the second source / drain 2 generally extends in a direction perpendicular to the substrate, the gate 8 can be surrounded by the semiconductor layer 4 and at least filled with the through hole T, as shown in Figure 2; alternatively, the gate 8 can be formed on the outer wall of the semiconductor layer 4, and the through hole T can be filled with an insulating layer, a barrier layer and / or a back gate, etc.

[0077] In other embodiments, referring to FIG3 , gate 8 is located on substrate 10 and extends perpendicular to substrate 10. Semiconductor layer 4 surrounds gate 8, and gate dielectric layer 7 is located between gate 8 and semiconductor layer 4 to insulate gate 8 from semiconductor layer 4.

[0078] As an example, as shown in FIG3 , the channel direction between the first source / drain 1 and the second source / drain 2 can generally extend in a direction parallel to the substrate 10. For example, the first source / drain 1 and the second source / drain 2 can be arranged in the same layer in a direction parallel to the substrate 10, and the first source / drain 1 and the second source / drain 2 are spaced apart in a direction parallel to the substrate 10.

[0079] On the other hand, the present disclosure also provides a method for manufacturing a semiconductor device according to some embodiments. It should be noted that the methods for manufacturing semiconductor devices in the embodiments of the present disclosure can all be used to manufacture corresponding semiconductor devices. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without conflict, so that those skilled in the art can understand the technical content of the present disclosure.

[0080] Referring to FIG. 4 , in some embodiments, the method for manufacturing the semiconductor device may specifically include the following steps S100 to S600 .

[0081] S100: providing a first source / drain, an interlayer dielectric layer, and a second source / drain stacked in sequence in a direction perpendicular to the substrate.

[0082] Of course, the stacked structure includes at least the stacked first source / drain, the interlayer dielectric layer, and the second source / drain, and may also include an insulating layer below the first source / drain and an insulating layer above the second source / drain. Both the insulating layer and the interlayer dielectric layer may be silicon oxide.

[0083] S200: Forming a through hole perpendicular to the substrate, penetrating the second source / drain and the interlayer dielectric layer and extending to the first source / drain. The hole may penetrate the stacked structure, extend to the first source / drain layer, penetrate the first source / drain layer, or extend only into a portion of the first source / drain layer.

[0084] S300: forming a self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer on the sidewall of the interlayer dielectric layer exposed to the through hole.

[0085] Of course, in the stacked structure, the insulating layer regions of the first source / drain and the second source / drain are removed in the through hole to form a self-assembled monolayer.

[0086] S400: Using the self-assembled monolayer as a mask, forming a contact layer on the sidewalls of the first source / drain and the second source / drain exposed in the through hole. The contact layer has the same pattern as the corresponding first source / drain or second source / drain.

[0087] S500: Removal of the self-assembled monolayer.

[0088] S600: forming a semiconductor layer on surfaces of the contact layer and the interlayer dielectric layer exposed to the through hole.

[0089] A semiconductor layer is formed in the through hole, covering each area and connecting to the contact layer. A channel is formed between the two spaced contact layers.

[0090] In the fabrication method provided in the above embodiment, a self-assembled monolayer adsorbed to the interlayer dielectric layer is selectively formed on the sidewalls of the interlayer dielectric layer exposed to the through-hole. The self-assembled monolayer is then used as a mask to form contact layers on the sidewalls of the first source / drain and the second source / drain exposed to the through-hole. This process is simple and low-cost.

[0091] It should be understood that, although the various steps in the flowchart of FIG4 are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in FIG4 may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0092] In order to more clearly illustrate the preparation methods in some of the above embodiments, please refer to Figures 1 to 3 and Figures 5 to 13 below to understand some embodiments of the present disclosure.

[0093] In step S100 , referring to FIG. 5 to FIG. 7 , a first source / drain 1 , an interlayer dielectric layer 5 , and a second source / drain 2 are provided as insulating stacks in a direction perpendicular to the substrate.

[0094] As an example, in the embodiments of the present disclosure, the substrate can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0095] The embodiment of the present disclosure does not specifically limit the method for forming the first source / drain 1, the interlayer dielectric layer 5, and the second source / drain 2 in step S100. As an example, the first source / drain 1, the interlayer dielectric layer 5, and the second source / drain 2 can be formed by the following steps, for example:

[0096] A first conductive material layer, an interlayer dielectric material layer, and a second conductive material layer are formed in sequence in a direction perpendicular to the substrate; thereafter, the second conductive material layer, the interlayer dielectric material layer, and the first conductive material layer are patterned simultaneously or in sequence to form a second source / drain 2, an interlayer dielectric layer 5, and a first source / drain 1, respectively.

[0097] This step can form multiple source and drain electrodes corresponding to multiple memory cells from a larger film layer, isolating the source and drain electrodes between different memory cells. The source and drain electrodes can be block or strip structures in different layers. The source and drain electrodes can be the initial pattern, which will be further patterned later.

[0098] In some embodiments, as shown in Figure 5, an insulating dielectric layer 9 may be formed on one surface of the substrate. Based on this, in step S100, the first source / drain 1 and the second source / drain 2 may be formed on the surface of the insulating dielectric layer 9 away from the substrate.

[0099] In the fabrication method provided in the above embodiment, insulating dielectric layer 9 is formed to isolate the substrate from first source / drain 1, preventing current from flowing directly through them. This helps reduce short circuits and leakage in the semiconductor device and ensures that current flows along the designed circuit path. Furthermore, insulating dielectric layer 9 prevents electrons from escaping from the substrate or entering the substrate through first source / drain 1, thereby improving the reliability of the semiconductor device.

[0100] The present disclosure does not specifically limit the material of the insulating dielectric layer 9. As an example, the insulating dielectric layer 9 may include, but is not limited to, a non-metallic oxide layer. The non-metallic oxide layer may be, for example, a silicon oxide (SiO2) layer.

[0101] It can be understood that the interlayer dielectric layer 5 is formed between the first source / drain 1 and the second source / drain 2 to achieve mutual insulation between the first source / drain 1 and the second source / drain 2 .

[0102] The present disclosure does not specifically limit the material of the interlayer dielectric layer 5. For example, the material of the interlayer dielectric layer 5 may include, but is not limited to, a low-k material. The interlayer dielectric layer 5 may be a single layer or a stacked multilayer structure, and the materials of each layer may be the same or different.

[0103] The present disclosure does not specifically limit the material of the interlayer dielectric layer 5. In some embodiments, the interlayer dielectric layer 5 may include, but is not limited to, a non-metallic oxide layer. The non-metallic oxide layer may be, for example, a silicon oxide layer.

[0104] As an example, the surface of the interlayer dielectric layer 5 may have at least hydroxyl groups.

[0105] For example, the interlayer dielectric layer 5 may include a silicon oxide film layer having hydroxyl groups on its surface. It is understood that the surface of the silicon oxide film layer will react with moisture in the environment, forming hydrogen bonds and adsorbing water molecules, so that a large number of hydroxyl groups (-OH) are formed on the surface of the silicon oxide film layer. In some embodiments, the hydroxyl groups on the surface of the interlayer dielectric layer 5 can be naturally adsorbed in the environment without the need for additional treatment processes. In addition, after removing the self-assembled monolayer (SAM), the hydroxyl groups are also processed and will not come into contact with the metal oxide semiconductor layer.

[0106] As an example, after forming the interlayer dielectric layer 5 on the surface of one side of the first source / drain electrode 1 and before forming the second source / drain electrode 2, the following step may be further included: performing a planarization process on the surface of the interlayer dielectric layer 5 away from the first source / drain electrode 1. The planarization process can eliminate undulations and unevenness on the surface of the interlayer dielectric layer 5, so that the interface between the second source / drain electrode 2 and the surface of the interlayer dielectric layer 5 has a better morphology, which is conducive to improving the production yield of the manufacturing method and the reliability of the semiconductor device.

[0107] In step S200, referring to Figure 8 , a through hole T is formed perpendicular to the substrate, penetrating the second source / drain electrodes 2 and the interlayer dielectric layer 5 and extending at least to the first source / drain electrodes 1. At this point, each source and drain electrode formed in the previous step is patterned to form the final electrode structure. Electrodes farther from the substrate are penetrated to form ring-shaped electrodes or electrodes with through holes. Whether electrodes closer to the substrate penetrate, partially penetrate, or remain on the top surface of the film layer depends on the requirements.

[0108] The embodiment of the present disclosure does not specifically limit the method of forming the through hole T in the above steps. As an example, the second source / drain 2, the interlayer dielectric layer 5 and the first source / drain 1 can be etched by a photolithography process, but is not limited to the etching process, to form the through hole T.

[0109] As an example, a photolithography and etching process may be used to etch the second source / drain 2 , the interlayer dielectric layer 5 , and the first source / drain 1 to form a through hole T.

[0110] It should be noted that, in some embodiments, the through hole T may extend only to the top surface of the film layer of the first source / drain 1; in other embodiments, as shown in Figure 8, the through hole T may extend into the film layer of the first source / drain 1, but does not pass through the first source / drain 1; in some other embodiments, the through hole T may pass through the upper and lower surfaces of the film layer of the first source / drain 1. In this case, the first source / drain 1 has an annular through hole, which surrounds the semiconductor layer on the side wall of the through hole.

[0111] In step S300 , referring to FIG. 9 , a self-assembled monolayer 6 is formed on the sidewall of the interlayer dielectric layer 5 exposed to the through hole T, and is in an adsorption relationship with the interlayer dielectric layer 5 .

[0112] In the above-mentioned step S300, a self-assembled monolayer 6 is formed on the sidewalls of the interlayer dielectric layer 5 exposed to the through-hole T. By utilizing the characteristic that the self-assembled monolayer 6 generally does not react with the precursor used for forming the contact layer in the subsequent process, the contact layer is not formed on the surface of the interlayer dielectric layer 5 exposed to the through-hole T, thereby achieving selective deposition of the contact layer and ensuring that the contact layer can be accurately formed on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed to the through-hole T.

[0113] A self-assembled monolayer (SAM) is a film or coating with a single-molecule thickness. Specifically, it refers to a monolayer with a specific structure and function that forms on a solid surface through molecular interactions and self-assembly. SAMs are typically constructed using surface-active molecules (such as fatty acids and phospholipids) or organic molecules with self-assembling properties.

[0114] SAM generally includes a head group and a tail group (referred to as tail group). The tail group of the embodiment of the present disclosure will be adsorbed to the interlayer dielectric layer 5 .

[0115] The present disclosure does not specifically limit the constituent materials of the self-assembled monolayer 6. In some embodiments, the self-assembled monolayer 6 may include long-chain organic molecules. The long-chain organic molecules may be bonded to the molecules of the interlayer dielectric layer 5 (such as silicon oxide) by chemical adsorption.

[0116] As an example, the long-chain organic molecule contains at least a fluoroalkyl group, and the fluoroalkyl group is the tail group of the long-chain organic molecule, referred to as a fluoro(F)alkyl tail group.

[0117] For example, the organic molecules of the self-assembled monolayer 6 may include 1H,1H,2H,2H-perfluorooctyltrichlorosilane ((Cl)3Si(CH2)2(CF2)5CF3, abbreviated as FOTS), and Figure 10(a) shows a chemical ratio model of FOTS. For another example, the organic molecules of the self-assembled monolayer 6 may include (heptadecafluoro-1,1,2,2-tetrahydrodecyl)triethoxysilane ((CH3CH2O)3Si(CH2)2(CF2)7CF3, abbreviated as HDFTEOS), and Figure 10(b) shows a chemical ratio model of HDFTEOS.

[0118] In some embodiments, the F-chain alkyl tail group in the long-chain organic molecule can be combined with the hydroxyl group on the surface of the interlayer dielectric layer 5 through chemical adsorption.

[0119] For example, the interlayer dielectric layer 5 includes a silicon oxide film layer having hydroxyl groups. FOTS and HDFTEOS both contain F-chain alkyl tail groups, and thus will bond with the hydroxyl-rich silicon dioxide layer and the silicon oxide film layer having hydroxyl groups, rather than bonding with the materials constituting the first source / drain 1 and the second source / drain 2. Consequently, a self-assembled monolayer 6 is formed on the surface of the silicon dioxide layer and the silicon oxide film layer having hydroxyl groups exposed to the gate through hole T.

[0120] Moreover, FOTS and HDFTEOS do not react with the precursors used in most atomic layer deposition processes (such as Ta[N(CH3)2]5), so the self-assembled monolayer 6 will not be formed on the second source / drain 2, the surface of the first source / drain 1 exposed to the gate through hole T, or the surface of the second source / drain 2 exposed to the gate through hole T, and the contact layer 3 can be selectively deposited on the surface of the first source / drain 1 exposed to the through hole T and the surface of the second source / drain 2 exposed to the through hole T.

[0121] As an example, during step S300 of forming the self-assembled monolayer 6, ammonia can be used as the first reaction gas, but is not limited to it. The first reaction gas is used to provide a suitable environment and conditions, promote the adsorption and chemical reaction of organic molecules, and regulate the properties and structure of the self-assembled monolayer 6.

[0122] In step S400 , referring to FIG. 11 , a contact layer 3 is formed on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed at the through hole T using the self-assembled monolayer 6 as a mask.

[0123] In the above step S400, the contact layer 3 is formed only on the sidewalls of the first source / drain electrode 1 and the second source / drain electrode 2 exposed in the through-hole T, and is not formed on the interlayer dielectric layer covered by the self-assembled monolayer 6. For example, the self-assembled monolayer 6 can be a long-chain organic molecule containing a F-chain alkyl tail group, which does not react with most precursors, thereby achieving selective deposition of the contact layer 3; that is, the contact layer 3 is deposited only on the sidewalls of the first source / drain electrode 1 and the second source / drain electrode 2 exposed in the through-hole T.

[0124] The present disclosure does not specifically limit the method for forming the contact layer 3 in the above steps. In some embodiments, the contact layer 3 can be formed on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed by the through hole T using, but not limited to, an atomic layer deposition (ALD) process.

[0125] As previously mentioned, in the embodiment of the present disclosure, the contact layer 3 may be formed of a conductive transition metal nitride material. The conductive transition metal nitride material may be, for example, tantalum nitride, vanadium nitride, chromium nitride, manganese nitride, iron nitride, cobalt nitride, nickel nitride, and the like.

[0126] The transition metal indicates a transition metal element in the periodic table.

[0127] The material of the contact layer 3 includes tantalum metal nitride (TaN x ), ITO, materials containing Ir, etc. x For example, the process of forming the contact layer 3 by using the atomic layer deposition process may specifically include the following steps, such as:

[0128] A precursor and a second reaction gas are alternately introduced into the reaction chamber so that the precursor and the second reaction gas are chemically adsorbed on the surface of the first source / drain electrode 1 exposed to the through-hole T and the surface of the second source / drain electrode 2 exposed to the through-hole T. The precursor may be, for example, a tantalum nitride precursor Ta[N(CH3)2]5, and the second reaction gas may be, for example, ammonia (NH3).

[0129] The embodiment of the present disclosure does not specifically limit the reaction temperature during the above-mentioned atomic layer deposition process. As an example, when using the atomic layer deposition process to form TaN x During the process, the reaction temperature can be 225°C to 300°C; for example, the reaction temperature can be 225°C, 250°C, 275°C or 300°C, etc.

[0130] In step S500 , please continue to refer to FIG. 1 , the self-assembled monolayer 6 is removed.

[0131] The present embodiment does not specifically limit the method for removing the self-assembled monolayer 6 in step S320. As an example, a water vapor hydrolysis process or a silane pyrolysis process can be used to remove the self-assembled monolayer 6 and remove the hydroxyl groups at the same time.

[0132] Please refer to FIG. 12 to FIG. 13 to understand that the atomic layer deposition process is used to form the constituent materials including TaN x The contact layer 3 is taken as an example. In this example, the interlayer dielectric layer 5 includes a main structure, such as a low-K material such as silicon dioxide or C-containing silicon oxide, and may also include an isolation layer between the silicon oxide and the semiconductor layer, such as an isolation layer that blocks H or O, and the isolation layer can absorb a self-assembled monolayer.

[0133] Exemplarily, the first source / drain electrode 1 and the second source / drain electrode 2 are both made of materials including copper, Ni, Mo, Ti, TiN, and the like.

[0134] In FIG. 12 (a) and FIG. 12 (b), the horizontal axis Number of ALD cycles represents the contact layer 3 (TaN) formed by the atomic layer deposition process. x ) in the process of atomic layer deposition cycles, the vertical axis is the Initial growth rate (A-cyvle -1 ) represents the initial growth rate.

[0135] In Figure 12 (a), bare SiO2 shows TaN x The relationship between the number of atomic layer deposition cycles and the initial growth rate when performing atomic layer deposition on an untreated silicon oxide layer; FOTS|SiO2 shows that when the silicon oxide layer is exposed on the surface of the through hole T to form a self-assembled monolayer 6 of organic molecules including FOTS, TaN x The relationship between the number of atomic layer deposition cycles and the initial growth rate is shown in the curve; HDFTEOS|SiO2 shows that when the silicon oxide layer is exposed on the surface of the through hole T to form a self-assembled monolayer 6 of organic molecules including HDFTEOS, TaN x The relationship between the number of atomic layer deposition cycles and the initial growth rate.

[0136] In Figure 12(b), bare Cu shows TaN x The relationship between the number of atomic layer deposition cycles and the initial growth rate when performing atomic layer deposition on a copper layer; FOTS|Cu shows the relationship between the number of atomic layer deposition cycles and the initial growth rate after the formation of a self-assembled monolayer of organic molecules including FOTS. x The relationship between the number of atomic layer deposition cycles and the initial growth rate when performing atomic layer deposition on a copper layer; HDFTEOS|Cu shows the relationship between the number of atomic layer deposition cycles and the initial growth rate after the formation of a self-assembled monolayer of organic molecules including HDFTEOS. x Figure 3. Relationship between the number of atomic layer deposition cycles and the initial growth rate during atomic layer deposition on a copper layer.

[0137] Comparing FIG12(a) with FIG12(b), it can be seen that the formation of the self-assembled monolayer 6 has substantially no effect on the initial growth rate of the contact layer 3 on the surface of the first source / drain electrode 1 exposed to the through-hole T and the surface of the second source / drain electrode 2 exposed to the through-hole T; however, the growth of the contact layer 3 is hindered at the self-assembled monolayer 6. Therefore, the embodiments of the present disclosure can inhibit the growth of the contact layer 3 on the surface exposed by the interlayer dielectric layer 5 by forming the self-assembled monolayer 6, thereby achieving selective deposition of the contact layer 3 on the inner sidewall of the through-hole.

[0138] In FIG. 13 (a) and FIG. 13 (b), the horizontal axis TaN x thickness The representative is the contact layer 3 (TaN x ) thickness, vertical axis Ta LEISS (eV-counts-s -1 ) can be used to characterize the content of Ta element.

[0139] In Figure 13 (a), bare SiO2 shows TaN x When atomic layer deposition is performed on an untreated silicon oxide layer, the TaN obtained by atomic layer deposition x The relationship curve between the thickness and the Ta element content; FOTS|SiO2 shows the TaN obtained by atomic layer deposition when the silicon oxide layer is exposed on the surface of the through hole T to form a self-assembled monolayer 6 of organic molecules including FOTS. x The relationship curve between the thickness of the Ta element and the content of the Ta element; HDFTEOS|SiO2 shows the TaN obtained by atomic layer deposition when the silicon oxide layer is exposed on the surface of the through hole T to form a self-assembled monolayer 6 of organic molecules including HDFTEOS. x The relationship curve between thickness and Ta element content.

[0140] In Figure 13 (b), bare Cu shows TaN x When atomic layer deposition is performed on a copper layer, the TaN obtained by atomic layer deposition x The relationship curve between the thickness and the Ta element content; FOTS|Cu shows the TaN obtained by atomic layer deposition after the formation of the self-assembled monolayer 6 of organic molecules including FOTS x The relationship curve between the thickness and the Ta element content; HDFTEOS|Cu shows the TaN obtained by atomic layer deposition after the formation of a self-assembled monolayer 6 of organic molecules including HDFTEOS x The relationship curve between thickness and Ta element content.

[0141] Comparing FIG13(a) with FIG13(b), it can be further seen that the formation of the self-assembled monolayer 6 has substantially no effect on the Ta content of the contact layer 3 on the surface of the first source / drain electrode 1 exposed to the through-hole T and the surface of the second source / drain electrode 2 exposed to the through-hole T; however, the growth of the contact layer 3 is hindered at the self-assembled monolayer 6. Therefore, the embodiments of the present disclosure can inhibit the growth of the contact layer 3 on the surface exposed by the interlayer dielectric layer 5 by forming the self-assembled monolayer 6, thereby achieving selective deposition of the contact layer 3.

[0142] In step S600 , referring to FIG. 2 , a semiconductor layer 4 is formed on the surfaces of the contact layer 3 and the interlayer dielectric layer 5 exposed to the through hole.

[0143] The present embodiment does not specifically limit the constituent material of the semiconductor layer 4. As an example, the semiconductor layer 4 can be a single-layer structure or a multi-layer structure. For example, the constituent material of the semiconductor layer 4 can include but is not limited to metal oxides. The material of the metal oxide can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the semiconductor device is small (for example, the leakage current can be less than or equal to 10 -15 A), thereby ensuring a low refresh rate of the semiconductor device. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a 、Sn x In y Zn z O a 、Al x Sn y Inz Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a 、Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO, IAZO, IGO, IZO (Indium-Zinc-Oxide), IZOx and other materials. As long as the leakage current of the semiconductor device can meet the requirements, the specific adjustment can be made according to the actual situation.

[0144] The present disclosure does not specifically limit the method for forming the semiconductor layer 4. As an example, the semiconductor layer 4 can be formed on the surfaces of the contact layer 3 and the interlayer dielectric layer 5 exposed to the through hole by using, but not limited to, an atomic layer deposition process.

[0145] It can be understood that when the first source / drain 1 and / or the second source / drain 2 are penetrated, a closed ring is formed inside the corresponding first source / drain 1 and / or the second source / drain 2, and the first source / drain 1 and / or the second source / drain 2 can completely surround the semiconductor layer 4.

[0146] In some embodiments, after forming the semiconductor layer 4 in step S600, the method for preparing the semiconductor device may further include the following steps:

[0147] A gate dielectric layer 7 is conformally covered on a surface of the semiconductor layer 4 away from the contact layer 3 ; and a gate 8 is formed on a surface of the gate dielectric layer 7 away from the semiconductor layer 4 .

[0148] As an example, the gate 8 may at least fill the through hole T. In some embodiments, the top surface of the gate 8 may also be higher than the top surface of the gate dielectric layer 7 .

[0149] The present embodiment does not specifically limit the materials constituting the gate dielectric layer 7. For example, the materials constituting the gate dielectric layer 7 may include, but are not limited to, high-k dielectric materials. Examples of high-k dielectric materials include hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), and hafnium lanthanum oxide (HfLaO).

[0150] The present disclosure does not specifically limit the material of the gate 8. As an example, the material of the gate 8 may include, but is not limited to, indium zinc oxide (IZO), indium tin oxide, titanium nitride, tungsten, and the like.

[0151] In another aspect, the present disclosure further provides an electronic device according to some embodiments. The semiconductor device may include the semiconductor device provided in any of the aforementioned embodiments.

[0152] The electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal, etc.

[0153] It is understood that the structure of the semiconductor device can refer to the relevant descriptions in some of the aforementioned embodiments. The semiconductor device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0154] In the embodiments of the present disclosure, the semiconductor device adopts the semiconductor device provided in some of the aforementioned embodiments, which can avoid the reduction of the on-state current and is conducive to improving the electrical performance of the semiconductor device. It is understood that the technical effects achieved by the aforementioned semiconductor devices can also be achieved by the semiconductor device described above, and will not be described in detail here.

[0155] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor device, comprising: Providing a stacked structure at least comprising a first source / drain, an interlayer dielectric layer and a second source / drain formed in sequence in a direction perpendicular to the substrate; forming a through hole in the stacked structure, wherein the through hole penetrates the second source / drain and the interlayer dielectric layer in a direction perpendicular to the substrate and extends at least to the first source / drain; At least when the interlayer dielectric layer is exposed to the sidewall of the through hole, a self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer is formed on the sidewall, so that the first source / drain and the second source / drain not covered by the self-assembled monolayer are exposed in the through hole; Using the self-assembled monolayer as a mask, forming a contact layer on the first source / drain and the second source / drain; removing the self-assembled monolayer; isolating the contact layer on the first source / drain and the contact layer on the second source / drain by the interlayer dielectric layer; A semiconductor layer is formed on the side wall of the through hole, and the semiconductor layer is connected to the contact layer on the first source / drain and the second source / drain.

2. The method for preparing a semiconductor device according to claim 1, wherein: The contact layer includes an anti-oxidation conductive layer and / or a film layer for reducing Schottky barrier.

3. The method for preparing a semiconductor device according to claim 1 or 2, wherein: The self-assembled monolayer includes long-chain organic molecules; the long-chain organic molecules are combined with the molecules of the interlayer dielectric layer through chemical adsorption.

4. The method for preparing a semiconductor device according to claim 3, wherein: The long-chain organic molecule contains at least a fluoroalkyl group, and the fluoroalkyl group is the tail group of the long-chain organic molecule; The contact layer is formed by an atomic layer deposition process; and the interlayer dielectric layer includes a non-metallic oxide layer.

5. The method for preparing a semiconductor device according to claim 4, wherein: The surface of the interlayer dielectric layer has at least hydroxyl groups; The fluoroalkyl group in the long-chain organic molecule is bonded to the hydroxyl group on the surface of the interlayer dielectric layer by chemical adsorption.

6. The method for preparing a semiconductor device according to claim 5, wherein: The interlayer dielectric layer includes a silicon oxide film layer with hydroxyl groups on the surface.

7. The method for preparing a semiconductor device according to any one of claims 1 to 6, wherein: The components of the self-assembled monolayer include 1H,1H,2H,2H-perfluorooctyltrichlorosilane and / or (heptadecafluoro-1,1,2,2-tetrahydrodecyl)triethoxysilane; In the process of forming the self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer, the first reaction gas at least includes ammonia.

8. The method for preparing a semiconductor device according to any one of claims 1 to 7, wherein: In the process of forming the contact layer in the through hole using the self-assembled monolayer as a mask, the reaction precursor at least includes pentamethyldiamine tantalum complex, the second reaction gas at least includes ammonia, and the reaction temperature is 225°C to 300°C.

9. The method for preparing a semiconductor device according to any one of claims 1 to 8, wherein: The self-assembled monolayer is removed by using a water vapor hydrolysis process or a silane thermal decomposition process.

10. The method for preparing a semiconductor device according to any one of claims 1 to 9, wherein: The contact layer includes a tantalum metal nitride layer.

11. A semiconductor device, wherein the semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 10.

12. The semiconductor device according to claim 11, wherein The thickness of each region of the semiconductor layer is the same.

13. The semiconductor device according to claim 11 or 12, wherein: The pattern of the contact layer on the first source / drain electrode overlaps with the pattern of the first source / drain electrode; The pattern of the anti-oxidation conductive layer on the second source / drain electrode overlaps with the pattern of the second source / drain electrode.

14. The semiconductor device according to any one of claims 11 to 13, wherein: The contact layer includes a tantalum metal nitride layer.

15. The semiconductor device according to any one of claims 11 to 14, wherein: The interlayer dielectric layer includes a silicon oxide film layer. 16 . An electronic device comprising the semiconductor device according to claim 11 .

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