Light-emitting substrate and manufacturing method therefor

Abstract

Disclosed are a light-emitting substrate and a manufacturing method therefor. The light-emitting substrate comprises: a base layer; and a plurality of light-emitting chips arranged on the base layer. Each light-emitting chip comprises: a first electrode, a second electrode, and a light-emitting body; the first electrode is located between the light-emitting body and the base layer; the light-emitting body comprises a first semiconductor layer, a light-emitting functional layer, and a second semiconductor layer which are sequentially arranged in the direction away from the first electrode; the second electrode is electrically connected to the second semiconductor layer; a trench is formed in the light-emitting body, and at least runs through the first semiconductor layer and the light-emitting functional layer in the thickness direction of the light-emitting body, so as to divide the light-emitting functional layer into a plurality of light-emitting parts and divide the first semiconductor layer into a plurality of first semiconductor parts; the first electrode comprises a plurality of first sub-electrodes which arranged at intervals, and the first sub-electrodes are connected to the first semiconductor parts in one-to-one correspondence; and the plurality of first sub-electrodes of the same light-emitting chip are configured to load voltages in the same state.

Description

Light-emitting substrate and manufacturing method thereof Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a light-emitting substrate and a manufacturing method thereof. Background Art

[0002] Miniature inorganic light-emitting diodes include MiniLED and MicroLED. MiniLED refers to light-emitting diode (LED) chips with a crystal size of approximately 100 to 300 microns. MicroLED refers to LED chips with a crystal size of less than 100 microns. Display devices using MiniLED / MicroLED offer advantages such as low power consumption, high brightness, high resolution, high color saturation, fast response, long life, and high efficiency.

[0003] Summary of the Invention

[0004] In a first aspect, the present disclosure provides a light-emitting substrate, comprising:

[0005] grassroots;

[0006] A plurality of light-emitting chips are provided on the base layer, the light-emitting chips comprising: a first electrode, a second electrode, and a light-emitting body, wherein the first electrode is located between the light-emitting body and the base layer, the light-emitting body comprising a first semiconductor layer, a light-emitting functional layer, and a second semiconductor layer sequentially arranged in a direction away from the first electrode; the second electrode is electrically connected to the second semiconductor layer; a groove is provided on the light-emitting body, the groove penetrating at least the first semiconductor layer and the light-emitting functional layer along the thickness direction of the light-emitting body, so as to divide the light-emitting functional layer into a plurality of light-emitting portions and the first semiconductor layer into a plurality of first semiconductor portions; the first electrode comprises a plurality of first sub-electrodes spaced apart from each other, the first sub-electrodes being connected to the first semiconductor portions in a one-to-one correspondence;

[0007] The plurality of first sub-electrodes of the same light-emitting chip are configured to be loaded with voltages of the same state, so that the light-emitting states of the plurality of light-emitting portions are the same.

[0008] In some embodiments, the light emitting body and the second electrode are located on the same side of the second semiconductor layer.

[0009] In some embodiments, the second electrode is located on a side of the second semiconductor layer away from the light emitting body.

[0010] In some embodiments, the sum of the light-emitting areas of the plurality of light-emitting portions is 50% to 80% of the orthographic projection area of ​​the second semiconductor layer on the base layer.

[0011] In some embodiments, the light-emitting chip further includes a reflective layer, which is disposed in the groove and is configured to reflect the light irradiated from the light-emitting portion onto the reflective layer toward the second semiconductor layer.

[0012] In some embodiments, the light-emitting chip further comprises: a plurality of current spreading layers, the current spreading layers corresponding one to one with the first sub-electrodes, the first sub-electrodes being electrically connected to the first semiconductor layer through the current spreading layers;

[0013] The trench has a first opening facing away from the second semiconductor layer, and an orthographic projection of the current spreading layer on the base layer overlaps with an orthographic projection of the first opening on the base layer;

[0014] An orthographic projection of the reflective layer on the base layer has no overlap with an orthographic projection of the current spreading layer on the base layer.

[0015] In some embodiments, the maximum distance from the reflective layer to the base layer is greater than or equal to the distance from the surface of the light-emitting portion away from the base layer to the base layer;

[0016] The minimum distance between the reflective layer and the base layer is less than or equal to the distance between the surface of the light emitting portion close to the base layer and the base layer.

[0017] In some embodiments, the reflective layer is conformal to the inner wall of the groove, and the cross-sectional area of ​​the groove gradually decreases in a direction away from the base layer;

[0018] The cross section of the groove is a cross section of the groove parallel to the base layer.

[0019] In some embodiments, an orthographic projection of the first electrode on the base layer does not overlap with an orthographic projection of the reflective layer on the base layer.

[0020] In some embodiments, the first electrode and the reflective layer are made of the same material.

[0021] In some embodiments, the light-emitting chip further includes a passivation layer, which covers at least the side walls of the groove and the surface of the current spreading layer away from the first semiconductor layer. The reflective layer is arranged on the surface of the passivation layer away from the inner wall of the groove, and the first sub-electrode is electrically connected to the current spreading layer through a via hole penetrating the passivation layer.

[0022] In some embodiments, the current spreading layer includes a first surface facing the first semiconductor layer, a second surface facing away from the first semiconductor layer, and a side surface connected therebetween, wherein the first surface includes a first subsurface in contact with the first semiconductor layer and a second subsurface not in contact with the first semiconductor layer;

[0023] The passivation layer also covers at least a portion of the second sub-surface and at least a portion of the side surface.

[0024] In some embodiments, the first semiconductor layer includes a third surface away from the light-emitting functional layer, and a maximum size of the third surface in the first direction is L-(N-1)*5 μm; a maximum size of the third surface in the second direction is W-(M-1)*5 μm;

[0025] The first direction is perpendicular to the second direction, L is the size of the light-emitting chip in the first direction, W is the size of the light-emitting chip in the second direction, N is the maximum number of the light-emitting parts in the first direction, and M is the maximum number of the light-emitting parts in the second direction.

[0026] In some embodiments, the orthographic projection of the groove on the base layer is annular;

[0027] The light-emitting chip includes a plurality of grooves, and the plurality of grooves are nested in sequence.

[0028] In some embodiments, the light-emitting chip is a mini-LED light-emitting chip or a Micro-LED light-emitting chip.

[0029] In some embodiments, the light-emitting substrate is a display panel, which includes multiple pixel areas, each of which includes a red sub-pixel area, a green sub-pixel area, and a blue sub-pixel area, and the light-emitting chip is disposed in at least one of the sub-pixel areas.

[0030] In a second aspect, the present disclosure further provides a method for manufacturing a light-emitting substrate, comprising:

[0031] forming a plurality of light-emitting bodies on a first substrate, wherein the light-emitting bodies include a second semiconductor layer, a light-emitting functional layer, and a first semiconductor layer sequentially arranged in a direction away from the first substrate;

[0032] forming a groove on each of the light-emitting bodies, wherein the groove penetrates at least the first semiconductor layer and the light-emitting functional layer along the thickness direction of the light-emitting body, so as to divide the light-emitting functional layer into a plurality of light-emitting portions and the first semiconductor layer into a plurality of first semiconductor portions;

[0033] A first electrode is formed on a side of each light-emitting body away from the first substrate, wherein the first electrode includes a plurality of first sub-electrodes, and the first sub-electrodes are connected to the first semiconductor portions in a one-to-one correspondence;

[0034] disposing a second substrate on the first electrode and removing the first substrate;

[0035] forming a second electrode on each of the second semiconductor layers to obtain a plurality of light-emitting chips including a first electrode, a second electrode and a light-emitting body;

[0036] transferring the plurality of light-emitting chips onto a substrate;

[0037] The plurality of first sub-electrodes of the same light-emitting chip are configured to be loaded with voltages of the same state, so that the light-emitting states of the plurality of light-emitting parts of the light-emitting chip are the same.

[0038] In some embodiments, the manufacturing method further comprises:

[0039] A reflective layer is formed in the groove, and the reflective layer is used to reflect the light irradiated from the light-emitting functional layer to the reflective layer toward the second semiconductor layer.

[0040] In some embodiments, the step of forming a groove on the light emitting body includes:

[0041] forming a current spreading layer corresponding one-to-one to the first semiconductor portion;

[0042] Using the current spreading layer as a mask, etching the light emitting body to form the groove;

[0043] The trench has a first opening facing away from the second semiconductor layer, and an orthographic projection of the current spreading layer on the first substrate overlaps with an orthographic projection of the first opening on the first substrate;

[0044] An orthographic projection of the reflective layer on the first substrate does not overlap with an orthographic projection of the current spreading layer on the first substrate.

[0045] In some embodiments, the reflective layer and the first sub-electrode are formed simultaneously, and the steps of forming the reflective layer and the first sub-electrode simultaneously include:

[0046] A conductive material layer is formed, a portion of which is located on a side of the current spreading layer away from the light-emitting functional layer to serve as the first sub-electrode; another portion of the conductive material layer is located in the groove to serve as the reflective layer.

[0047] In some embodiments, before the step of forming a plurality of first electrodes, the method further includes:

[0048] forming a passivation layer, wherein the passivation layer covers at least the inner wall of the trench and the surface of the current spreading layer away from the light-emitting functional layer;

[0049] forming a via hole corresponding to the current spreading layer on the passivation layer;

[0050] The reflective layer is provided on a surface of the passivation layer away from the inner wall of the groove, and the first electrode is electrically connected to the current spreading layer by penetrating the via hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0052] FIG1 is a schematic diagram of a light-emitting substrate provided in some embodiments of the present disclosure.

[0053] FIG2 is a schematic diagram of a single light-emitting chip provided in some embodiments of the present disclosure.

[0054] FIG3 is a schematic diagram of a single light-emitting chip provided in some other embodiments of the present disclosure.

[0055] FIG4 is a curve showing the relationship between luminous efficiency and current density under different luminous areas.

[0056] FIG5 is a schematic diagram of a groove provided in some embodiments of the present disclosure.

[0057] FIG6 is a schematic diagram showing the positional relationship between the grooves of the light-emitting chip and the light-emitting functional layer provided in some examples of the present disclosure.

[0058] FIG7 is a schematic diagram showing the positional relationship between the grooves of the light-emitting chip and the light-emitting functional layer provided in some other examples of the present disclosure.

[0059] 8A to 8I are schematic diagrams of a manufacturing process of a light-emitting substrate provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0060] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0061] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0062] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0063] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 10°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 10°.

[0064] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0065] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0066] Micro-inorganic light-emitting diodes include MiniLED and MicroLED. MiniLED refers to light-emitting diode (LED) chips with a grain size of approximately 100 to 300 microns. MicroLED refers to LED chips with a grain size of less than 100 microns. MiniLED / MicroLED display devices offer advantages such as low power consumption, high brightness, high resolution, high color saturation, fast response, long life, and high efficiency. Furthermore, multiple Mini-LED / Micro-LED display devices can be seamlessly spliced ​​together to create ultra-large display products, which have broad application prospects in large-scale display areas such as command and monitoring centers, commercial centers, high-end conferences, and cinemas.

[0067] Among them, the luminous efficiency of light-emitting diode chips has always been a concern in the display field.

[0068] Figure 1 is a schematic diagram of a light-emitting substrate provided in some embodiments of the present disclosure, Figure 2 is a schematic diagram of a single light-emitting chip provided in some embodiments of the present disclosure, and Figure 3 is a schematic diagram of a single light-emitting chip provided in other embodiments of the present disclosure. As shown in Figures 1 to 3, the light-emitting substrate includes a base layer 10 and a plurality of light-emitting chips arranged on the base layer 10.

[0069] The light-emitting chip 20 includes a first electrode 21, a second electrode 22, and a light-emitting body electrically connected thereto. The first electrode 21 is located between the light-emitting body and the substrate 10. The light-emitting body includes a first semiconductor layer 23, a light-emitting functional layer 25, and a second semiconductor layer 24, arranged in sequence away from the first electrode 21. One of the first semiconductor layer 23 and the second semiconductor layer 24 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. The second electrode 22 is electrically connected to the second semiconductor layer 24.

[0070] As shown in Figures 2 and 3, a groove V is formed on the light-emitting body. The groove V penetrates at least the first semiconductor layer 23 and the light-emitting functional layer 25 along the thickness direction of the light-emitting body, thereby dividing the light-emitting functional layer 25 into multiple light-emitting portions 251 and the first semiconductor layer 23 into multiple first semiconductor portions 231. The first electrode 21 includes multiple first sub-electrodes 211 spaced apart from each other, and the first sub-electrodes 211 are connected to the first semiconductor portions 231 in a one-to-one correspondence. The groove V does not completely penetrate the second semiconductor layer 24. For example, the depth of the groove V can be greater than or equal to the sum of the thicknesses of the first semiconductor layer 23 and the light-emitting functional layer 25, and the depth of the groove V can be less than the sum of the thicknesses of the first semiconductor layer 23, the second semiconductor layer 24, and the light-emitting functional layer 25.

[0071] The multiple first sub-electrodes 211 of the same light-emitting chip 20 are configured to load voltages of the same state, so that the multiple light-emitting portions 251 of the light-emitting chip 20 have the same light-emitting state.

[0072] It should be noted that the light-emitting state of the light-emitting unit 251 refers to the state of being on or off; and the voltage in the same state refers to the voltage that can make the light-emitting states of the plurality of light-emitting units 251 the same.

[0073] In some embodiments, the plurality of first sub-electrodes 211 are configured to apply the same or approximately the same voltage to ensure that the plurality of light-emitting portions 251 of the same light-emitting chip 20 have the same light-emitting state and the same or substantially the same brightness when emitting light. The "approximately the same" voltage refers to a voltage with a difference of no more than 10%.

[0074] The base layer 10 may be a driving backplane, which may provide voltage to the first electrode 21 and the second electrode 22 of each light emitting chip 20 to drive the light emitting chip 20 to light up or turn off.

[0075] In the embodiment of the present disclosure, a groove V is provided on the light-emitting body, thereby dividing the light-emitting functional layer 25 into a plurality of light-emitting portions 251. Compared with the light-emitting functional layer 25 in which the groove V is not provided, the total light-emitting area of ​​the plurality of light-emitting portions 251 is reduced, that is, the total resistance of the plurality of light-emitting portions 251 is reduced, thereby increasing the current density of the light-emitting chip 20, and further improving the luminous efficiency (EQE) of the light-emitting chip 20.

[0076] FIG4 is a curve showing the relationship between luminous efficiency and current density under different luminous areas. In the embodiment of the present disclosure, the current density of the light emitting chip is less than 50A / cm 2 4 , it can be seen that when the current density increases, the luminous efficiency of the light emitting chip 20 is improved.

[0077] In some embodiments, the N-type semiconductor layer may include n-type GaN, and the P-type semiconductor layer may include In x Al y Ga 1-x-y N (0 ≤ x < 1, 0 ≤ y < 1, 0 ≤ x + y < 1) composition p-type nitride semiconductor layer, the p-type impurity can be magnesium. For example, the P-type semiconductor layer can be a single layer structure, but as in some example embodiments, it can have a multi-layer structure containing different components. The light emitting portion 251 can include a light emitting layer, and the light emitting layer can be a multi-quantum well light emitting layer, in which the quantum well layer and the quantum barrier layer are alternately stacked with each other. For example, the quantum well layer and the quantum barrier layer can respectively include In x Al y Ga 1-x-yDifferent components of N(0≤x≤1, 0≤y≤1, 0≤x + y≤1). In one example, the quantum well layer may include In x Ga 1-x components of N(0 < x≤1), and the quantum barrier layer may include GaN or AlGaN.

[0078] In addition, the light emitting portion 251 may further include other film layer structures. For example, an electron blocking layer located between the light emitting layer and the first semiconductor layer 23, and a hole blocking layer located between the light emitting layer and the second semiconductor layer 24.

[0079] It should be noted that the light emitting area of the light emitting portion 251 can be regarded as the surface area of the light emitting layer in the light emitting portion 251 close to the first semiconductor layer 23.

[0080] In some embodiments, the thickness of the P-type semiconductor layer can be between and the thickness of the light emitting functional layer 25 is between and the thickness of the N-type semiconductor layer can be between 2.5 μm and 3.5 μm.

[0081] In some embodiments, as shown in FIG. 2, the second electrode 22 can be disposed on the side of the second semiconductor layer 24 away from the light emitting body.

[0082] In some embodiments, the total light emitting area of the plurality of light emitting portions 251 is 50% - 80% of the positive projection area of the second semiconductor layer 24 on the base layer 10, so as to maximize the light emitting efficiency of the light emitting chip 20. For example, the total light emitting area of the plurality of light emitting portions 251 is 50%, or 60%, or 70%, or 80% of the positive projection area of the second semiconductor layer 24 on the base layer 10.

[0083] In some embodiments, as shown in FIGS. 2 and 3, the light emitting chip 20 may further include a reflective layer 40. The reflective layer 40 is disposed in the trench V and is used to reflect the light irradiated from the light emitting portion 251 to the reflective layer 40 towards the second semiconductor layer 24, so that the light of the light emitting portion 251 can pass through the second semiconductor layer 24 as much as possible to improve the light extraction efficiency.

[0084] Among them, the reflective layer 40 can be made of a metal with a high reflectivity to improve the light reflection effect. For example, the material of the reflective layer 40 may include at least one of aluminum (Al), gold (Au), chromium (Cr), titanium (Ti), silver (Ag), zinc (Zn), platinum (Pt).

[0085] As shown in FIG2 , the second electrode 22 can be located on a side of the second semiconductor layer 24 away from the base layer 10. In this case, the second electrode 22 can be made of a transparent conductive material such as indium tin oxide (ITO) to prevent affecting the light output effect of the light-emitting chip 20. In other embodiments, as shown in FIG3 , the light-emitting body and the second electrode 22 can be located on the same side of the second semiconductor layer 24.

[0086] In some embodiments, the maximum distance D1 from the reflective layer 40 to the base layer 10 is greater than or equal to the distance D2 from the surface of the light-emitting portion 251 away from the base layer 10 to the base layer 10, and the minimum distance D4 from the reflective layer 40 to the base layer 10 is less than or equal to the distance D3 from the surface of the light-emitting portion 251 close to the base layer 10 to the reference surface, so that as much light as possible from the light-emitting portion 251 is reflected by the reflective layer 40.

[0087] In one example, the light-emitting portion 251 includes a first surface facing the base layer 10, a second surface facing away from the base layer 10, and a side surface connected between the first surface and the second surface, wherein the positive projection of the reflective layer 40 on the base layer 10 can completely cover the side surface of the light-emitting portion 251, thereby maximizing the light reflection effect of the light-emitting portion 251.

[0088] In some embodiments, as shown in Figures 2 and 3, the reflective layer 40 is conformal to the inner wall of the groove V, and the cross-sectional area of ​​the groove V gradually decreases in the direction approaching the reference plane to ensure that the reflective layer 40 in the groove V can reflect the light from the light-emitting portion 251 toward the second semiconductor layer 24.

[0089] The cross section of the groove V is a cross section of the groove V parallel to the base layer 10 .

[0090] Here, conformal means that the surface of the reflective layer 40 facing the trench V has the same or substantially the same morphology as the inner wall of the trench V. For example, a passivation layer 30 is provided between the reflective layer 40 and the inner wall of the trench V, and the thickness of the passivation layer 30 is uniformly distributed at various positions, so that the surface of the reflective layer 40 facing the trench V has the same morphology as the inner wall of the trench V.

[0091] In one example, the longitudinal cross-section of the groove V can be a triangle, trapezoid, or other shape, for example, with the side edges of the longitudinal cross-section forming an arc. The longitudinal cross-section of the groove V refers to a cross-section perpendicular to the base layer 10 and perpendicular to the extension direction of the groove V. FIG5 is a schematic diagram of a groove provided in some embodiments of the present disclosure. As shown in FIG5 , the side edges S of the longitudinal cross-section of the groove V can form an inwardly concave arc.

[0092] In some embodiments, as shown in Figures 2 and 3, the light-emitting chip 20 may further include multiple current spreading layers 50. The current spreading layers 50 correspond one-to-one with the first sub-electrodes 211, and the first sub-electrodes 211 are electrically connected to the first semiconductor layer 23 through the current spreading layers 50. The trench V has a first opening facing away from the second semiconductor layer 24, and the orthographic projection of the current spreading layer 50 on the base layer 10 overlaps with the orthographic projection of the first opening on the base layer 10. The orthographic projection of the reflective layer 40 on the base layer 10 does not overlap with the orthographic projection of the current spreading layer 50 on the base layer 10. This non-overlap can mean a gap between the two orthographic projections, or a contact between the two orthographic projections without overlapping.

[0093] During the manufacturing process of the reflective layer 40 , the current spreading layer 50 in FIG. 2 and FIG. 3 can serve as a blocking layer to prevent the reflective layer 40 from being electrically connected to the first sub-electrode 211 and thus interfering with the electric field between the first sub-electrode 211 and the second electrode 22 .

[0094] In some embodiments, the current spreading layer 50 may be made of a metal material, so that the light emitting body may be etched using the current spreading layer 50 as a mask to form a trench V whose opening overlaps with the projection of the current spreading layer 50 .

[0095] In some embodiments, the orthographic projection of the first electrode 21 on the base layer 10 does not overlap with the orthographic projection of the reflective layer 40 on the base layer 10 , so as to prevent the first electrode 21 from being electrically connected to the reflective layer 40 .

[0096] In some embodiments, the reflective layer 40 and the first sub-electrode 211 are made of the same material, allowing them to be formed simultaneously, simplifying the fabrication process. For example, a conductive material layer can be deposited such that a portion of the conductive material layer is deposited on the side of the current spreading layer 50 away from the light-emitting portion 251, thereby serving as the first sub-electrode 211; the remaining portion of the conductive material layer is located in the trench V, thereby serving as the reflective layer 40.

[0097] In some embodiments, the overlap width between the orthographic projection of the current spreading layer 50 on the base layer 10 and the orthographic projection of the first opening on the base layer 10 is greater than or equal to 1 μm, thereby ensuring that the current spreading layer 50 can act as a barrier during the deposition of the conductive material layer, preventing the reflective layer 40 in the trench V from electrically connecting to the first sub-current. However, it should be understood that the provision of the current spreading layer 50 should not affect the deposition of the reflective layer 40. For example, the orthographic projection of the current spreading layer 50 on the base layer 10 is located within the orthographic projection of the surface of the light-emitting portion 251 facing the base layer 10 on the base layer 10.

[0098] In some embodiments, as shown in Figures 2 and 3, the light-emitting chip 20 further includes a passivation layer 30. The passivation layer 30 covers at least the sidewalls of the trench V and the surface of the current spreading layer 50 away from the light-emitting functional layer 23. The reflective layer 40 is disposed on the surface of the passivation layer 30 away from the inner wall of the trench V. The first sub-electrode 211 is electrically connected to the current spreading layer 50 via a via extending through the passivation layer 30. The provision of the passivation layer 30 insulates and separates the reflective layer 40 from the light-emitting portion 251 and protects the side surfaces of the light-emitting functional layer 25.

[0099] The passivation layer 30 may be made of silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), etc. The passivation layer 30 may be one layer or multiple layers.

[0100] In some embodiments, the current spreading layer 50 includes a first surface facing the first semiconductor layer 23, a second surface facing away from the first semiconductor layer 23, and side surfaces connected therebetween. The first surface includes a first subsurface in contact with the first semiconductor layer 23 and a second subsurface not in contact with the first semiconductor layer 23. The passivation layer 30 also covers at least a portion of the second subsurface and at least a portion of the side surfaces. In other words, the passivation layer 30 half-encloses the current spreading layer 50, thereby improving the stability of the light-emitting chip 20.

[0101] In some embodiments, the first semiconductor layer 23 includes a third surface away from the light-emitting functional layer 25. This third surface is the sum of the surfaces of the multiple first semiconductor portions 231 away from the light-emitting functional layer 25. Due to process precision, the width of the first opening of the groove V between two adjacent light-emitting portions 251 must be at least 5 μm. When the groove V is located at the edge of the light-emitting chip 20, and is adjacent to the light-emitting portion 251 only on one side, with no light-emitting portion 251 on the other side, the first opening of the groove V must be at least 2.5 μm. In this case, the maximum size of the third surface in the first direction is L-(N-1)*5 μm; the maximum size of the third surface in the second direction is W-(M-1)*5 μm, to ensure that the required groove V can be formed on the light-emitting body. The first and second directions are both parallel to the base layer 10 and perpendicular to each other. L is the size of the light-emitting chip 20 in the first direction, W is the size of the light-emitting chip 20 in the second direction, N is the maximum number of light-emitting portions 251 in the first direction, and M is the maximum number of light-emitting portions 251 in the second direction.

[0102] In practical applications, the shape and distribution of the grooves V can be set according to actual needs.

[0103] Figure 6 is a schematic diagram of the positional relationship between the grooves of the light-emitting chip and the light-emitting functional layer provided in some examples of the present disclosure. As shown in Figure 6, in some examples, the light-emitting functional layer 25 is divided into multiple light-emitting portions 251, and the multiple light-emitting portions 251 are arranged in one row and multiple columns, or multiple rows and one column, or multiple rows and multiple columns, wherein one of the first direction and the second direction can be a row direction, and the other can be a column direction.

[0104] Figure 7 is a schematic diagram of the positional relationship between the grooves and the light-emitting functional layer of the light-emitting chip provided in other examples of the present disclosure. As shown in Figure 7, in other examples, the positive projection of the groove V on the base layer 10 is a ring, which can be a rectangular ring, a circular ring, or an elliptical ring; the light-emitting chip 20 includes a plurality of grooves V, and the plurality of grooves V are nested in sequence.

[0105] In some embodiments, the light-emitting chip 20 is a mini-LED light-emitting chip or a Micro-LED light-emitting chip. In one example, the driving backplane may be a silicon substrate provided with a driving circuit, and the driving circuit may be embedded in the silicon substrate. In another example, the driving backplane may include a substrate and a driving circuit provided on the substrate, and the substrate may be a glass substrate or a flexible substrate made of materials such as polyimide (PI). In the process of making the light-emitting substrate, the driving backplane may be made first, and a plurality of light-emitting chips 20 may be made on other substrates, and then the plurality of light-emitting chips 20 may be transferred to the driving backplane. A first soldering pad and a second soldering pad are provided on the driving backplane, and the first sub-electrode 211 of the light-emitting chip is electrically connected to the above-mentioned driving circuit through the first soldering pad, and the second electrode 22 is electrically connected to the above-mentioned driving circuit through the second soldering pad.

[0106] In some embodiments of the present disclosure, the light-emitting substrate can be used in a backlight module of a display device and serve as a backlight panel. The display device may also include a liquid crystal panel, which is disposed on the light-emitting side of the light-emitting substrate. For example, the light-emitting chip 20 may emit white light.

[0107] In other embodiments, the light-emitting substrate can serve as a display panel, wherein the display panel includes multiple pixel regions, each of which can include multiple sub-pixel regions, such as a red sub-pixel region, multiple green sub-pixel regions, and multiple blue sub-pixel regions. The light-emitting chip 20 is disposed in at least one sub-pixel region. For example, a light-emitting chip 20 is disposed in each red sub-pixel region, each green sub-pixel region, and each sub-blue pixel region. The light-emitting chip 20 in each sub-pixel region emits the same color as the sub-pixel region.

[0108] The present disclosure also provides a method for manufacturing a light-emitting substrate, including the following steps S10 to S60:

[0109] S10. Form a plurality of light-emitting bodies on the first substrate, wherein the light-emitting bodies include a second semiconductor layer, a light-emitting functional layer, and a first semiconductor layer sequentially arranged in a direction away from the first substrate.

[0110] S20, forming a groove on each light-emitting body, wherein the groove penetrates at least the first semiconductor layer and the light-emitting functional layer along the thickness direction of the light-emitting body, so as to divide the light-emitting functional layer into a plurality of light-emitting portions and the first semiconductor layer into a plurality of first semiconductor portions.

[0111] S30 , forming a first electrode on a side of each light-emitting body away from the first substrate, wherein the first electrode includes a plurality of first sub-electrodes, and the first sub-electrodes are connected to the first semiconductor portions in a one-to-one correspondence.

[0112] S40 , disposing a second substrate on the first electrode, and removing the first substrate.

[0113] S50 , forming a second electrode connected to each second semiconductor layer to obtain a plurality of light-emitting chips including a first electrode, a second electrode and a light-emitting body.

[0114] S60: Transferring the plurality of light-emitting chips to the substrate.

[0115] The plurality of first sub-electrodes of the same light-emitting chip are configured to be loaded with voltages of the same state, so that the light-emitting states of the plurality of light-emitting parts of the light-emitting chip are the same.

[0116] FIG8A to FIG8I are schematic diagrams of a manufacturing process of a light-emitting substrate provided in some embodiments of the present disclosure. The manufacturing process includes: preparing a plurality of light-emitting chips 20, and then transferring the plurality of light-emitting chips 20 to a base layer 10. Specifically, the manufacturing method of the light-emitting substrate includes:

[0117] S100 , as shown in FIG8A , a plurality of light emitting bodies 20 a are formed on a first substrate SUB1 , wherein the light emitting bodies 20 a include a second semiconductor layer 24 , a light emitting functional layer 25 and a first semiconductor layer 23 , which are sequentially arranged in a direction away from the first substrate SUB1 .

[0118] The first substrate SUB1 may be a glass substrate, and the light-emitting body 20a may be disposed on the first substrate SUB1 by adhesive bonding, metal bonding, etc. A plurality of light-emitting bodies 20a may be transferred to the first substrate SUB1, or a single light-emitting body may be transferred to the first substrate SUB1 and patterned to form a plurality of light-emitting bodies 20a.

[0119] S200: forming a groove V on each light-emitting body 20a. Specifically, this step includes:

[0120] S210: As shown in FIG8B , a plurality of current spreading layers 50 are formed on the light emitting body 20a. The material of the current spreading layer 50 may include metal.

[0121] S220. As shown in FIG8C , the light emitting body is etched using the current spreading layer 50 as a mask to form a groove V. The groove V penetrates at least the first semiconductor layer 23 and the light emitting functional layer 25 along the thickness direction of the light emitting body 20a, thereby dividing the light emitting functional layer 25 into a plurality of light emitting portions 251 and the first semiconductor layer 23 into a plurality of first semiconductor portions 231. The first semiconductor portions 231 correspond one to one with the current spreading layer 50.

[0122] The trench V has a first opening facing away from the second semiconductor layer 24 , and an orthographic projection of the current spreading layer 50 on the first substrate SUB1 overlaps with an orthographic projection of the first opening on the first substrate SUB1 .

[0123] S300 , as shown in FIG8D , a passivation layer 30 is formed. The passivation layer 30 at least covers the inner wall of the trench V and the surface of the current spreading layer 50 away from the light-emitting functional layer 25 .

[0124] S400 , as shown in FIG. 8E , forming a via hole 30 v corresponding to the current spreading layer 50 on the passivation layer 30 .

[0125] In some embodiments, the current spreading layer 50 includes a first surface facing the first semiconductor layer 23, a second surface facing away from the first semiconductor layer 23, and side surfaces connected therebetween. The first surface includes a first subsurface in contact with the first semiconductor layer 23 and a second subsurface not in contact with the first semiconductor layer 23. After the via hole 30v is formed, the passivation layer 30 further covers at least a portion of the second subsurface and at least a portion of the side surfaces.

[0126] S500 , forming a reflective layer 40 in the groove V, and forming a first electrode 21 on a side of each light emitting body away from the first substrate SUB1 . The reflective layer 40 is used to reflect light from the light emitting functional layer 25 to the reflective layer 40 toward the second semiconductor layer 24 .

[0127] Among them, the reflective layer 40 and the first electrode 21 are formed simultaneously. Specifically, the process of synchronously forming the reflective layer 40 and the first electrode 21 includes: as shown in Figure 8F, forming a conductive material layer, a portion of the conductive material layer is located on the side of the current spreading layer 50 away from the light-emitting functional layer 25 to serve as the first sub-electrode 211; another portion of the conductive material layer is located in the groove V to serve as the reflective layer 40.

[0128] The conductive material layer may be a metal material layer.

[0129] S600: As shown in FIG8G , a second substrate SUB2 is disposed on the first electrode 21, and the first substrate SUB1 is removed. The second substrate SUB2 can be disposed on the first electrode 21 by adhesive bonding, metal bonding, etc. The second substrate SUB2 can be a glass substrate.

[0130] S700 , as shown in FIG8H , forming a second electrode 22 on each second semiconductor layer 24 , thereby obtaining a plurality of light emitting chips 20 including a first electrode 21 , a second electrode 22 and a light emitting body.

[0131] S800: As shown in FIG8I , multiple light-emitting chips 20 are transferred onto a substrate 10. The substrate 10 includes multiple pixel regions, each of which is provided with light-emitting chips 20. Furthermore, multiple first sub-electrodes 211 of the same light-emitting chip 20 are configured to be loaded with the same voltage, so that the multiple light-emitting portions 251 of the light-emitting chip 20 emit the same light.

[0132] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A light-emitting substrate, comprising: Grassroots; A plurality of light-emitting chips are arranged on the base layer, the light-emitting chips comprising: a first electrode, a second electrode and a light-emitting body, the first electrode is located between the light-emitting body and the base layer, the light-emitting body comprises a first semiconductor layer, a light-emitting functional layer and a second semiconductor layer arranged in sequence in a direction away from the first electrode; the second electrode is electrically connected to the second semiconductor layer; a groove is provided on the light-emitting body, the groove at least penetrates the first semiconductor layer and the light-emitting functional layer in a thickness direction of the light-emitting body, so as to divide the light-emitting functional layer into a plurality of light-emitting parts, and divide the first semiconductor layer into a plurality of first semiconductor parts; the first electrode comprises a plurality of first sub-electrodes spaced from each other, and the first sub-electrodes are connected to the first semiconductor parts in a one-to-one correspondence; The plurality of first sub-electrodes of the same light-emitting chip are configured to load voltages of the same state, so that the light-emitting states of the plurality of light-emitting portions are the same.

2. The light-emitting substrate according to claim 1, wherein: The light emitting body and the second electrode are located on the same side of the second semiconductor layer.

3. The light-emitting substrate according to claim 1, wherein: The second electrode is located at a side of the second semiconductor layer away from the light emitting body.

4. The light-emitting substrate according to any one of claims 1 to 3, wherein The sum of the light emitting areas of the plurality of light emitting portions is 50% to 80% of the orthographic projection area of ​​the second semiconductor layer on the base layer.

5. The light-emitting substrate according to any one of claims 1 to 3, wherein The light emitting chip further includes a reflective layer, which is disposed in the groove and is used to reflect the light irradiated by the light emitting portion to the reflective layer toward the second semiconductor layer.

6. The light emitting substrate according to claim 5, wherein: The light emitting chip further comprises: a plurality of current spreading layers, the current spreading layers corresponding to the first sub-electrodes one by one, and the first sub-electrodes being electrically connected to the first semiconductor layer through the current spreading layers; The trench has a first opening facing away from the second semiconductor layer, and an orthographic projection of the current spreading layer on the base layer overlaps with an orthographic projection of the first opening on the base layer; An orthographic projection of the reflective layer on the base layer has no overlap with an orthographic projection of the current spreading layer on the base layer.

7. The light-emitting substrate according to claim 5, wherein: The maximum distance from the reflective layer to the base layer is greater than or equal to the distance from the surface of the light-emitting portion away from the base layer to the base layer; The minimum distance from the reflective layer to the base layer is less than or equal to the distance from the surface of the light emitting portion close to the base layer to the base layer.

8. The light emitting substrate according to claim 5, wherein: The reflective layer is conformal to the inner wall of the groove, and the cross-sectional area of ​​the groove gradually decreases in a direction away from the base layer; The cross section of the groove is a cross section of the groove parallel to the base layer.

9. The light emitting substrate according to claim 5, wherein: An orthographic projection of the first electrode on the base layer has no overlap with an orthographic projection of the reflective layer on the base layer.

10. The light emitting substrate according to claim 5, wherein: The first electrode and the reflective layer are made of the same material.

11. The light emitting substrate according to claim 5, wherein: The light-emitting chip also includes a passivation layer, which covers at least the side walls of the groove and the surface of the current spreading layer away from the first semiconductor layer. The reflective layer is arranged on the surface of the passivation layer away from the inner wall of the groove. The first sub-electrode is electrically connected to the current spreading layer through a via hole penetrating the passivation layer.

12. The light emitting substrate according to claim 11, wherein: The current spreading layer comprises a first surface facing the first semiconductor layer, a second surface facing away from the first semiconductor layer, and a side surface connected therebetween, wherein the first surface comprises a first subsurface in contact with the first semiconductor layer, and a second subsurface not in contact with the first semiconductor layer; The passivation layer also covers at least a portion of the second sub-surface and at least a portion of the side surface.

13. The light-emitting substrate according to any one of claims 1 to 3, wherein: The first semiconductor layer includes a third surface away from the light-emitting functional layer, the maximum size of the third surface in the first direction is L-(N-1)*5 μm; the maximum size of the third surface in the second direction is W-(M-1)*5 μm; The first direction is perpendicular to the second direction, L is the size of the light-emitting chip in the first direction, W is the size of the light-emitting chip in the second direction, N is the maximum number of the light-emitting parts in the first direction, and M is the maximum number of the light-emitting parts in the second direction.

14. The light-emitting substrate according to any one of claims 1 to 3, wherein: The orthographic projection of the groove on the base layer is a ring; The light emitting chip comprises a plurality of the grooves, and the plurality of grooves are nested in sequence.

15. The light-emitting substrate according to any one of claims 1 to 3, wherein: The light-emitting chip is a mini-LED light-emitting chip or a Micro-LED light-emitting chip.

16. The light-emitting substrate according to any one of claims 1 to 3, wherein: The light-emitting substrate is a display panel, which includes a plurality of pixel areas, including a red sub-pixel area, a green sub-pixel area and a blue sub-pixel area, and the light-emitting chip is disposed in at least one of the sub-pixel areas.

17. A method for manufacturing a light-emitting substrate, wherein: include: forming a plurality of light-emitting bodies on a first substrate, wherein the light-emitting bodies include a second semiconductor layer, a light-emitting functional layer and a first semiconductor layer which are sequentially arranged in a direction away from the first substrate; forming a groove on each of the light-emitting bodies, wherein the groove penetrates at least the first semiconductor layer and the light-emitting functional layer along the thickness direction of the light-emitting body, so as to divide the light-emitting functional layer into a plurality of light-emitting portions and divide the first semiconductor layer into a plurality of first semiconductor portions; A first electrode is formed on a side of each of the light-emitting bodies away from the first substrate, wherein the first electrode includes a plurality of first sub-electrodes, and the first sub-electrodes are connected to the first semiconductor parts in a one-to-one correspondence; Disposing a second substrate on the first electrode, and removing the first substrate; forming a second electrode on each of the second semiconductor layers to obtain a plurality of light-emitting chips including a first electrode, a second electrode and a light-emitting body; Transferring a plurality of the light-emitting chips to a substrate; The plurality of first sub-electrodes of the same light-emitting chip are configured to load voltages of the same state, so that the light-emitting states of the plurality of light-emitting parts of the light-emitting chip are the same.

18. The method according to claim 17, wherein: The production method further comprises: A reflective layer is formed in the groove, and the reflective layer is used to reflect the light irradiated from the light-emitting functional layer to the reflective layer toward the second semiconductor layer.

19. The method according to claim 18, wherein: The step of forming a groove on the light emitting body comprises: forming a current spreading layer corresponding one-to-one to the first semiconductor portion; Using the current spreading layer as a mask, etching the light emitting body to form the groove; The groove has a first opening facing away from the second semiconductor layer, and an orthographic projection of the current spreading layer on the first substrate overlaps with an orthographic projection of the first opening on the first substrate; An orthographic projection of the reflective layer on the first substrate has no overlap with an orthographic projection of the current spreading layer on the first substrate.

20. The method according to claim 19, wherein: The reflective layer is formed synchronously with the first sub-electrode, and the steps of synchronously forming the reflective layer and the first sub-electrode include: A conductive material layer is formed, a portion of which is located on a side of the current spreading layer away from the light-emitting functional layer to serve as the first sub-electrode; another portion of the conductive material layer is located in the groove to serve as the reflective layer.

21. The method according to claim 19, wherein: Before the step of forming a plurality of first electrodes, the method further includes: forming a passivation layer, wherein the passivation layer at least covers the inner wall of the groove and the surface of the current spreading layer away from the light-emitting functional layer; forming a via hole corresponding to the current spreading layer on the passivation layer; The reflective layer is arranged on a surface of the passivation layer away from the inner wall of the groove, and the first electrode is electrically connected to the current spreading layer by penetrating the via hole.

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