Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that exhibits a fast operating speed. The semiconductor device includes a transistor, and the transistor includes a plurality of oxide semiconductors having a fin shape in a cross-sectional view in the channel width direction. Below the oxide semiconductor there is disposed an insulator having a shape in plan view that matches or substantially matches the oxide semiconductor. A gate insulator is disposed so as to cover the insulator and the oxide semiconductor, and a gate electrode is disposed on the gate insulator. In a cross-sectional view in the channel width direction of the transistor, the bottom surface of the gate electrode is disposed below the bottom surface of the oxide semiconductor. The insulator under the oxide semiconductor functions to capture or fix hydrogen.

Description

Semiconductor device and method for manufacturing the same

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor layer. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic units, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0010] Another object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated.Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity.Another object of one embodiment of the present invention is to provide a memory device with high operation speed.Another object of one embodiment of the present invention is to provide a memory device with low power consumption.Another object of one embodiment of the present invention is to provide a novel memory device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention provides a transistor including a first insulator and a second insulator. The transistor includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, and the third insulator. The first insulator is provided over a substrate, the oxide semiconductor is provided over the first insulator, the first conductor and the second conductor are provided over the oxide semiconductor, and the second insulator is provided over the first conductor and the second conductor. The second insulator has an opening that overlaps with a region between the first conductor and the second conductor in the oxide semiconductor in a plan view. The third insulator has an opening so as to have a region in contact with the oxide semiconductor. the third conductor is provided inside the opening, and the third conductor is provided on the third insulator inside the opening, the shape of the first insulator in a plan view and the shape of the oxide semiconductor in a plan view are the same or substantially the same at least in a region overlapping with the opening, the bottom surface of the third conductor is located below the bottom surface of the oxide semiconductor in a cross-sectional view in the channel width direction of the transistor, the first insulator has a metal oxide, the height of the oxide semiconductor is equal to or greater than the width of the oxide semiconductor in a cross-sectional view in the channel width direction of the transistor, and the semiconductor device has two or more regions where the oxide semiconductor and the third conductor overlap in a plan view.

[0013] Alternatively, in the above aspect, the oxide semiconductor may have a circumferential shape in which both ends coincide or approximately coincide in plan view.

[0014] Alternatively, in the above aspect, the side surface of the opening may coincide or substantially coincide with the side surface of the first conductor and the side surface of the second conductor in a plan view.

[0015] Alternatively, in the above embodiment, the width of the oxide semiconductor may be 5 nm to 50 nm in a cross-sectional view of the transistor in the channel width direction, and the height of the oxide semiconductor may be 1.5 to 10 times the width of the oxide semiconductor in the cross-sectional view of the transistor in the channel width direction.

[0016] Alternatively, in the above aspect, the oxide semiconductor may contain indium, may be formed perpendicular or substantially perpendicular to the surface of the substrate, and when a cross section of the oxide semiconductor is observed using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate may be observed.

[0017] Alternatively, in the above aspect, the oxide semiconductor may contain indium, may be formed perpendicular or substantially perpendicular to a surface of the substrate, may have a first region, a second region in contact with the first region, and a third region in contact with the second region, and in cross-sectional observation of the oxide semiconductor using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate may be observed in each of the first region, the second region, and the third region.

[0018] Alternatively, in the above embodiment, the second region may contain zinc, and the second region may have crystals whose c-axes are approximately parallel to the normal to the side surfaces of the oxide semiconductor.

[0019] Alternatively, in the above aspect, the indium content in the first region may be higher than the indium content in the second region, and the indium content in the third region may be higher than the indium content in the second region.

[0020] Another embodiment of the present invention includes a transistor, a capacitor, a first insulator, a second insulator, and a third insulator. The transistor includes a first oxide semiconductor, a first conductor, a second conductor, a third conductor, and a fourth insulator. The capacitor includes a second oxide semiconductor, a second conductor, a fourth conductor, and a fifth insulator. The first insulator and the second insulator are provided on the same surface of a substrate. The first oxide semiconductor is provided over the first insulator. The second oxide semiconductor is provided over a first conductor provided on the first oxide semiconductor; a second conductor provided on the first oxide semiconductor and the second oxide semiconductor; a third insulator provided on the first conductor and the second conductor; the third insulator having a first opening overlapping a region between the first conductor and the second conductor in the first oxide semiconductor in a plan view; the third insulator having a second opening overlapping the second oxide semiconductor and reaching the second conductor; the third conductor is provided on the fourth insulator inside the first opening, the fifth insulator is provided inside the second opening overlapping the second conductor, the fourth conductor is provided on the fifth insulator inside the second opening, and the shape of the first insulator in a plan view and the shape of the first oxide semiconductor in a plan view are identical or substantially identical at least in the region overlapping with the first opening, and the third conductor is provided inside the first opening so as to have a region in contact with the first oxide semiconductor; In the semiconductor device, the shape of the second insulator in a plan view and the shape of the second oxide semiconductor in a plan view are the same or substantially the same in a region overlapping with the opening, the bottom surface of the third conductor is located below the bottom surface of the first oxide semiconductor in a cross-sectional view in the channel width direction of the transistor, the height of the first oxide semiconductor is equal to or greater than the width of the first oxide semiconductor in a cross-sectional view in the channel width direction of the transistor, and the semiconductor device has two or more regions where the first oxide semiconductor and the third conductor overlap in a plan view.

[0021] Alternatively, in the above aspect, the first insulator and the second insulator may include a metal oxide.

[0022] Alternatively, in the above embodiment, the height of the second oxide semiconductor may be equal to or greater than the width of the second oxide semiconductor in a cross-sectional view of the transistor in the channel width direction, and the transistor may have two or more regions where the second oxide semiconductor and the fourth conductor overlap with each other in a plan view.

[0023] Alternatively, in the above embodiment, the metal oxide may have a function of capturing or fixing hydrogen.

[0024] Alternatively, in the above embodiment, the metal oxide may be a high-k material.

[0025] Alternatively, in the above embodiment, the metal oxide may be an oxide containing one or both of aluminum and hafnium.

[0026] Alternatively, in the above embodiment, the metal oxide may be hafnium silicate.

[0027] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming an insulating film over a substrate; forming a first insulator over the insulating film; forming an oxide semiconductor film to cover the first insulator; and processing the oxide semiconductor film by anisotropic etching until a top surface of the first insulator is exposed, thereby forming an oxide semiconductor in contact with a side surface of the first insulator. The first insulator is removed, and a region of the insulating film that does not overlap with the oxide semiconductor is removed to form a second insulator. A first conductor is formed to cover the oxide semiconductor and the second insulator. A third insulator is formed over the first conductor. An opening overlapping with the oxide semiconductor is formed in the third insulator by processing the third insulator. The first conductor is processed to form the second conductor and the third conductor opposite each other across the opening in a plan view. A fourth insulator is formed inside the opening so as to be in contact with the oxide semiconductor, the second insulator, and the third insulator. The fourth conductor is formed on the fourth insulator to fill the opening.

[0028] Alternatively, in the above embodiment, aluminum oxide or silicon nitride may be used as the first insulator.

[0029] According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to another embodiment of the present invention, a highly reliable semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to another embodiment of the present invention, a novel semiconductor device can be provided. According to another embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to another embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0030] According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a memory device with a large storage capacity can be provided. According to one embodiment of the present invention, a memory device with a high operating speed can be provided. According to one embodiment of the present invention, a memory device with low power consumption can be provided. According to one embodiment of the present invention, a novel memory device can be provided.

[0031] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0032] FIG. 1A is a plan view illustrating an example of a semiconductor device. FIGS. 1B to 1D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 2A to 2C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 3A to 3C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 4A and 4B are plan views illustrating an example of a part of a semiconductor device. FIGS. 5A to 5D are cross-sectional views illustrating an example of a method for manufacturing an oxide semiconductor. FIGS. 6A to 6D are cross-sectional views illustrating an example of an oxide semiconductor. FIGS. 7A and 7B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 8A to 8C are cross-sectional views illustrating an example of a semiconductor device. FIG. 9A is a plan view illustrating an example of a semiconductor device. FIGS. 9B to 9D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 10A and 10B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views illustrating an example of a semiconductor device. FIG. 12A is a plan view illustrating an example of a semiconductor device. FIGS. 12B to 12D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views illustrating an example of a semiconductor device. 14A to 14C are cross-sectional views showing an example of a semiconductor device. FIGS. 15A and 15B are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 16B to 16D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 17A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 17B to 17D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 18A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 18B to 18D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 19A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 19B to 19D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 20A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 20B to 20D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 21A and 21B are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 22A and 22B are cross-sectional views showing an example of a manufacturing method of a semiconductor device. 23A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 23B to 23D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.FIG. 24A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 24B to 24D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 25A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 25B to 25D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 26A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 26B to 26D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 27A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 27B to 27D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 28A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 28B to 28D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 29A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 29B to 29D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 30 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 31A to 31H are diagrams illustrating an example of a circuit configuration of a memory cell. 32A and 32B are perspective views illustrating an example of the configuration of a semiconductor device. FIG. 33 is a block diagram illustrating a CPU. FIG. 34 is a block diagram illustrating a CPU. FIGS. 35A and 35B are perspective views of a semiconductor device. FIGS. 36A and 36B are perspective views of a semiconductor device. FIGS. 37A and 37B are diagrams illustrating the hierarchy of memory devices in a semiconductor device. FIGS. 38A and 38B are diagrams showing an example of electronic equipment, and FIGS. 38C to 38E are diagrams showing an example of a mainframe computer. FIG. 39 is a diagram showing an example of space equipment. FIG. 40 is a diagram showing an example of a storage system applicable to a data center.

[0033] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0034] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0035] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0036] In order to make the invention easier to understand, particularly in plan views (which may also be called top views) or perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0037] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, an ordinal number assigned to a component in one part of this specification may not match an ordinal number assigned to the same component in another part of this specification or in the claims.

[0038] It should be noted that the terms "film" and "layer" can be interchanged in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". Furthermore, the term "conductor" can be interchanged with the term "conductive layer" or the term "conductive film" in some cases or depending on the situation. Furthermore, the term "insulator" can be interchanged with the term "insulating layer" or the term "insulating film" in some cases or depending on the situation.

[0039] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0040] Although the drawings used in this embodiment mode show the case where the sidewall of the insulator in the opening portion is perpendicular or approximately perpendicular to the substrate surface or the surface where the insulator is formed, the sidewall may have a tapered shape.

[0041] In this specification and the like, the opening also includes, for example, a groove, a slit, and the like.

[0042] In this specification, the term "tapered shape" refers to a shape in which at least a portion of the side surface of the structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily need to be completely flat, and may be substantially planar with a slight curvature or a substantially planar with a slight unevenness.

[0043] In this specification, "having the same or approximately the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a manufacturing process for a memory device, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process have a configuration in which the heights from the reference surface are equal. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "having the same or approximately the same height." For example, in the case of a structure having two layers (here, a first layer and a second layer) with different heights relative to a reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less is also referred to as "having the same or approximately the same height."

[0044] In this specification, "side edges that coincide or substantially coincide" means that, in a plan view (which may also be referred to as a top view), at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "side edges that coincide or substantially coincide" is also used.

[0045] In this specification, the phrase "the shapes in plan view are the same or approximately the same" means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be disposed inside the lower layer, or the upper layer may be disposed outside the lower layer. In these cases, the phrase "the shapes in plan view are the same or approximately the same" may also be used. Furthermore, when the shapes in plan view are the same or approximately the same, it can also be said that the edges are aligned or approximately aligned, or that the side edges are aligned or approximately the same.

[0046] Embodiment 1 In this embodiment, a semiconductor device including an oxide semiconductor layer and a method for manufacturing the semiconductor device will be described with reference to drawings.

[0047] One embodiment of the present invention is a semiconductor device including a transistor, the transistor including a plurality of oxide semiconductors each having a fin-like shape in a cross section in a channel width direction. In the semiconductor device of one embodiment of the present invention, a gate insulator is provided to cover the fin-like oxide semiconductor, and a gate electrode is provided over the gate insulator. The fin-like oxide semiconductor can increase the channel width of the transistor compared to a case where the oxide semiconductor is flat.

[0048] In a semiconductor device according to one embodiment of the present invention, an insulator having a shape in a plan view (which may also be referred to as a top view shape) that is identical or substantially identical to that of the oxide semiconductor is provided under the oxide semiconductor. The thickness of the insulator under the oxide semiconductor is made thicker than the thickness of the gate insulator. This allows the bottom surface of the gate electrode to be located below the bottom surface of the oxide semiconductor in a cross-sectional view of the transistor in the channel width direction.

[0049] By providing the bottom surface of the gate electrode below the bottom surface of the oxide semiconductor, a gate electric field can be applied sufficiently from the top to the bottom of the oxide semiconductor. In other words, in a cross-sectional view of the transistor in the channel width direction, the entire oxide semiconductor is electrically surrounded by the electric field of the gate electrode, and can function as a channel formation region. This improves the electrical characteristics of the transistor. Furthermore, the channel width of the transistor can be increased.

[0050] The insulator under the oxide semiconductor preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor. Therefore, defects in which hydrogen enters oxygen vacancies in the channel formation region (hereinafter referred to as V Ｏ H) can be reduced. Therefore, the electrical characteristics of the transistor can be improved.

[0051] 1A to 1D are diagrams illustrating a structure example of a semiconductor device including a transistor 200 over a substrate (not shown).

[0052] FIG. 1A is a plan view illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 1A , which is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 1A , which is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 1A , which is also a cross-sectional view of the transistor 200 in the channel length direction. The dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of FIG. 1A , some elements are omitted and shown transparently for clarity. In the subsequent plan views, some elements may be omitted or may be shown in a transparent manner. Fig. 2A shows an enlarged view of the vicinity of the conductor 260 in Fig. 1D. Fig. 2B shows an enlarged view of the vicinity of the oxide semiconductor 230 in Fig. 1B. Fig. 2C shows an enlarged view of the vicinity of the oxide semiconductor 230 in Fig. 1C.

[0053] The semiconductor device according to this embodiment includes an insulator 215 on a substrate (not shown), an insulator 216 on the insulator 215, an insulator 221 on the insulator 216, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide semiconductor 230 on the insulator 224, conductors 242a and 242b on the oxide semiconductor 230 and the insulator 222, an insulator 250 on the oxide semiconductor 230 and the insulator 222, and a conductor 260 (conductors 260a and 260b) on the insulator 250. Note that hereinafter, the conductors 242a and 242b may be collectively referred to as the conductor 242.

[0054] An insulator 275 is provided over the conductor 242a, the conductor 242b, and the insulator 222, and an insulator 280 is provided over the insulator 275. The insulators 275 and 280 have an opening 201 that overlaps with a region between the conductor 242a and the conductor 242b of the oxide semiconductor 230 in a plan view. The conductor 242a and the conductor 242b are in contact with the oxide semiconductor 230. The conductor 242a and the conductor 242b are provided to face each other with the opening 201 interposed therebetween in a plan view.

[0055] The insulator 250 is provided inside the opening 201 so as to have a region in contact with the oxide semiconductor 230. The insulator 250 is provided inside the opening 201 so as to be in contact with the oxide semiconductor 230, the insulator 222, the insulator 224, the conductor 242a, the conductor 242b, the insulator 275, and the insulator 280. The conductor 260 is provided on the insulator 250 inside the opening 201. Specifically, the conductor 260 is provided on the insulator 250 so as to fill the opening 201. Furthermore, an insulator 282 is provided on the insulator 280 and the conductor 260. Furthermore, an insulator 283 is provided on the insulator 282.

[0056] The insulators 275, 280, 282, and 283 each have an opening 202a that reaches the conductor 242a and an opening 202b that reaches the conductor 242b. The insulator 241a is provided in contact with the inner wall of the opening 202a, and the conductor 240a is provided in contact with the side surface of the insulator 241a. The lower surface of the conductor 240a is in contact with the upper surface of the conductor 242a. The insulator 241b is provided in contact with the inner wall of the opening 202b, and the conductor 240b is provided in contact with the side surface of the insulator 241b. The lower surface of the conductor 240b is in contact with the upper surface of the conductor 242b. Note that hereinafter, the conductors 240a and 240b may be collectively referred to as the conductor 240. The insulators 241a and 241b may be collectively referred to as the insulator 241. Furthermore, the openings 202a and 202b may be collectively referred to as openings 202.

[0057] The oxide semiconductor 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region that functions as a first gate insulator of the transistor 200.

[0058] The conductor 242a has a region functioning as one of the source electrode and the drain electrode of the transistor 200. The conductor 240a functions as a plug connected to the conductor 242a. The conductor 242b has a region functioning as the other of the source electrode and the drain electrode of the transistor 200. The conductor 240b functions as a plug connected to the conductor 242b.

[0059] The oxide semiconductor 230 is formed in contact with the top surface of the insulator 224. The shape of the insulator 224 in a plan view is the same as or substantially the same as the shape of the oxide semiconductor 230 in a plan view. The oxide semiconductor 230 overlaps with the insulator 224 in a plan view. The bottom surface of the insulator 224 is in contact with the insulator 222. The side surface of the insulator 224 is in contact with the insulator 250, the conductor 242a, and the conductor 242b. The top surface of the insulator 224 is in contact with the bottom surface of the oxide semiconductor 230. Note that the insulators 221 and 222 do not necessarily have to be provided. In this case, the bottom surface of the insulator 224 is in contact with the insulator 216.

[0060] 2B and 2C , the oxide semiconductor 230 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction of the transistor 200. Therefore, the oxide semiconductor 230 can be said to have a fin-like shape. In addition, the stack including the insulator 224 and the oxide semiconductor 230 over the insulator 224 can also be said to have a fin-like shape.

[0061] Here, the aspect ratio of the oxide semiconductor 230 in a cross-sectional view of the transistor 200 in the channel width direction refers to the ratio of the length L of the oxide semiconductor 230 in the A1-A2 direction (which can also be referred to as the width L of the oxide semiconductor 230) to the length H of the oxide semiconductor 230 in a direction perpendicular to the surface on which it is formed (for example, the insulator 222) (which can also be referred to as the height H of the oxide semiconductor 230). Here, when the height H is equal to or greater than the width L, the oxide semiconductor 230 is said to have a fin-like shape. When the height H is less than the width L, the oxide semiconductor 230 may be said to have a flat plate-like shape. Note that the width L can be the width of the bottom surface of the oxide semiconductor 230.

[0062] The aspect ratio of the oxide semiconductor 230 is preferably as large as possible within a range in which the oxide semiconductor 230 does not collapse during the manufacturing process of the transistor 200. The height H of the oxide semiconductor 230 can be 1 to 100 times, preferably 1 to 50 times, more preferably 1 to 30 times, and even more preferably 1.5 to 10 times the width L of the oxide semiconductor 230. The width L can be, for example, 5 to 100 nm, preferably 5 to 50 nm, and more preferably 10 to 30 nm. The height H can be, for example, 5 to 2000 nm, preferably 7.5 to 1000 nm, more preferably 10 to 500 nm, and even more preferably 15 to 300 nm. When the aspect ratio of the oxide semiconductor 230 is in the above range, the insulator 250, the conductor 260, the conductor 242, the conductor 240, and the like can be provided to cover the oxide semiconductor 230 with good coverage.

[0063] 2B , in a cross-sectional view of the transistor 200 in the channel width direction, the angle θ between the side surface of the oxide semiconductor 230 and the top surface of the insulator 224 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°. Note that the angle θ may be the angle between the side surface of the insulator 224 and the top surface of the insulator 222.

[0064] The insulator 250, the conductor 260, and the conductor 242 are provided to cover the oxide semiconductor 230 having such a high aspect ratio. In the transistor 200, as shown in FIG. 2B , parts of the insulator 250 and the conductor 260 are provided so as to sandwich the oxide semiconductor 230 in two. As a result, in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230 and the conductor 260 are provided to face each other with the insulator 250 sandwiched between them at the top, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230. That is, the top, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230 each function as a channel formation region. Therefore, the channel width of the transistor 200 is larger by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230 than when the oxide semiconductor 230 is flat.

[0065] The increase in the channel width as described above can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, in the above structure, by providing the oxide semiconductor 230, the channel width can be increased without increasing the area occupied by the transistor 200. This enables miniaturization or high integration of the semiconductor device. Furthermore, the memory capacity of a memory device using the semiconductor device can be increased. Furthermore, the above structure increases the area where the conductor 260 and the oxide semiconductor 230 face each other, so that the transistor 200 can be made normally off by controlling the threshold voltage.

[0066] 2B and 2C , the upper portion of the oxide semiconductor 230 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulator 250 and the conductor 242 near the upper portion of the oxide semiconductor 230. While FIGS. 2B and 2C illustrate a symmetrical structure in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the oxide semiconductor 230, the present invention is not limited to this. For example, an asymmetrical structure may also be obtained in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the oxide semiconductor 230.

[0067] Because the oxide semiconductor 230 has a high aspect ratio, it is preferably formed in a sidewall shape on the side surface of a pillar (the insulator 223 described later). Therefore, the oxide semiconductor 230 is preferably formed by an ALD method, which has good coverage. When the oxide semiconductor 230 has a stacked structure, it is preferable to form at least one layer, preferably a layer in contact with the pillar, by the ALD method.

[0068] 1A , by forming the oxide semiconductor 230 in a sidewall shape in contact with the side surfaces of the pillars, the oxide semiconductors 230 can be formed simultaneously. By forming the oxide semiconductors 230 in this manner, the distance between adjacent oxide semiconductors 230 can be set according to the size and shape of the pillars. Therefore, the distance between the oxide semiconductors 230 can be reduced, the area occupied by the transistor 200 can be reduced, and the semiconductor device can be highly integrated.

[0069] Because the oxide semiconductor 230 is formed in a sidewall shape in contact with the pillar, as shown in FIG. 1A , the oxide semiconductor 230 has a circumferential shape (which can also be referred to as a frame shape, annular shape, doughnut shape, or closed curve shape) in plan view, with both ends coinciding or approximately coinciding. The oxide semiconductor 230 can also be said to have a shape having an opening in the center. Note that in FIG. 1A , the shape of the oxide semiconductor 230 in plan view is line-symmetrical about A1-A2, but the present invention is not limited to this. For example, the shape of the oxide semiconductor 230 in plan view may be asymmetric. Note that the shape of the insulator 224 in plan view coincides or approximately coincides with the shape of the oxide semiconductor 230 in plan view, and the insulator 224 overlaps the oxide semiconductor 230 in plan view. Therefore, the shape of the insulator 224 in plan view also becomes a circumferential shape with both ends coinciding or approximately coinciding. Like the oxide semiconductor 230, the insulator 224 can also be said to have a shape having an opening in the center.

[0070] In the structure illustrated in FIG. 1A , two pillars are arranged in the A1-A2 direction, and a circumferential oxide semiconductor 230 is formed in contact with the side surface of each pillar. As illustrated in FIG. 1A , the oxide semiconductor 230 preferably overlaps with the conductor 260 at two or more locations in a plan view. That is, the semiconductor device of one embodiment of the present invention has two or more regions where the oxide semiconductor 230 and the conductor 260 overlap. With this structure, as illustrated in FIG. 1B , a plurality of fin-shaped oxide semiconductors 230 are formed in a cross-sectional view of the transistor 200 in the channel width direction. Each of the plurality of fin-shaped oxide semiconductors 230 functions as a channel formation region. That is, the transistor 200 functions as a multi-channel transistor. Therefore, the channel width of the transistor 200 can be further increased.

[0071] 2B , the thickness t2 of the insulator 250 inside the opening 201 is preferably thinner than the thickness t1 of the insulator 224. In other words, the thickness t1 is preferably thicker than the thickness t2. With this structure, in a cross-sectional view of the transistor 200 in the channel width direction, the bottom surface of the conductor 260 (conductor 260 a) provided inside the opening 201 can be positioned lower than the bottom surface of the oxide semiconductor 230 by the difference (t1 − t2) between the thickness t1 and the thickness t2.

[0072] By providing the bottom surface of the conductor 260 below the bottom surface of the oxide semiconductor 230, a gate electric field can be applied sufficiently from the top to bottom of the oxide semiconductor 230. In other words, in a cross-sectional view of the transistor 200 in the channel width direction, the entire oxide semiconductor 230 is electrically surrounded by the electric field of the conductor 260, allowing it to function as a channel formation region. This structure prevents the bottom end of the oxide semiconductor 230 from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, poor characteristics of the transistor, such as normally-on, due to the parasitic channel can be suppressed. That is, the electrical characteristics of the transistor 200 can be improved.

[0073] Furthermore, as described above, the oxide semiconductor 230 functions as a channel formation region from the top end to the bottom end, whereby the channel width can be increased, thereby improving the on-state current, transconductance, frequency characteristics, and the like of the transistor 200.

[0074] When the bottom surface of the conductor 260 is located below the bottom surface of the oxide semiconductor 230, at least part of the insulator 224 can function as a gate insulator of the transistor 200. For example, a region of the insulator 224 between the bottom surface of the conductor 260 (the conductor 260a) and the oxide semiconductor 230 in a cross-sectional view can function as the gate insulator of the transistor 200.

[0075] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is provided so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to provide a transistor in which the short channel effect is less likely to occur.

[0076] Note that the S-channel structure electrically surrounds the channel formation region, and therefore, can be said to be substantially equivalent to a gate all around (GAA) structure or a lateral gate all around (LGAA) structure. By forming the transistor 200 with the S-channel structure, the GAA structure, or the LGAA structure, a channel formation region formed at or near the interface between the oxide semiconductor 230 and a gate insulator can be formed over the entire bulk of the oxide semiconductor 230. Therefore, the current density flowing through the transistor can be increased, which is expected to result in an increase in the on-state current or the field-effect mobility of the transistor. In one embodiment of the present invention, the oxide semiconductor 230 has a CAAC structure and a fin-shaped structure. The CAAC structure is formed so that the a-b plane is parallel or substantially parallel to the channel length direction. With this structure, a current path flowing from one of the source and drain of the transistor to the other can be parallel to the a-b plane of the CAAC structure. In other words, an oxide semiconductor having a CAAC structure and a fin-like structure has a conduction path equivalent to that of a two-dimensional semiconductor material. By using such an oxide semiconductor for a semiconductor layer of a transistor, a device having two-dimensional conduction can be manufactured. In addition, the CAAC structure can also be referred to as a crystal structure for two-dimensional conduction.

[0077] The insulator 224 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Therefore, defects (VＯ H) can be reduced.

[0078] When VoH is formed in the oxide semiconductor 230, electrons that serve as carriers may be generated. Therefore, when VoH is formed in the channel formation region of the oxide semiconductor 230, the transistor 200 may have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, when VoH in the channel formation region is reduced, the channel formation region becomes i-type or substantially i-type, and a semiconductor device with favorable electrical characteristics can be provided.

[0079] Examples of insulators that have the function of capturing or fixing hydrogen include metal oxides with an amorphous structure. For example, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium as the insulator 224. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides with an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0080] Furthermore, a high-dielectric constant (high-k) material is preferably used for the insulator 224. Note that an example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulator 224 makes the insulator 224 more likely to function as a gate insulator. Therefore, the entire oxide semiconductor 230, including the bottom surface of the oxide semiconductor 230 and its vicinity, can function as a channel formation region. Therefore, the current density flowing through the transistor 200 can be increased, which is expected to improve the on-state current or the field-effect mobility of the transistor 200. Furthermore, the electrical characteristics of the transistor 200 are expected to be improved.

[0081] In this specification and the like, a high-k material refers to a material having a higher relative dielectric constant than silicon oxide.

[0082] It is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 224, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). It is preferable to use hafnium silicate, for example, as the insulator 224.

[0083] Note that a material with a low dielectric constant may be used as the insulator 224. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or resin may be used as the insulator 224. By using a material with a low dielectric constant as the insulator 224, it is possible to reduce, for example, parasitic capacitance occurring between wirings (not shown).

[0084] 3A, 3B, and 3C are cross-sectional views showing an example in which the insulators 221 and 222 shown in FIGS. 1B, 1C, and 1D, respectively, are omitted, and an insulator 225 is provided below the insulator 224. FIGS. 3A, 3B, and 3C are enlarged views of the vicinity of a region including the insulator 224 in FIGS. 1B, 1C, and 1D, respectively.

[0085] The shape of the insulator 225 in a plan view is the same as or substantially the same as the shape of the insulator 224 in a plan view. As described above, the shape of the insulator 224 in a plan view is the same as or substantially the same as the shape of the oxide semiconductor 230 in a plan view. As described above, the shape of the insulator 225 in a plan view is the same as or substantially the same as the shape of the oxide semiconductor 230 in a plan view. The insulator 225 overlaps with the insulator 224 and the oxide semiconductor 230 in a plan view. The bottom surface of the insulator 225 is in contact with the insulator 216, the side surface of the insulator 225 is in contact with the insulator 250, the conductor 242a, and the conductor 242b, and the top surface of the insulator 225 is in contact with the bottom surface of the insulator 224. Note that the insulators 225 and 224 may be collectively regarded as one insulator having a stacked structure. Furthermore, at least one of the insulator 221 and the insulator 222 may be provided between the insulator 216 and the insulator 225 , the insulator 250 , the insulator 275 , and the conductor 242 .

[0086] The insulator 225 preferably has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, hafnium aluminate, an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, silicon nitride oxide, or the like can be used for the insulator 225. For example, it is preferable to use silicon nitride, which has particularly high hydrogen barrier properties, for example.

[0087] Although the above description has been given of a configuration in which two circumferential oxide semiconductors 230 are provided, the present invention is not limited to this. For example, a configuration in which one or three or more circumferential oxide semiconductors 230 are provided may be used. Furthermore, the circumferential oxide semiconductors 230 may be joined to form an oxide semiconductor 230 having a shape with multiple openings. For example, as shown in FIG. 4A , an oxide semiconductor 230 having a shape in which three openings are arranged in the A1-A2 direction in a planar view may be used. In this case, three pillars are formed adjacent to each other at a short distance, and the oxide semiconductor 230 is formed between the pillars. Furthermore, as shown in FIG. 4B , an oxide semiconductor 230 having a lattice shape in a planar view may be used. In this case, lattice-shaped trenches are formed in the pillars, and the oxide semiconductor 230 is formed to fill the trenches. The number of oxide semiconductors 230 is not limited to two, and a configuration in which one or three or more oxide semiconductors 230 are provided may also be used. In this way, it is preferable that the oxide semiconductor 230 has a structure including a plurality of portions extending in the channel width direction (A1-A2 direction) and a plurality of portions extending in the channel length direction (A5-A6 direction), which can prevent the oxide semiconductor 230 from collapsing during the manufacturing process of the transistor when the oxide semiconductor 230 has a high aspect ratio.

[0088] [Oxide Semiconductor Layer] Here, an oxide semiconductor layer that can be used for the oxide semiconductor 230 will be described. The oxide semiconductor layer contains a metal oxide.

[0089] Note that it is preferable that hydrogen in the oxide semiconductor layer be reduced as much as possible. Hydrogen in the oxide semiconductor layer is generated by oxygen vacancies (V Ｏ ) and V Ｏ Defects with hydrogen in the ＯSince a gate insulating film (H) is formed, transistor characteristics (e.g., the Id-Vg characteristics of the transistor at an initial stage or the Id-Vg characteristics in a long-term reliability test) may be deteriorated. Therefore, a material that releases little hydrogen is preferably used as a material surrounding the oxide semiconductor layer, for example, as a material used for an insulator in contact with the oxide semiconductor layer. Examples of the material that releases little hydrogen include silicon nitride, silicon nitride oxide, aluminum oxide, and hafnium oxide. This can prevent hydrogen from entering the oxide semiconductor layer. In particular, using silicon nitride for at least one of the insulators in contact with the oxide semiconductor layer can improve the reliability of the transistor. Note that a material that releases little hydrogen may have a function of capturing or fixing (also referred to as gettering) hydrogen inside the insulator.

[0090] When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids.

[0091] By using a crystalline metal oxide for an oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure.

[0092] The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention has a plurality of microcrystals. Furthermore, no clear grain boundary is observed between the plurality of microcrystals. The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention preferably has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when observed from the orientation direction.

[0093] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a crystal structure different from either a single-crystal structure or a polycrystalline structure. In particular, the oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure.

[0094] The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected in the a-b plane without any clear grain boundaries. When a cross section of an oxide semiconductor layer having the CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having the CAAC structure can also be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. The bright spots are, for example, arranged in a direction parallel to the surface on which the oxide semiconductor layer is formed.

[0095] In addition, a structure in which metal atoms in each of a plurality of microcrystals are arranged in layers parallel or substantially parallel to the surface on which the metal atoms are formed, and the layers in which the metal atoms are arranged are stacked in a direction perpendicular or substantially perpendicular to the surface on which the metal atoms are formed, is sometimes referred to as a CAAC structure. If the microcrystals have such a configuration, the crystal structure of the microcrystals is not limited to a hexagonal system. For example, some of the plurality of microcrystals may have a crystal structure other than a hexagonal system (e.g., a cubic system crystal structure).

[0096] For example, the CAAC structure is formed so that the c-axis is perpendicular or substantially perpendicular to the surface on which the metal is formed. In the CAAC structure, metal atoms are arranged in layers parallel or substantially parallel to the surface on which the metal is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 110° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the metal is formed.

[0097] A polycrystalline structure has crystal grain boundaries. Furthermore, when a heat treatment is performed after forming an oxide semiconductor layer with a polycrystalline structure, tiny gaps (also referred to as nanocracks or microcracks) or tiny spaces (also referred to as nanospaces or microspaces) can be formed between crystalline portions. When tiny gaps or tiny spaces are formed in the oxide semiconductor layer, the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In contrast, in the CAAC structure, crystal grain boundaries are not clearly observed in the a-b plane, so a highly reliable semiconductor device can be realized. Furthermore, because there are fewer crystal grain boundaries, the energy barrier against carrier conduction in the transistor channel is small, and an improvement in on-current is expected. Furthermore, it is expected that an increase in the electrical resistance of a semiconductor layer of a transistor including an oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, so that the transistor can be suitable for high-speed operation.

[0098] A metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. For example, the on-state current of the transistor can be increased by increasing the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Note that carriers flow from the source to the drain through the channel formation region. Therefore, the on-state current of a transistor can be increased by providing a channel formation region in which carriers can easily flow in the channel length direction.

[0099] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0100] When an oxide semiconductor layer having a CAAC structure is subjected to electron diffraction, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed or a normal vector of the surface of the oxide semiconductor layer.

[0101] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0102] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface on which the film is formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0103] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the layer has crystallinity. Furthermore, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0104] The method for creating a Voronoi diagram will now be described. First, image analysis of a TEM image involves performing FFT processing, filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of the line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal regions enclosed by the lines connecting the Voronoi points are defined as Voronoi regions. In this way, a Voronoi diagram can be created.

[0105] In the creation of a Voronoi diagram, an example of the observation range of the TEM is a rectangular region of 50 nm in length and 50 nm in width, although the observation range is not limited to this.

[0106] Furthermore, when the distribution of the orientation of the hexagonal lattice is analyzed using lattice points extracted by image analysis of a planar TEM image, the difference in the orientation of the hexagonal lattice at the boundary between two structures with different hexagonal lattice orientations is small, and the boundary is observed to be blurred, and it appears that the two structures are connected in a manner that makes them intertwine. In other words, no clear boundary is observed in the CAAC structure.

[0107] The orientation of the hexagonal lattice can be calculated by calculating the orientation of a hexagon formed by the six lattice points closest to each lattice point.

[0108] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not limited. The oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0109] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain the element M. Furthermore, the metal oxide preferably contains two or three elements selected from indium, the element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain the element M. Note that the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, tin, yttrium, and aluminum, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0110] The main component in a metal oxide refers to a metal element whose proportion relative to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more, or 1 atomic % or more.

[0111] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed. The metal atoms are observed as bright spots in the TEM image. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Furthermore, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0112] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum. Examples of usable metal oxides include aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as a metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as a metal oxide according to one embodiment of the present invention.

[0113] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0114] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0115] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0116] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0117] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, and hydrogen.

[0118] [Method for Forming Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide using two types of film formation methods.

[0119] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a metal oxide having a CAAC structure is deposited. A sputtering method can be used to form a metal oxide with high crystallinity. Alternatively, a pulsed laser deposition (PLD) method or another method may be used.

[0120] Here, when a metal oxide is formed using the above-described film formation method (hereinafter referred to as the first film formation method), a mixed layer may be formed at the interface between the metal oxide and the surface on which the metal oxide is to be formed. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide. By first forming a metal oxide as a first layer on the surface on which the metal oxide is to be formed using a film formation method (hereinafter referred to as the second film formation method) that causes less damage than the sputtering method, PLD method, etc., which are described as the first film formation method, and then providing a metal oxide formed using the first film formation method as a second layer, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface on which the metal oxide is to be formed can be suppressed. Furthermore, impurities contained in the surface on which the metal oxide is to be formed can be suppressed from being mixed into the second layer. These factors can further enhance the crystallinity of the second layer.

[0121] Atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can reduce damage to the surface to be formed compared to sputtering. Examples of the second film formation method include molecular beam epitaxy (MBE) and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method for growing a thin film whose crystalline structure reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that cause little damage to the surface on which the film is formed. The wet method is also one of the film formation methods that cause little damage to the surface on which the film is formed. For example, a spray coating method can be mentioned as a wet method.

[0122] A third layer can be further formed on the second layer, for example, by the second film formation method.

[0123] After the oxide semiconductor layer is formed, heat treatment is preferably performed.

[0124] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductor layers (the first and third layers) can be increased by using the second layer (i.e., CAAC) having high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor layer. In other words, the second layer serves as a nucleus or seed to cause solid-phase growth of a metal oxide in the upper and lower oxide semiconductor layers, thereby forming oxide semiconductor layers with high crystallinity. An oxide semiconductor layer formed by such a film formation method, specifically, an oxide semiconductor layer having a CAAC structure, can be referred to as an axial growth CAAC (AG CAAC).

[0125] Even when a method that easily forms a metal oxide with high crystallinity is not used as a method for forming the first layer and the third layer, the crystallinity of the first layer and the third layer can be increased by using the method for forming an oxide semiconductor layer of one embodiment of the present invention. Furthermore, heat treatment has a function of assisting in increasing the crystallinity of the first layer and the third layer.

[0126] 5A to 5D , an example of a method for manufacturing the oxide semiconductor 30 will be described. The oxide semiconductor 30 can be used as the oxide semiconductor 230, for example.

[0127] First, a layer 29 is formed. The layer 29 corresponds to an insulating film or a conductive film included in the semiconductor device. For example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film can be used as the layer 29. Alternatively, for example, a conductive film that functions as an electrode of the semiconductor device can be used as the layer 29. The layer 29 does not need to be crystalline. In other words, the layer 29 may have an amorphous structure. Furthermore, when the layer 29 is crystalline, it may have a crystal structure that has low lattice matching with the metal oxide included in the oxide semiconductor 30.

[0128] Next, an oxide semiconductor 30a is formed on the layer 29 (FIG. 5A).

[0129] In a manufacturing method of one embodiment of the present invention, the oxide semiconductor 30b is formed by a sputtering method, as described later. When a metal oxide film is formed by a sputtering method, a mixed layer (also called alloying) of components of the metal oxide film to be formed and components contained in a layer on which the film is to be formed may be formed due to sputtering particles emitted from a target or the like, or energy imparted to the substrate by the sputtering particles or the like. There is a concern that alloying may inhibit crystallization of the oxide semiconductor layer thereover. Furthermore, when alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. There is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor.

[0130] Therefore, before forming the oxide semiconductor 30b, the oxide semiconductor 30a is formed in advance using a film formation method that causes minimal damage to the surface on which the oxide semiconductor 30b is to be formed. This suppresses alloying of the components contained in the oxide semiconductor 30 with the components contained in the layer 29, and reduces the thickness of the alloyed region, or makes the alloyed region thin enough that it cannot be observed. Here, the oxide semiconductor 30a is formed using the ALD method.

[0131] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0132] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Because the ALD method can deposit atoms layer by layer, it has the following advantages: it is possible to form an ultrathin film; it is possible to form a film on a surface with a high aspect ratio or large steps; it is possible to form a film with few defects such as pinholes; it is possible to form a film with excellent coverage; and it is possible to form a film at a low temperature. By using the ALD method for the oxide semiconductor 30a and the oxide semiconductor 30c (described later), the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio.

[0133] Furthermore, the PEALD method may be preferable because it allows film formation at lower temperatures by utilizing plasma. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods.

[0134] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor 30a by ALD will be described.

[0135] First, a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed onto the surface of layer 29. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer in which indium and oxygen are combined.

[0136] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the layer of indium and oxygen. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer of element M and oxygen.

[0137] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the layer in which element M and oxygen are bonded. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0138] By repeating the above-described method, an In-M-Zn oxide can be formed as the oxide semiconductor 30a on the layer 29 by the ALD method.

[0139] The substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the substrate heating temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0140] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the chamber, and then discharge the excess precursor and reaction products, etc. from the chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the chamber, and then discharge the excess reactant and reaction products, etc. from the chamber.

[0141] Furthermore, unless otherwise specified in this specification and elsewhere, when ozone, oxygen, or water is used as a reactant or oxidant, it is understood that these are not limited to gaseous or molecular states, but also include plasma, radical, and ionic states.

[0142] When the oxide semiconductor 30a is formed using the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed.

[0143] Next, an In-M-Zn oxide is formed as the oxide semiconductor 30b on the oxide semiconductor 30a by sputtering (FIG. 5B). The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure.

[0144] When the oxide semiconductor 30b is formed by sputtering, a mixed layer 31 is formed on or near the surface of the oxide semiconductor 30a. During the formation of the oxide semiconductor 30b, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 31. In a subsequent heat treatment step, the mixed layer 31 or the minute crystalline regions formed in the mixed layer 31 may act as nuclei, causing at least a portion of the oxide semiconductor 30a to crystallize.

[0145] Sputtering methods include RF sputtering, which uses a high-frequency power supply as a sputtering power supply; DC sputtering, which uses a direct-current power supply; and pulsed DC sputtering, which changes the voltage applied to an electrode in a pulsed manner. DC sputtering can be suitably used to form a metal conductive film and can improve productivity due to its high film formation rate. Pulsed DC sputtering can be suitably used to form a metal conductive film and a semiconductor film. RF sputtering can be suitably used to form an insulating film. Compounds such as oxides, nitrides, and carbides can be formed by reactive sputtering using a reactive gas. The metal oxide used for the oxide semiconductor layer of one embodiment of the present invention can be formed by a method appropriately selected from these methods depending on the conductivity of the sputtering target and the like.

[0146] An In-Mn-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0147] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0148] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0149] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.

[0150] In forming the oxide semiconductor 30b by sputtering, it is preferable to heat the substrate. In forming the metal oxide, increasing the substrate temperature (stage temperature) during metal oxide formation may result in the formation of a metal oxide with high crystallinity. In forming the oxide semiconductor 30b by sputtering, the substrate heating temperature is preferably 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0151] Here, a model for forming a CAAC structure using a sputtering method will be described. First, microcrystals are formed during sputtering film formation. The microcrystals may be formed by energy imparted to the substrate by sputtered particles (sometimes referred to as atomic particles) or gas particles. Alternatively, planar or pellet-shaped sputtered particles (sometimes referred to as nanoclusters) that peel off from the sputtering target and deposit on the surface to be formed may become the microcrystals. Subsequently, sputtered particles are adsorbed onto the ends of the microcrystals, causing the microcrystals to grow laterally (in a direction substantially parallel to the surface to be formed). As the microcrystals grow laterally, adjacent microcrystals connect to each other, eliminating the ends of the microcrystals. Once the ends of the microcrystals are eliminated, sputtered particles are adsorbed onto the microcrystals, causing the microcrystals to grow vertically (in a direction substantially perpendicular to the surface to be formed). Sputtered particles are adsorbed onto the ends of the vertically grown microcrystals, causing the microcrystals to grow laterally. In this way, the CAAC structure is formed by the microcrystals repeatedly growing laterally and vertically. That is, the CAAC structure is formed by the growth of microcrystals contained in an oxide semiconductor, using the microcrystals as nuclei or seeds.

[0152] Note that a CAAC structure is difficult to form in an oxide semiconductor containing impurities such as silicon, carbon, or water. Therefore, the oxide semiconductor 30b is preferably formed using a deposition method that prevents the impurities from being mixed in. Sputtering is suitable for forming the oxide semiconductor 30b because it can form an oxide semiconductor with a low impurity concentration by using a sputtering target with a reduced impurity concentration and a deposition gas with a reduced impurity amount.

[0153] Next, the oxide semiconductor 30c is formed on the oxide semiconductor 30b (FIG. 5C). Here, the oxide semiconductor 30c is formed by the ALD method. For the formation of the oxide semiconductor 30c by the ALD method, the method for forming the oxide semiconductor 30a can be referred to.

[0154] When an oxide semiconductor 30c having a lower crystallinity than the CAAC structure is formed on an oxide semiconductor 30b having a CAAC structure by using an ALD method, the oxide semiconductor 30c may grow epitaxially around the oxide semiconductor 30b as a nucleus. Therefore, when the oxide semiconductor 30c is formed, the oxide semiconductor 30c may have a region having the CAAC structure. Furthermore, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 30c.

[0155] The oxide semiconductor 30c can be used, for example, as a layer in contact with a gate insulator of a transistor. By increasing the crystallinity of the layer in contact with the gate insulator, carrier mobility can be increased when the transistor is in an on state.

[0156] Furthermore, by forming the oxide semiconductor 30c using the ALD method, damage to the oxide semiconductor 30b is reduced, and the oxide semiconductor 30 as a whole can have high crystallinity.

[0157] By using the ALD method, which has high coverage, as a method for forming the oxide semiconductors 30a and 30c, the oxide semiconductor layer as a whole can have coverage. In addition, by forming the oxide semiconductor 30b with high crystallinity using a sputtering method, the crystallinity of the upper and lower oxide semiconductor layers (the oxide semiconductors 30a and 30c) can be improved by epitaxial growth or the like from the oxide semiconductor 30b. This allows the crystallinity of the oxide semiconductor 30 to be improved throughout the entire layer. Therefore, the oxide semiconductor 30 can have both high coverage and high crystallinity.

[0158] Next, a heat treatment step may be carried out.

[0159] The heat treatment temperature is, for example, 100° C. or higher and 800° C. or lower, preferably 250° C. or higher and 650° C. or lower, and more preferably 350° C. or higher and 550° C. or lower. The heat treatment temperature is typically, for example, 400° C.±25° C. (375° C. or higher and 425° C. or lower). The treatment time is, for example, 10 hours or shorter, or 1 minute to 5 hours or shorter, or 1 minute to 2 hours or shorter. When a rapid thermal annealing (RTA) apparatus is used, the treatment time is, for example, 1 second to 5 minutes or shorter. It is expected that the heat treatment will repair atomic-level gaps in the crystal portions of the CAAC structure of the oxide semiconductor 30b with the oxide semiconductor 30c (in other words, the crystal molecules formed by the ALD method).

[0160] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0161] The heat treatment step may enhance the crystallinity of the region having the CAAC structure in the oxide semiconductor 30c. Furthermore, if the region is formed only below the oxide semiconductor 30c after the ALD deposition, the heat treatment step may cause the region to expand upward (FIG. 5D). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 30c.

[0162] Furthermore, the heat treatment process may further repair the oxide semiconductor 30b by the oxide semiconductor 30c (in other words, the crystal molecules formed by the ALD method) filling gaps in the atomic-level crystal portions of the CAAC structure of the oxide semiconductor 30b.

[0163] Furthermore, it is preferable that at least a portion of the oxide semiconductor 30a is converted into CAAC by the heat treatment ( FIG. 5D ). It is expected that the CAAC conversion is facilitated by the mixed layer 31 formed in the oxide semiconductor 30a during the deposition of the oxide semiconductor 30b, which acts as a nucleus or seed. It is preferable that the region in the oxide semiconductor 30a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 29.

[0164] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 30a, the CAAC can be formed up to the vicinity of the layer 29 regardless of the material or crystallinity of the layer 29. For example, even if the layer 29 has an amorphous structure, the oxide semiconductor 30a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0165] After the oxide semiconductor 30c is formed, a microwave plasma treatment may be performed.

[0166] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0167] It is preferable to reduce the impurity concentration in the oxide semiconductor 30 by performing microwave plasma treatment in an atmosphere containing oxygen. Examples of impurities include hydrogen and carbon. Although the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0168] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or more and 1000 Pa or less, and more preferably being 300 Pa or more and 700 Pa or less. The microwave plasma treatment is preferably carried out with the substrate heated. The substrate temperature can be set to room temperature (e.g., 25°C) or more and 500°C or less, preferably 100°C or more and 500°C or less, more preferably 200°C or more and 500°C or less, even more preferably 300°C or more and 500°C or less, more preferably 400°C or more and 500°C or less, and even more preferably 400°C or more and 450°C or less.

[0169] Alternatively, after the microwave plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The heat treatment temperature is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0170] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. By performing the microwave plasma treatment in an atmosphere containing oxygen, the oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the oxide semiconductor layer. By the action of plasma, microwaves, or the like, defects (V) in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer can be formed. Ｏ In this way, the V contained in the oxide semiconductor layer can be separated into oxygen vacancies and hydrogen, and the hydrogen impurities can be removed from the oxide semiconductor layer. ＯH can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, oxygen vacancies formed in the oxide semiconductor layer can be further reduced by supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the oxide semiconductor layer.

[0171] Oxygen to be implanted into the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). Note that the oxygen to be implanted into the oxide semiconductor layer can be in one or more of the above forms, and is particularly preferably an oxygen radical.

[0172] In this manner, the impurities in the oxide semiconductor layer can be reduced. When crystal growth is performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0173] Note that one or both of the heat treatment and the microwave plasma treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0174] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher one or more of a relative dielectric constant, a film density, and a film hardness than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0175] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, or the like) can be realized.

[0176] In the oxide semiconductor 30, it is preferable that a region having a CAAC structure is widely present throughout the entire layer including the oxide semiconductor 30a and the oxide semiconductor 30c. Fig. 6A shows the crystallization of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c. The crystals in the region having the CAAC structure in the oxide semiconductor 30a are connected to the crystals in the region having the CAAC structure in the oxide semiconductor 30b. The crystals in the region having the CAAC structure in the oxide semiconductor 30c are connected to the crystals in the region having the CAAC structure in the oxide semiconductor 30b. The oxide semiconductor 30 can sometimes be expressed as a single layer with no clearly observed interface. The oxide semiconductor 30 can sometimes be expressed as a single layer.

[0177] The regions having the CAAC structure in the oxide semiconductors 30a, 30b, and 30c can be observed as bright spots aligned parallel to the surface on which they are formed, for example, in cross-sectional observation using a high-resolution TEM. Furthermore, it is preferable that the c-axes of the CAAC structures in the oxide semiconductors 30a, 30b, and 30c are each substantially parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0178] Furthermore, there are cases where a portion of the oxide semiconductor 30a or the oxide semiconductor 30c is not crystallized. The example shown in Fig. 6B shows a state in which the vicinity of the interface with the layer 29 in the oxide semiconductor 30a is not crystallized. Fig. 6C shows a state in which the vicinity of the surface in the oxide semiconductor 30c is not crystallized. Fig. 6D shows a state in which the vicinity of the interface with the layer 29 in the oxide semiconductor 30a and the vicinity of the surface of the oxide semiconductor 30c are not crystallized.

[0179] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor 30, the boundaries between the stacked oxide semiconductors 30a, 30b, and 30c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0180] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 30b and the crystals of the oxide semiconductor 30a or the oxide semiconductor 30c is small. This allows the oxide semiconductor 30a or the oxide semiconductor 30c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 30b. In this case, for example, when a cross section of the oxide semiconductor 30 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor 30a or the oxide semiconductor 30c.

[0181] As long as the lattice mismatch between the crystal of the oxide semiconductor 30b and the crystal of the oxide semiconductor 30a or the oxide semiconductor 30c is small, the crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c is not particularly limited. The crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0182] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0183] When the oxide semiconductor 30 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor 30 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. Furthermore, in transistors used in smaller semiconductor devices, the film thickness of the oxide semiconductor 30 is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, and further preferably 5 nm to 12 nm.

[0184] The oxide semiconductor 30b preferably has a thickness of, for example, 200 nm or less. When the oxide semiconductor 30b has a layer shape, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0185] Alternatively, if the oxide semiconductor 30b can function as a crystal nucleus, the oxide semiconductor 30b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor 30b exist discretely.

[0186] The oxide semiconductor 30a and the oxide semiconductor 30c each have a thickness of, for example, 1 nm to 50 nm, preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 2 nm to 20 nm.

[0187] The thickness of the region where the component contained in the oxide semiconductor 30 and the component contained in the layer 29 are alloyed is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Figures 5A and 5B show an example in which no alloy region is formed between the layer 29 and the oxide semiconductor 30a.

[0188] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0189] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 30a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 30a contains In) that is the main component of the oxide semiconductor 30a but is not the main component of the layer that will become the surface (here, layer 29) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 30a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 30a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0190] For example, when a silicon oxide layer is used as the layer 29 and an SIMS analysis is performed on the oxide semiconductor 30 formed on the layer 29, the interface is defined as a depth at which the silicon concentration is 50% of the maximum concentration of the layer 29, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0×10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 0.5 nm and the interface is defined as thickness t_s. The thickness t_s is preferably 3 nm or less, and more preferably 2 nm or less.

[0191] By reducing the alloyed region, it is possible to form the CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor 30 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably more than 0 nm and 2 nm, more preferably 1 nm or more and 2 nm, inclusive.

[0192] The oxide semiconductor 30a has a region that is provided, for example, at a depth of 0 nm to 3 nm from the top surface of the layer 29. The oxide semiconductor 30c is provided, for example, at a depth of 0 nm to 3 nm from the top surface of the oxide semiconductor 30. The oxide semiconductors 30a, 30b, and 30c have, for example, approximately the same thickness. Alternatively, the oxide semiconductors 30a, 30b, and 30c may have different thicknesses.

[0193] Although the oxide semiconductor 30 has a three-layer structure of the oxide semiconductors 30a to 30c in the above description, the present invention is not limited to this. The oxide semiconductor 30 may have a two-layer structure or a stacked structure of four or more layers.

[0194] When the oxide semiconductor 30 has a two-layer structure, it is possible to configure the oxide semiconductor 30 so that an oxide semiconductor 30a and an oxide semiconductor 30b are stacked in this order. By configuring in this manner, alloying of the components contained in the oxide semiconductor 30 and the components contained in the layer 29 can be suppressed, and the thickness of the alloyed region can be reduced, or the thickness can be made so thin that the alloyed region cannot be observed.

[0195] Alternatively, when the oxide semiconductor 30 has a five-layer structure, the oxide semiconductor 30 can have a structure in which a first oxide semiconductor, a second oxide semiconductor, a third oxide semiconductor, a fourth oxide semiconductor, and a fifth oxide semiconductor are stacked in this order. For example, the first oxide semiconductor, the third oxide semiconductor, and the fifth oxide semiconductor are preferably formed by the second film formation method, more preferably by an ALD method. The second oxide semiconductor and the fourth oxide semiconductor are preferably formed by the first film formation method, more preferably by a sputtering method. With such a structure, even if the third oxide semiconductor has a composition that makes it difficult to form a CAAC structure, crystal growth can be promoted from one or both of the second oxide semiconductor and the fourth oxide semiconductor, thereby improving the crystallinity of the third oxide semiconductor.

[0196] When the oxide semiconductor 30 has a stacked structure of two or more layers, typically a stacked structure of two to five layers, it is preferable to deposit each layer successively without exposing it to the atmosphere. For example, it is preferable to deposit each layer successively using a multi-chamber film deposition apparatus. This allows the oxide semiconductor 30 to be deposited while suppressing impurities that may be mixed into each layer.

[0197] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0198] The CAAC structure of an oxide semiconductor layer can sometimes be evaluated from a map showing crystal orientation. For example, in a region having the CAAC structure, it is observed that crystals are c-axis oriented.

[0199] A map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing a fast Fourier transform (FFT) on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the direction of the crystal axis of each region. Specifically, for example, two spots of high intensity are observed in the FFT pattern of a region having layered crystal portions. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots. The FFT pattern reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0200] The c-axis orientation rate can be calculated by calculating the proportion of the c-axis oriented region in the map showing the crystal orientation.

[0201] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by performing TEM observation of a cross section or a plan view of the oxide semiconductor layer and using the map showing the crystal orientation described above. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0202] Furthermore, when performing analysis using a cross-sectional TEM image, the observation range of the cross-sectional TEM image is, for example, a region with a width of 100 nm in the horizontal direction, with the direction perpendicular to the surface to be formed being the vertical direction. However, the observation range is not limited to this.

[0203] In the oxide semiconductor layer of one embodiment of the present invention, when the c-axis orientation rate is calculated as the percentage of regions whose orientation is within 20° of the c-axis, the c-axis orientation rate is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0204] The c-axis orientation rates of the region where the oxide semiconductor 30a is formed, the region where the oxide semiconductor 30b is formed, and the region where the oxide semiconductor 30c is formed are denoted by Rc1, Rc2, and Rc3, respectively. Here, the c-axis orientation rate is calculated as, for example, the percentage of regions where the difference from the c-axis is within 20°. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. It is preferable that Rc3 / Rc1 be greater than 1. It is also preferable that Rc2 / Rc1 be greater than 1.

[0205] [Composition of Oxide Semiconductor Layer] The oxide semiconductor 30a preferably has a different composition from the oxide semiconductor 30b. The oxide semiconductor 30c preferably has a different composition from the oxide semiconductor 30b. The oxide semiconductor 30a may have the same composition as the oxide semiconductor 30c. Alternatively, the oxide semiconductor 30a and the oxide semiconductor 30c may have different compositions.

[0206] The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 30b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor 30b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 30b preferably contains, in addition to zinc, the element M. By containing the element M in the oxide semiconductor 30b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Specifically, the oxide semiconductor 30b preferably has a metal oxide composition having an In:M:Zn=1:1:1 atomic ratio or a composition thereabout, an In:M:Zn=1:1:1.2 atomic ratio or a composition thereabout, an In:M:Zn=1:1:0.5 atomic ratio or a composition thereabout, an In:M:Zn=1:1:2 atomic ratio or a composition thereabout, an In:M:Zn=4:2:3 atomic ratio or a composition thereabout, an In:M:Zn=1:3:2 atomic ratio or a composition thereabout, or an In:M:Zn=1:3:4 atomic ratio or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio. Furthermore, the element M is preferably one or more of gallium, tin, yttrium, and aluminum.

[0207] The oxide semiconductor 30b may not contain the element M. For example, it may be an In-Zn oxide. Specifically, it may have a composition with an atomic ratio of In:Zn=1:1 or a ratio therebetween, an atomic ratio of In:Zn=2:1 or a ratio therebetween, or an atomic ratio of In:Zn=4:1 or a ratio therebetween. Alternatively, indium oxide may be used. Furthermore, the oxide semiconductor 30b may have a trace amount of the element M. For example, it may have a composition with an atomic ratio of In:Ga:Zn=4:0.1:1 or a ratio therebetween, or an atomic ratio of In:Ga:Zn=2:0.1:1 or a ratio therebetween. Furthermore, it may have a composition with an atomic ratio of In:Sn:Zn=4:0.1:1 or a ratio therebetween, or an atomic ratio of In:Sn:Zn=2:0.1:1 or a ratio therebetween.

[0208] The oxide semiconductor 30a and the oxide semiconductor 30c can be metal oxides having a high proportion of In. It is particularly preferable that the oxide semiconductor 30a and the oxide semiconductor 30c be metal oxides having a higher proportion of In than the oxide semiconductor 30b. For example, the ALD method can be used to form the oxide semiconductor 30a and the oxide semiconductor 30c. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-current can be increased and the frequency characteristics can be improved.

[0209] An oxide semiconductor with a high In content tends to be polycrystalline. Using a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. In the oxide semiconductor layer of one embodiment of the present invention, the crystal orientation of the oxide semiconductor 30b can be reflected in the oxide semiconductors 30a and 30c with a high In content. Therefore, even when a metal oxide with a high In content is used as the oxide semiconductors 30a and 30c, polycrystallization can be suppressed.

[0210] Alternatively, the oxide semiconductors 30a and 30c may not contain the element M. For example, they may be In-Zn oxides. Specifically, they may have a composition with an atomic ratio of In:Zn=1:1 or a ratio therebetween, an atomic ratio of In:Zn=2:1 or a ratio therebetween, or an atomic ratio of In:Zn=4:1 or a ratio therebetween. Alternatively, indium oxide may be used. Furthermore, the oxide semiconductors 30a and 30c may contain a trace amount of the element M. Specifically, they may have a composition with an atomic ratio of In:Ga:Zn=4:0.1:1 or a ratio therebetween, an atomic ratio of In:Ga:Zn=2:0.1:1 or a ratio therebetween, an atomic ratio of In:Sn:Zn=4:0.1:1 or a ratio therebetween, or an atomic ratio of In:Sn:Zn=2:0.1:1 or a ratio therebetween.

[0211] Alternatively, metal oxides with a high Ga content may be used for the oxide semiconductors 30a and 30c. For example, metal oxides with a higher Ga content than the oxide semiconductor 30b may be used for the oxide semiconductors 30a and 30c. For example, metal oxides with an atomic ratio of In:Ga:Zn = 1:1:1 or a composition thereabout, metal oxides with an atomic ratio of In:Ga:Zn = 1:3:2 or a composition thereabout, or metal oxides with an atomic ratio of In:Ga:Zn = 1:3:4 or a composition thereabout are preferably used for the oxide semiconductors 30a and 30c, respectively. Increasing the Ga content may result in the band gaps of the oxide semiconductors 30a and 30c being larger than those of the oxide semiconductor 30b. By sandwiching the oxide semiconductor 30b between the oxide semiconductors 30a and 30c, which have larger band gaps, the oxide semiconductor 30b can function primarily as a current path (channel). Furthermore, the trap levels at and near the interface of the oxide semiconductor 30b can be reduced. This allows a buried channel transistor in which the channel is located away from the insulator interface to be realized, thereby increasing the . In addition, the influence of interface states that may be formed on the back channel side can be reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation), and improving the reliability of the transistor.

[0212] Alternatively, one of the oxide semiconductors 30a and 30c may be a metal oxide having a higher proportion of In than the oxide semiconductor 30b, and the other may be a metal oxide having a higher proportion of Ga than the oxide semiconductor 30b.

[0213] The oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c may each have a plurality of layers each having the above-described composition stacked together. For example, the oxide semiconductor 30c may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0214] The oxide semiconductor 30a and the oxide semiconductor 30c may be made of a metal oxide having the same composition as the oxide semiconductor 30b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0215] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 30a and 30c have compositions that make it difficult to form a CAAC structure when they are formed as a single layer, crystal growth occurs with the oxide semiconductor 30b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 30a and 30c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductors 30a and 30c and the oxide semiconductor 30b.

[0216] The composition of the metal oxide used in the oxide semiconductor 30 can be analyzed by, for example, EDX, X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0217] [Impurities in Oxide Semiconductor] Here, a description will be given of the influence of each impurity in the oxide semiconductor 30. The impurities contained in the oxide semiconductor 30 can be quantified using XPS, SIMS, EDX, ICP-MS, ICP-AES, or the like.

[0218] It is preferable that the channel formation region of a transistor using the oxide semiconductor 30 as a semiconductor layer have fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or metal elements than the source and drain regions. Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H may be formed, and electrons serving as carriers may be generated. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor 30, the transistor is likely to have normally-on characteristics. Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0219] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor 30. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in the oxide semiconductor 30 refer to, for example, elements other than the main components constituting the oxide semiconductor 30. For example, an element with a concentration of less than 1 atomic % or less than 0.1 atomic % may be referred to as an impurity.

[0220] When the oxide semiconductor 30 contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor 30. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor 30 obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10１８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor 30 obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0221] Furthermore, when nitrogen is contained in the oxide semiconductor 30, electrons serving as carriers are generated, the carrier concentration increases, and the oxide semiconductor 30 is likely to become n-type. As a result, a transistor using the oxide semiconductor 30 containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in the oxide semiconductor 30, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor 30 obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0222] Furthermore, hydrogen contained in the oxide semiconductor 30 may react with oxygen bonded to metal atoms to form water, which may form oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor 30 containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor 30. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor 30 obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0223] Furthermore, when the oxide semiconductor 30 contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using the oxide semiconductor 30 containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor 30 obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0224] When the oxide semiconductor 30 in which the impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0225] The average thickness of the oxide semiconductor 30 in the channel formation region is preferably 30 nm or less, more preferably 15 nm or less, and even more preferably 10 nm or less.

[0226] The oxide semiconductor 30a is an oxide semiconductor layer formed on a surface to be formed. The thickness of the oxide semiconductor 30a is preferably 0.5 nm or more and 3 nm or less.

[0227] In addition, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide semiconductor 230 is observed, it may be possible to see that metal atoms of the metal oxide are arranged in a layered manner in a region having a CAAC structure. In this case, for example, the metal atoms are arranged in a direction perpendicular or substantially perpendicular to the substrate surface.

[0228] The metal atoms arranged in a layered manner in the region having the CAAC structure can be observed as bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. Therefore, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide semiconductor 230 is observed, it may be possible to confirm that the bright spots are arranged in a direction perpendicular or substantially perpendicular to the substrate surface.

[0229] The oxide semiconductor 30, which is an AG CAAC, can be used as the oxide semiconductor 230 of the transistor 200. For example, as shown in FIGS. 2B and 2C , the oxide semiconductor 230 can have a structure including an oxide semiconductor 230a, an oxide semiconductor 230b in contact with the oxide semiconductor 230a, and an oxide semiconductor 230c in contact with the oxide semiconductor 230b. Here, the oxide semiconductor 230a corresponds to the oxide semiconductor 30a, the oxide semiconductor 230b corresponds to the oxide semiconductor 30b, and the oxide semiconductor 230c corresponds to the oxide semiconductor 30c.

[0230] Here, the pillar (the insulator 223 described later) corresponds to the layer 29. That is, the surface on which the oxide semiconductor 230 is formed is the pillar, and the pillar is removed in the transistor 200. During the manufacturing process, one side surface of the oxide semiconductor 230a is in contact with the pillar and the other side surface of the oxide semiconductor 230b. After the pillar is removed, one side surface of the oxide semiconductor 230a is in contact with the insulator 250. One side surface of the oxide semiconductor 230b is in contact with the oxide semiconductor 230a and the other side surface of the oxide semiconductor 230c. One side surface of the oxide semiconductor 230c is in contact with the oxide semiconductor 230b and the other side surface of the oxide semiconductor 230c is in contact with the oxide semiconductor 230b and the insulator 250. Here, since the side surfaces of the pillars are formed perpendicular or approximately perpendicular to the substrate surface (which can also be referred to as the surface of the insulator 222), the side surfaces of the oxide semiconductors 230 (oxide semiconductors 230a to 230c) are also perpendicular or approximately perpendicular to the substrate surface.

[0231] As described above, in the cross section of the oxide semiconductor 230 (the oxide semiconductors 230a to 230c) observed using the TEM image, it is confirmed that metal atoms are arranged in layers parallel to or substantially parallel to the surface where the oxide semiconductor 230 is formed. In other words, in the cross section of the oxide semiconductor 230 (the oxide semiconductors 230a to 230c) observed using the TEM image, it is confirmed that metal atoms are arranged in layers perpendicular to or substantially perpendicular to the substrate surface. It can also be said that the c-axis of AG CAAC is substantially parallel to the normal direction to the side surface of the oxide semiconductor 230.

[0232] In this manner, by using the oxide semiconductor 230 which is AG CAAC for the channel formation region of the transistor 200, a transistor with favorable on-state current, field-effect mobility, S value, frequency characteristics, and reliability can be provided.

[0233] When the oxide semiconductor 230 has a three-layer structure including the oxide semiconductors 230a to 230c as described above, the oxide semiconductor 230 is formed in the order of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c, centered on the region where the pillars were formed. Therefore, as shown in FIG. 7A , in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230c, the oxide semiconductor 230b, the oxide semiconductor 230a, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are arranged symmetrically in this order. That is, to achieve a bilaterally symmetrical structure in a cross-sectional view of the oxide semiconductor 230, it is preferable that the oxide semiconductors 230a and 230c have approximately the same composition. It is also preferable that the oxide semiconductors 230a and 230c have approximately the same film thickness. When the angle between the side surface of the oxide semiconductor 230 and the top surface of the insulator 222 is equal to or greater than 80° and less than 90°, that is, when the side surface of the oxide semiconductor 230 is slightly tilted, the tilt of the oxide semiconductor 230 is arranged symmetrically as shown in Fig. 7B. When the oxide semiconductor 230 is formed at an angle, the upper part of the oxide semiconductor 230 may be thinner than the lower part of the oxide semiconductor 230, as shown in Fig. 7B.

[0234] A channel formation region and a source region and a drain region sandwiching the channel formation region in the transistor 200 are formed in the oxide semiconductor 230. At least part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0235] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0236] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0237] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0238] Note that when the carrier concentration of the oxide semiconductor 230 is reduced, the impurity concentration in the oxide semiconductor 230 is reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0239] To stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region in the oxide semiconductor 230. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide semiconductor 230 refer to, for example, elements other than the main components constituting the oxide semiconductor 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0240] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide semiconductor 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in a region closer to the channel formation region.

[0241] As described above, impurities, oxygen vacancies, and V Ｏ In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is i-type (intrinsic) or substantially i-type. Here, by providing an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0242] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0243] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, and suppress reduction in the hydrogen concentration in the source and drain regions.

[0244] [Insulator and Conductor] The insulator 250 in contact with the channel formation region of the oxide semiconductor 230 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0245] 2A and 2B , the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. In this case, the insulator 250a and the insulator 250c preferably have a function of capturing or fixing hydrogen.

[0246] As an insulator having the function of capturing or fixing hydrogen, there is a metal oxide having an amorphous structure, as described above. For the insulator 250a and the insulator 250c, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium is preferably used.

[0247] Furthermore, it is preferable to use a high-k material for the insulator 250a and the insulator 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium, as described above. By using a high-k material for the insulator 250a and the insulator 250c, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0248] For the insulators 250a and 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0249] In this embodiment, an aluminum oxide film is used as the insulator 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulator 250a in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 and the like can be more effectively captured and fixed.

[0250] In this embodiment, hafnium oxide is used as the insulator 250c. By providing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0251] Next, it is preferable to use a thermally stable insulator such as silicon oxide or silicon oxynitride for the insulator 250b. Note that in this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0252] The silicon oxide film used as the insulator 250b is preferably formed using a PEALD method.

[0253] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 250a, the insulator 250d, the insulator 250c, and the insulator 275.

[0254] In this specification and the like, a barrier insulator refers to an insulator with barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulator with barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulator. Furthermore, for example, an insulator with barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0255] Examples of oxygen barrier insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, hafnium aluminate, and hafnium silicate. For example, the insulators 250a, 250c, 250d, and 275 each preferably have a single-layer structure or a stacked-layer structure of the oxygen barrier insulators.

[0256] The insulator 250a preferably has a barrier property against oxygen. The insulator 250a is preferably at least less permeable to oxygen than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. The insulator 250a having a barrier property against oxygen can prevent the side surfaces of the conductor 242a and the conductor 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0257] The insulator 250a is provided in contact with the top surface and side surface of the oxide semiconductor 230, the side surface of the insulator 224, and the top surface of the insulator 222. The insulator 250a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the oxide semiconductor 230 during heat treatment or the like. Thus, oxygen vacancies can be reduced in the oxide semiconductor 230.

[0258] Furthermore, the insulator 250a prevents excessive oxygen from being supplied from the insulator 280 to the oxide semiconductor 230, and enables an appropriate amount of oxygen to be supplied to the oxide semiconductor 230. Therefore, excessive oxidation of the source and drain regions can be suppressed, which can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0259] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and can therefore be suitably used as the insulator 250a.

[0260] The insulator 250d also preferably has a barrier property against oxygen. The insulator 250d is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260 and between the insulator 280 and the conductor 260. With this structure, oxygen contained in the channel formation region of the oxide semiconductor 230 can be prevented from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor 230. Furthermore, oxygen contained in the oxide semiconductor 230 and oxygen contained in the insulator 280 can be prevented from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250d is preferably at least less permeable to oxygen than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0261] The insulator 250d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide semiconductor 230.

[0262] It is preferable that the insulator 275 also has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. This prevents oxygen contained in the insulator 280 from diffusing into the conductor 242. Therefore, it is possible to prevent the conductor 242 from being oxidized by the oxygen contained in the insulator 280 and increasing its resistivity. It is preferable that the insulator 275 is at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator having at least nitrogen and silicon.

[0263] A barrier insulator against hydrogen is preferably provided near each of the source and drain regions in order to suppress a decrease in the hydrogen concentrations in the source and drain regions of the oxide semiconductor 230. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, the insulator 275.

[0264] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 preferably has a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0265] By providing the insulator 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making it possible to make the source and drain regions n-type.

[0266] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0267] The insulators 250a to 250d function as part of the gate insulator. The insulators 250a to 250d, together with the conductor 260, are provided in the opening 201 formed in the insulator 280. To miniaturize the transistor 200, the insulators 250a to 250d preferably have a small thickness. The thickness of the insulators 250a to 250d is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. It is preferable that at least a portion of each of the insulators 250a to 250d have a region having the above-described thickness.

[0268] Furthermore, the thickness of the silicon oxide film used as the insulator 250 is preferably 0.7 nm or more and 3 nm or less.

[0269] In order to thin the film thicknesses of the insulators 250a to 250d as described above, it is preferable to form the insulators by atomic layer deposition (ALD). Furthermore, to provide the insulators 250a to 250d inside the opening 201, it is preferable to form the insulators by ALD. Examples of ALD methods include thermal ALD, which uses only thermal energy to cause a reaction between a precursor and a reactant, and plasma-enhanced ALD, which uses a plasma-excited reactant. The PEALD method may be preferable because it uses plasma, which enables film formation at a lower temperature.

[0270] The ALD method allows atoms to be deposited layer by layer, and therefore has the advantages of enabling extremely thin films to be formed, films to be formed on structures with high aspect ratios, films with few defects such as pinholes, films with excellent coverage, and films to be formed at low temperatures, etc. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the opening 201 formed in the insulator 280 and the side ends of the conductors 242a and 242b, and with the thin film thickness as described above.

[0271] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0272] Although the above description has been given of a structure in which the insulator 250 has a four-layer structure of the insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can have a structure including at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0273] For example, as shown in Fig. 8A, the insulator 250 may have a three-layer structure. In this case, it is preferable that the insulator 250 has a layered structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In other words, this is a structure in which the insulator 250d is removed from the structure shown in Fig. 2A.

[0274] It is preferable to use the ALD process two or more times in forming the insulator 250. For example, the insulator 250 preferably has a stacked structure of multiple insulating films, and two or more of the multiple insulating films are preferably formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulator 250. Furthermore, it is possible to increase productivity by continuously forming two or more different films, for example, two or more insulating films, using the ALD process.

[0275] In addition to the above structure, it is preferable to have a structure that suppresses hydrogen from being mixed into the transistor 200 or the like. For example, it is preferable to provide an insulator that has a function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor 200 or the like. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 283, the insulator 282, the insulator 222, the insulator 221, or the like. Furthermore, the insulator 215 provided under the transistor 200 may have a structure similar to either or both of the insulator 282 and the insulator 283. In this case, the insulator 215 may have a stacked structure of the insulator 282 and the insulator 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom.

[0276] It is preferable that one or more of the insulators 283, 282, 222, and 221 function as barrier insulators that suppress diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, one or more of the insulators 283, 282, 222, and 221 suppress diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., impurities are less likely to permeate through the insulating material), or that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., oxygen is less likely to permeate through the insulating material).

[0277] The insulators 283, 282, 222, and 221 each preferably have an insulator that functions to suppress the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, hafnium aluminate, an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulators 283 and 221 are preferably made of silicon nitride or the like, which has a higher hydrogen barrier property. Furthermore, for example, the insulator 282 is preferably made of aluminum oxide or the like, which has a high ability to capture or fix hydrogen. Furthermore, for example, the insulator 222 is preferably made of hafnium oxide or the like, which is a high-k material and has a high ability to capture or fix hydrogen.

[0278] At least one of the insulators 221 and 222 can have a stacked structure of silicon oxide or silicon oxynitride in addition to the above-described materials. For example, the insulator 221 can have a stacked structure of silicon nitride and silicon oxide. For example, the insulator 222 can have a stacked structure of hafnium oxide and silicon oxide.

[0279] With this structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film or the like provided above the insulator 283 to the transistor 200 and the like. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film or the like provided below the insulator 221 to the transistor 200 and the like. Furthermore, hydrogen contained in the insulator 280, the insulator 250, and the like can be captured and fixed to the insulator 282 or the insulator 222. Furthermore, the provision of the insulators 282 and 283 can prevent oxygen contained in the insulator 280 and the like from diffusing upward from the transistor 200 and the like. Furthermore, the provision of the insulators 222 and 221 can prevent oxygen contained in the oxide semiconductor 230 and the like from diffusing downward from the transistor 200 and the like. Thus, by surrounding the transistor 200 from above and below with insulators that have a function of preventing the diffusion of impurities such as water and hydrogen and oxygen, the diffusion of excess oxygen and hydrogen into the oxide semiconductor can be reduced. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0280] Furthermore, it is preferable to use silicon nitride or the like, which has a higher hydrogen barrier property, for the insulators 275 and 250d. It is also preferable to use aluminum oxide or the like, which has a high ability to capture or fix hydrogen, for the insulator 250a. It is also preferable to use hafnium oxide or the like, which has a high ability to capture or fix hydrogen, for the insulator 250c.

[0281] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as the conductors 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 are conductors that contain at least metal and nitrogen.

[0282] The conductor 242a and the conductor 242b are provided apart from each other and in contact with the oxide semiconductor 230. The conductor 242 is provided so as to cover the oxide semiconductor 230 having a high aspect ratio, for example, as shown in FIG. 2C . Furthermore, the conductor 242a (the conductor 242b) preferably has a structure in which it is in contact with two or more fin-shaped oxide semiconductors 230 in a cross-sectional view, as shown in FIG. 1C .

[0283] Here, as shown in FIG. 2C , a conductor 242a is provided near the source or drain of the transistor 200 so as to be folded in half with the oxide semiconductor 230 sandwiched therebetween. As a result, in a cross-sectional view of the transistor 200 in the channel width direction, the conductor 242a is in contact with the oxide semiconductor 230 at the top, the side surface on the A3 side, and the side surface on the A4 side of the oxide semiconductor 230. Therefore, compared to when the oxide semiconductor 230 is flat, the contact area between the conductor 242a and the oxide semiconductor 230 is increased by the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230. Furthermore, as shown in FIG. 1C , the contact area can be further increased by using a structure in which multiple fin-shaped oxide semiconductors 230 and the conductor 242a are in contact with each other. While FIGS. 1C and 2C show the vicinity of the conductor 242a, the same applies to the conductor 242b. That is, similar to the contact area between the conductor 242a and the oxide semiconductor 230 described above, the contact area between the conductor 242b and the oxide semiconductor 230 is large.

[0284] By increasing the contact area between the conductor 242 and the oxide semiconductor 230 as described above, the on-state current, frequency characteristics, and the like of the transistor 200 can be improved without increasing the area occupied by the transistor 200. As a result, a semiconductor device with high operating speed can be provided. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, as a result, miniaturization or high integration of the semiconductor device can be achieved. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0285] The conductor 242a and the conductor 242b are preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion because they are in contact with the oxide semiconductor 230. This can suppress a decrease in the conductivity of the conductor 242a and the conductor 242b. Furthermore, it can suppress the extraction of oxygen from the oxide semiconductor 230, which can cause excessive oxygen vacancies to be formed. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the conductor 242a and the conductor 242b, because this can reduce the hydrogen concentration in the oxide semiconductor 230.

[0286] As the conductor 242, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen.

[0287] Note that hydrogen contained in the oxide semiconductor 230 and the like might diffuse to the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used for the conductor 242a and the conductor 242b, hydrogen contained in the oxide semiconductor 230 and the like is likely to diffuse to the conductor 242a or the conductor 242b, and the diffused hydrogen might bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide semiconductor 230 and the like might be absorbed by the conductor 242a or the conductor 242b.

[0288] To prevent a decrease in the conductivity of the conductor 242a and the conductor 242b, a crystalline oxide such as CAAC-OS can be used as the oxide semiconductor 230. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. The use of CAAC-OS can prevent the conductor 242a or the conductor 242b from extracting oxygen from the oxide semiconductor 230. Furthermore, a decrease in the conductivity of the conductor 242a and the conductor 242b can be prevented.

[0289] 8B , the conductor 242a and the conductor 242b may have a two-layer structure. The conductor 242a may be a stacked film of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b may be a stacked film of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, the layers in contact with the oxide semiconductor 230 (the conductors 242a1 and 242b1) are preferably made of the above-described conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion. This can prevent a decrease in the conductivity of the conductor 242a and the conductor 242b. Furthermore, it can prevent oxygen from being extracted from the oxide semiconductor 230, thereby preventing excessive oxygen vacancies from being formed. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the layers in contact with the oxide semiconductor 230 (the conductor 242a1 and the conductor 242b1) because the hydrogen concentration in the oxide semiconductor 230 can be reduced.

[0290] Furthermore, the conductors 242a2 and 242b2 preferably have higher conductivity than the conductors 242a1 and 242b1. For example, the film thickness of the conductors 242a2 and 242b2 is preferably greater than the film thickness of the conductors 242a1 and 242b1. For the conductors 242a2 and 242b2, it is preferable to use a conductor that can be used for the conductor 260b described below. By using the above structure, the resistance of the conductors 242a2 and 242b2 can be reduced. This increases the on-state current of the transistor 200, thereby improving the operating speed of the semiconductor device according to this embodiment.

[0291] For example, tantalum nitride or titanium nitride can be used as the conductor 242a1 and the conductor 242b1, and tungsten can be used as the conductor 242a2 and the conductor 242b2.

[0292] 8C , in a cross-sectional view of the transistor 200 in the channel length direction, the conductor 242a1 and the conductor 242b1 may be configured to protrude further than the conductor 242a2 and the conductor 242b2, respectively. The protruding portions of the conductor 242a1 and the conductor 242b1 are covered with an insulator 250. Here, the distance between the conductor 242a1 and the conductor 242b1 is smaller than the distance between the conductor 242a2 and the conductor 242b2. This configuration shortens the distance between the source and the drain, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0293] 1B and 1D , the conductor 260 is provided inside the opening 201. In a cross-sectional view of the transistor 200 in the channel width direction, the conductor 260 is provided so as to cover the top surface of the insulator 222, the side surface of the oxide semiconductor 230, and the top surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. The top surface of the conductor 260 is provided so as to be flush or substantially flush with the height of the uppermost portion of the insulator 250 and the top surface of the insulator 280.

[0294] The sidewall of the opening 201 may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By tapering the sidewall, the coverage of the insulator 250 and the like provided in the opening 201 is improved, and defects such as voids can be reduced.

[0295] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction, as shown in Figures 1A and 1B. With this configuration, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0296] A part of the conductor 260 is folded in half to sandwich the fin-shaped oxide semiconductor 230. As a result, in a cross-sectional view of the transistor 200 in the channel width direction, as shown in FIG. 2B , the oxide semiconductor 230 and the conductor 260 are arranged to face each other with the insulator 250 sandwiched between them at the top, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230. That is, the top, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230 each function as a channel formation region. Therefore, compared to when the oxide semiconductor 230 is flat, the channel width of the transistor 200 is increased by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230.

[0297] 1D and other figures, the conductor 260 is shown as a two-layer structure consisting of a conductor 260a and a conductor 260b provided on the conductor 260a. For example, the conductor 260a is provided inside the opening 201 so as to be in contact with the insulator 250. Furthermore, the conductor 260b is provided on the conductor 260a so as to fill the opening 201. In other words, the conductor 260a is provided so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0298] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0299] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 280, etc. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0300] The conductor 260b is preferably made of a highly conductive material. For example, the conductor 260b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0301] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill the opening 201. Here, the side surface of the insulator 280 in the opening 201 coincides with or substantially coincides with the side surface of the conductor 242a and the side surface of the conductor 242b. Therefore, the conductor 260 can be provided so as to overlap with the region between the conductor 242a and the conductor 242b without alignment.

[0302] The insulators 216 and 280 preferably have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as an interlayer film, for example, parasitic capacitance occurring between wirings (not shown) can be reduced.

[0303] For example, it is preferable that the insulators 216 and 280 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0304] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0305] Furthermore, the top surfaces of the insulators 216 and 280 may each be flattened.

[0306] It is preferable that the concentration of impurities such as water and hydrogen be reduced in the insulator 280. For example, it is preferable that the insulator 280 have an oxide containing silicon such as silicon oxide or silicon oxynitride.

[0307] Conductor 240a is formed inside opening 202a. Conductor 240b is formed inside opening 202b. The lower surface of conductor 240a contacts the upper surface of conductor 242a, and the lower surface of conductor 240b contacts the upper surface of conductor 242b. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 283 are approximately the same.

[0308] The conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240 may also have a layered structure in which a first conductor is provided in contact with the side surface of the insulator 241 and a second conductor is provided further inside. In this case, the above-mentioned conductive material can be used as the second conductor. Here, the first conductor corresponds to the conductor 240a1 shown in FIG. 2C , and the second conductor corresponds to the conductor 240a2 shown in FIG. 2C .

[0309] When the conductor 240 has a stacked structure, the first conductor provided near the insulators 283, 282, 280, and 275 is preferably made of a conductive material that has a function of suppressing permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. The conductive material that has a function of suppressing permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulator 283 can be prevented from entering the oxide semiconductor 230 through the conductors 240a and 240b.

[0310] The insulator 241a is formed in contact with the inner wall of the opening 202a. The insulator 241b is formed in contact with the inner wall of the opening 202b. The inner side surface of the insulator 241a is in contact with the conductor 240a, and the inner side surface of the insulator 241b is in contact with the conductor 240b.

[0311] The insulator 241 can be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 can be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. Providing the insulator 241 can prevent impurities such as water and hydrogen contained in the insulator 280, etc. from entering the oxide semiconductor 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0312] The insulator 241 may have a stacked structure. In this case, the insulator 241 may have a first insulator in contact with the inner wall of the opening 202 and a second insulator inside the first insulator. For the first insulator and the second insulator, the insulator 241 preferably uses, for example, a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0313] For example, it is preferable to use aluminum oxide formed by thermal ALD as the first insulator and silicon nitride formed by PEALD as the second insulator, which can suppress oxidation of the conductor 240 and further reduce hydrogen contamination of the conductor 240.

[0314] Note that the insulator 241 may have a stacked structure of three or more layers. Although the conductor 240 has a two-layer stacked structure in the above description, the conductor 240 may have a single layer or a stacked structure of three or more layers.

[0315] For example, as shown in FIG. 2C , a structure may be used in which the conductor 240a covers the oxide semiconductor 230 and the conductor 242a that is folded in half with the oxide semiconductor 230 sandwiched therebetween. As a result, in a cross-sectional view of the transistor 200 in the channel width direction, the conductor 240a contacts the conductor 242a at the top, the side surface on the A3 side, and the side surface on the A4 side of the oxide semiconductor 230. Therefore, compared to when the oxide semiconductor 230 is flat, the contact area between the conductor 240a and the conductor 242a is increased by the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230. Furthermore, as shown in FIG. 1C , a structure in which the conductor 240a covers multiple fin-shaped oxide semiconductors 230 can further increase the contact area between the conductor 240a and the conductor 242a. Note that although FIGS. 1C and 2C illustrate the conductor 240a and the conductor 242a, the same applies to the conductor 240b and the conductor 242b. That is, similar to the contact area between the conductors 240a and 242a described above, the contact area between the conductors 240b and 242b is large.

[0316] As described above, by increasing the contact area between the conductor 240 and the conductor 242, the contact resistance between the conductor 240 and the conductor 242 can be reduced. This allows the on-state current, frequency characteristics, and the like of the transistor 200 to be improved without significantly increasing the area occupied by the transistor 200. This makes it possible to provide a semiconductor device with a high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0317] <Structural Example 2 of Semiconductor Device> A structural example of a semiconductor device according to one embodiment of the present invention will be described below. Specifically, the structural example will be described as being different from the structures illustrated in FIGS. 1A to 1D.

[0318] 1A to 1D , the insulator 224 is provided only in the region overlapping with the oxide semiconductor 230, but this is not limiting. For example, as shown in FIGS. 9A to 9D , the insulator 224 may be provided not only in the region overlapping with the oxide semiconductor 230 but also outside the opening 201. Here, FIGS. 9A to 9D correspond to FIGS. 1A to 1D , respectively, and therefore the above description can be referred to for detailed configurations.

[0319] In the semiconductor device of one embodiment of the present invention, the shape of the insulator 224 in a plan view can be made to match or substantially match the shape of the oxide semiconductor 230 in a plan view at least in a region overlapping with the opening 201. In the examples shown in Figures 9A to 9D , the insulator 275 is provided between the insulator 224 and the insulator 280. In the examples shown in Figures 9A to 9D , the conductors 242a and 242b are in contact with the top surface of the insulator 224.

[0320] In FIG. 1A , the shape of the opening where the conductor 240 and the insulator 241 are provided is rectangular in plan view, but this is not limiting. For example, the opening may be circular, approximately circular (e.g., elliptical), polygonal (e.g., rectangular), or polygonal (e.g., rectangular) with rounded corners in plan view. As shown in FIG. 1C , the opening is formed to overlap multiple fin-shaped oxide semiconductors 230, but this is not limiting. For example, as shown in FIG. 10A , a portion of the opening (which can also be referred to as a portion of the conductor 240) can overlap with the oxide semiconductor 230, while another portion of the opening (which can also be referred to as another portion of the conductor 240) does not overlap with the oxide semiconductor 230. By configuring the conductor 240 so that a portion of the conductor 240 overlaps with the oxide semiconductor 230, the arrangement margin of the conductor 240 can be increased. Furthermore, for example, as shown in FIG. 10B , the opening and the conductor 240 can be provided in a region that does not overlap with the oxide semiconductor 230.

[0321] 1D , 10A , and 10B , the conductor 240a and the conductor 240b are provided symmetrically with respect to the conductor 260, but the present invention is not limited to this. For example, as shown in FIG. 11A , in a cross-sectional view of the transistor 200 in the channel length direction, part of the conductor 240a may overlap with the oxide semiconductor 230, and the conductor 240b may not overlap with the oxide semiconductor 230. For example, as shown in FIG. 11B , in a cross-sectional view of the transistor 200 in the channel length direction, the conductor 240a may be provided in a region overlapping with the oxide semiconductor 230, and the conductor 240b may be provided in a region not overlapping with the oxide semiconductor 230.

[0322] 12A to 12D , the semiconductor device of this embodiment may have a structure in which a conductor 205 is provided under an insulator 221. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200. The insulators 222 and 221 each have a region that functions as a second gate insulator of the transistor 200. Here, FIGS. 12A to 12D correspond to FIGS. 1A to 1D , respectively, and therefore the above description can be referred to for detailed configurations.

[0323] In the transistor 200, the conductor 205 is provided to overlap with the oxide semiconductor 230 and the conductor 260. Here, the conductor 205 is preferably provided to be embedded in an opening 203 formed in the insulator 216. The conductor 205 is preferably provided to extend in the channel width direction as shown in FIGS. 12A and 12B . With such a structure, the conductor 205 functions as a wiring when a plurality of transistors are provided.

[0324] 12D , the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening 203. The conductor 205b is provided so as to fill a recess in the conductor 205a formed along the opening 203. Here, the height of the upper surface of the conductor 205 coincides with or approximately coincides with the height of the upper surface of the insulator 216.

[0325] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0326] By using a conductive material that can reduce hydrogen diffusion for the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide semiconductor 230 via the insulator 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0327] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0328] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0329] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match the electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore, diffusion of the impurities into the oxide semiconductor 230 can be suppressed.

[0330] Although the above describes a layered structure of conductor 205a and conductor 205b, the present invention is not limited to this, and conductor 205 may have a single-layer structure or a layered structure of three or more layers. For example, when conductor 205 has a three-layer layered structure, the layered structure of conductor 205a and conductor 205b may further include a conductor made of the same material as conductor 205a provided on conductor 205b. In this case, the conductor may be formed so that the top surface of conductor 205b is lower than the top of conductor 205a, and the conductor fills the recess formed by conductor 205a and conductor 205b.

[0331] <Configuration Example of Memory Cell> A configuration example of a memory cell including the transistor 200 will be described below.

[0332] 13A, the transistor 200, the capacitor 460, and the transistor 310 formed on a silicon substrate can be used to function as a 2T (transistor) 1C (capacitor) memory cell. As shown in Fig. 13A, a structure can be adopted in which a layer including the transistor 200 and the capacitor 460 is provided over a layer including the transistor 310. Fig. 14A shows a cross-sectional view of the transistor 200 in the channel width direction, Fig. 14B shows a cross-sectional view of the capacitor 460 in the same direction, and Fig. 14C shows a cross-sectional view of the transistor 310 in the channel width direction.

[0333] The transistor 310 is provided over a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that includes part of the substrate 311, a low-resistance region 314a that functions as one of a source region and a drain region, and a low-resistance region 314b that functions as the other of the source region and the drain region. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single-crystal silicon substrate.

[0334] As shown in FIG. 14C , the transistor 310 has a semiconductor region 313 (a part of the substrate 311) where a channel is formed, which has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0335] Note that the transistor 310 illustrated in FIG. 13A is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0336] A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0337] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. Conductors 328 and the like are embedded in the insulators 320 and 322. Conductors 330 and the like are embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0338] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0339] The transistor 200 and the capacitor 460 are provided over the insulator 326. Here, the transistor 200 is the transistor 200 shown in FIG. 8C . The structure of the layers in which the transistor 200 and the capacitor 460 are formed is the same as that described above, and is indicated by the same hatching patterns and symbols. For detailed structure, refer to the above description. Note that an insulator 285 is formed over the insulator 283, and a conductor 413 electrically connected to the conductor 240a is formed over the insulator 285. The insulator 285 can be formed using an insulating material that can be used for the insulator 216. The conductor 413 can be formed using a conductive material that can be used for the conductor 242.

[0340] The capacitor 460 includes an oxide semiconductor 452, a conductor 242b1 over the oxide semiconductor 230 and the oxide semiconductor 452, an insulator 454 over the conductor 242b1, and a conductor 456 over the insulator 454. As shown in FIGS. 13A , 14A , and 14B , the oxide semiconductor 452 has a structure similar to that of the oxide semiconductor 230 and can be formed in the same process. The conductor 242b1 is also used in the transistor 200. The insulator 454 has a structure similar to that of the insulator 250 and can be formed in the same process. The conductor 456 has a structure similar to that of the conductor 260 and can be formed in the same process.

[0341] Here, the capacitor 460 has a conductor 242b1 that functions as a first electrode, a conductor 456 that functions as a second electrode, and an insulator 454 that functions as a dielectric. That is, the capacitor 460 constitutes a metal-insulator-metal (MIM) capacitor.

[0342] The capacitor 460 has a structure similar to that of the transistor 200 and can be formed in the same layer as the transistor 200 in parallel. Specifically, the insulator 275 and the insulator 280 have an opening 461 that overlaps with the oxide semiconductor 452. However, the capacitor 460 differs from the transistor 200 in that the conductor 242b1 overlaps with the opening 461. Therefore, the opening 461 reaches the conductor 242b1.

[0343] The insulator 454 overlaps with the conductor 242b1 and is provided inside the opening 461. The insulator 454 is in contact with the top surface of the conductor 242b1 inside the opening 461. The conductor 456 is provided inside the opening 461 and on the insulator 454.

[0344] 14B , the oxide semiconductor 452 of the capacitor 460 has a high aspect ratio, similar to the oxide semiconductor 230, and a plurality of oxide semiconductors 230 can be provided. Therefore, similar to the oxide semiconductor 230, the height of the oxide semiconductor 452 is larger than the width of the oxide semiconductor 452 in a cross-sectional view. Furthermore, the semiconductor device of one embodiment of the present invention has two or more regions where the oxide semiconductor 452 and the conductor 456 overlap with each other in a plan view. Therefore, the area where the conductor 242b1, the insulator 454, and the conductor 456, which are provided along the top surface and side surface of the oxide semiconductor 452, face each other can be increased. This allows the capacitance to be increased without significantly increasing the area occupied by the capacitor 460.

[0345] 13A , 14A, and 14B , the insulator 424 has a similar structure to the insulator 224 and can be formed in the same process. The insulators 224 and 424 are provided over the substrate 311, specifically, over the insulator 222. That is, the insulators 224 and 424 are provided on the same formation surface of the substrate 311. As described above, the shape of the insulator 224 in a plan view and the shape of the oxide semiconductor 230 in a plan view are the same or substantially the same, at least in the region overlapping with the opening 201.

[0346] The oxide semiconductor 452 is formed in contact with the top surface of the insulator 424. The shape of the insulator 424 in a plan view is the same as or substantially the same as the shape of the oxide semiconductor 452 in a plan view at least in a region overlapping with the opening 461. The oxide semiconductor 452 overlaps with the insulator 424 in a plan view. The bottom surface of the insulator 424 is in contact with the insulator 222, the side surface of the insulator 424 is in contact with the conductor 242b1, and the top surface of the insulator 424 is in contact with the bottom surface of the oxide semiconductor 452.

[0347] As described above, the thickness of the insulator 224 is preferably thicker than the thickness of the insulator 250 inside the opening 201. The insulator 424 has a structure similar to that of the insulator 224, and the insulator 454 has a structure similar to that of the insulator 250. For the above reasons, the thickness of the insulator 424 is preferably thicker than the thickness of the insulator 454. In this case, as shown in FIG. 14B , the bottom surface of the conductor 456 provided inside the opening 461 can be located below the bottom surface of the oxide semiconductor 452.

[0348] Furthermore, it is preferable to provide a conductor 458 in an opening 462 formed in the insulators 215, 216, 221, and 222. The conductor 458 can have a structure similar to that of the conductor 240, for example. The upper surface of the conductor 458 is in contact with the lower surface of the conductor 242b1 and can be electrically connected to the conductor 330. Note that while only one conductor 458 is shown in FIG. 13A , this is not limiting, and two or more conductors may be used to electrically connect the conductor 242b1 and the conductor 330. Furthermore, a configuration in which a portion of the conductor 242b1 is embedded in the opening 462 may also be used.

[0349] With the above-described structure, one of the source and drain of the transistor 200, one electrode of the capacitor 460, and the gate of the transistor 310 are electrically connected to form a 2T1C memory cell. Note that a 1T1C memory cell can also be formed by using a structure that does not include the transistor 310. Also, a 2T0C memory cell can be formed by using a structure that does not include the capacitor 460.

[0350] Here, the transistor 310 is preferably provided so as to overlap with at least one of the transistor 200 and the capacitor 460. For example, the transistor 310 is preferably configured to overlap with the transistor 200. With such a configuration, the area occupied by the memory cell can be reduced.

[0351] 13A illustrates a structure in which the transistor 200 and the capacitor 460 include the oxide semiconductor 230 and the oxide semiconductor 452, respectively, but the present invention is not limited to this. For example, as illustrated in FIG. 13B , a structure may be used in which the oxide semiconductor 230 is formed over the insulator 224, and the insulator 250, the conductor 260, the insulator 454, and the conductor 456 are formed over the oxide semiconductor 230. That is, the transistor 200 and the capacitor 460 may share the oxide semiconductor 230. Alternatively, the insulator 224 may overlap not only with the transistor 200 but also with the capacitor 460. As described above, it is not necessary to separately pattern the oxide semiconductor 230 and the insulator 224 for the transistor 200 and the capacitor 460, and therefore the area occupied by the transistor 200 and the capacitor 460 can be reduced.

[0352] Although FIG. 13A illustrates a configuration in which the transistor 310 is formed on a silicon substrate, the present invention is not limited to this. For example, as shown in FIG. 15A , two transistors (hereinafter referred to as transistors 200a and 200b) having the same structure as the transistor 200 described above may be provided. Here, the transistors 200a and 200b are formed in the same layer and are provided so that their channel length directions intersect each other. Note that the transistors 200a and 200b have the same structure as the transistor 200, and therefore, the components are indicated by the same hatched patterns and symbols. FIG. 15A illustrates an example in which the transistors 200a and 200b have the same structure as the transistor 200 shown in FIGS. 1B and 1D .

[0353] 15A , a capacitor 400 is provided on the insulator 285. The capacitor 400 includes a conductor 410 on the insulator 285, an insulator 430 on the conductor 410, and a conductor 420 on the insulator 430. The conductor 240b, the insulator 241b, the conductor 240c, and the insulator 241c are provided in contact with the bottom surface of the conductor 410. The conductor 240c and the insulator 241c are formed so as to be embedded in the opening 202c of the insulators 282, 283, and 285, and have a structure similar to that of the conductor 240b and the insulator 241c. The bottom surface of the conductor 240c is in contact with the top surface of the conductor 260 of the transistor 200b. With this structure, one of the source and drain of the transistor 200a, one electrode of the capacitor 400, and the gate of the transistor 200b are electrically connected to each other.

[0354] The capacitor 400 includes a conductor 410 that functions as a first electrode, a conductor 420 that functions as a second electrode, and an insulator 430 that functions as a dielectric. In other words, the capacitor 400 constitutes an MIM capacitor.

[0355] The conductor 410 and the conductor 420 can be formed using a conductive material that can be used for the conductor 260. For example, tungsten can be used for the conductor 410 and the conductor 420. Here, by using a structure in which the conductor 420 covers the conductor 410, the conductor 420 can function as the capacitor 400 on the side of the conductor 410. This increases the electrostatic capacitance of the capacitor 400. Furthermore, the conductor 413 can be formed simultaneously with the conductor 410.

[0356] Although the conductors 410, 413, and 420 each have a single-layer structure, they are not limited to this structure and may have a stacked structure of two or more layers. For example, a stacked structure of a conductor having barrier properties and a conductor with high conductivity may be used. For example, a stacked structure of titanium nitride and tungsten on titanium nitride may be used.

[0357] A high-k material is preferably used for the insulator 430 of the capacitor 400. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such high-k materials, the insulator 430 can be made thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor 400. Furthermore, since the insulator 430 is formed to cover the conductor 410, it is preferable to form the insulator 430 using a film formation method with good coverage, such as an ALD method or a CVD method.

[0358] The insulator 430 may also have a layered structure. It is preferable to use a layered structure of a high-k material and a material with a higher dielectric strength than the high-k material. Examples of materials with a high dielectric strength (materials with a low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added. The insulator 430 can have a layered structure of aluminum oxide, which is a high-k material, and silicon oxide with a high dielectric strength on the aluminum oxide.

[0359] For example, the insulator 430 can be an insulator stacked in the order of zirconium oxide, aluminum oxide, and zirconium oxide. Alternatively, for example, an insulator stacked in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Alternatively, for example, an insulating film stacked in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By stacking and using an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor 400 can be suppressed.

[0360] Furthermore, a material that can have ferroelectricity may be used as the insulator 430. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of zirconium atoms to the number of element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0361] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0362] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0363] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, may also be used.

[0364] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulator 430 can have a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, not only materials that exhibit ferroelectricity are referred to as ferroelectrics, but also as materials capable of exhibiting ferroelectricity.

[0365] 15A, the shape of the capacitor 400 is a planar type, but the shape of the capacitor 400 in the memory device shown in this embodiment is not limited to this. For example, the shape of the capacitor 400 may be a cylinder type or a pillar type.

[0366] An insulator 487 is provided to cover the capacitor 400, and an insulator 488 is provided to cover the insulator 487. The insulator 487 is preferably an insulator that has a function of capturing or fixing hydrogen. For example, the insulator 487 is preferably made of aluminum oxide. The insulator 488 is preferably an insulator that has a function of suppressing diffusion of hydrogen. For example, the insulator 488 is preferably made of silicon nitride, which has a higher hydrogen barrier property.

[0367] 15A shows a structure in which the transistors 200a and 200b are provided in the same layer, but the present invention is not limited to this. For example, as shown in FIG. 15B, a structure in which a layer 401a including the transistor 200a is stacked on a layer 401b including the transistor 200b may be used. Note that the layers 401a and 401b have the same structure as the layers from the insulator 215 to the insulator 285 shown in FIG. 15A.

[0368] 15B, the conductor 240c and the insulator 241c can be formed in the openings 202c provided in the insulators 282 to 285 of the layer 401b and the insulators 215 to 285 of the layer 401a. With this structure, the conductor 410 of the capacitor 400 and the conductor 260 of the transistor 200b can be electrically connected. Note that the conductor 410 and the conductor 260 of the transistor 200b do not need to be connected only by the conductor 240c. Two or more conductors may be used to electrically connect the conductor 410 and the conductor 260 of the transistor 200b.

[0369] Here, the transistor 200b is preferably provided so as to overlap with at least one of the transistor 200a and the capacitor 400. For example, the oxide semiconductor 230 of the transistor 200b is preferably provided so as to overlap with at least one of the oxide semiconductor 230 of the transistor 200a and the conductor 410 of the capacitor 400. With such a structure, the area occupied by the memory cell can be reduced.

[0370] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for the semiconductor device will be described below. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0371] <<Substrate>> Examples of substrates for forming transistors include insulating substrates, semiconductor substrates, and conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include semiconductor substrates having an insulator region within the semiconductor substrate, such as SOI (Silicon-On-Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride, substrates having a metal oxide, substrates in which a conductor or semiconductor is provided on an insulator substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductor substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0372] <<Insulators>> Examples of insulators that can be used for at least one of the insulators 215, 216, 221, 222, 223, 224, 225, 241, 250, 275, 280, 282, 283, 285, 315, 320, 322, 324, 326, 424, 430, 454, 487, and 488 include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0373] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for an insulator functioning as a gate insulator, such as insulator 250, enables lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for an insulator functioning as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select a material depending on the function of the insulator.

[0374] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0375] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0376] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0377] The insulator functioning as the gate insulator preferably has a region containing oxygen that is released by heating. For example, when silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with an oxide semiconductor, oxygen vacancies in the oxide semiconductor can be compensated for.

[0378] Conductors that can be used for at least one of conductor 205, conductor 240, conductor 242, conductor 260, conductor 316, conductor 328, conductor 330, conductor 410, conductor 413, conductor 420, conductor 456, and conductor 458 include metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys containing the above-mentioned metal elements, and alloys combining the above-mentioned metal elements. Examples of conductors include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Also, semiconductors with high conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0379] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0380] When an oxide is used for the channel formation region of a transistor, a conductor that functions as a gate electrode, such as the conductor 260, preferably has a stacked structure in which a material containing the metal element described above and a conductive material containing oxygen are combined. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0381] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0382] <Example of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described below with reference to Figures 16A to 29D. Here, the case of manufacturing the semiconductor device illustrated in Figures 1A to 1D will be described as an example.

[0383] 16A to 29D , unless otherwise specified, (A) in each figure shows a plan view. Also, (B) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in (A) of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Also, (C) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in (A) of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Also, (D) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in (A) of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200.

[0384] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed as a film by appropriately using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0385] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0386] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0387] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0388] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0389] The CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which have a faster film formation rate.

[0390] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases while depositing the film. When depositing a film while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to when depositing a film using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0391] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0392] First, a substrate (not shown) is prepared, and an insulator 215 is formed on the substrate (see FIGS. 16A to 16D ). As described above, the insulator 215 can be formed using an insulator similar to one or more of the insulators 282 and 283. The insulator 215 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, is preferable because it can reduce the hydrogen concentration in the insulator 215.

[0393] Next, the insulator 216 is deposited over the insulator 215. The insulator 216 is preferably deposited by a sputtering method. The hydrogen concentration in the insulator 216 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. However, the deposition of the insulator 216 is not limited to a sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate. In this embodiment, silicon oxide is deposited as the insulator 216 by a sputtering method.

[0394] The insulators 215 and 216 are preferably successively formed without exposure to the air. For example, a multi-chamber film formation apparatus is preferably used. This allows the insulators 215 and 216 to be formed with reduced hydrogen content and reduces the amount of hydrogen mixed into the films between film formation steps.

[0395] 12A to 12D can be formed by forming an opening 203 in the insulator 216 that reaches the insulator 215 and forming a conductor 205 inside the opening 203. The conductor 205 can be formed by depositing a conductive film that can be used for the conductor 205 so as to fill the opening 203 and removing part of the conductive film by CMP treatment.

[0396] Next, an insulator 221 is formed on the insulator 216 (see FIGS. 16A to 16D).

[0397] The insulator 221 is preferably formed using any of the above insulators that have barrier properties against oxygen, hydrogen, and water. The insulator 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon nitride is formed as the insulator 221 by a PEALD method.

[0398] Next, an insulator 222 is formed on the insulator 221 (see FIGS. 16A to 16D).

[0399] The insulator 222 is preferably an insulator containing one or both of an oxide of aluminum and hafnium. As the insulator containing one or both of an oxide of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or hafnium aluminate is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of an oxide of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. When the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in structures provided around the transistor are prevented from diffusing into the transistor through the insulator 222, and thus oxygen vacancies in the oxide semiconductor 230 can be suppressed.

[0400] The insulator 222 can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, hafnium oxide is formed as the insulator 222 by thermal ALD.

[0401] In this embodiment, silicon nitride is deposited as the insulator 221 by a PEALD method, and hafnium oxide is deposited as the insulator 222 by a thermal ALD method. By using silicon nitride, which has a function of suppressing hydrogen diffusion, for the insulator 221 in this manner, diffusion of hydrogen from a lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide, which has a function of capturing or fixing hydrogen, for the insulator 222, hydrogen contained in the oxide semiconductor 230 can be captured or fixed to the insulator 222. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0402] Next, an insulating film 224f that will become the insulator 224 is formed on the insulator 222 (see FIGS. 16A to 16D).

[0403] The insulating film 224f is preferably an insulating film that captures or fixes hydrogen. This prevents hydrogen contained in structures provided around the transistor from diffusing into the transistor through the insulator 224, thereby reducing VoH in the channel formation region. Furthermore, a high-k material is preferably formed as the insulating film 224f. This makes it easier for the insulator 224 to function as a gate insulator, and allows the entire oxide semiconductor 230 to function as a channel formation region.

[0404] The insulating film 224f is preferably formed of a metal oxide having an amorphous structure. For example, an oxide containing one or both of aluminum and hafnium is preferably used as the metal oxide, and specifically, hafnium silicate is preferably used. The insulating film 224f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0405] When a hafnium silicate film is formed as the insulating film 224f, a film formation gas or a film formation target containing hafnium and silicon can be used in the above-described film formation method. For example, a co-sputtering method using a silicon oxide target and a hafnium oxide target can be used. Alternatively, a thermal ALD method using hafnium tetrachloride and silicon tetrachloride as precursors can be used. Alternatively, for example, a hafnium oxide film can be formed by forming the hafnium oxide film using the above-described method and then adding silicon to the hafnium oxide film. Examples of methods for adding silicon include ion implantation, in which a source gas is ionized and the ions are mass-separated before addition, and ion doping, in which a source gas is ionized and the ions are added without mass separation.

[0406] Next, an insulating film is formed over the insulating film 224f and etched to form the insulator 223 (see FIGS. 16A to 16D ). The insulator 223 functions as a template for forming the oxide semiconductor 230. The insulator 223 can be, for example, an insulator that can be used for at least one of the insulators 216, 221, and 222. The insulator 223 can be, for example, aluminum oxide, silicon nitride, or silicon oxide. The insulator 223 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0407] The insulator 223 is processed into an island shape using, for example, lithography. This processing can be performed using dry etching or wet etching. Dry etching is suitable for fine processing. In this embodiment, as shown in FIGS. 16A and 16B , two columnar insulators 223 are formed and arranged in the A1-A2 direction.

[0408] 16B and 16C , the side surface of the insulator 223 may be configured to be perpendicular or approximately perpendicular to the top surface of the insulator 222. With such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors.

[0409] Next, an oxide semiconductor film 230f that will become the oxide semiconductor 230 is formed to cover the insulator 223 (see FIGS. 17A to 17D ). The oxide semiconductor film 230f is a metal oxide film that will become the oxide semiconductor 230 in a later step, and any of the above-described metal oxide films can be used. The oxide semiconductor film 230f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0410] Since the oxide semiconductor film 230f is formed along the insulator 223, it is preferable that the oxide semiconductor film 230f has good coverage. Therefore, it is preferable that the oxide semiconductor film 230f be formed by an ALD method or the like, which has good coverage. Furthermore, since it is preferable that the oxide semiconductor 230 has a high aspect ratio, it is preferable that the oxide semiconductor film 230f have a thin film thickness. Therefore, it is preferable that the oxide semiconductor film 230f be formed by an ALD method, which allows for adjustment of the film thickness to a thin film thickness. By forming the oxide semiconductor film 230f in this manner, the oxide semiconductor film 230f is formed in contact with the top surface and side surface of the insulator 223.

[0411] Here, the oxide semiconductor film 230f is preferably formed by the same method as the above-described method for forming the oxide semiconductor 30. By forming the oxide semiconductor film 230f in this manner, the oxide semiconductor film 230f and the oxide semiconductor 230 can be formed so as to well cover, for example, the insulator 223.

[0412] For example, when the oxide semiconductor 230 has a three-layer structure including oxide semiconductors 230a to 230c as shown in FIGS. 2B and 2C , films to be the oxide semiconductors 230a to 230c are deposited by ALD, and a film to be the oxide semiconductor 230b is deposited by sputtering. Specifically, the film to be the oxide semiconductor 230a can be deposited to have an atomic ratio of In:Zn=2:1 or a composition therebetween. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230a. Alternatively, the film to be the oxide semiconductor 230b can be deposited using an oxide target having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition therebetween. Alternatively, the film to be the oxide semiconductor 230c can be deposited to have an atomic ratio of In:Zn=2:1 or a composition therebetween. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230c.

[0413] Next, heat treatment is preferably performed within a temperature range in which the oxide semiconductor film 230f does not become polycrystallized. The heat treatment of the oxide semiconductor film 230f can be performed by the same method as the heat treatment of the oxide semiconductor 30 described above.

[0414] For example, the heat treatment can be carried out at a flow rate ratio of nitrogen gas to oxygen gas of 4:1 at a temperature of 450° C. for one hour.

[0415] By forming the oxide semiconductor 230 using the above method and then performing heat treatment, the oxide semiconductor 230 can be converted into an AG CAAC. As a result, the on-state current, the S value, the field-effect mobility, the frequency characteristics, and the like of the transistor 200 can be improved, and a semiconductor device with favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0416] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0417] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film 230f and the like as much as possible. Note that highly purified gas can also be used in the heat treatment before and after this step.

[0418] Furthermore, the heat treatment using oxygen gas as described above can reduce impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f. Reducing the impurities in the film in this manner can improve the crystallinity of the oxide semiconductor film 230f, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor film 230f, reducing in-plane variations in the crystalline regions in the oxide semiconductor film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0419] Furthermore, by performing heat treatment, oxygen can be supplied to the oxide semiconductor film 230f, and oxygen vacancies in the oxide semiconductor film 230f can be reduced, thereby improving the reliability of the transistor 200.

[0420] Furthermore, by the heat treatment, hydrogen in the oxide semiconductor film 230f moves to the insulating film 224f and is absorbed into the insulating film 224f. In other words, hydrogen in the oxide semiconductor film 230f diffuses into the insulating film 224f. Therefore, the hydrogen concentration in the insulating film 224f increases, but the hydrogen concentration in each oxide semiconductor film 230f decreases. Note that by providing the insulator 221 under the insulating film 224f, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.

[0421] In particular, the oxide semiconductor film 230f (later the oxide semiconductor 230) functions as a channel formation region of the transistor 200. The transistor 200 formed using the oxide semiconductor film 230f in which the hydrogen concentration is reduced has high reliability, which is preferable.

[0422] Note that it is preferable to perform a treatment for increasing the crystallinity of the oxide semiconductor film 230f during or after the formation of the oxide semiconductor film 230f. Examples of the treatment for increasing the crystallinity of the oxide semiconductor film 230f include heat treatment, plasma treatment, microwave (typically, 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0423] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor film 230f multiple times during the formation of the oxide semiconductor film 230f. For example, when the oxide semiconductor film 230f is formed by an ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time an oxide semiconductor film 230f having a thickness within a predetermined range is formed, in order to improve productivity. Specifically, it is preferable to form a first oxide semiconductor film having a thickness of 1 nm to 10 nm as the oxide semiconductor film 230f, perform the first microwave plasma treatment, and then form a second oxide semiconductor film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the methods for forming the first oxide semiconductor film and the second oxide semiconductor film are not particularly limited, and ALD or sputtering can be used for each. In particular, forming the first oxide semiconductor film by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed into the first oxide semiconductor film and the second oxide semiconductor film. This is particularly suitable when the elements contained in the layers constituting the formation surface inhibit crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor film and the second oxide semiconductor film may have different compositions. Although a stacked structure of the first oxide semiconductor film and the second oxide semiconductor film is illustrated here, the present invention is not limited to this. The oxide semiconductor film 230f can be formed as a single layer or a stacked structure of three or more layers.

[0424] Furthermore, treatment for increasing the crystallinity of the oxide semiconductor film 230f may be performed after the oxide semiconductor film 230f is formed. Specifically, this treatment may be performed directly on the formed oxide semiconductor film 230f, or may be performed via another film, such as an insulating film, formed on the oxide semiconductor film 230f. For example, microwave plasma treatment may be performed after the oxide semiconductor film 230f is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like) may be formed after the oxide semiconductor film 230f is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor film 230f via the insulating film.

[0425] Note that the above-described treatment for increasing the crystallinity of the oxide semiconductor film 230f can also serve as treatment for removing impurities contained in the oxide semiconductor film 230f. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor film 230f can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor film 230f in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor film 230f can be reduced.

[0426] When the treatment for increasing the crystallinity of the oxide semiconductor film 230f is performed, the substrate temperature is preferably set to room temperature (for example, 25° C.) or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably set to 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0427] By increasing the crystallinity of the oxide semiconductor film 230f, a highly reliable transistor can be realized.

[0428] Next, a portion of the oxide semiconductor film 230f is removed by anisotropic etching (see FIGS. 18A to 18D ). Specifically, the oxide semiconductor film 230f is processed by anisotropic etching until, for example, the top surface of the insulator 223 is exposed, thereby removing the portion of the oxide semiconductor film 230f. The oxide semiconductor film 230f is etched mainly in a region parallel to the substrate surface, and a sidewall-shaped oxide semiconductor 230 is formed in contact with the side surface of the insulator 223. Note that when removing the portion of the oxide semiconductor film 230f by anisotropic etching, an insulator serving as a hard mask may be provided in the portion. Silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be suitably used as the insulating film.

[0429] Anisotropic etching can form the oxide semiconductor 230 with a high aspect ratio. By using the oxide semiconductor 230, the channel width of the transistor 200 can be increased without increasing the occupation area, thereby improving the on-state current and frequency characteristics of the transistor 200. Furthermore, the contact area between the oxide semiconductor 230 and the conductors 242a and 242b can be increased without increasing the occupation area, thereby improving the on-state current and frequency characteristics of the transistor 200.

[0430] 18A , the oxide semiconductor 230 has a circumferential shape in a plan view, with both ends aligned or substantially aligned. The oxide semiconductor 230 can also be said to have an opening in the center. When the oxide semiconductor 230 has a three-layer structure including the oxide semiconductors 230a to 230c as described above, the circumferential oxide semiconductor 230 is formed in the order of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c, with the region where the insulator 223 was formed at the center. Therefore, as shown in FIG. 7A , in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230c, the oxide semiconductor 230b, the oxide semiconductor 230a, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are arranged symmetrically in this order.

[0431] Although the above description has been given of a configuration in which two circumferential oxide semiconductors 230 are provided, the present invention is not limited to this. For example, one or three or more circumferential oxide semiconductors 230 may be provided. Furthermore, the circumferential oxide semiconductors 230 may be joined to form an oxide semiconductor 230 having a shape with multiple openings. For example, as shown in FIG. 4A , an oxide semiconductor 230 having three openings arranged in the A1-A2 direction in a planar view can be formed. In this case, three insulators 223 are formed adjacent to each other at a short distance in the steps shown in FIGS. 16A to 16D . Furthermore, as shown in FIG. 4B , an oxide semiconductor 230 having a lattice shape in a planar view can be formed. In this case, a lattice-shaped trench is formed in the insulator 223 in the steps shown in FIGS. 16A to 16D .

[0432] 18A , the oxide semiconductor 230 has a circumferential structure in plan view, but etching may be further performed to remove a portion of the oxide semiconductor 230. For example, in the structure shown in FIG. 18A , by removing a portion, the oxide semiconductor 230 may have a rectangular shape extending in the A5-A6 direction in plan view.

[0433] The anisotropic etching of the oxide semiconductor film 230f is preferably performed by dry etching.

[0434] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, or BBr ３ Gases such as fluorine-containing gases can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, gases containing no halogen gas but hydrocarbon gas or hydrogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0435] A capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used as the dry etching apparatus. A capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, a high-frequency voltage of the same frequency may be applied to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to the parallel-plate electrodes. Such a CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. The DF-CCP etching apparatus may be configured, for example, to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus. The etching apparatus can be appropriately configured according to the object to be etched. In the above-mentioned dry etching apparatus, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, so that highly anisotropic etching can be performed.

[0436] Next, the insulator 223 is removed (see FIGS. 19A to 19D ). Dry etching, wet etching, or the like can be used to remove the insulator 223. It is preferable to remove the insulator 223 by, for example, wet etching. While FIGS. 19B and 19C illustrate a structure in which curved shapes are formed on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the oxide semiconductor 230, this is not limiting. For example, a structure in which a curved shape is formed only on the side of the oxide semiconductor 230 that is not in contact with the insulator 223 shown in FIGS. 18B and 18C may be used.

[0437] As described above, the insulator 223 is removed during the manufacturing process of the semiconductor device of one embodiment of the present invention. Therefore, the insulator 223 is also referred to as a sacrificial layer.

[0438] Next, the insulating film 224f is processed to form the insulator 224 (see FIGS. 20A to 20D ). The insulating film 224f can be processed, for example, using the oxide semiconductor 230 as a mask. In this case, the region of the insulating film 224f that does not overlap with the oxide semiconductor 230 can be removed. Therefore, as shown in FIG. 20A , the insulator 224 can be formed to overlap with the oxide semiconductor 230. Furthermore, the insulator 224 can be formed to match or approximately match the shape of the oxide semiconductor 230 in a plan view. Note that when the semiconductor device shown in FIGS. 9A to 9D is manufactured, the steps shown in FIGS. 20A to 20D are not performed.

[0439] The insulating film 224f can be processed by dry etching or wet etching. Dry etching is suitable for fine processing. The above description can be referred to for the conditions for the dry etching and the dry etching apparatus.

[0440] When processing the insulating film 224f, the insulator 222 below the insulating film 224f may also be processed. In this case, the film thickness of the region of the insulator 222 that does not overlap with the insulator 224 may be thinner than the film thickness of the region of the insulator 222 that overlaps with the insulator 224.

[0441] 18A to 18C show an example in which two insulators 223 and two oxide semiconductors 230 are formed for one transistor 200, but the present invention is not limited thereto. As shown in the cross-sectional view of FIG. 21A , two transistors (transistor 200_1 and transistor 200_2) may each be formed with two insulators 223 and two oxide semiconductors 230. As shown in the cross-sectional view of FIG. 21B , insulators 223 with different widths may be formed, and three fin-shaped oxide semiconductors 230 may be formed for each of the transistors 200_1 and 200_2 in the cross-sectional view along the A1-A2 direction. In this case, part of the oxide semiconductor 230 is removed to separate the oxide semiconductor 230 of the transistor 200_1 from the oxide semiconductor 230 of the transistor 200_2 into a linear shape extending in the A5-A6 direction in a plan view.

[0442] Furthermore, the insulator 223 does not necessarily have to be removed. For example, as shown in FIG. 22A , a configuration in which part of the insulator 223 remains can be used. For example, the insulator 223 can remain in a region where the conductor 240 will be provided in a later step. For example, when removing the insulator 223 in the above step, a mask can be formed by lithography in the region where the conductor 240 will be provided, thereby allowing the insulator 223 to remain in that region. In this case, the insulator 224 can be formed by processing the insulating film 224f using the insulator 223 as a mask in addition to the oxide semiconductor 230. In the example shown in FIG. 22A , the insulator 224 can be formed to overlap with the insulator 223 in addition to the oxide semiconductor 230. The insulator 223 can be formed on the insulator 224 and embedded inside the circumferential oxide semiconductor 230. 22B , in the transistor 200, the conductor 242a (conductor 242b) and the conductor 240a (conductor 240b) are formed to cover the oxide semiconductor 230, the insulator 223, and the insulator 224. Here, the conductor 242a (conductor 242b) is in contact with the side surface and the top surface of the oxide semiconductor 230, the top surface of the insulator 223, and the side surface of the insulator 224.

[0443] Next, a conductive film 242f is formed over the insulator 222 and the oxide semiconductor 230 (see FIGS. 23A to 23D). The conductive film 242f can be formed using a conductor corresponding to the conductors 242a and 242b.

[0444] The conductive film 242f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the conductive film 242f is preferably formed by sputtering. Alternatively, as shown in FIG. 8B and other figures, a stacked structure of tantalum nitride and tungsten on the tantalum nitride may be used. By forming the conductive film 242f to cover the oxide semiconductor 230, the contact area between the oxide semiconductor 230 and the conductors 242a and 242b can be increased without increasing the area occupied by the oxide semiconductor 230. This can improve the on-state current and frequency characteristics of the transistor 200.

[0445] Next, the conductive film 242f is processed into an island shape by lithography to form a conductor 242A (see FIGS. 24A to 24D). At this time, the conductor 242A is preferably formed to cover the oxide semiconductor 230 and the insulator 224. The conductor 242A can be formed to be in contact with the oxide semiconductor 230. Furthermore, the insulator 222 is exposed in a region that does not overlap with the conductor 242A.

[0446] For the above processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. Note that the above description can be referred to for the conditions for the dry etching method and the dry etching apparatus.

[0447] The side surface of the conductor 242A may be configured to be perpendicular or approximately perpendicular to the upper surface of the insulator 222. By using such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors.

[0448] However, the present invention is not limited to the above, and the side surfaces of the oxide semiconductor 230 and the conductor 242A may be tapered. The taper angle of the side surfaces of the oxide semiconductor 230 and the conductor 242A may be, for example, greater than or equal to 60° and less than 90°. Tapering the side surfaces in this manner improves coverage with the insulator 275 and the like in subsequent steps, and reduces defects such as voids.

[0449] In the lithography method, first, a resist is exposed through a mask. Next, the exposed region is removed or left using a developer to form a resist mask. Next, an etching process is performed through the resist mask, thereby processing a conductor, semiconductor, insulator, or the like into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be used in some cases.

[0450] The resist mask that is no longer needed after processing can be removed by performing a dry etching treatment such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), a wet etching treatment, a dry etching treatment followed by a wet etching treatment, or a wet etching treatment followed by a dry etching treatment.

[0451] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as a hard mask material is formed on the conductive film 242f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 242f and the like may be performed after removing the resist mask or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242f. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0452] Alternatively, a spin-on-carbon (SOC) film and a spin-on-glass (SOG) film may be formed between the workpiece and the resist mask. Using the SOC film and the SOG film as masks can improve the durability of the mask pattern. For example, a lithography method can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0453] Next, an insulator 275 is formed to cover the conductor 242A, and then an insulator 280 is formed on the insulator 275 (see FIGS. 25A to 25D). That is, the insulator 275 and the insulator 280 are formed in this order on the conductor 242A. The insulators described above can be used as the insulators 275 and 280.

[0454] Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222 .

[0455] As the insulator 280, it is preferable to form an insulator with a flat upper surface by forming an insulating film to be the insulator 280 and performing CMP treatment on the insulating film. Note that it is also possible to form a silicon nitride film on the insulator 280 by, for example, a sputtering method and perform CMP treatment on the silicon nitride until it reaches the insulator 280.

[0456] The insulators 275 and 280 can each be formed by, for example, sputtering, CVD, MBE, PLD, or ALD.

[0457] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film by a PEALD method as the insulator 275. Alternatively, it is preferable to form an aluminum oxide film by a sputtering method and then form a silicon nitride film thereon by a PEALD method as the insulator 275. By using the above structure for the insulator 275, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0458] In this manner, the oxide semiconductor 230 and the conductor 242A can be covered with the insulator 275, which has a function of suppressing oxygen diffusion. This can suppress oxygen from diffusing directly from the insulator 280 or the like into the oxide semiconductor 230 and the conductor 242A in a later step.

[0459] The insulator 280 is preferably formed using silicon oxide by a sputtering method. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. The hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 and the like can be removed, and the moisture and hydrogen concentrations in the oxide semiconductor 230 can be further reduced. The heat treatment can be performed under the above-described heat treatment conditions.

[0460] Next, the insulator 280, the insulator 275, and the conductor 242A are processed by lithography. By processing the insulator 280 and the insulator 275, an opening 201 overlapping with the oxide semiconductor 230 is formed in the insulator 280 and the insulator 275. By processing the conductor 242A, the conductor 242A is divided, and the conductor 242a and the conductor 242b are formed (see FIGS. 26A to 26D ). The conductor 242a and the conductor 242b can be formed to be in contact with the oxide semiconductor 230. The conductor 242a and the conductor 242b can be formed to face each other across the opening 201 in a plan view. Note that when the semiconductor device shown in FIGS. 9A to 9D is manufactured, in addition to the insulator 280, the insulator 275, and the conductor 242A, for example, the insulating film 224f shown in FIGS. 19A to 19D is also processed. By processing the insulating film 224f, the insulator 224 shown in FIGS. 9A to 9D is formed.

[0461] The lithography method may be any of the above-described methods, as appropriate. To finely process the conductor 242A, the insulator 275, and the insulator 280, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0462] The above processing is preferably performed using a dry etching method. Dry etching is capable of anisotropic etching and is therefore suitable for forming openings 201 with a high aspect ratio. The above description can be referred to for the conditions for the dry etching method and the dry etching apparatus.

[0463] 8C , it is preferable to form the conductor 242a1 and the conductor 242b1 by further performing etching after forming the conductor 242a2 and the conductor 242b2. With this configuration, the transistor 200 and the capacitor 460 shown in FIGS. 13A and 13B can be fabricated in parallel. In this case, for example, when the conductor 242A of the transistor 200 is etched to form the conductor 242a1 and the conductor 242b1, the capacitor 460 is not subjected to the etching process, and the oxide semiconductor 452 is covered with the conductor 242b1. This allows the capacitor 460, including the conductor 242b1, the insulator 454, and the conductor 456, to be fabricated in parallel with the transistor 200.

[0464] Note that after processing the conductor 242A, ashing treatment using oxygen plasma may be performed. By performing such oxygen plasma treatment, impurities generated during the etching treatment and diffused into the oxide semiconductor 230 and the like can be removed. Examples of the impurities include those originating from components contained in the workpiece of the etching treatment and components contained in the gas used in the etching treatment. Examples include chlorine, fluorine, tantalum, silicon, and hafnium. In particular, when chlorine gas is used in processing the conductor 242A as shown in the etching treatment, the oxide semiconductor 230 is exposed to an atmosphere containing chlorine gas. Therefore, it is preferable to remove chlorine attached to the oxide semiconductor 230. Removing the impurities attached to the oxide semiconductor 230 in this manner can improve the electrical characteristics and reliability of the transistor.

[0465] Furthermore, a cleaning treatment may be performed to remove impurities and the like attached to the surface of the oxide semiconductor 230 in the etching step. Examples of the cleaning method include wet cleaning using a cleaning solution or the like (also referred to as wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment. The cleaning methods may be combined as appropriate. Note that the cleaning treatment may deepen the grooves in some cases.

[0466] Wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0467] In this specification, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution are adjusted appropriately depending on the impurities to be removed, the configuration of the semiconductor device to be cleaned, etc. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0468] Note that the ultrasonic cleaning is preferably performed at a frequency of 200 kHz or higher, more preferably 900 kHz or higher, because damage to the oxide semiconductor 230 and the like can be reduced by using such a frequency.

[0469] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0470] In this embodiment, wet cleaning is performed using diluted ammonia water as the cleaning treatment. By performing the cleaning treatment, impurities attached to the surface of the oxide semiconductor 230 or diffused into the oxide semiconductor 230 can be removed. Furthermore, the crystallinity of the oxide semiconductor 230 can be improved.

[0471] It is preferable to perform heat treatment after the etching or the cleaning. The temperature of the heat treatment is 100° C. to 650° C., preferably 250° C. to 600° C., more preferably 300° C. to 550° C., and still more preferably 350° C. to 400° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment is preferably performed in an atmosphere containing oxygen. For example, the heat treatment is preferably performed at 350° C. for 1 hour with a flow ratio of nitrogen gas to oxygen gas of 4:1. This allows oxygen to be supplied to the oxide semiconductor 230, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the oxide semiconductor 230. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide semiconductor 230 to convert the hydrogen into H ２ As a result, hydrogen remaining in the oxide semiconductor 230 is recombined with the oxygen vacancies to form V Ｏ The formation of H can be suppressed. Therefore, the electrical characteristics of the transistor including the oxide semiconductor 230 can be improved, and reliability can be improved. Furthermore, variation in the electrical characteristics of a plurality of transistors formed over the same substrate can be suppressed. Note that the heat treatment may be performed under reduced pressure. Alternatively, heat treatment may be performed in an oxygen atmosphere and then successively in a nitrogen atmosphere without exposure to the air. Furthermore, the heat treatment can also serve as the heat treatment for the oxide semiconductor film 230f described above. Therefore, the heat treatment may cause growth of a crystalline region in the oxide semiconductor 230.

[0472] Note that when heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide semiconductor 230, the sheet resistance of a region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b may decrease. Also, the carrier concentration may increase. Therefore, the resistance of the region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b can be reduced in a self-aligned manner.

[0473] Next, the insulator 250 is formed to cover the opening 201 (see FIGS. 27A to 27D ). The insulator 250 is formed inside the opening 201 so as to be in contact with the oxide semiconductor 230, the insulator 222, the insulator 224, the conductor 242a, the conductor 242b, the insulator 275, and the insulator 280. The insulator 250 is formed to have a region provided on the insulator 280.

[0474] The insulator 250 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulator 250 is preferably formed using an ALD method. The insulator 250 is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer, etc.) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, the insulator 250 must be formed with good coverage on the bottom and side surfaces of the opening 201. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the opening 201, allowing the insulator 250 to be formed with good coverage on the opening 201.

[0475] When the insulator 250 is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using an oxidizing agent such as HCl, hydrogen diffusing into the oxide semiconductor 230 can be reduced.

[0476] The insulator 250 can have a stacked structure as shown in Figures 2A and 2B, etc. For example, as shown in Figures 2A and 2B, the insulator 250 can have a stacked structure of insulators 250a to 250d. In this case, aluminum oxide can be formed as the insulator 250a by a thermal ALD method, silicon oxide can be formed as the insulator 250b by a PEALD method, hafnium oxide can be formed as the insulator 250c by a thermal ALD method, and silicon nitride can be formed as the insulator 250d by a PEALD method.

[0477] Furthermore, after the insulator 250 or any of the insulators constituting the insulator 250 is formed, microwave plasma treatment is preferably performed in an atmosphere containing oxygen. For the microwave plasma treatment, for example, a microwave plasma treatment apparatus having a power supply that generates high-density plasma using microwaves is preferably used. Here, the frequency of the microwave plasma treatment apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. The use of high-density plasma enables the generation of high-density oxygen radicals. Furthermore, the power of the power supply that applies microwaves in the microwave plasma treatment apparatus is preferably 1000 W to 10,000 W, more preferably 2000 W to 5,000 W. Furthermore, the microwave plasma treatment apparatus may have a power supply that applies RF to the substrate side. Furthermore, applying RF to the substrate side allows oxygen ions generated by high-density plasma to be efficiently guided into the oxide semiconductor 230.

[0478] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

[0479] Furthermore, for example, the microwave plasma treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less. By performing microwave plasma treatment in an atmosphere containing oxygen in this manner, the carrier concentration in the oxide semiconductor 230 can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber in the microwave plasma treatment, an excessive reduction in the carrier concentration in the oxide semiconductor 230 can be prevented.

[0480] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to a region between the conductor 242 a and the conductor 242 b of the oxide semiconductor 230. The action of the plasma, microwaves, or the like can reduce the V Ｏ The H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Here, when the insulator 250 has the structure shown in FIGS. 2A and 2B, it is preferable to use an insulator (e.g., aluminum oxide) that has the function of capturing or fixing hydrogen as the insulator 250a. With such a structure, hydrogen generated by microwave plasma treatment can be captured or fixed in the insulator 250. In this way, V included in the channel formation region can be removed. Ｏ As a result, oxygen vacancies in the channel formation region and V ＯBy supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0481] The oxygen implanted into the channel formation region can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also called O radicals). The oxygen implanted into the channel formation region can take one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0482] Furthermore, the microwave plasma treatment can also remove impurities such as carbon in the oxide semiconductor 230. Removal of carbon, which is an impurity in the oxide semiconductor 230, can improve the crystallinity of the oxide semiconductor 230. As a result, the oxide semiconductor 230 can be made into a CAAC-OS. In particular, when the oxide semiconductor film 230f is formed by an ALD method, carbon contained in a precursor might be taken into the oxide semiconductor 230, so it is preferable to remove carbon by microwave plasma treatment.

[0483] Meanwhile, the oxide semiconductor 230 has a region overlapping with either the conductor 242a or the conductor 242b. This region can function as a source region or a drain region. Here, the conductor 242a and the conductor 242b preferably function as a shielding film against the action of microwaves, high frequency waves such as RF, oxygen plasma, and the like when microwave plasma treatment is performed in an atmosphere containing oxygen. Therefore, the conductor 242a and the conductor 242b preferably have a function of shielding electromagnetic waves of 300 MHz to 300 GHz, for example, 2.4 GHz to 2.5 GHz.

[0484] The conductors 242a and 242b shield the oxide semiconductor 230 from microwaves, high-frequency waves such as RF, oxygen plasma, and the like, and therefore these effects do not reach a region of the oxide semiconductor 230 that overlaps with either the conductor 242a or the conductor 242b. As a result, the microwave plasma treatment can reduce V Ｏ Since the amount of H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0485] In this manner, oxygen vacancies and V Ｏ By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions that function as source or drain regions can be suppressed, and the conductivity (low resistance region state) before the microwave plasma treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0486] Furthermore, by performing microwave plasma treatment to modify the film quality of the insulator 250, diffusion of hydrogen, water, impurities, and the like can be suppressed. Therefore, diffusion of hydrogen, water, impurities, and the like through the insulator 250 into the oxide semiconductor 230, etc., can be suppressed by a post-process such as forming the conductor 260 or a post-treatment such as heat treatment. In this way, improving the film quality of the insulator 250 can improve the reliability of the transistor.

[0487] When the insulator 250 has a stacked structure of insulators 250a to 250d, microwave plasma treatment is preferably performed after the formation of the insulator 250b. Furthermore, microwave plasma treatment may be performed again after the formation of the insulator 250c. In this manner, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice or more). The microwave plasma treatment may also serve as the heat treatment of the oxide semiconductor film 230f. Therefore, the microwave plasma treatment may cause a crystalline region of the oxide semiconductor 230 to grow.

[0488] After the microwave plasma treatment, heat treatment may be performed while the reduced pressure state is maintained. By performing such treatment, hydrogen in the insulator 250 and the oxide semiconductor 230 can be efficiently removed. Alternatively, the step of performing heat treatment while the reduced pressure state is maintained after the microwave plasma treatment may be repeated multiple times. By repeatedly performing the heat treatment, hydrogen in the insulator 250 and the oxide semiconductor 230 can be more efficiently removed. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The heat treatment can also serve as the heat treatment for the oxide semiconductor film 230f. Therefore, the heat treatment may cause growth of a crystalline region in the oxide semiconductor 230.

[0489] Next, the conductor 260a and the conductor 260b are formed in this order on the insulator 250 (see FIGS. 28A to 28D). Specifically, the conductor 260a is formed so as to cover the opening 201, and the conductor 260b is formed on the conductor 260a so as to fill the opening 201. Furthermore, the conductor 260a and the conductor 260b are formed so as to have a region provided on the insulator 280.

[0490] The conductor 260a and the conductor 260b can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. In this embodiment, a titanium nitride film is formed as the conductor 260a by a CVD method, and a tungsten film is formed as the conductor 260b by a CVD method. Note that the formation of the conductor 260a and the conductor 260b may be performed while heating the substrate. The substrate heating can also serve as the heat treatment for the oxide semiconductor film 230f described above. Therefore, the substrate heating may cause the growth of a crystalline region of the oxide semiconductor 230.

[0491] Next, the insulator 250, the conductor 260a, and the conductor 260b are polished by CMP until the insulator 280 is exposed. That is, the regions of the insulator 250, the conductor 260a, and the conductor 260b exposed from the opening 201 are removed (see FIGS. 29A to 29D). For example, the regions of the insulator 250, the conductor 260a, and the conductor 260b that overlap with the insulator 280 are removed.

[0492] As a result, the insulator 250 is formed inside the opening 201 so as to be in contact with the oxide semiconductor 230, the insulator 222, the insulator 224, the conductor 242a, the conductor 242b, the insulator 275, and the insulator 280. The conductor 260 is formed on the insulator 250 so as to fill the opening 201. Specifically, the conductor 260a is formed inside the opening 201 so as to be in contact with the insulator 250. The conductor 260b is formed on the conductor 260a so as to fill the opening 201. In this manner, the transistor 200 is formed.

[0493] Next, the insulator 282 is formed over the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 1A to 1D). The insulator 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably formed by a sputtering method. Alternatively, the insulator 282 may be formed by forming a first layer by an ALD method and then forming a second layer thereon by a sputtering method.

[0494] Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere by a sputtering method, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. At this time, the insulator 282 is preferably deposited while heating the substrate. Depositing the insulator 282 in this manner allows a suitable amount of oxygen to be supplied from the insulator 280 to the oxide semiconductor 230 through the insulator 250. Furthermore, providing the insulator 250a in the insulator 250 can prevent excessive oxygen from being supplied into the insulator 250 and causing excessive oxidation of the conductors 242a and 242b near the insulator 250.

[0495] The aluminum oxide film is formed using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen implanted into the insulator 280 can be controlled by the magnitude of the bias power applied to the substrate by the sputtering method. For example, the smaller the bias power, the less oxygen is implanted into the insulator 280, and the more likely the oxygen amount is to saturate even if the insulator 282 is thin. Furthermore, the greater the bias power, the more oxygen is implanted into the insulator 280. By reducing the RF power, the amount of oxygen implanted into the insulator 280 can be suppressed. Note that when applying a substrate bias using an RF power supply, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0496] Furthermore, by forming a second layer by sputtering on top of the first layer formed by ALD, the upper end of the insulator 250 and the upper surface of the conductor 260 can be protected from the impact of ion collisions caused by sputtering film formation.

[0497] Alternatively, heat treatment may be performed before the formation of the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed and the moisture and hydrogen concentrations in the insulator 280 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0498] Next, the insulator 283 is formed over the insulator 282 (see FIGS. 1A to 1D). The insulator 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is formed as the insulator 283 by a sputtering method.

[0499] Here, it is preferable to successively form the insulators 282 and 283 without exposing them to the air environment. By forming the insulators 282 and 283 without exposing them to the air environment, impurities or moisture from the air environment can be prevented from adhering to the insulators 282 and 283, and the interface or the vicinity of the interface between the insulators 282 and 283 can be kept clean.

[0500] In this embodiment, a silicon nitride film is formed as the insulator 283, and an aluminum oxide film is formed as the insulator 282. In this manner, by using silicon nitride, which has a function of suppressing hydrogen diffusion, for the insulator 283, diffusion of hydrogen from the upper layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide, which has a function of capturing or fixing hydrogen, for the insulator 282, hydrogen contained in the insulator 280 and the like can be captured or fixed to the insulator 282. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0501] Next, an opening 202a reaching the conductor 242a and an opening 202b reaching the conductor 242b are formed in the insulators 275, 280, 282, and 283 (see FIGS. 1A to 1D ). The opening 202 can be formed by, for example, lithography. The opening 202 is preferably formed by processing the workpiece using dry etching. Since dry etching allows anisotropic etching, it is suitable for forming openings 202 with a high aspect ratio. When performing anisotropic etching, reactive ion etching, for example, is preferably performed. The conditions for the dry etching method and the dry etching apparatus can be found above. In FIG. 1A , the shapes of the openings reaching the conductor 242a and the openings reaching the conductor 242b are rectangular in plan view, but this is not limiting. For example, these openings may have a circular shape, an approximately circular shape such as an oval, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners in a plan view.

[0502] Next, after the opening 202 is formed, heat treatment may be performed. The temperature of the heat treatment is, for example, 100° C. to 600° C., preferably 250° C. to 550° C., more preferably 350° C. to 450° C. Note that the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. The heat treatment is preferably performed in an atmosphere containing neither oxidizing gas nor oxygen gas because the conductors 242a and 242b are exposed. For example, the heat treatment is preferably performed in a nitrogen gas atmosphere at 400° C. for one hour. Note that the heat treatment may be performed under reduced pressure. By the heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250. This can reduce oxygen vacancies in the channel formation region of the oxide semiconductor 230. The heat treatment can also serve as the heat treatment for the oxide semiconductor film 230f. Therefore, the heat treatment may cause a crystalline region of the oxide semiconductor 230 to grow.

[0503] Here, because the side surface of the insulator 280 is exposed at the opening 202, the heat treatment can outwardly diffuse oxygen contained in the insulator 280, thereby controlling the amount of oxygen contained in the insulator 280. Meanwhile, because the insulators 282 and 283, which have a barrier property against oxygen, are provided on the insulator 280, oxygen does not outwardly diffuse from the top surface of the insulator 280. This can prevent excessive outward diffusion of oxygen from the insulator 280 and the formation of oxygen vacancies in the insulator 280. Furthermore, the oxide semiconductor 230, the conductor 242a, and the conductor 242b are covered with the insulator 275. This can prevent excessive oxygen from diffusing directly from the insulator 280 to the oxide semiconductor 230, the conductor 242a, and the conductor 242b during the heat treatment.

[0504] In this manner, the amount of oxygen in the insulator 280 can be more suitably adjusted, and an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. This reduces oxygen vacancies in the oxide semiconductor 230 and prevents excessive oxygen from being supplied to the oxide semiconductor 230. This improves the electrical characteristics and reliability of the transistor 200. Furthermore, the step of exposing the side surface of the insulator 280 can be combined with the step of forming the opening 202, thereby simplifying the manufacturing process of the semiconductor device.

[0505] Next, an insulating film to be the insulator 241 is formed and anisotropically etched to form the insulator 241a in the opening 202a and the insulator 241b in the opening 202b (see FIGS. 1A to 1D). The insulating film to be the insulator 241 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. As the insulating film to be the insulator 241, it is preferable to use an insulating film that has a function of suppressing oxygen permeation. For example, it is preferable to form a silicon nitride film by PEALD. Silicon nitride is preferable because it has high blocking properties against hydrogen.

[0506] Furthermore, dry etching, for example, can be used to anisotropically etch the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening 202, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductors 240a and 240b. Note that this anisotropic etching may form recesses in parts of the upper surfaces of the conductors 242a and 242b.

[0507] Next, conductive films that become the conductors 240a and 240b are formed. The conductive films that become the conductors 240a and 240b preferably have a layered structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, they may be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive films that become the conductors 240a and 240b can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0508] Next, CMP treatment is performed to remove parts of the conductive film that will become the conductors 240a and 240b, thereby exposing the top surface of the insulator 283. As a result, the conductive film remains only in the openings 202, thereby forming the conductors 240a and 240b with flat top surfaces (see FIGS. 1A to 1D). Note that the CMP treatment may remove part of the top surface of the insulator 283.

[0509] As described above, by providing the conductor 240a in contact with the conductor 242a, the conductor 240a functioning as one of the source and drain of the transistor 200 can be electrically connected to a wiring. Furthermore, by providing the conductor 240b in contact with the conductor 242b, the conductor 240b functioning as the other of the source and drain of the transistor 200 can be electrically connected to a wiring.

[0510] Note that a conductive film functioning as a wiring or a conductive film functioning as a plug can be formed over the conductor 240a and the conductor 240b.

[0511] In this manner, the semiconductor device shown in FIGS. 1A to 1D can be manufactured.

[0512] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0513] Embodiment 2 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0514] Fig. 30 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 30 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 30 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0515] The transistor described in Embodiment 1 can be applied to the memory cell 950. By using the transistor, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0516] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0517] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0518] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0519] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0520] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0521] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0522] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0523] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0524] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply voltage of the semiconductor device 900 is V ＤＤ and the low power supply voltage is GND (ground potential). ＨＭ is the high power supply voltage used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 30, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it may be set to a plurality of power domains. In this case, a power switch can be provided for each power domain.

[0525] 31A to 31H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0526] 31A shows an example of a circuit configuration of a DRAM memory cell. In this specification, a DRAM using an OS transistor is referred...

Claims

a transistor, a first insulator, and a second insulator; the transistor includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, and a third insulator; the first insulator is provided on a substrate; the oxide semiconductor is provided on the first insulator, the first conductor and the second conductor are provided on the oxide semiconductor; the second insulator is provided on the first conductor and the second conductor; the second insulator has an opening overlapping a region between the first conductor and the second conductor of the oxide semiconductor in a plan view; the third insulator is provided inside the opening so as to have a region in contact with the oxide semiconductor; the third conductor is provided on the third insulator within the opening, a shape of the first insulator in a plan view and a shape of the oxide semiconductor in a plan view are identical or substantially identical to each other at least in a region overlapping with the opening; a bottom surface of the third conductor is located below a bottom surface of the oxide semiconductor in a cross-sectional view of the transistor in a channel width direction; the first insulator comprises a metal oxide; In a cross-sectional view of the transistor in a channel width direction, a height of the oxide semiconductor is equal to or greater than a width of the oxide semiconductor, The semiconductor device has two or more regions where the oxide semiconductor and the third conductor overlap in a plan view. 　 a transistor, a capacitor, a first insulator, a second insulator, and a third insulator; the transistor includes a first oxide semiconductor, a first conductor, a second conductor, a third conductor, and a fourth insulator; the capacitor includes a second oxide semiconductor, the second conductor, a fourth conductor, and a fifth insulator; the first insulator and the second insulator are provided on the same surface to be formed on a substrate; the first oxide semiconductor is provided on the first insulator; the second oxide semiconductor is provided on the second insulator; the first conductor is provided on the first oxide semiconductor; the second conductor is provided on the first oxide semiconductor and the second oxide semiconductor; the third insulator is provided on the first conductor and the second conductor; the third insulator has a first opening overlapping a region between the first conductor and the second conductor in the first oxide semiconductor in a plan view; the third insulator overlaps the second oxide semiconductor and has a second opening reaching the second conductor; the fourth insulator is provided inside the first opening so as to have a region in contact with the first oxide semiconductor; the third conductor is provided on the fourth insulator within the first opening, the fifth insulator is provided inside the second opening so as to overlap the second conductor; the fourth conductor is provided on the fifth insulator within the second opening, a shape of the first insulator in a plan view and a shape of the first oxide semiconductor in a plan view are identical or substantially identical to each other at least in a region overlapping with the first opening; a shape of the second insulator in a plan view and a shape of the second oxide semiconductor in a plan view are identical or substantially identical to each other at least in a region overlapping with the second opening; a bottom surface of the third conductor is provided below a bottom surface of the first oxide semiconductor in a cross-sectional view of the transistor in a channel width direction; In a cross-sectional view of the transistor in a channel width direction, a height of the first oxide semiconductor is equal to or greater than a width of the first oxide semiconductor, The semiconductor device has two or more regions where the first oxide semiconductor and the third conductor overlap in a plan view. 　 In claim 2, The semiconductor device, wherein the first insulator and the second insulator include a metal oxide. 　 In claim 2 or 3, In a cross-sectional view of the transistor in a channel width direction, a height of the second oxide semiconductor is equal to or greater than a width of the second oxide semiconductor, The semiconductor device has two or more regions where the second oxide semiconductor and the fourth conductor overlap in a plan view. 　 In claim 1 or claim 3, The metal oxide has a function of capturing or adhering hydrogen. 　 In claim 5, The semiconductor device, wherein the metal oxide is a high-k material. 　 In claim 6, The metal oxide is an oxide containing one or both of aluminum and hafnium. 　 In claim 6, The semiconductor device, wherein the metal oxide is hafnium silicate. 　 In claim 1, The semiconductor device, in which, in a plan view, the oxide semiconductor has a circumferential shape whose ends are coincident or approximately coincident. 　 In claim 1, A semiconductor device in which, in a plan view, a side surface of the opening coincides or substantially coincides with a side surface of the first conductor and a side surface of the second conductor. 　 In claim 1, When viewed in a cross section of the transistor in a channel width direction, a width of the oxide semiconductor is 5 nm to 50 nm. In a cross-sectional view of the transistor in a channel width direction, the height of the oxide semiconductor is 1.5 to 10 times the width of the oxide semiconductor. 　 In any one of claims 1 and 9 to 11, the oxide semiconductor contains indium; the oxide semiconductor is formed perpendicular or substantially perpendicular to a surface of the substrate; A semiconductor device in which bright points arranged in layers in a direction perpendicular to the surface of the substrate are confirmed in a cross-section of the oxide semiconductor using a transmission electron microscope. 　 In any one of claims 1 and 9 to 11, the oxide semiconductor contains indium; the oxide semiconductor is formed perpendicular or substantially perpendicular to a surface of the substrate; the oxide semiconductor has a first region, a second region in contact with the first region, and a third region in contact with the second region; A semiconductor device in which, when a cross-section of the oxide semiconductor is observed using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are confirmed in each of the first region, the second region, and the third region. 　 In claim 13, the second region comprises zinc; the second region has crystals; The c-axis of the crystal is approximately parallel to a normal direction to a side surface of the oxide semiconductor. 　 In claim 13, a content of indium in the first region is higher than a content of indium in the second region; The semiconductor device, wherein the third region has a higher indium content than the second region. 　 An insulating film is formed on a substrate; forming a first insulator on the insulating film; forming an oxide semiconductor film to cover the first insulator; the oxide semiconductor film is processed by anisotropic etching until a top surface of the first insulator is exposed, thereby forming an oxide semiconductor in contact with a side surface of the first insulator; removing the first insulator; forming a second insulator by removing a region of the insulating film that does not overlap with the oxide semiconductor; forming a first conductor covering the oxide semiconductor and the second insulator; forming a third insulator on the first conductor; forming an opening in the third insulator that overlaps with the oxide semiconductor by processing the third insulator; forming a second conductor and a third conductor that face each other across the opening in a plan view by processing the first conductor; forming a fourth insulator in the opening so as to be in contact with the oxide semiconductor, the second insulator, and the third insulator; The method for manufacturing a semiconductor device further comprises forming a fourth conductor on the fourth insulator so as to fill the opening. 　 In claim 16, A method for manufacturing a semiconductor device, wherein aluminum oxide or silicon nitride is used as the first insulator.

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