Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component for which it is not necessary to design the internal structure per capacitance, while suppressing an increase in capacitance and an increase in DC resistance.　A multilayer ceramic electronic component 100 according to the present invention includes a multilayer ceramic capacitor and a conductor section. The multilayer ceramic capacitor is provided with: a laminate including a plurality of dielectric layers stacked on one another and including a first principal face and a second principal face that are opposite to each other in the stacking direction, a first side face and a second side face that are opposite to each other in the width direction, which is perpendicular to the stacking direction, and a first end face and a second end face that are opposite to each other in the length direction, which is perpendicular to the stacking direction and the width direction, the laminate including a first internal electrode layer exposed at the first end face and the second end face, as well as a second internal electrode layer exposed at the first side face and the second side face; a first external electrode and a second external electrode connected to the first internal electrode layer; and a third external electrode and a fourth external electrode connected to the second internal electrode layer. The conductor section is electrically connected to the first external electrode and the second external electrode and is electrically connected to neither the third external electrode nor the fourth external electrode. The DC resistance RdcA of the conductor section is smaller than the DC resistance RdcB of the multilayer ceramic capacitor, and the conductor section is a lead frame.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] For example, feedthrough three-terminal capacitors are known as decoupling capacitors used to stabilize power supply voltages supplied to integrated circuit components (ICs) operating at high speeds and as noise suppression components for power lines supplied to integrated circuit components (ICs). A feedthrough three-terminal capacitor generally includes a laminate having first and second main surfaces facing each other, first and second side surfaces facing each other, and first and second end surfaces facing each other. A plurality of first internal electrode layers and second internal electrode layers are alternately arranged in the stacking direction within the laminate. Each of the first internal electrode layers has both ends extending to the first end surface and the second end surface, and each of the second internal electrode layers has both ends extending to the first side surface and the second side surface. The first internal electrode layer is connected to a first external electrode and a second external electrode, and the second internal electrode layer is connected to a third external electrode and a fourth external electrode.

[0003] When a typical feedthrough three-terminal capacitor is used as a noise filter, a direct current flows through the signal internal electrodes (first internal electrode layers). However, when the capacitance is low, the number of signal internal electrodes (first internal electrode layers) decreases, which increases the direct current resistance and causes the problem of increased heat generation from the capacitor.

[0004] Therefore, as a structure of a low-capacitance feedthrough three-terminal capacitor that can suppress an increase in capacitance while suppressing an increase in DC resistance, a structure such as that described in Patent Document 1 is provided. By increasing the number of signal internal electrodes (first internal electrode layers) and arranging the signal internal electrodes (first internal electrode layers) to face each other, both the capacitance and the DC resistance are suppressed.

[0005] Japanese Patent Application Publication No. 9-55335

[0006] However, the structure described in Patent Document 1 has the following problems. That is, there is a limit to how many signal internal electrodes (first internal electrode layers) can be increased within a given size constraint, making it difficult to accommodate larger currents. Furthermore, it is necessary to design an internal structure for each individual product with different capacitances, which reduces the expandability of the product lineup.

[0007] Therefore, a primary object of the present invention is to provide a multilayer ceramic electronic component that suppresses increases in capacitance and DC resistance, and does not require the internal structure to be designed for each capacitance.

[0008] A multilayer ceramic electronic component according to the present invention comprises: a laminate including a plurality of laminated dielectric layers, the laminate including first and second main surfaces opposing each other in the lamination direction, first side surfaces and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first end surfaces and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; a multilayer ceramic capacitor including first internal electrode layers exposed at the first end surfaces and the second end surfaces and second internal electrode layers exposed at the first side surfaces and the second side surfaces, the multilayer ceramic capacitor comprising first external electrodes and second external electrodes connected to the first internal electrode layers, and third external electrodes and fourth external electrodes connected to the second internal electrode layers; and a conductor portion electrically connected to the first external electrodes and the second external electrodes but not electrically connected to the third external electrodes and the fourth external electrodes, wherein a DC resistance RdcA of the conductor portion is smaller than a DC resistance RdcB of the multilayer ceramic capacitor, and the conductor portion is a lead frame.

[0009] In the multilayer ceramic electronic component according to the present invention, the DC resistance RdcA of the conductor connected to the multilayer ceramic capacitor is smaller than the DC resistance RdcB of the multilayer ceramic capacitor. This allows DC current to flow through the conductor and AC current to escape to the multilayer ceramic capacitor. More specifically, DC current flows more easily toward a conductor with lower DC resistance than the multilayer ceramic capacitor. On the other hand, AC current flows more easily toward a conductor with lower impedance and therefore flows more easily to the multilayer ceramic capacitor with lower impedance. This configuration prevents the capacitance and DC resistance of the multilayer ceramic capacitor from increasing. Furthermore, simply attaching a conductor to an existing multilayer ceramic capacitor allows it to handle large currents without having to design a new internal structure for each individual capacitance of the multilayer ceramic capacitor. This also enhances the flexibility of the product lineup.

[0010] According to the present invention, it is possible to provide a multilayer ceramic electronic component and a mounting structure for a multilayer ceramic electronic component that do not require the internal structure to be designed for each capacitance, while suppressing increases in capacitance and DC resistance.

[0011] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0012] 1. An external perspective view showing a multilayer ceramic electronic component according to a first embodiment of the present invention. 2. A front view of the multilayer ceramic electronic component according to the first embodiment of the present invention. 3. A plan view of the multilayer ceramic electronic component according to the first embodiment of the present invention. 4. A perspective view of the multilayer ceramic capacitor according to the first embodiment of the present invention. 5. A front view of the multilayer ceramic capacitor according to the first embodiment of the present invention. 6. A plan view of the multilayer ceramic capacitor according to the first embodiment of the present invention. 7. A cross-sectional view taken along line VII-VII in FIG. 4. 8. A cross-sectional view taken along line VIII-VIII in FIG. 4. 9. A cross-sectional view taken along line IX-IX in FIG. 7. 10. A cross-sectional view taken along line X-X in FIG. 13. 11. A cross-sectional view in the lamination direction showing a mounting structure of the multilayer ceramic electronic component according to the first embodiment of the present invention. 12. A cross-sectional view in the width direction showing a mounting structure of the multilayer ceramic electronic component according to the first embodiment of the present invention. 13. A cross-sectional view corresponding to the cross-sectional view of FIG. 7. 14. A cross-sectional view corresponding to the cross-sectional view of FIG. 8. 15. A cross-sectional view taken along line XV-XV in FIG. 13. 16. A cross-sectional view taken along line XVI-XVI in FIG. 13. Fig. 1 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of Fig. 7. Fig. 2 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of Fig. 8. Fig. 3 is an external perspective view showing a multilayer ceramic electronic component according to a second embodiment of the present invention. Fig. 4 is a front view of the multilayer ceramic electronic component according to the second embodiment of the present invention. Fig. 5 is a plan view of the multilayer ceramic electronic component according to the second embodiment of the present invention.

[0013] A. First Embodiment 1. Multilayer Ceramic Electronic Component A multilayer ceramic electronic component 100 according to an embodiment of the present invention will be described.

[0014] Fig. 1 is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention, Fig. 2 is a front view of the multilayer ceramic electronic component according to an embodiment of the present invention, and Fig. 3 is a plan view of the multilayer ceramic electronic component according to a first embodiment of the present invention.

[0015] As shown in FIGS. 1 to 3, a multilayer ceramic electronic component 100 according to an embodiment of the present invention includes a multilayer ceramic capacitor 10 and a conductor portion 40 .

[0016] (a) Multilayer Ceramic Capacitor A multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0017] Fig. 4 is a perspective view of the multilayer ceramic capacitor according to the first embodiment of the present invention. Fig. 5 is a front view of the multilayer ceramic capacitor according to the first embodiment of the present invention. Fig. 6 is a plan view of the multilayer ceramic capacitor according to the first embodiment of the present invention. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 4. Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 4. Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 7. Fig. 10 is a cross-sectional view taken along line XX in Fig. 7.

[0018] The multilayer ceramic capacitor 10 has a laminate 12 and external electrodes 30. The configuration of each will be described below in the order of the laminate 12 and the external electrodes 30.

[0019] (Laminate) The laminate 12 includes a plurality of stacked dielectric layers 14. The laminate 12 further includes a first main surface 12a and a second main surface 12b facing in a stacking direction x, a first side surface 12c and a second side surface 12d facing in a width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f facing in a length direction z perpendicular to the stacking direction x and the width direction y. The laminate 12 has a rectangular parallelepiped shape. It is preferable that the corners and ridges of the laminate 12 are rounded. The corners refer to the intersections of three adjacent faces of the laminate 12, and the ridges refer to the intersections of two adjacent faces of the laminate 12. Furthermore, irregularities may be formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0020] As shown in Figures 3 to 9, the laminate 12 has an inner layer portion 15a in which a plurality of internal electrode layers 16 are arranged alternately with dielectric layers 14 interposed therebetween, a first outer layer portion 15b1 located on the first main surface 12a side and formed from a plurality of dielectric layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 15a on the first main surface 12a side, and a second outer layer portion 15b2 located on the second main surface 12b side and formed from a plurality of dielectric layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 15a on the second main surface 12b side.

[0021] Here, the plurality of dielectric layers 14 for inner layers constituting the inner layer portion 15a are formed so as to be sandwiched between a first inner electrode layer 16a and a second inner electrode layer 16b, which will be described later.

[0022] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 10 to 1000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the dielectric layers 14 is preferably 0.5 μm to 15 μm.

[0023] The dielectric layer 14 can be formed of, for example, a ceramic dielectric material. Examples of such dielectric materials include dielectric ceramics containing components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3. When the dielectric material is a primary component, it may contain a secondary component, such as a manganese compound, an iron compound, a chromium compound, a cobalt compound, or a nickel compound, in a smaller amount than the primary component, depending on the desired characteristics of the laminate 12.

[0024] Furthermore, the dielectric layer 14 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3. The size of the crystal grains is appropriately designed depending on the thickness of the dielectric layer 14. In this embodiment, the thinner the thickness of the dielectric layer 14, the greater the capacitance of the capacitor, so it is preferable that the crystal grain size be 1 μm or less.

[0025] Furthermore, the dielectric layers 14 for the outer layers constituting the first outer layer portion 15b1 and the second outer layer portion 15b2 are formed from the same dielectric ceramic material as the dielectric layers 14 of the inner layer portion 15a. The dielectric layers 14 of the first outer layer portion 15b1 and the second outer layer portion 15b2 may be formed from a material different from that of the dielectric layers 14 of the inner layer portion 15a. The dielectric layers 14 of the first outer layer portion 15b1 and the second outer layer portion 15b2 may each have a multi-layer structure or a single-layer structure. Furthermore, when the dielectric layers 14 of the first outer layer portion 15b1 and the second outer layer portion 15b2 each have a multi-layer structure, it is preferable that the segregated portions of Si in the dielectric layers 14 of the first outer layer portion 15b1 and the second outer layer portion 15b2 located closest to the first internal electrode layer 16a and the second internal electrode layer 16b are larger than the segregated portions of Si in the other dielectric layers of the first outer layer portion 15b1 and the second outer layer portion 15b2. This improves the bending strength of the multilayer ceramic capacitor 10 from the lamination direction x side.

[0026] The laminate 12 includes side portions (hereinafter referred to as "W gaps") 22a, 22b of the laminate 12 located between the first internal electrode layer 16a and the first side surface 12c and between the first internal electrode layer 16a and the second side surface 12d.

[0027] The laminate 12 also includes ends (hereinafter referred to as "L gaps") 24a, 24b of the laminate 12 located between the second internal electrode layer 16b and the first end face 12e, and between the second internal electrode layer 16b and the second end face 12f.

[0028] (Internal electrode layer) As shown in Figures 7 to 10, the internal electrode layer 16 has a first internal electrode layer 16a exposed at the first end face 12e and the second end face 12f, and a second internal electrode layer 16b exposed at the first side face 12c and the second side face 12d.

[0029] The first internal electrode layer 16a has a first opposing electrode portion 18a that faces the second internal electrode layer 16b, a first extraction electrode portion 20a that is located on one end side of the first internal electrode layer 16a and extends from the first opposing electrode portion 18a to the first end face 12e of the laminate 12, and a second extraction electrode portion 20b that is located on one end side of the first internal electrode layer 16a and extends from the first opposing electrode portion 18a to the second end face 12f of the laminate 12.

[0030] The second internal electrode layer 16b has a second opposing electrode portion 18b opposing the first internal electrode layer 16a, a third extraction electrode portion 20c located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the first side surface 12c of the laminate 12, and a fourth extraction electrode portion 20d located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the second side surface 12d of the laminate 12.

[0031] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 18a may be tapered in plan view, with a slope increasing in either direction.

[0032] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 18b may be tapered in plan view, with a slope increasing in either direction.

[0033] The shapes of the first lead electrode portion 20a and the second lead electrode portion 20b of the first internal electrode layer 16a are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either side.

[0034] The shapes of the third lead electrode portion 20c and the fourth lead electrode portion 20d of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either side.

[0035] The width of the first opposing electrode portion 18a of the first internal electrode layer 16a and the width of the first extraction electrode portion 20a and the second extraction electrode portion 20b of the first internal electrode layer 16a may be formed to be the same width, or one of them may be formed to be narrower in width.

[0036] The width of the second opposing electrode portion 18b of the second internal electrode layer 16b and the width of the third extraction electrode portion 20c and the fourth extraction electrode portion 20d of the second internal electrode layer 16b may be formed to be the same width, or either one may be formed to be narrower in width.

[0037] In this embodiment, the width in the longitudinal direction z of the third extraction electrode portion 20c and the fourth extraction electrode portion 20d of the second internal electrode layer 16b is formed to be narrower than the width in the longitudinal direction z of the second opposing electrode portion 18b of the second internal electrode layer 16b.

[0038] Furthermore, although it is preferable that the first internal electrode layer 16a has a uniform thickness, the thickness of the edge portion of the first internal electrode layer 16a may be thicker than the thickness of the central portion. Increasing the thickness of the edge portion of the first internal electrode layer 16a improves coverage. This shortens the current path and improves ESL characteristics. Furthermore, the thickness of the edge portion of the first internal electrode layer 16a may be thinner than the thickness of the central portion. By making the edge portion thinner, the step corresponding to the thickness of the first internal electrode layer 16a is alleviated, thereby suppressing structural defects.

[0039] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys, but are not limited to these.

[0040] In this embodiment, the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0041] The thickness of each of the first internal electrode layers 16a and the second internal electrode layers 16b is preferably 0.5 μm or more and 1.5 μm or less. The number of stacked first internal electrode layers 16a and second internal electrode layers 16b can be appropriately changed depending on the size, etc. Increasing the number of first internal electrode layers 16a can prevent the DC resistance from increasing. The total number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 10 or more and 1,000 or less.

[0042] The first lead electrode portion 20a and the second lead electrode portion 20b of the first internal electrode layer 16a may be curved. Also, the third lead electrode portion 20c and the fourth lead electrode portion 20d of the second internal electrode layer 16b may be curved. In this case, they may be arranged so as to be curved toward either the first main surface 12a or the second main surface 12b. In this case, by making the mounting surface the curved surface, the current path can be shortened.

[0043] The distance between the first internal electrode layer 16a closest to the first main surface 12a and the first internal electrode layer 16a closest to the second main surface 12b of the first internal electrode layer 16a extended to the first end face 12e and the second end face 12f may be shorter than the distance between the first opposing electrode portion 18a of the first internal electrode layer 16a closest to the first main surface 12a and the first opposing electrode portion 18a of the first internal electrode layer 16a closest to the second main surface 12b.

[0044] Furthermore, the distance between the second internal electrode layer 16b closest to the first main surface 12a and the second internal electrode layer 16b closest to the second main surface 12b among the second internal electrode layers 16b extended to the first side surface 12c and the second side surface 12d may be shorter than the distance between the second opposing electrode portion 18b of the second internal electrode layer 16b closest to the first main surface 12a and the second opposing electrode portion 18b of the second internal electrode layer 16b closest to the second main surface 12b.

[0045] In order to increase the capacitance of the capacitor, it is necessary to increase the area of ​​the internal electrode layers 16, and therefore it is preferable that the LW surface coverage of the internal electrode layers 16 is 90% or more. Here, the LW surface coverage of the internal electrode layers 16 is defined as the ratio of the area inside the edge of the internal electrode layers 16 when viewed from the LW surface of the laminate 12 minus the area of ​​the gap. The higher the LW surface coverage of the internal electrode layers 16, the higher the capacitance of the capacitor. However, even if the LW surface coverage is low, the dielectric layers 14 are bonded to each other via gaps, which increases the interlayer bonding strength and makes delamination less likely to occur.

[0046] (External Electrodes) The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0047] The first external electrode 30a is connected to the first internal electrode layer 16a and is formed on the first end face 12e. The first external electrode 30a is disposed so as to wrap around a part of the first main face 12a and a part of the second main face 12b. Preferably, the first external electrode 30a is disposed so as to wrap around from the first end face 12e to a part of the first side face 12c and a part of the second side face 12d.

[0048] The second external electrode 30b is connected to the first internal electrode layer 16a and is formed on the second end face 12f. The second external electrode 30b is disposed so as to wrap around a part of the first main face 12a and a part of the second main face 12b. Preferably, the second external electrode 30b is disposed so as to wrap around from the second end face 12f to a part of the first side face 12c and a part of the second side face 12d.

[0049] The third external electrode 30c is connected to the second internal electrode layer 16b and formed on the first side surface 12c. Preferably, the third external electrode 30c is disposed on a part of the first main surface 12a and a part of the second main surface 12b. Alternatively, the third external electrode 30c may be disposed on a part of either the first main surface 12a or the second main surface 12b, continuing from the first side surface 12c.

[0050] The fourth external electrode 30d is connected to the second internal electrode layer 16b and formed on the second side surface 12d. Preferably, the fourth external electrode 30d is disposed on a part of the first main surface 12a and a part of the second main surface 12b. Alternatively, the fourth external electrode 30d may be disposed on a part of either the first main surface 12a or the second main surface 12b, continuing from the second side surface 12d.

[0051] The third external electrode 30c and the fourth external electrode 30d may be directly joined together.

[0052] The first external electrode 30a has a first base electrode layer 32a containing a conductive metal disposed on the laminate 12, and a first plating layer 34a disposed so as to cover the first base electrode layer 32a. The second external electrode 30b has a second base electrode layer 32b containing a conductive metal disposed on the laminate 12, and a second plating layer 34b disposed so as to cover the second base electrode layer 32b. The third external electrode 30c has a third base electrode layer 32c containing a conductive metal disposed on the laminate 12, and a third plating layer 34c disposed so as to cover the third base electrode layer 32c. The fourth external electrode 30d has a fourth base electrode layer 32d containing a conductive metal disposed on the laminate 12, and a fourth plating layer 34d disposed so as to cover the fourth base electrode layer 32d.

[0053] The base electrode layer 32 includes a first base electrode layer 32 a, a second base electrode layer 32 b, a third base electrode layer 32 c, and a fourth base electrode layer 32 d. The first base electrode layer 32 a, the second base electrode layer 32 b, the third base electrode layer 32 c, and the fourth base electrode layer 32 d each include at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0054] The baking layer includes a glass component and a metal. The baking layer may be a multi-layered layer.

[0055] The glass component of the baking layer contains at least one element selected from B, Si, Ba, Mg, Al, Li, and the like.

[0056] The metal of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like.

[0057] The baked layer is formed by applying a conductive paste containing glass and metal to the laminate 12 and baking it, and may be baked simultaneously with the internal electrode layer 16 or may be baked after the internal electrode layer 16 has been baked.

[0058] When a baked layer is provided as the first base electrode layer 32a and the second base electrode layer 32b, the thickness of the baked layer at the center of the stacking direction x of the first base electrode layer 32a and the second base electrode layer 32b located on the first end face 12e and the second end face 12f is preferably, for example, 20 μm or more and 50 μm or less.

[0059] Furthermore, when baked layers are provided on the first and second main surfaces 12a, 12b, the first and second side surfaces 12c, 12d as the first and second base electrode layers 32a, 32b, respectively, it is preferable that the thickness of the baked layers at the center in the longitudinal direction z of the first and second base electrode layers 32a, 32b located on the first and second main surfaces 12a, 12b, the first and second side surfaces 12c, 12d is, for example, 5 μm or more and 20 μm or less.

[0060] When a baking layer is provided as the third base electrode layer 32c and the fourth base electrode layer 32d, the thickness of the baking layer at the center in the stacking direction x of the third base electrode layer 32c and the fourth base electrode layer 32d located on the first side surface 12c and the second side surface 12d is preferably, for example, 20 μm or more and 50 μm or less.

[0061] Furthermore, when baked layers are provided on the first principal surface 12a and the second principal surface 12b as the third underlying electrode layer 32c and the fourth underlying electrode layer 32d, the thickness of the baked layer at the center in the width direction y of the third underlying electrode layer 32c and the fourth underlying electrode layer 32d located on the first principal surface 12a and the second principal surface 12b is preferably, for example, 5 μm or more and 20 μm or less.

[0062] Next, a case where the base electrode layer 32 is formed by a conductive resin layer will be described. The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the laminate 12 without providing a baked layer. The conductive resin layer may also completely cover the baked layer, or may cover only a portion of the baked layer. Furthermore, the conductive resin layer may be a multi-layer structure.

[0063] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than, for example, a baked layer made of a plating film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0064] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing these. Alternatively, a metal powder whose surface is coated with Ag can also be used. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. The reason for using Ag-coated metal is that it allows the base metal to be inexpensive while maintaining the above-mentioned properties of Ag.

[0065] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the metals (conductive fillers) contained in the conductive resin layer come into contact with each other, an electrical path is formed inside the conductive resin layer.

[0066] The metal contained in the conductive resin layer may be spherical or flat, but it is preferable to use a mixture of spherical metal powder and flat metal powder. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the metal (conductive filler) contained in the conductive resin layer may be, for example, approximately 0.3 μm or more and 10 μm or less.

[0067] The metal contained in the conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0068] The resin for the conductive resin layer may be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, adhesion, etc.

[0069] The resin contained in the conductive resin layer is preferably contained in an amount of 25 vol % or more and 65 vol % or less with respect to the volume of the entire conductive resin.

[0070] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent for the epoxy resin.

[0071] When conductive resin electrode layers are provided as the first and second base electrode layers 32 a and 32 b, the thickness of the conductive resin electrode layers at the center of the first and second base electrode layers 32 a and 32 b located on the first end face 12 e and the second end face 12 f in the stacking direction x is preferably, for example, approximately 20 μm or more and 70 μm or less.

[0072] Furthermore, when conductive resin electrode layers are provided as the first base electrode layer 32a and the second base electrode layer 32b on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, the thickness of the conductive resin electrode layer at the center in the longitudinal direction z of the first base electrode layer 32a and the second base electrode layer 32b located on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d is preferably, for example, approximately 5 μm or more and 20 μm or less.

[0073] When conductive resin electrode layers are provided as the third and fourth base electrode layers 32c and 32d, the thickness of the conductive resin electrode layers at the center in the stacking direction x of the third and fourth base electrode layers 32c and 32d located on the first and second side surfaces 12c and 12d is preferably, for example, approximately 20 μm or more and 70 μm or less.

[0074] Furthermore, when conductive resin electrode layers are provided on the first principal surface 12a and the second principal surface 12b as the third underlying electrode layer 32c and the fourth underlying electrode layer 32d, the thickness of the conductive resin electrode layer at the center in the width direction y of the third underlying electrode layer 32c and the fourth underlying electrode layer 32d located on the first principal surface 12a and the second principal surface 12b is preferably, for example, approximately 5 μm or more and 20 μm or less.

[0075] In addition, only conductive resin electrode layers may be arranged as the first base electrode layer 32a and the second base electrode layer 32b, and only conductive resin electrode layers may be arranged as the third base electrode layer 32c and the fourth base electrode layer 32d.

[0076] (Plating Layer) The plating layer 34 includes a first plating layer 34a, a second plating layer 34b, a third plating layer 34c, and a fourth plating layer 34d.

[0077] The first plating layer 34a is disposed so as to cover the first base electrode layer 32a. The second plating layer 34b is disposed so as to cover the second base electrode layer 32b. The third plating layer 34c is disposed so as to cover the third base electrode layer 32c. The fourth plating layer 34d is disposed so as to cover the fourth base electrode layer 32d.

[0078] The plating layer 34 contains at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0079] The plating layer 34 may also be formed of multiple layers. The plating layer 34 preferably has a two-layer structure with Ni plating and Sn plating in that order. The Ni plating layer can prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer also improves the wettability of the solder when mounting the multilayer ceramic capacitor 10, allowing for easier mounting. When the plating layer 34 has a three-layer structure, it is preferably Sn plating, Ni plating, and Sn plating from the laminate 12 side.

[0080] The thickness of each plating layer 34 is preferably 1 μm or more and 6 μm or less.

[0081] Any one or each of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d may have a plating layer formed directly on the surface of the laminate 12. That is, the multilayer ceramic capacitor 10 may have a structure including plating layers that are directly and electrically connected to the first internal electrode layers 16a and the second internal electrode layers 16b. In such a case, a catalyst may be disposed on the surface of the laminate 12 as a pretreatment, and then the plating layer may be formed directly.

[0082] The first direct plating layer is disposed on the first end face 12e and is formed to be joined to the first internal electrode layer 16a. The second direct plating layer is disposed on the second end face 12f and is formed to be joined to the first internal electrode layer 16a. The third direct plating layer is disposed on the first side face 12c and is formed to be joined to the second internal electrode layer 16b. The fourth direct plating layer is disposed on the second side face 12d and is formed to be joined to the second internal electrode layer 16b.

[0083] Each of the direct plating layers preferably contains at least one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal.

[0084] For example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the direct plating layer be formed using Cu, which has good bonding properties with Ni.

[0085] When the plating layer 34 is formed directly on the laminate 12, the thickness of each plating layer 34 is preferably 1 μm or more and 15 μm or less.

[0086] When the plating layer 34 is formed directly on the laminate 12, it is preferable that the plating layer 34 does not contain glass. In addition, the metal content per unit volume of the plating layer 34 is preferably 99% by volume or more.

[0087] A case will be described in which the base electrode layer 32 is formed as a thin film layer and the plating layer 34 is formed directly on the thin film layer.

[0088] The first thin film layer disposed on the first main surface 12a is connected to the first direct plating layer disposed around the first end face 12e. The second thin film layer disposed on the first main surface 12a is connected to the second direct plating layer disposed around the second end face 12f. The third thin film layer disposed on the first main surface 12a is connected to the third direct plating layer disposed around the first side face 12c. The fourth thin film layer disposed on the first main surface 12a is connected to the fourth direct plating layer disposed around the second side face 12d.

[0089] Similarly, the first thin film layer disposed on the second main surface 12b is connected to the first direct plating layer disposed around the first end face 12e. The second thin film layer disposed on the second main surface 12b is connected to the second direct plating layer disposed around the second end face 12f. The third thin film layer disposed on the second main surface 12b is connected to the third direct plating layer disposed around the first side face 12c. The fourth thin film layer disposed on the second main surface 12b is connected to the fourth direct plating layer disposed around the second side face 12d.

[0090] The dimension in the length direction z of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 is defined as dimension L. The dimension L is preferably 1.0 mm or more and 3.2 mm or less. The dimension in the stacking direction x of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 is defined as dimension T. The dimension T is preferably 0.3 mm or more and 2.5 mm or less. The dimension in the width direction y of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 is defined as dimension W. The dimension W is preferably 0.5 mm or more and 2.5 mm or less.

[0091] (b) Conductor Portion Next, a description will be given of the conductor portion 40. The conductor portion 40 is electrically connected to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10 via a conductive adhesive 50.

[0092] The conductor portion 40 is configured as, for example, a plate-shaped lead frame and includes a first terminal joint portion 42 a connected to the first external electrode 30 a, a second terminal joint portion 42 b connected to the second external electrode 30 b, and a connecting portion 44 on the first main surface 12 a of the laminate 12, extending from the first terminal joint portion 42 a in a direction connecting the first end face 12 e and the second end face 12 f to the second terminal joint portion 42 b.

[0093] The first terminal joint 42a of the conductor 40 is a portion that is connected to the first external electrode 30a that is disposed on the first end face 12e of the laminate 12. The first terminal joint 42a is formed in a plate shape, and one main surface that faces the first end face 12e of the laminate 12 is connected to the first end face 12e with a conductive adhesive 50. The shape of the first terminal joint 42a is not particularly limited, but is preferably rectangular.

[0094] The second terminal joint portion 42b of the conductor portion 40 is a portion that is connected to the second external electrode 30b that is disposed on the second end face 12f of the laminate 12. The second terminal joint portion 42b is formed in a plate shape, and one main surface that faces the second end face 12f of the laminate 12 is connected to the second end face 12f with a conductive adhesive 50. The shape of the second terminal joint portion 42b is not particularly limited, but is preferably rectangular.

[0095] One end of the connecting portion 44 of the conductor portion 40 is connected to one end of the first terminal joint portion 42a, and the other end is connected to one end of the second terminal joint portion 42b. The connecting portion 42 is disposed at a predetermined distance t from the first main surface 12a of the laminate 12. The distance t, which is the shortest distance between the connecting portion 42 and the laminate 12, is preferably equal to or greater than the maximum thickness in the stacking direction x of the third external electrode 30c and the fourth external electrode 30d disposed on the first main surface 12a. For example, the distance t is preferably equal to or greater than 10 μm. The shape of the connecting portion 44 is not particularly limited, but is preferably rectangular.

[0096] Furthermore, the dimensions in the width direction y of the first terminal joint portion 42 a, the second terminal joint portion 42 b, and the connecting portion 44 that constitute the conductor portion 40 are preferably approximately the same as the maximum dimension in the width direction y of the multilayer ceramic capacitor 10. Here, "approximately the same" means 0.95 to 1.05 times the maximum dimension in the width direction y of the multilayer ceramic capacitor 10. This has the effect of further reducing the resistance of the conductor portion 40, which already has a low DC resistance, and allowing a large current to flow.

[0097] Furthermore, it is preferable that the thickness of each of the first terminal bonding portion 42a, the second terminal bonding portion 42b, and the connecting portion 44 constituting the conductor portion 40 is 0.1 mm or less, which has the effect of facilitating processing of the conductor portion 40, which is a plate-shaped lead frame, making it easier to ensure the shape, and further enabling the overall dimensions to be reduced.

[0098] Each of the first terminal joint portion 42a, the second terminal joint portion 42b, and the linking portion 44 that constitute the conductor portion 40 preferably has a terminal body and a plating film formed on the surface of the terminal body.

[0099] The terminal body is preferably made of Ni, Fe, Cu, Ag, Cr, or an alloy containing one or more of these metals as a main component. Specifically, the base metal of the terminal body may be, for example, an Fe-42Ni alloy, an Fe-18Cr alloy, or a Cu-8Sn alloy.

[0100] The plating film may include, for example, a lower-layer plating film and an upper-layer plating film. The lower-layer plating film is formed on the surface of the terminal body, and the upper-layer plating film is formed on the surface of the lower-layer plating film. Note that each of the lower-layer plating film and the upper-layer plating film may be composed of multiple plating layers.

[0101] The lower layer plating film is preferably made of Ni, Fe, Cu, Ag, Cr, or an alloy containing one or more of these metals as a main component. More preferably, the lower layer plating film is made of Ni, Fe, Cr, or an alloy containing one or more of these metals as a main component. The thickness of the lower layer plating film is preferably about 0.2 μm or more and 5.0 μm or less.

[0102] The upper layer plating film is preferably made of Sn, Ag, Au, or an alloy containing one or more of these metals as a primary component. More preferably, the upper layer plating film is made of Sn or an alloy containing Sn as a primary component. By forming the upper layer plating film from Sn or an alloy containing Sn as a primary component, the solderability between the first terminal bonding portion 42 a, the second terminal bonding portion 42 b, and the connecting portion 44 and the external electrodes can be improved. The thickness of the upper layer plating film is preferably approximately 1.0 μm or more and 5.0 μm or less.

[0103] In addition, the heat resistance of the external electrode can be improved by forming each of the terminal body and the lower layer plating film from high-melting point Ni, Fe, Cr or an alloy containing one or more of these metals as its main component.

[0104] The conductive adhesive 50 may be, for example, a high heat resistant epoxy adhesive or solder.

[0105] As described above, the conductive adhesive 50 is disposed so as to electrically connect the first external electrode 30a of the multilayer ceramic capacitor 10 to the first terminal joint 42a of the conductor portion 40. The conductive adhesive 50 is also disposed so as to electrically connect the second external electrode 30b of the multilayer ceramic capacitor 10 to the second terminal joint 42b of the conductor portion 40. This allows a direct current to flow through the conductor portion 40, reducing the current flowing through the multilayer ceramic capacitor 10 and suppressing a temperature rise.

[0106] The DC resistance RdcA of the conductor portion 40 is smaller than the DC resistance RdcB of the multilayer ceramic capacitor 10. In other words, RdcA<RdcB.

[0107] The DC resistance RdcA of the conductor portion 40 is smaller than the DC resistance RdcB of the multilayer ceramic capacitor 10, so that DC current flows preferentially to the conductor portion 40, reducing the current flowing to the multilayer ceramic capacitor 10 and suppressing temperature rise. In particular, since the conductor portion 40 is formed of a plate-shaped lead frame, the DC resistance RdcA of the conductor portion 40 is lower than the DC resistance RdcB of the multilayer ceramic capacitor 10, so that DC current can flow to the conductor portion 40 side formed of the plate-shaped lead frame, thereby further suppressing heat generation in the multilayer ceramic capacitor 10.

[0108] On the other hand, if the DC resistance RdcA of the conductor portion 40 becomes larger than the DC resistance RdcB of the multilayer ceramic capacitor 10, current will flow more through the multilayer ceramic capacitor 10 than through the conductor portion 40, making it difficult to achieve the effect of large current resistance.

[0109] The conductor portion 40 is not electrically connected to the third external electrode 30c and the fourth external electrode 30d. By arranging the conductor portion 40 so that it is electrically connected only to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10, a direct current flows through the conductor portion 40, reducing the current flowing through the multilayer ceramic capacitor 10 and suppressing a temperature rise.

[0110] The DC resistance values ​​of the conductor portion 40 and the multilayer ceramic capacitor 10 are measured after removing the conductive adhesive 50 that bonds them together, and then the DC resistance values ​​are compared. The DC resistance values ​​of the conductor portion 40 and the multilayer ceramic capacitor 10 are measured using a four-terminal method with a current of 100 mA applied, in accordance with JIS C2139. The locations where the terminals are applied are not limited, and Rdc may be measured at two points: the tip of the conductor portion 40 and the center of the multilayer ceramic capacitor 10 in the stacking direction x.

[0111] In the multilayer ceramic electronic component 100 shown in FIG. 1 , the DC resistance RdcA of the conductor portion 40 connected to the multilayer ceramic capacitor 10 is smaller than the DC resistance RdcB of the multilayer ceramic capacitor 10. This allows DC current to flow through the conductor portion and AC current to escape to the multilayer ceramic capacitor 10. More specifically, because DC current tends to flow toward a portion with lower DC resistance, it tends to flow toward a conductor portion with lower DC resistance than the multilayer ceramic capacitor 10. On the other hand, because AC current tends to flow toward a portion with lower impedance, it tends to flow toward the multilayer ceramic capacitor 10 with lower impedance. This configuration prevents the capacitance and DC resistance of the multilayer ceramic capacitor 10 from increasing. Furthermore, simply attaching the conductor portion 40 to an existing multilayer ceramic capacitor 10 allows it to handle large currents without having to design a new internal structure for each individual capacitance of the multilayer ceramic capacitor 10. This also enhances the flexibility of the product lineup.

[0112] 2. Mounting Structure of Multilayer Ceramic Electronic Component Next, a mounting structure 500 for the multilayer ceramic electronic component 100 according to the embodiment of the present invention will be described.

[0113] 11 and 12 are cross-sectional views in the stacking direction and width direction, respectively, showing the mounting structure of a multilayer ceramic electronic component according to an embodiment of the present invention.

[0114] 11 and 12 , a mounting structure 500 for a multilayer ceramic electronic component according to this embodiment includes a multilayer ceramic electronic component 100 according to this embodiment and a mounting substrate 60. The mounting substrate 60 includes a substrate core material 62 and connecting conductors (conductor lands) 64.

[0115] The core material 62 of the substrate is, for example, a substrate made of a material in which a base material made of a mixture of glass cloth and nonwoven glass cloth is impregnated with epoxy resin or polyimide resin, or a ceramic substrate manufactured by baking a sheet made of a mixture of ceramic and glass. The core material 62 of the substrate may be a single-layer substrate or a substrate made of multiple laminated layers. The thickness of the core material 62 of the substrate is not particularly limited, but is preferably, for example, 200 μm to 800 μm.

[0116] One main surface of the core material 62 of the substrate is provided with conductor lands 64 and constitutes a substrate-side mounting surface 62 a on which the multilayer ceramic electronic component 100 is mounted.

[0117] The conductor lands 64 include a first conductor land 64a, a second conductor land 64b, a third conductor land 64c, and a fourth conductor land 64d.

[0118] The first conductor land 64a is a portion that is electrically connected and mechanically joined to the first external electrode 30a of the multilayer ceramic capacitor 10 by the bonding material 66. The second conductor land 64b is a portion that is electrically connected and mechanically joined to the second external electrode 30b of the multilayer ceramic capacitor 10 by the bonding material 66. The third conductor land 64c is a portion that is electrically connected and mechanically joined to the third external electrode 30c of the multilayer ceramic capacitor 10 by the bonding material 66. The fourth conductor land 64d is a portion that is electrically connected and mechanically joined to the fourth external electrode 30d of the multilayer ceramic capacitor 10 by the bonding material 66.

[0119] The conductor land 64 may be provided on the main surface of the core material 62 of the substrate opposite to the substrate-side mounting surface 62a.

[0120] The material of the conductor lands 64 is not particularly limited, but metals such as Cu, Au, Pd, and Pt can be used. The thickness of the conductor lands 64, i.e., the dimension in the stacking direction x, is not particularly limited, but is preferably 20 μm or more and 200 μm or less, for example. The bonding material 66 can be, for example, a high-heat-resistant epoxy adhesive or solder.

[0121] In the above description, the mounting substrate 60 corresponds to the mounting substrate of the present invention. The core material 62 of the substrate corresponds to the core material of the substrate of the present invention. The substrate-side mounting surface 62a corresponds to the mounting surface of the present invention. The multiple conductor lands 64 correspond to the multiple connecting conductors of the present invention. However, the connecting conductors of the present invention are not limited to so-called lands or other conductors that are provided between the multilayer ceramic capacitor 10 and the mounting substrate 60 and can electrically connect the two, and are not limited by other uses, functions, shapes, names, etc.

[0122] In the mounting structure 500 of the multilayer ceramic electronic component shown in FIGS. 11 and 12 , the multilayer ceramic electronic component 100 is preferably mounted so that the conductor portion 40 of the multilayer ceramic electronic component 100 is disposed facing away from the mounting substrate 60. That is, the conductor portion 40 of the multilayer ceramic electronic component 100 is preferably disposed on the first main surface side (non-mounting surface side) of the multilayer ceramic capacitor 10, and the multilayer ceramic capacitor 10 of the multilayer ceramic electronic component 100 is preferably mounted on the mounting substrate 60 side. Mounting in this manner eliminates the need to increase the distance between the multilayer ceramic capacitor 10 and the mounting substrate 60, making it easier to achieve a low ESL effect. Furthermore, mounting can be performed without affecting the mounting of the multilayer ceramic electronic component 100 to the mounting substrate.

[0123] 3. Method for Manufacturing the Multilayer Ceramic Electronic Component Next, a method for manufacturing the multilayer ceramic capacitor 10 of the multilayer ceramic electronic component 100 according to the embodiment of the present invention will be described.

[0124] (a) Manufacturing Method of Multilayer Ceramic Capacitor First, a dielectric sheet for the dielectric layers and a conductive paste for the internal electrode layers are prepared. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder and a solvent. Known binders and solvents can be used.

[0125] Next, a conductive paste for the internal electrode layers is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing. This prepares a dielectric sheet on which the patterns of the first internal electrode layer 16a and the second internal electrode layer 16b are formed. More specifically, for example, a screen plate for printing the first internal electrode layer 16a and a screen plate for printing the second internal electrode layer 16b are separately prepared, and the internal electrode layers 16 of this embodiment can be printed using a printer capable of printing the two types of screen plates separately. Here, a sheet on which the first internal electrode layer 16a is printed and a sheet on which the second internal electrode layer 16b is printed are stacked to obtain a desired structure, thereby forming a portion that becomes the internal layer portion 15a. In this embodiment, the internal electrode layer 16 is printed by screen printing.

[0126] Next, a predetermined number of dielectric sheets not printed with an internal electrode layer pattern are stacked to form the portion that will become the first outer layer portion 15b1 on the first main surface 12a side. After that, the portion that will become the internal layer portion 15a prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode layer pattern are stacked on top of this portion that will become the internal layer portion 15a to form the portion that will become the second outer layer portion 15b2 on the second main surface 12b side. In this way, a laminated sheet is produced.

[0127] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0128] The laminated block is then cut to a predetermined size to produce laminated chips, which may have rounded corners and ridges by barrel polishing or the like.

[0129] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the dielectric layers 14 and the internal electrode layers 16, but is preferably 900°C or higher and 1400°C or lower.

[0130] A third base electrode layer 32c of the third external electrode 30c and a fourth base electrode layer 32d of the fourth external electrode 30d are formed on the first side surface 12c and the second side surface 12d of the laminate 12 obtained by firing.

[0131] When a baked layer is formed as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied, and then a baking process is performed to form the base electrode layer 32. The baking temperature at this time is preferably 700° C. or higher and 900° C. or lower. In this embodiment, the base electrode layer 32 is formed as a baked layer.

[0132] Various methods can be used to form the baked layers as the third and fourth base electrode layers 32c and 32d. For example, the third and fourth base electrode layers 32c and 32d can be formed by extruding a conductive paste through a slit. In this method, by increasing the amount of conductive paste extruded, the third and fourth base electrode layers 32c and 32d can be formed not only on the first and second side faces 12c and 12d, but also on a portion of the first and second principal faces 12a and 12b.

[0133] Alternatively, the electrodes may be formed by a roller transfer method. In the case of the roller transfer method, when the third and fourth base electrode layers 32c and 32d are formed not only on the first and second side faces 12c and 12d but also on a part of the first and second main faces 12a and 12b, the third and fourth base electrode layers 32c and 32d can be formed on a part of the first and second main faces 12a and 12b by increasing the pressing pressure during the roller transfer.

[0134] Next, the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the fired laminate 12. As with the third and fourth base electrode layers 32c and 32d, when baking layers are formed as the first and second base electrode layers 32a and 32b, a conductive paste containing a glass component and a metal component is applied, followed by baking to form the first and second base electrode layers 32a and 32b. The baking temperature is preferably 700°C or higher and 900°C or lower.

[0135] Regarding the baking process, the first base electrode layer 32a of the first external electrode 30a, the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d may be baked simultaneously, or the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d on the side surface side may be baked separately from the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b on the end surface side.

[0136] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed directly on the laminate 12 without forming a baked layer.

[0137] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate 12, and then performing a heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0138] The conductive resin paste can be applied by, for example, a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method, similar to the method of forming the base electrode layer 32 as a baked layer.

[0139] When the base electrode layer 32 is formed as a thin film layer, masking or the like is performed, and the base electrode layer 32 can be formed in the desired location by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0140] Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 32. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0141] In this manner, the multilayer ceramic capacitor 10 shown in FIG. 1 can be manufactured.

[0142] (b) Manufacturing Method of Multilayer Ceramic Electronic Component Next, the conductor portion 40 is attached to the multilayer ceramic capacitor 10. First, the conductor portion 40 is prepared. The conductor portion 40 is made of a plate-shaped lead frame.

[0143] Next, the terminal joint portions 42a and 42b of the conductor portion 40 are aligned with the first transfer jig so as to face up, and are held by suction.

[0144] Next, at the position where the multilayer ceramic capacitor 10 will be mounted on the second transferring jig, a conductive adhesive 50, such as terminal joining solder, is applied in advance by screen printing or the like. Next, the multilayer ceramic capacitors 10 are aligned on the second transferring jig. Then, the first transferring jig is inverted with the prepared plurality of conductors 40 held by suction.

[0145] Next, the conductor portion 40 held by the first feeding jig is placed over the multilayer ceramic capacitors 10 aligned on the second feeding jig. Then, the multilayer ceramic capacitors 10 aligned on the second feeding jig are subjected to a reflow process with the conductor portion 40 held by the first feeding jig placed over them. When attaching the conductor portion 40, the reflow temperature for soldering using the conductive adhesive 50 is preferably set to 270°C or higher and 290°C or lower, and the heat is applied for 30 seconds or longer. During the reflow process, the conductive adhesive 50 is drawn up by capillary action and fills the gaps between the first external electrode 30a and the first terminal joint 42a of the conductor portion 40 and between the second external electrode and the second terminal joint 42b of the conductor portion 40. As a result, the first external electrode 30 a and the first terminal joint portion 42 a and the second external electrode 30 b and the second terminal joint portion 42 b are connected via the conductive adhesive 50 .

[0146] The multilayer ceramic capacitor 10 and the conductor portion 40 may be joined by welding.

[0147] Then, the multilayer ceramic electronic component 100 is removed from the second transferring jig, and the desired multilayer ceramic electronic component 100 is obtained.

[0148] In this manner, the multilayer ceramic electronic component 100 shown in FIG. 1 is manufactured.

[0149] 4. Modifications of the Multilayer Ceramic Capacitor According to the Present Embodiment Hereinafter, modifications (first modification and second modification) of the multilayer ceramic capacitor in the multilayer ceramic electronic component according to the first embodiment will be described. In addition, in each of these modifications, components corresponding to those in the above-described embodiment will be assigned the same reference numerals, and detailed description thereof will be omitted.

[0150] (1) First Modification A multilayer ceramic capacitor 10A according to a first modification of this embodiment differs from the multilayer ceramic capacitor 10 according to this embodiment only in the structure of the laminate 12A of the multilayer ceramic capacitor 10A. Therefore, the same parts as those in the multilayer ceramic capacitor 10 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0151] Fig. 13 is a cross-sectional view showing a first modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of Fig. 7. Fig. 14 is a cross-sectional view showing a first modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of Fig. 8. Fig. 15 is a cross-sectional view taken along line XV-XV in Fig. 13. Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 13.

[0152] The multilayer ceramic capacitor 10A includes a laminate 12A and external electrodes 30.

[0153] The laminate 12A includes a plurality of stacked dielectric layers 14. The laminate 12A further includes a first main surface 12a and a second main surface 12b facing in a stacking direction x, a first side surface 12c and a second side surface 12d facing in a width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f facing in a length direction z perpendicular to the stacking direction x and the width direction y.

[0154] At the ends (L gap) 24a, 24b of the laminate 12A, a first dummy electrode 25a is arranged so as to be exposed at the first end face 12e, and a second dummy electrode 25b is arranged so as to be exposed at the second end face 12f.

[0155] The first dummy electrode 25a and the second dummy electrode 25b are preferably arranged on the same plane as the second internal electrode layer 16b and have the same thickness as the second internal electrode layer 16b.

[0156] The current path can be shortened by reducing the coverage of the first dummy electrode 25a and the second dummy electrode 25b.

[0157] The first dummy electrode 25a and the second dummy electrode 25b may be disposed on the first outer layer portion 15b1 and the second outer layer portion 15b2. In this case, they are preferably disposed on portions corresponding to positions obtained by translating the ends (L gaps) 24a and 24b of the laminate 212 in the stacking direction x. By disposing them in this manner, when the plating layer 34 is provided without providing the base electrode layer 32, the plating layer 34 can be easily formed.

[0158] In addition, when the first dummy electrode 25a and the second dummy electrode 25b are arranged on the same plane as the second internal electrode layer 16b, the first dummy electrode 25a and the second dummy electrode 25b can be arranged on the same plane as the second internal electrode layer 16b by printing the first dummy electrode 25a and the second dummy electrode 25b together with the second internal electrode layer 16b when printing the second internal electrode layer 16b.

[0159] In addition, a third dummy electrode 25c may be arranged on the sides (W gap) 22a, 22b of the laminate 12A so as to be exposed on the first side surface 12c, and a fourth dummy electrode 25d may be arranged so as to be exposed on the second side surface 12d.

[0160] The third dummy electrode 25c and the fourth dummy electrode 25d are preferably arranged on the same plane as the first internal electrode layer 16a and have the same thickness as the first internal electrode layer 16a.

[0161] The current path can be shortened by reducing the coverage of the third dummy electrode 25c and the fourth dummy electrode 25d.

[0162] The third dummy electrode 25c and the fourth dummy electrode 25d may be disposed on the first outer layer portion 15b1 and the second outer layer portion 15b2. In this case, they are preferably disposed on portions corresponding to positions obtained by translating the side portions (W gaps) 22a and 22b of the laminate 12A in the stacking direction x. By disposing them in this manner, when the plating layer 34 is provided without providing the base electrode layer 32, the plating layer 34 can be easily formed.

[0163] In addition, when the third dummy electrode 25c and the fourth dummy electrode 25d are arranged on the same plane as the first internal electrode layer 16a, the third dummy electrode 25c and the fourth dummy electrode 25d can be arranged on the same plane as the first internal electrode layer 16a by printing the third dummy electrode 25c and the fourth dummy electrode 25d together with the second internal electrode layer 16b when printing the first internal electrode layer 16a.

[0164] In the multilayer ceramic capacitor 10A shown in FIGS. 13 to 16, the first dummy electrode 25a, the second dummy electrode 25b, the third dummy electrode 25c, and the fourth dummy electrode 25d are arranged on the side portions (W gaps) 22a, 22b of the laminate 12A and the end portions (L gaps) 24a, 24b of the laminate 12A, and therefore distortion during pressing can be prevented.

[0165] (2) Second Modification A multilayer ceramic capacitor 10B according to a second modification of this embodiment differs from the multilayer ceramic capacitor 10 according to this embodiment only in the structure of the laminate 12B of the multilayer ceramic capacitor 10B. Therefore, the same parts as those in the multilayer ceramic capacitor 10 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0166] Fig. 17 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of Fig. 7. Fig. 18 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of Fig. 8.

[0167] The laminate 12B includes a plurality of stacked dielectric layers 14. The laminate 12B further includes a first main surface 12a and a second main surface 12b facing in a stacking direction x, a first side surface 12c and a second side surface 12d facing in a width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f facing in a length direction z perpendicular to the stacking direction x and the width direction y.

[0168] The laminate 12B has an inner layer portion 15a, and a first outer layer portion 15b1 and a second outer layer portion 15b2 arranged so as to sandwich the inner layer portion 15a in the stacking direction x.

[0169] The dielectric layer 14 of the inner layer portion 15a may be disposed so as to be sandwiched between the first inner electrode layers 16a. In this case, the first inner electrode layers 16a and the first inner electrode layers 16a are disposed continuously with the dielectric layer 14 of the inner layer portion 15a interposed therebetween.

[0170] The dielectric layer 14 of the inner layer portion 15a may be disposed so as to be sandwiched between the second internal electrode layers 16b. In this case, the second internal electrode layers 16b are disposed continuously via the dielectric layer 14 of the inner layer portion 15a. The dielectric layer 14 of the inner layer portion 15a is composed of dielectric ceramic particles having a perovskite structure, with a perovskite-type compound containing, for example, Ba and Ti as the main component. At least one of Si, Mg, Ba, and Mn may be added as an additive to these main components. The additive is present between the ceramic particles.

[0171] The inner layer portion 15a of the laminate 12B has a capacitance forming portion 26 where the first internal electrode layer 16a and the second internal electrode layer 16b face each other via the dielectric layer 14 to form a capacitance, and an internal electrode laminate portion 28 which is a region where two or more first internal electrode layers 16a are continuously laminated. The multilayer ceramic capacitor 10B exhibits capacitor characteristics due to this capacitance forming portion 26.

[0172] Moreover, the internal electrode laminate portion 28 is arranged so as to be divided by the second internal electrode layer 16b into a plurality of internal electrode laminate portions 28. This disperses the aggregate of the first internal electrode layers 16a, thereby improving the heat dissipation effect and achieving the effect of suppressing a temperature rise.

[0173] As shown in Figures 20 and 21, in the multilayer ceramic capacitor 10B, the internal electrode laminate portion 28 is divided by two second internal electrode layers 16b, and the internal electrode laminate portion 28 is divided into a first internal electrode laminate portion 28a, a second internal electrode laminate portion 28b, and a third internal electrode laminate portion 28c.

[0174] The second internal electrode layer 16b arranged so as to divide the internal electrode laminated portion 28, which is a region where two or more first internal electrode layers 16a are continuously laminated, may be arranged singly. This makes it possible to laminate more first internal electrode layers 16a, thereby obtaining the effect of reducing DC resistance.

[0175] Furthermore, the second internal electrode layers 16b arranged so as to divide the internal electrode laminate portion 28, which is a region where two or more first internal electrode layers 16a are continuously laminated, may be arranged by continuously laminating two or more layers. This makes it possible to ensure more sufficient connectivity between the second internal electrode layers 16b and the external electrodes 30 even if the number of second internal electrode layers 16b is reduced.

[0176] The second internal electrode layer 16b may be disposed in an internal electrode laminate portion 28, which is a region where two or more first internal electrode layers 16a located on the first main surface 12a side of the laminate 12B are continuously laminated, i.e., between the first internal electrode laminate portion 28a and the first main surface 12a, and in an internal electrode laminate portion 28, which is a region where two or more first internal electrode layers 16a located on the second main surface 12b side of the laminate 12B are continuously laminated, i.e., between the third internal electrode laminate portion 28c and the second main surface 12b. This allows the capacitance forming portion 26 to be formed also in the vicinity of the first outer layer portion 15b1 and the second outer layer portion 15b2, thereby obtaining part of the capacitance, shortening the current path to the mounting board and achieving the effect of low ESL.

[0177] Furthermore, the second internal electrode layer 16b does not have to be disposed in the internal electrode laminate portion 28, which is a region where two or more first internal electrode layers 16a located on the first main surface 12a side of the laminate 12B are continuously laminated, i.e., between the first internal electrode laminate portion 28a and the first main surface 12a, or in the internal electrode laminate portion 28, which is a region where two or more first internal electrode layers 16a located on the second main surface 12b side of the laminate 12B are continuously laminated, i.e., between the third internal electrode laminate portion 28c and the second main surface 12b. This increases the distance from the surface of the laminate 12B to the capacitance forming portion 26 where capacitance is formed, and provides the effect of making it less likely for insulation resistance degradation to occur even if a crack occurs from the surface of the laminate 12B due to an external load.

[0178] The thickness of the dielectric layer 14 adjacent to the second internal electrode layer 16b is preferably greater than the thickness of the dielectric layer 14 sandwiched between the first internal electrode layers 16a, which makes it possible to stack more first internal electrode layers 16a and further increase the effect of reducing DC resistance.

[0179] Furthermore, it is preferable that the thickness of the second internal electrode layer 16b is greater than the thickness of the first internal electrode layer 16a, so that even when the capacitance is further reduced, connectivity between the third lead electrode portion 20c of the second internal electrode layer 16b and the third external electrode 30c arranged on the first side surface 12c can be ensured, and connectivity between the fourth lead electrode portion 20d of the second internal electrode layer 16b and the fourth external electrode 30d arranged on the second side surface 12d can be ensured.

[0180] B. Second Embodiment 1. Multilayer Ceramic Electronic Component Next, a multilayer ceramic electronic component 200 according to a second embodiment of the present invention will be described.

[0181] Fig. 19 is an external perspective view showing a multilayer ceramic electronic component according to a second embodiment of the present invention. Fig. 20 is a front view of the multilayer ceramic electronic component according to the second embodiment of the present invention. Fig. 21 is a plan view of the multilayer ceramic electronic component according to the second embodiment of the present invention. In Figs. 19 to 21, parts that are the same as those in the multilayer ceramic electronic component 100 shown in Fig. 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0182] 19 to 21 are configured by metal terminals, unlike the conductor portions 40. In this case, the metal terminals are preferably made of metal with a circular cross section perpendicular to the longitudinal direction z. For example, if a metal terminal shaped like a rolled metal plate is used, it is easier to process than a metal plate itself, and has the effect of making it easier to connect to the multilayer ceramic capacitor 10.

[0183] Furthermore, if the conductor portion 140 is made of a conductor such as a lead wire, the lead wire itself can be used, which eliminates the need for additional processing and reduces material costs.

[0184] The conductor portion 140 is composed of a first terminal joint portion 142a, one end of which is connected to a first external electrode 30a arranged on the first main surface 12a, a second terminal joint portion 142b, the other end of which is connected to a second external electrode 30b arranged on the first main surface 12a, and a connecting portion 144 that connects the first terminal joint portion 142a and the second terminal joint portion 142b.

[0185] The first terminal joint portion 142a of the conductor portion 140 is a portion that is connected to the first external electrode 30a that is disposed on the first main surface 12e of the laminate 12. The first terminal joint portion 142a is connected to the first main surface 12a by the conductive adhesive 50.

[0186] The second terminal joint portion 142b of the conductor portion 140 is a portion that is connected to the second external electrode 30b disposed on the second main surface 12a of the laminate 12. The second terminal joint portion 142b is connected to the first main surface 12a by the conductive adhesive 50.

[0187] The connecting portion 144 of the conductor portion 140 is not electrically connected to the third external electrode 30c and the fourth external electrode 30d. More specifically, the distance w1 in the width direction y between the conductor portion 140 and the third external electrode 30c is preferably 10 μm or more. Similarly, the distance w2 in the width direction y between the conductor portion 140 and the fourth external electrode 30d is preferably 10 μm or more. This makes it difficult for the first side surface external electrode 30c and the second side surface external electrode 30d to be electrically connected to each other, even when an impact or the like is applied to the multilayer ceramic electronic component 200.

[0188] The connecting portion 144 of the conductor portion 140 may be insulated near the third external electrode 30 c and the fourth external electrode 30 d. Specifically, it is preferable that an insulating portion 146 coated with an insulating resin or the like be disposed in the connecting portion 144 of the conductor portion 140 in the vicinity of the third external electrode 30 c and the fourth external electrode 30 d.

[0189] When a lead wire is used as the material for the conductor portion 140, it is preferable to use, for example, a copper wire such as tough pitch copper or a copper-coated steel wire for the core wire of the lead wire. It is preferable to plate the surface layer of the lead wire with an Sn-based alloy. It is preferable that the diameter of the lead wire is 0.5 mm or more and 0.8 mm or less.

[0190] The DC resistance RdcA of the conductor portion 40 is smaller than the DC resistance RdcB of the multilayer ceramic capacitor 10. In other words, RdcA<RdcB.

[0191] The conductive adhesive 50 for connecting the conductor portion 140 and the external electrode 30 is the same as the conductive adhesive 50 used in the first embodiment.

[0192] The DC resistance values ​​of the conductor portion 140 and the multilayer ceramic capacitor 10 are measured after removing the conductive adhesive 50 that bonds them together, and then the DC resistance values ​​are compared. The DC resistance values ​​of the conductor portion 40 and the multilayer ceramic capacitor 10 are measured using a four-terminal method with a current of 100 mA applied, in accordance with JIS C2139. The locations where the terminals are applied are not limited, and Rdc may be measured at two points: the tip of the conductor portion 140 and the center of the multilayer ceramic capacitor 10 in the stacking direction x.

[0193] The multilayer ceramic capacitor 10 in the multilayer ceramic electronic component 200 according to the second preferred embodiment may be the multilayer ceramic capacitors 10A and 10B shown in the respective modified examples of the multilayer ceramic electronic component 100 according to the first preferred embodiment.

[0194] 19 has the same effects as the multilayer ceramic electronic component 100, and also has the following effect. That is, when the conductor portion 140 uses a metal terminal shaped like a rolled metal plate, it is easier to process than the metal plate itself, and it is easier to connect to the multilayer ceramic capacitor 10. Furthermore, when the conductor portion 140 is formed of a conductor such as a lead wire, the conductor itself can be used, eliminating the need for additional processing and reducing material costs.

[0195] 2. Manufacturing Method of Multilayer Ceramic Electronic Component The manufacturing method of the multilayer ceramic capacitor 10 according to the second embodiment is the same as that of the multilayer ceramic capacitor 10 according to the first embodiment, and therefore a description thereof will be omitted.

[0196] The conductor portion 140 is attached to the multilayer ceramic capacitor 10 manufactured by the same method as the multilayer ceramic capacitor according to the first embodiment.

[0197] First, the conductor portion 140 is prepared. For example, a conductor such as a lead wire is prepared as a metal terminal for the conductor portion 140. Then, the first terminal joint portion 142a of the conductor portion 140 is connected to the first external electrode 30a by soldering or welding, and the second terminal joint portion 142b of the conductor portion 140 is connected to the second external electrode 30b by soldering or welding.

[0198] In this manner, the multilayer ceramic electronic device 200 shown in FIG. 19 is manufactured.

[0199] As described above, the embodiments of the present invention have been disclosed in the above description, but the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0200] 100, 200 Multilayer ceramic electronic component 10, 10A, 10B Multilayer ceramic capacitor 500 Mounting structure of multilayer ceramic electronic component 12 Laminate 12a First main surface 12b Second main surface 12c First side surface 12d Second side surface 12e First end surface 12f Second end surface 14 Dielectric layer 15a Inner layer portion 15b1 First outer layer portion 15b2 Second outer layer portion 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18a First opposing electrode portion 18b Second opposing electrode portion 20a First lead electrode portion 20b Second lead electrode portion 20c Third lead electrode portion 20d Fourth lead electrode portion 22a, 22b Side portions (W gap) 24a, 24b End (L gap) 30 External electrode 30a First external electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 32c Third base electrode layer 32d Fourth base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 34c Third plating layer 34d Fourth plating layer 40, 140 Conductor portion 42a, 142a First terminal joint portion 42b, 142b Second terminal joint portion 44, 144 Linking portion 146 Insulating portion 50 Conductive adhesive 60 Mounting substrate 62 Core material 62a Substrate-side mounting surface 64a, 64b, 64c, 64d Connecting conductor (land) 66 Joining material (solder) 25a First dummy electrode 25b Second dummy electrode 25c Third dummy electrode 25d Fourth dummy electrode 26 Capacitance forming portion 28 Internal electrode laminated portion 28a First internal electrode laminated portion 28b Second internal electrode laminated portion 28c Third internal electrode laminated portion x Stacking direction y Width direction z Length direction T Dimension in stacking direction W Dimension in width direction L Dimension in length direction

Claims

1. A laminate including a plurality of laminated dielectric layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction, the laminate having a first internal electrode layer exposed to the first end surface and the second end surface, and a second internal electrode layer exposed to the first side surface and the second side surface, a first external electrode and a second external electrode connected to the first internal electrode layer, and a third external electrode and a fourth external electrode connected to the second internal electrode layer, and a conductor portion electrically connected to the first external electrode and the second external electrode, but not electrically connected to the third external electrode and the fourth external electrode, a DC resistance RdcA of the conductor portion being smaller than a DC resistance RdcB of the laminated ceramic capacitor, The multilayer ceramic electronic component, wherein the conductor portion is a lead frame.

2. The multilayer ceramic electronic component according to claim 1, wherein the distance in the stacking direction between the conductor portion and the first main surface is longer than a thickness in the stacking direction of the third external electrode and the fourth external electrode arranged on the first main surface.

3. A laminate including a plurality of laminated dielectric layers, the laminate including a first main surface and a second main surface opposed to each other in a lamination direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the lamination direction and the width direction, the laminate having a first internal electrode layer exposed to the first end surface and the second end surface, and a second internal electrode layer exposed to the first side surface and the second side surface, a first external electrode and a second external electrode connected to the first internal electrode layer, and a third external electrode and a fourth external electrode connected to the second internal electrode layer, and a conductor portion electrically connected to the first external electrode and the second external electrode, but not electrically connected to the third external electrode and the fourth external electrode, a DC resistance RdcA of the conductor portion being smaller than a DC resistance RdcB of the laminated ceramic capacitor, The conductor portion is a metal terminal.

4. The monolithic ceramic electronic component according to claim 3, wherein the distance between said conductor portion and said third external electrode or said fourth external electrode is 10 μm or more.

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