Diamond semiconductor device, semiconductor module, and diamond semiconductor device production method

Abstract

Provided is a diamond semiconductor device having a trench portion on the front side thereof, said diamond semiconductor device comprising a diamond layer, a diamond epitaxial layer provided on the diamond layer, a gate insulating film provided above the epitaxial layer, and a gate electrode provided on the gate insulating film, wherein the epitaxial layer has a side wall portion provided on a side wall of the trench portion and a bottom portion provided on the bottom surface of the trench portion, and at least one of the side wall portion and the bottom portion has a thickness of not less than 10 nm but less than 200 nm.

Description

Diamond semiconductor device, semiconductor module, and method for manufacturing diamond semiconductor device

[0001] The present invention relates to a diamond semiconductor device, a semiconductor module, and a method for manufacturing a diamond semiconductor device.

[0002] Patent Document 1 discloses a diamond semiconductor device having a hydrogenated layer.

[0003] It is desirable to improve the electrical properties of diamond semiconductor devices. General disclosure

[0004] In a first aspect of the present invention, there is provided a diamond semiconductor device having a trench portion on its front surface, comprising a diamond layer, a diamond epitaxial layer provided on the diamond layer, a gate insulating film provided above the epitaxial layer, and a gate electrode provided on the gate insulating film. The epitaxial layer may have sidewall portions provided on the sidewalls of the trench portion and a bottom portion provided on the bottom surface of the trench portion. The thickness of at least one of the sidewall portions or the bottom portion may be 10 nm or more and less than 200 nm.

[0005] In a second aspect of the present invention, there is provided a semiconductor module comprising the above-mentioned diamond semiconductor device.

[0006] In a third aspect of the present invention, there is provided a method for manufacturing a diamond semiconductor device having a trench portion on its front surface, comprising the steps of: preparing a diamond layer; forming an epitaxial layer of diamond on the diamond layer, the epitaxial layer having a sidewall portion provided on the sidewall of the trench portion and a bottom portion provided on the bottom surface of the trench portion; forming a gate insulating film above the epitaxial layer; and forming a gate electrode on the gate insulating film. At least one of the sidewall portion or the bottom portion may have a thickness of 10 nm or more and less than 200 nm.

[0007] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0008] 3A shows an example of the configuration of the diamond semiconductor device 100. FIG. 3B shows an example of a top view of the diamond semiconductor device 100. FIG. 3C shows a modified example of the diamond semiconductor device 100. FIG. 3D shows an example of a method for manufacturing the diamond semiconductor device 100 of FIG. 3A. FIG. 3E shows an example of a method for manufacturing the diamond semiconductor device 100 of FIG. 3A. FIG. 3F shows a modified example of the diamond semiconductor device 100. FIG. 3G shows a modified example of the diamond semiconductor device 100. FIG. 3H shows an example of the electrical characteristics of the diamond semiconductor device 100. FIG. 3I shows an overview of the configuration of a semiconductor module 200.

[0009] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0010] 1 shows an example of the configuration of a diamond semiconductor device 100. The diamond semiconductor device 100 includes a diamond layer 15. The diamond layer 15 has a diamond substrate 10 and a doped region 20. The diamond layer 15 has the diamond substrate 10 on the back surface 12 side, and the doped region 20 on the front surface 11 side.

[0011] The diamond substrate 10 is a P-type substrate made of diamond. The doping concentration of the P-type dopant in the diamond substrate 10 is 1×10 １９ cm －３ The diamond substrate 10 may be of the above type. The diamond substrate 10 may contain a P-type dopant. In one example, the P-type dopant is a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The diamond substrate 10 in this example is P+ type, but is not limited to this. The diamond semiconductor device 100 in this example has a gate structure on the front surface 11 side.

[0012] In this specification, one side in a direction parallel to the depth direction of the diamond substrate 10 is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.

[0013] In this specification, the doping concentration of a dopant may refer to the concentration of a dopant that is intentionally introduced. That is, the doping concentration of a dopant does not necessarily include the doping concentration of unintentionally remaining impurities. The dopant may be introduced during epitaxial growth or may be implanted after growth.

[0014] The doped region 20 is provided above the diamond substrate 10. In this example, the doped region 20 contains an N-type dopant. The N-type dopant may be a Group V element such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). In this example, the N-type dopant is nitrogen. The doping concentration of the N-type dopant in the doped region 20 is 1×10 １５ cm －３ That's it, 1 x 10 ２３ cm －３ It may be the following:

[0015] The doped region 20 may be a region epitaxially grown on the diamond substrate 10. The doped region 20 may be formed by microwave plasma chemical vapor deposition (MPCVD). The N-type dopant may be introduced during epitaxial growth or by other methods such as ion implantation after epitaxial growth of an undoped diamond layer.

[0016] The doped region 20 of this example has a first region 21 and a second region 22. By making the doped region 20 a stacked structure, it is possible to alleviate electric field concentration in the diamond semiconductor device 100. The doped region 20 may have a region containing a P-type dopant. The doped region 20 of this example has a P-type doped layer 25.

[0017] The doped layer 25 is provided above the diamond substrate 10. In this example, the doped layer 25 is provided in contact with the upper surface of the diamond substrate 10. The doped layer 25 in this example contains a P-type dopant. The doped layer 25 in this example is P-type, but is not limited to this. The doping concentration of the P-type dopant in the doped layer 25 is 1×10 １６ cm －３ That's it, 1 x 10 ２１ cm －３ The thickness of the doped layer 25 may be less than the thickness of the diamond substrate 10. The thickness of the doped layer 25 may be greater than the thickness of the first region 21 and may be greater than the thickness of the second region 22.

[0018] The doped layer 25 is a P-type region in contact with the epitaxial layer 30. The doped layer 25 may be in contact with the epitaxial layer 30 provided on the sidewall of the trench portion 50, or may be in contact with the epitaxial layer 30 provided on the bottom surface of the trench portion 50. The upper end of the doped layer 25 may be provided above the bottom surface of the trench portion 50. The lower end of the doped layer 25 may be provided below the bottom surface of the trench portion 50.

[0019] The first region 21 is provided above the diamond substrate 10. In this example, the first region 21 is provided in contact with the upper surface of the doped layer 25. In this example, the first region 21 contains an N-type dopant. The doping concentration of the N-type dopant in the first region 21 is 1×10 １５ cm －３ That's it, 1 x 10 １８ cm －３ The thickness of the first region 21 may be thinner than the thickness of the diamond substrate 10 and may be thinner than the thickness of the doped layer 25. The doping concentration of the N-type dopant and the thickness of the first region 21 may be determined taking into consideration the withstand voltage of the diamond semiconductor device 100.

[0020] The second region 22 is provided by stacking with the first region 21. In this example, the second region 22 is provided above the first region 21. In this example, the second region 22 contains an N-type dopant. The doping concentration of the N-type dopant in the second region 22 is different from that in the first region 21. In this example, the doping concentration of the N-type dopant in the second region 22 is higher than that in the first region 21. However, the doping concentration of the N-type dopant in the second region 22 may be lower than that in the first region 21. The doping concentration of the N-type dopant in the second region 22 is 1×10 １８ cm －３ That's it, 1 x 10 ２１ cm －３ The doping concentration of the N-type dopant and the thickness of the second region 22 may be determined in consideration of the withstand voltage of the diamond semiconductor device 100. Furthermore, by setting the doping concentration of the N-type dopant in the second region 22 to a high concentration, it becomes easier to suppress leakage current in the off state.

[0021] The thickness of the second region 22 may be the same as or different from the thickness of the first region 21. The thickness of the second region 22 may be thinner than the thickness of the first region 21. By reducing the thickness of the second region 22, it is possible to reduce the on-resistance while suppressing the leakage current in the off state.

[0022] The epitaxial layer 30 is provided on the diamond layer 15. In this example, the epitaxial layer 30 is provided on the doped region 20, but it may also be provided on the diamond substrate 10. The epitaxial layer 30 is made of diamond. The epitaxial layer 30 may be formed after a trench is formed in the doped region 20 to provide the trench portion 50. The epitaxial layer 30 may be provided on the sidewalls and bottom surface of the trench to provide the trench portion 50. The epitaxial layer 30 contacts the doped layer 25 at the bottom surface of the trench, but may also contact the diamond substrate 10.

[0023] The thickness of the epitaxial layer 30 may be 10 nm or more and less than 200 nm. The thickness of the epitaxial layer 30 may be 10 nm or more and 100 nm or less. The thickness of the epitaxial layer 30 may be 30 nm or more and 100 nm or less. The thickness of the epitaxial layer 30 may particularly refer to the thickness of the sidewall portion 36 or the bottom portion 38 described below. By reducing the thickness of the epitaxial layer 30, the drift length, which is the distance that holes penetrate the epitaxial layer 30 when the diamond semiconductor device 100 is on, is shortened, thereby reducing the drift resistance and making it possible to reduce the on-resistance. Furthermore, by reducing the thickness of the epitaxial layer 30, it is possible to improve the short-circuit resistance, as described below.

[0024] The epitaxial layer 30 may include an N-type dopant. The N-type dopant may be nitrogen. The epitaxial layer 30 may have a lower doping concentration of the N-type dopant than the doped region 20. The doping concentration of the N-type dopant in the epitaxial layer 30 may be 1×10 １６ cm －３ By reducing the doping concentration of the N-type dopant in the epitaxial layer 30, when holes from the termination layer 40 flow into the epitaxial layer 30, pass through the epitaxial layer 30 to the doped layer 25, and then flow to the diamond substrate 10, the potential barrier in the epitaxial layer 30 becomes smaller, thereby reducing the on-resistance.

[0025] The epitaxial layer 30 may contain a P-type dopant. The doping concentration of the P-type dopant in the epitaxial layer 30 may be set to a range that allows the gate to be turned on and off. In one example, the doping concentration of the P-type dopant in the epitaxial layer 30 is 1×10 １５ cm －３ That's it, 1 x 10 １９ cm －３ The following is the result.

[0026] The epitaxial layer 30 of this example has a top portion 34, a sidewall portion 36, and a bottom portion 38. The top portion 34, the sidewall portion 36, and the bottom portion 38 may be formed by the same epitaxial growth process after the formation of the diamond layer 15. However, the top portion 34, the sidewall portion 36, and portions of the bottom portion 38 may be formed by different epitaxial growth processes.

[0027] The upper end 34 is provided on the mesa portion 152 of the diamond layer 15. A portion of the upper end 34 may be provided below the contact region 60. The thickness of the upper end 34 may be 300 nm or more and 1 μm or less. The thickness of the upper end 34 may be the thickness between the second region 22 and the termination layer 40.

[0028] The sidewall portion 36 is provided on the sidewall of the trench portion 50. The sidewall portion 36 is formed by epitaxial growth on the trench sidewall of the trench portion 50. The sidewall portion 36 may be provided on the sidewall of the trench with a constant thickness. The sidewall portion 36 may have different thicknesses at the upper and lower ends of the trench. The thickness of the sidewall portion 36 may be the same as or different from the thickness of the upper end portion 34.

[0029] The bottom portion 38 is provided on the bottom surface of the trench in the trench portion 50. The thickness of the bottom portion 38 may be the same as or different from the thickness of the sidewall portion 36.

[0030] Here, the thickness of the epitaxial layer 30 may be the thickness of a portion where holes penetrate the epitaxial layer 30 during on-operation. The thickness of the epitaxial layer 30 may be the thickness of a region where the layer doped with a P-type dopant (diamond layer 15 in this example) and the epitaxial layer 30 come into contact. The thickness of the region where the diamond layer 15 and the epitaxial layer 30 come into contact may be the thickness of the sidewall portion 36 that comes into contact with the diamond layer 15, or the thickness of the bottom portion 38 that comes into contact with the diamond layer 15.

[0031] The termination layer 40 is provided on the epitaxial layer 30. In this example, the termination layer 40 is provided between the epitaxial layer 30 and the gate insulating film 52. The termination layer 40 may be a layer that induces a two-dimensional hole gas (2DHG) in the epitaxial layer 30. The termination layer 40 may be a layer that has almost no conductivity when no gate voltage is applied, in order to achieve normally-off characteristics. The termination layer 40 may be a hydrogen-terminated layer, a silicon oxide-terminated layer, or may include both a hydrogen-terminated region and a silicon oxide-terminated region. The termination layer 40 may be hydrogen-terminated by hydrogen radical irradiation, or silicon oxide-terminated by a reduction reaction of silicon dioxide and diamond in a high-temperature atmosphere.

[0032] The termination layer 40 includes a C-H bond, a C-O bond, a C-Si bond, a C-Si-O bond, a C-F bond, a C-OH bond, a C-N bond, or a C-NH bond. ２ The termination layer 40 may include at least one of the following bonds. The termination layer 40 may have the same bonds throughout the entire region of the termination layer 40, or different bonds in different regions. The termination layer 40 may have the same bonds over the entire surface between the epitaxial layer 30 and the gate insulating film 52. The termination layer 40 may have C—H bonds over the entire surface between the epitaxial layer 30 and the gate insulating film 52.

[0033] The gate insulating film 52 is provided on the front surface 11 side of the diamond layer 15. The gate insulating film 52 may be provided above the epitaxial layer 30, or may be provided on the termination layer 40. The gate insulating film 52 may be provided on the sidewalls and bottom surface of the trench in the gate trench portion 50. The thickness of the gate insulating film 52 may be 50 nm or more and 200 nm or less. The thickness of the gate insulating film 52 is, for example, 100 nm.

[0034] The material of the gate insulating film 52 is aluminum oxide (Al ２ O ３ The composition of aluminum oxide does not necessarily have to be Al:O=2:3. The material of the gate insulating film 52 may be silicon oxide (SiO ２The gate insulating film 52 may be a single layer or may have a laminated structure in which different materials are laminated. The gate insulating film 52 in this example is a single layer of Al formed by atomic layer deposition (ALD). ２ O ３ is.

[0035] The trench portion 50 is provided so as to extend in the depth direction of the diamond layer 15. The trench portion 50 includes a trench, a gate insulating film 52, and a gate electrode 110, and may function as a gate trench portion. The trench portion 50 may include an epitaxial layer 30 and a termination layer 40 provided in the trench. The trench portion 50 may be provided so as to extend from the upper surface of the doped region 20 to the doped layer 25. The lower end of the trench portion 50 in this example terminates within the doped layer 25. However, the lower end of the trench portion 50 may be provided so as to extend to the diamond substrate 10.

[0036] The contact region 60 is provided above the epitaxial layer 30. The contact region 60 may be provided in contact with the source electrode 120. The contact region 60 may contain a P-type dopant. The P-type dopant may be a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The P-type dopant may be introduced during epitaxial growth, or may be introduced by other methods such as ion implantation after epitaxial growth of the undoped diamond layer. The thickness of the contact region 60 may be thicker than the thickness of the epitaxial layer 30. The thickness of the contact region 60 may be thinner than the thickness of the epitaxial layer 30.

[0037] The gate electrode 110 is provided above the diamond layer 15. In this example, the gate electrode 110 is provided on the gate insulating film 52. The gate electrode 110 may be provided on the sidewalls and bottom surface of the trench in the trench portion 50. The gate electrode 110 may also be provided outside the trench portion 50. That is, the gate electrode 110 may be provided above the mesa portion 152. The gate electrode 110 may contain aluminum (Al). The gate electrode 110 may be provided in a region inside the region where the gate insulating film 52 is provided, as viewed from above. That is, the gate electrode 110 may be provided so as to overlap the gate insulating film 52, as viewed from above.

[0038] The source electrode 120 is provided above the diamond layer 15. The source electrode 120 may be provided on the front surface 11 side of the diamond layer 15. The source electrode 120 may be provided on the contact region 60. The source electrode 120 may be provided in the same region as the contact region 60 when viewed from above, or may be provided inside the contact region 60. The source electrode 120 may be a laminated film formed by laminating titanium (Ti) and gold (Au). The source electrode 120 may be a laminated film formed by laminating titanium (Ti), platinum (Pt), and gold (Au). A source voltage may be applied to the source electrode 120 provided on the front surface 11 side of the diamond layer 15.

[0039] The drain electrode 130 is provided in contact with the diamond substrate 10. The drain electrode 130 is provided on the rear surface 12 side of the diamond layer 15. The drain electrode 130 may be provided on the entire rear surface 12, or on a part of the rear surface 12. The drain electrode 130 may be a laminated film formed by laminating titanium (Ti) and gold (Au). The drain electrode 130 may be a laminated film formed by laminating titanium (Ti), platinum (Pt), and gold (Au). The drain electrode 130 is provided in contact with the rear surface 12 of the diamond substrate 10. A drain-source voltage may be applied to the drain electrode 130 provided on the rear surface 12 side of the diamond layer 15.

[0040] The diamond semiconductor device 100 of this example has a gate electrode 110 and a source electrode 120 on the front surface 11 side of the diamond layer 15, and a drain electrode 130 on the back surface 12 side of the diamond layer 15. When the diamond semiconductor device 100 is turned on, a current flows from the source electrode 120 to the contact region 60 and the termination layer 40 in this order, and holes pass through the epitaxial layer 30 and move into the diamond substrate 10, causing a current to flow to the drain electrode 130.

[0041] The diamond semiconductor device 100 of this example can reduce the on-resistance by adjusting the thickness of the epitaxial layer 30 to lower the resistance when holes penetrate the epitaxial layer 30. Furthermore, the diamond semiconductor device 100 of this example can obtain an IV waveform with a saturated region by adjusting the thickness of the epitaxial layer 30, and can improve the short-circuit withstand capability.

[0042] In this example, the case where the diamond semiconductor device 100 is a P-type channel field effect transistor has been described, but the diamond semiconductor device 100 may be an N-type channel field effect transistor. When the diamond semiconductor device 100 functions as an N-type channel field effect transistor, the P-type dopant may be replaced with an N-type dopant, and the N-type dopant may be replaced with a P-type dopant.

[0043] 2 shows an example of a top view of the diamond semiconductor device 100. A gate electrode 110 and a source electrode 120 are provided on the top surface of the diamond semiconductor device 100, but a drain electrode 130 is not provided. The drain electrode 130 is provided on the bottom surface of the diamond semiconductor device 100. The gate electrode 110 and the source electrode 120 may have pads for connection to the outside of the diamond semiconductor device 100. A trench portion 50 is provided between opposing portions of the source electrode 120. Note that although the diamond semiconductor device 100 in this example has one trench portion 50, it may also be an integrated device having a plurality of trench portions 50.

[0044] Figure 3A shows a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example differs from the diamond semiconductor device 100 of Figure 1 in the structure of the epitaxial layer 30. In this example, differences from the diamond semiconductor device 100 of Figure 1 will be particularly described. The upper end portion 34 of this example includes a first upper end portion 341 and a second upper end portion 342.

[0045] The first upper end 341 is provided above the doped region 20. In this example, the first upper end 341 is provided on the second region 22. The first upper end 341 may be formed continuously with the doped region 20 by epitaxial growth. The first upper end 341 may have an N-type dopant or a P-type dopant. The first upper end 341 may have the same doping concentration as other regions of the epitaxial layer 30. If the first upper end 341 includes an N-type dopant, the doping concentration of the N-type dopant at the first upper end 341 may be less than the doping concentration of the N-type dopant at the doped region 20.

[0046] The second top end 342 is provided on the first top end 341. The second top end 342, like the sidewall portion 36 and the bottom portion 38, may be formed in a regrowth step after the formation of the diamond layer 15. The second top end 342 may have an N-type dopant or a P-type dopant. The second top end 342 may have the same doping concentration as the sidewall portion 36 or the bottom portion 38. The second top end 342 may have the same doping concentration as the first top end 341.

[0047] The thickness of the upper end portion 34 may be greater than the thickness of at least one of the sidewall portion 36 or the bottom portion 38. In this example, the thickness of the upper end portion 34 is the sum of the thickness of the first upper end portion 341 and the thickness of the second upper end portion 342. The thickness of the sidewall portion 36 may be 10 nm or more and less than 200 nm, 10 nm or more and 100 nm or less, or 30 nm or more and 100 nm or less. The thickness of the bottom portion 38 may be 10 nm or more and less than 200 nm, 10 nm or more and 100 nm or less, or 30 nm or more and 100 nm or less. The thickness of the upper end portion 34 may be 10 nm or more and 1 μm or less. In this example, the upper end portion 34 has a thickness greater than the thickness of at least one of the sidewall portion 36 or the bottom portion 38 by stacking the first upper end portion 341 and the second upper end portion 342.

[0048] In the diamond semiconductor device 100 of this example, the on-resistance of the termination layer 40 on the upper end 34 can be reduced by making the upper end 34 thicker than the region other than the upper end 34 of the epitaxial layer 30.

[0049] Fig. 3B shows an example of a method for manufacturing the diamond semiconductor device 100 of Fig. 3A. In step S300, a P-type diamond substrate 10 is prepared.

[0050] In step S302, a doped region 20 containing an N-type dopant is formed above the diamond substrate 10. In this example, the doped region 20 is formed by epitaxial growth on the diamond substrate 10. In this example, the doped layer 25 is formed by introducing a P-type dopant during epitaxial growth. In this example, the first region 21 and the second region 22 are formed by introducing an N-type dopant during epitaxial growth. The first region 21 and the second region 22 may be formed by successive epitaxial growth after the epitaxial growth of the doped layer 25. The first region 21 and the second region 22 may have different doping concentrations by changing the amount of N-type dopant during epitaxial growth.

[0051] Next, a diamond epitaxial layer 30 is formed on the diamond layer 15. In this example, a first epitaxial region 31, which is part of the epitaxial layer 30, is formed on the doped region 20. The first epitaxial region 31 is a region that constitutes the first upper end 341 of the diamond semiconductor device 100. The first epitaxial region 31 may be formed by epitaxial growth continuous with the epitaxial growth of the doped region 20.

[0052] In step S304, the diamond layer 15 and the first epitaxial region 31 are etched to form the trench portion 50. In this example, the trench of the trench portion 50 is formed by etching the first epitaxial region 31, the second region 22, the first region 21 and the doped layer 25. This forms a first upper end 341 in a region corresponding to the upper end 34 of the diamond semiconductor device 100.

[0053] Fig. 3C shows an example of a method for manufacturing the diamond semiconductor device 100 of Fig. 3A. This figure shows a process subsequent to step S304 of Fig. 3B.

[0054] In step S306, after forming the trench portion 50, the second epitaxial region 32 is formed on the first epitaxial region 31 and on the sidewall of the trench portion 50. In this example, the second epitaxial region 32 is formed on the upper surface of the first upper end portion 341 and on the sidewall and bottom surface of the trench portion 50. The second epitaxial region 32 becomes the second upper end portion 342, sidewall portion 36, and bottom portion 38 of the diamond semiconductor device 100. In other words, the second upper end portion 342, sidewall portion 36, and bottom portion 38 may be formed by the same epitaxial growth process.

[0055] In step S308, a termination layer 40, a contact region 60, and a gate insulating film 52 are formed. The termination layer 40 is formed by subjecting the epitaxial layer 30 to a process such as hydrogen termination. The gate insulating film 52 is formed above the epitaxial layer 30. The gate insulating film 52 may be formed by an ALD method. In step S308, the gate electrode 110, the source electrode 120, and the drain electrode 130 may be formed. The gate electrode 110 is formed on the gate insulating film 52. The source electrode 120 may be formed on the contact region 60. The drain electrode 130 is formed on the back surface of the diamond substrate 10.

[0056] In this example, the epitaxial layer 30 is epitaxially grown in multiple stages, such as the first epitaxial region 31 and the second epitaxial region 32. This allows the thickness of the upper end portion 34 to be increased. The upper end portion 34 in this example is composed of the first epitaxial region 31 and the second epitaxial region 32.

[0057] Figure 4 shows a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example differs from the diamond semiconductor device 100 of Figure 1 in the configuration of the diamond layer 15. In this example, differences from the diamond semiconductor device 100 of Figure 1 will be particularly described.

[0058] The diamond substrate 10 in this example is P+ type. The doping concentration of the P-type dopant in the diamond substrate 10 is 1×10 １８ cm －３ That's it, 1 x 10 ２２ cm －３ It may be the following:

[0059] The diamond layer 15 of this example has a first region 21 and a second region 22, but does not have a doped layer 25. The first region 21 may be provided on the diamond substrate 10. The lower end of the first region 21 may be at the same depth as the lower end of the trench portion 50.

[0060] The trench portion 50 may be provided extending from the upper surface of the doped region 20 to the diamond substrate 10. The lower end of the trench portion 50 may be deeper than the lower end of the doped region 20. The lower end of the trench portion 50 may be the lower end of the epitaxial layer 30. The lower end of the trench portion 50 may be provided in contact with the diamond substrate 10. A portion of the sidewall of the trench portion 50 may be in contact with the diamond substrate 10.

[0061] In the diamond semiconductor device 100 of this example, the diamond substrate 10 is of P+ type, so that it can be electrically connected to the bottom surface of the trench portion 50 without going through the P-type doped layer 25 .

[0062] Figure 5 shows a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example differs from the diamond semiconductor device 100 of Figure 1 in that it includes a third region 23. In this example, the differences from the diamond semiconductor device 100 of Figure 1 will be particularly described.

[0063] The third region 23 is provided by stacking with the second region 22. The third region 23 may have a lower doping concentration of the N-type dopant than the second region 22. By providing the third region 23, the diamond semiconductor device 100 can further suppress the influence of the N-type dopant on the epitaxial layer 30.

[0064] The diamond semiconductor device 100 of this example does not have the first upper end 341 of the epitaxial layer 30, but may have the first upper end 341. The first upper end 341 may be formed by epitaxially growing the first epitaxial region 31 after the epitaxial growth of the third region 23.

[0065] 6 shows a modified example of the diamond semiconductor device 100. In this example, the drain electrode 130 is provided above the diamond layer 15.

[0066] The diamond semiconductor device 100 of this example includes a gate electrode 110, a source electrode 120, and a drain electrode 130 on the front surface 11 side of the diamond layer 15. When the diamond semiconductor device 100 is turned on, a current flows from the source electrode 120 to the contact region 60 and the termination layer 40 in this order, and holes pass through the epitaxial layer 30 and move into the diamond substrate 10, causing a current to flow to the drain electrode 130.

[0067] The trench portion 70 is provided so as to extend from the front surface 11 of the diamond layer 15 to the diamond substrate 10. The lower end of the trench portion 70 may be provided so as to contact the diamond substrate 10. The trench portion 70 of this example functions as a drain trench.

[0068] The drain electrode 130 may be provided in the trench portion 70. The drain electrode 130 may be in contact with the diamond substrate 10. A titanium carbide (TiC) layer may be provided in the region where the drain electrode 130 is in contact with the diamond layer 15 and / or the epitaxial layer 30. The epitaxial layer 30 may or may not be provided between the drain electrode 130 and the doped region 20.

[0069] The termination layer 42 may be provided between the source electrode 120 and the drain electrode 130 in a top view. The termination layer 42 may be provided between the contact region 60 and the drain electrode 130 in a top view. The termination layer 42 may be a layer terminated so that holes do not flow between the contact region 60 and the drain electrode 130. The termination layer 42 may be a layer terminated so that holes do not flow between the contact region 60 and the drain electrode 130. The termination layer 42 may have a C—H bond, a C—O bond, a C—Si bond, a C—Si—O bond, a C—F bond, a C—OH bond, a C—N bond, or a C—NH bond. ２ The termination layer 42 may be oxygen-terminated, and may be a region in which the drain electrode 130 is electrically isolated from the source electrode 120 and the contact region 60.

[0070] The diamond semiconductor device 100 may share the diamond substrate 10 and may be provided with other elements on the front surface 11 side. By sharing the diamond substrate 10, it is possible to set the substrate potential to a common value among a plurality of elements. The diamond semiconductor device 100 may share the diamond substrate 10 and may be provided with other field effect transistors or other elements such as diodes. The diamond semiconductor device 100 may share the diamond substrate 10 and may be provided with an epitaxial layer other than diamond, such as gallium nitride (GaN) or silicon carbide (SiC).

[0071] The doped region 20 of this example has a first region 21, a second region 22, and a third region 23. The doped region 20 of this example may be applied to other examples of the diamond semiconductor device 100. The first region 21 may be N-type, and the second region 22 and the third region 23 may be N-type.

[0072] The first region 21 in this example may be an undoped layer into which no N-type dopant has been introduced. The first region 21 is provided on the diamond substrate 10. The first region 21 may be a layer epitaxially grown on the diamond substrate 10 into which no dopant has been intentionally introduced. The undoped first region 21 may be omitted.

[0073] The second region 22 is provided on the first region 21. The second region 22 is provided between the first region 21 and the third region 23. The second region 22 may contain an N-type dopant. The second region 22 may be formed by nitrogen doping. The thickness of the second region 22 may be the same as or different from the thickness of the first region 21.

[0074] The third region 23 is provided on the second region 22. The third region 23 may contain an N-type dopant. The doping concentration of the N-type dopant in the third region 23 may be different from the doping concentration of the N-type dopant in the second region 22. The doping concentration of the N-type dopant in the third region 23 may be lower than the doping concentration of the N-type dopant in the second region 22. The third region 23 may be formed by nitrogen doping. The thickness of the third region 23 may be the same as or different from the thickness of the first region 21 or the thickness of the second region 22.

[0075] The doped region 20 of this example has a concentration distribution in which the second region 22 has a higher doping concentration of the N-type dopant than the first region 21 and the third region 23. The doped region 20 may have a concentration distribution in which the doping concentration of the N-type dopant is high near the center in the depth direction and is lower on the front surface 11 side and the back surface 12 side than the center in the depth direction. The doped region 20 of this example has a stacked structure of three layers, but may have four or more layers, and the doping concentration may be gradually changed.

[0076] Although the diamond semiconductor device 100 of this example has three doped regions 20, namely, the first region 21, the second region 22, and the third region 23, the doped regions 20 disclosed in other modified examples may be applied as appropriate. Also, the trench portion 70 functioning as the drain trench portion may be applied to the diamond semiconductor device 100 of Fig. 1, Fig. 3A, Fig. 4 or Fig. 5.

[0077] 7A shows an example of the electrical characteristics of the diamond semiconductor device 100. The vertical axis shows the drain current density [mA / mm] normalized by the gate width, and the horizontal axis shows the drain-source voltage [V]. The curves in this example are obtained when the thickness of the epitaxial layer 30 is changed from 30 nm to 180 nm. In other words, this figure shows the dependency of the electrical characteristics of the diamond semiconductor device 100 on the thickness of the epitaxial layer 30.

[0078] When the thickness of the epitaxial layer 30 is in the range of 30 nm to less than 200 nm, the drain current exhibits good rise characteristics. The rise characteristics may be the rise characteristics of the drain current density at a drain-source voltage of approximately 0 V to -1.0 V. If the thickness of the epitaxial layer 30 is made too thin, the band bending becomes sharper, resulting in a decrease in carriers. When the thickness of the epitaxial layer 30 is in the range of 30 nm to 100 nm, the rise characteristics improve as the thickness of the epitaxial layer 30 increases. On the other hand, if the thickness of the epitaxial layer 30 is made too thick, the rise characteristics deteriorate and the on-resistance may also increase.

[0079] Figure 7B shows an example of the electrical characteristics of the diamond semiconductor device 100. The vertical axis shows the drain current density [mA / mm] normalized by the gate width, and the horizontal axis shows the drain-source voltage [V]. The electrical characteristics of this example show the range of drain-source voltage from 0 V to -30 V. This figure shows the dependency of the electrical characteristics of the diamond semiconductor device 100 on the thickness of the epitaxial layer 30. The curves of this example are obtained when the thickness of the epitaxial layer 30 is changed from 30 nm to 1000 nm.

[0080] When the thickness of the epitaxial layer 30 is in the range of 30 nm to less than 200 nm, the channel of the diamond semiconductor device 100 pinches off and saturation characteristics are observed. That is, the IV waveform of the diamond semiconductor device 100 has a linear region and a saturation region. By reducing the thickness of the epitaxial layer 30, the drain current does not increase even at drain-source voltages of -5 V or less (for example, -30 V), and short-circuit resistance can be improved. In this way, the static characteristics of the diamond semiconductor device 100 can be improved by adjusting the thickness of the epitaxial layer 30.

[0081] 8 shows an outline of the configuration of the semiconductor module 200. The semiconductor module 200 includes the diamond semiconductor device 100. The semiconductor module 200 includes a gate terminal 210, a source terminal 220, and a drain terminal 230. The gate terminal 210, the source terminal 220, and the drain terminal 230 may be external connection terminals for electrically connecting the semiconductor module 200 to the outside.

[0082] The gate terminal 210 is connected to the gate electrode 110 of the diamond semiconductor device 100. The source terminal 220 is connected to the source electrode 120 of the diamond semiconductor device 100. The drain terminal 230 is connected to the drain electrode 130 of the diamond semiconductor device 100. The diamond semiconductor device 100 may be provided on the insulating substrate of the semiconductor module 200 with the drain electrode 130 facing downward. The drain electrode 130 may be electrically connected to the drain terminal 230 via metal wiring on the insulating substrate.

[0083] The semiconductor module 200 may have a single diamond semiconductor device 100, or may have a plurality of diamond semiconductor devices 100. The semiconductor module 200 may have an inverter circuit. The semiconductor module 200 may have an inverter circuit that combines a P-type channel diamond semiconductor device 100 and an N-type channel semiconductor element. The N-type channel semiconductor element may be the N-type channel diamond semiconductor device 100, or may be another semiconductor element such as GaN or SiC.

[0084] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0085] DESCRIPTION OF SYMBOLS 10: Diamond substrate, 11: Front surface, 12: Back surface, 15: Diamond layer, 20: Doped region, 21: First region, 22: Second region, 23: Third region, 25: Doped layer, 30: Epitaxial layer, 31: First epitaxial region, 32: Second epitaxial region, 34: Upper end, 341: First upper end, 342: Second upper end, 36: Side wall portion, 38: Bottom portion, 40: Termination layer, 42: Termination layer, 50: Trench portion, 52: Gate insulating film, 60: Contact region, 70: Trench portion, 110: Gate electrode, 120: Source electrode, 130: Drain electrode, 152: Mesa portion, 100: Diamond semiconductor device, 200: Semiconductor module, 210: Gate terminal, 220: Source terminal, 230: Drain terminal

Claims

1. A diamond semiconductor device having a trench portion on a front surface thereof, comprising: a diamond layer; a diamond epitaxial layer provided on the diamond layer; a gate insulating film provided above the epitaxial layer; and a gate electrode provided on the gate insulating film, wherein the epitaxial layer has a sidewall portion provided on a sidewall of the trench portion, and a bottom portion provided on a bottom surface of the trench portion, and at least one of the sidewall portion or the bottom portion has a thickness of 10 nm or more and less than 200 nm.

2. The diamond semiconductor device according to claim 1, wherein the thickness of at least one of the sidewall portion or the bottom portion is 10 nm or more and 100 nm or less.

3. The diamond semiconductor device according to claim 1, wherein the thickness of at least one of the sidewall portion or the bottom portion is 30 nm or more and 100 nm or less.

4. The diamond semiconductor device according to claim 1, wherein the epitaxial layer has an upper end portion provided on a mesa portion of the diamond layer, and the thickness of the upper end portion is greater than the thickness of at least one of the sidewall portion or the bottom portion.

5. The diamond semiconductor device according to claim 4, wherein the thickness of the sidewall portion is 10 nm or more and less than 200 nm.

6. The diamond semiconductor device according to claim 4, wherein the thickness of the upper end portion is 10 nm or more and 1 μm or less.

7. The diamond semiconductor device according to claim 4, wherein the thickness of the upper end portion is 300 nm or more and 1 μm or less.

8. The diamond semiconductor device according to claim 1, wherein the diamond layer comprises: a P-type diamond substrate; and a doped region containing an N-type dopant provided above the diamond substrate.

9. The diamond semiconductor device according to claim 8, wherein the doped region comprises: a first region provided above the diamond substrate; and a second region provided in a stacked state with the first region and having a doping concentration of an N-type dopant different from that of the first region.

10. The doping concentration of the N-type dopant in the first region is 1×10 １５ cm －３ That's it, 1 x 10 １８ cm －３ The diamond semiconductor device according to claim 9, wherein:

11. The doping concentration of the N-type dopant in the second region is 1×10 １８ cm －３ That's it, 1 x 10 ２１ cm －３ The diamond semiconductor device according to claim 9, wherein:

12. The diamond semiconductor device according to claim 9, wherein the doping concentration of the N-type dopant in the second region is greater than the doping concentration of the N-type dopant in the first region, and the thickness of the second region is thinner than the thickness of the first region.

13. A diamond semiconductor device as described in claim 9, wherein the doped region has a third region stacked with the second region and having a lower doping concentration of the N-type dopant than the second region.

14. The diamond semiconductor device according to claim 8, wherein the epitaxial layer has a lower doping concentration of the N-type dopant than the doped region.

15. The diamond semiconductor device according to claim 1, further comprising a termination layer provided between the epitaxial layer and the gate insulating film.

16. The diamond semiconductor device according to claim 8, comprising: a source electrode provided above the diamond layer; and a drain electrode in contact with the diamond substrate.

17. A semiconductor module comprising a diamond semiconductor device according to any one of claims 1 to 16.

18. A method for manufacturing a diamond semiconductor device having a trench portion on a front surface thereof, comprising the steps of: preparing a diamond layer; forming an epitaxial layer of diamond on the diamond layer, the epitaxial layer having a sidewall portion provided on the sidewall of the trench portion and a bottom portion provided on a bottom surface of the trench portion; forming a gate insulating film above the epitaxial layer; and forming a gate electrode on the gate insulating film, wherein a thickness of at least one of the sidewall portion or the bottom portion is 10 nm or more and less than 200 nm.

19. A method for manufacturing a diamond semiconductor device as described in claim 18, wherein the step of preparing the diamond layer comprises the steps of: preparing a P-type diamond substrate; and forming a doped region containing an N-type dopant above the diamond substrate; and the step of forming the epitaxial layer comprises the steps of: forming a first epitaxial region, which is a part of the epitaxial layer, on the doped region; and etching the diamond layer and the first epitaxial region to form the trench portion, and then forming a second epitaxial region on the first epitaxial region and on a side wall of the trench portion.

Images