Surface-enhanced raman spectroscopy chip and manufacturing method thereof

Abstract

One embodiment of the present invention relates to a two-dimensional MXene-based surface-enhanced Raman spectroscopy chip and a manufacturing method thereof, wherein an MXene layer is formed on a substrate having a 3D nanostructure, thereby enhancing a SERS amplification effect, and the amplification effect becomes higher as the thickness decreases at a thin thickness of 5 nm or less, and provides a surface-enhanced Raman spectroscopy chip, comprising: a substrate; and an Mxene layer positioned on the substrate, wherein the Mxene layer has a thickness of less than 5 nm.

Description

Surface-enhanced Raman scattering chip and its manufacturing method

[0001] The present invention relates to a surface-enhanced Raman scattering chip and a method for manufacturing the same, and more particularly, to a two-dimensional maxene-based surface-enhanced Raman scattering chip manufactured through nanostructure control and a method for manufacturing the same.

[0002]

[0003] Raman signals, generated from the vibrational / rotational modes of molecules by an incident laser, possess unique molecular characteristics and thus exhibit excellent selectivity. However, the signal itself is very weak. To solve this problem, plasmonic nanostructures are utilized to amplify the Raman signal, resulting in superior sensitivity, speed, and selectivity. Chips with this signal detection function are called SERS (Surface-Enhanced Raman Spectroscopy) chips.

[0004] As demand for analytical technologies with high sensitivity and selectivity increases in the fields of food safety and the environment, SERS chips are attracting attention for their portability, speed, and low cost.

[0005] Previously, there was research on the increase in the Raman enhancement factor (EF) value as the thickness of MXene increased from 5 nm to 120 nm, but no prior research has been conducted on the SERS amplification effect in a thickness range thinner than 5 nm.

[0006] [Prior patent]

[0007] Republic of Korea Patent No. 10-1733147

[0008]

[0009] The technical problem to be achieved by the present invention is to provide a two-dimensional maxene-based surface-enhanced Raman scattering chip and a method for manufacturing the same, characterized in that the chip has a higher amplification effect as the thickness decreases at a thin thickness of 5 nm or less.

[0010]

[0011] The technical problems to be solved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present invention belongs from the description below.

[0012]

[0013] To achieve the above technical task, one embodiment of the present invention provides a surface-enhanced Raman scattering chip.

[0014] The surface-enhanced Raman scattering chip according to one embodiment of the present invention,

[0015] A surface-enhanced Raman scattering chip comprising a substrate; and an MXene layer positioned on the substrate, wherein the MXene layer has a thickness of less than 5 nm.

[0016]

[0017] Additionally, according to one embodiment of the present invention, the MXene layer may have a surface-enhanced Raman scattering chip characterized in that three or fewer MXene unit layers are stacked.

[0018]

[0019] Additionally, according to one embodiment of the present invention, there may be a surface-enhanced Raman scattering chip characterized in that the MXene layer has a thickness of 2 nm or less.

[0020]

[0021] Additionally, according to one embodiment of the present invention, there may be a surface-enhanced Raman scattering chip characterized in that the MXene layer is composed of one MXene unit layer.

[0022]

[0023] In addition, according to one embodiment of the present invention, the MXene layer may have a surface-enhanced Raman scattering chip characterized in that the coverage of MXene constituting the MXene layer is 45% to 85%.

[0024]

[0025] Additionally, according to one embodiment of the present invention, there may be a surface-enhanced Raman scattering chip characterized in that the substrate is a substrate having electrical insulation properties.

[0026]

[0027] In addition, according to one embodiment of the present invention, there may be a surface-enhanced Raman scattering chip characterized in that the substrate having the insulating property is a Si / SiN or Si / SiO2 substrate.

[0028] Additionally, according to one embodiment of the present invention, there may be a surface-enhanced Raman scattering chip characterized by further including a 3-(triethoxysilyl)propylamine (3-aminopropyltriethoxysilane) coating layer between the substrate and the MXene layer.

[0029]

[0030] In addition, according to one embodiment of the present invention, there may be a surface-enhanced Raman scattering chip including a substrate having a 3D nanostructure on which a nano-pattern is formed; and an MXene layer positioned on the substrate having the 3D nanostructure on which the nano-pattern is formed, wherein the MXene layer has a thickness of less than 5 nm.

[0031]

[0032] In addition, according to one embodiment of the present invention, there may be a surface-enhanced Raman scattering chip characterized in that the 3D nanostructure in which the nano-pattern is formed is a 3D nanostructure in which a trench-shaped nano-pattern is formed.

[0033]

[0034] In addition, according to one embodiment of the present invention, the 3D nanostructure formed with the trench-shaped nano pattern may have a surface-enhanced Raman scattering chip characterized by a line width of 20 nm to 50 nm and a depth of 50 nm to 100 nm.

[0035]

[0036] In addition, according to one embodiment of the present invention, there may be a surface-enhanced Raman scattering chip characterized in that the substrate having a 3D nanostructure on which the nano-pattern is formed is an insulating Si / SiN or Si / SiO2 substrate.

[0037]

[0038] In addition, according to one embodiment of the present invention, there may be a surface-enhanced Raman scattering chip characterized by further including a 3-aminopropyltriethoxysilane coating layer between a substrate having a 3D nanostructure on which the nano-pattern is formed and an MXene layer.

[0039]

[0040]

[0041] In order to achieve the above technical task, another embodiment of the present invention provides a method for manufacturing a surface-enhanced Raman scattering chip.

[0042] The method for manufacturing the surface-enhanced Raman scattering chip according to one embodiment of the present invention is as follows:

[0043] A method for manufacturing a surface-enhanced Raman scattering chip may include a step of preparing an aqueous MXene solution; and a step of forming an MXene layer by coating the prepared aqueous MXene solution on a substrate, wherein the formed MXene layer has a thickness of less than 5 nm.

[0044] In addition, according to one embodiment of the present invention, there may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that it further includes a step of forming a 3-aminopropyltriethoxysilane coating layer on a substrate between the step of preparing the MXene aqueous solution and the step of forming the MXene layer.

[0045] In addition, according to one embodiment of the present invention, there may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the step of preparing the MXene aqueous solution is such that the concentration of the MXene aqueous solution is 5 mg / ml or less.

[0046]

[0047] In addition, according to one embodiment of the present invention, there may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the step of preparing the MXene aqueous solution is such that the concentration of the MXene aqueous solution is 0.25 mg / ml to 1 mg / ml.

[0048]

[0049] In addition, according to one embodiment of the present invention, there may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the substrate is a 3D nanostructure in which a trench-shaped nano pattern is formed.

[0050] In addition, according to one embodiment of the present invention, there may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the 3D nanostructure formed with the trench-shaped nano-pattern has a line width of 20 nm to 50 nm and a depth of 50 nm to 100 nm.

[0051]

[0052] In addition, according to one embodiment of the present invention, there may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the substrate is a Si / SiN or Si / SiO2 substrate having insulating properties.

[0053]

[0054] According to one embodiment of the present invention, a two-dimensional maxine-based surface-enhanced Raman scattering chip and a method for manufacturing the same can be provided, characterized in that the thinner the thickness is, the higher the amplification effect is.

[0055] According to one embodiment of the present invention, a 2D MXene-based surface-enhanced Raman scattering chip with improved SERS amplification effect and a method for manufacturing the same can be provided by forming an MXene layer on a substrate having a 3D nanostructure.

[0056]

[0057] The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the detailed description of the present invention or the composition of the invention described in the claims.

[0058]

[0059] Figure 1 is a schematic diagram showing the outline shape of an MXene SERS Chip formed on a Si / SiO2 substrate according to one embodiment of the present invention.

[0060] Figure 2 is a schematic diagram showing the schematic shape of an MXene SERS Chip formed on a substrate having a 3D nanostructure according to one embodiment of the present invention.

[0061] Figure 3 shows SEM images of the MXene SERS Chip formed on a flat SiO2 substrate according to one embodiment of the present invention, according to coverage (thickness).

[0062] Figure 4 shows the Raman intensity according to the MXene coverage of the MXene SERS Chip formed on a flat SiO2 substrate according to one embodiment of the present invention.

[0063] Figure 5 shows the Raman intensity according to the MXene coverage of an MXene SERS Chip formed on a substrate having a 3D nanostructure according to an embodiment of the present invention.

[0064] FIG. 6 shows an SEM image according to MXene coverage formed on a substrate having an APTES-treated 3D nanostructure according to an embodiment of the present invention.

[0065] FIG. 7 is a graph showing Raman intensity at different depths (50, 80, 100 nm) for a 40 nm line width of a substrate having a 3D nanostructure according to an embodiment of the present invention.

[0066] FIG. 8 shows SEM images at different depths (50, 80, 100 nm) for a 40 nm line width of a substrate having a 3D nanostructure according to one embodiment of the present invention.

[0067] FIG. 9 is a graph showing Raman intensity at different line widths (20 nm, 40 nm) for a depth of 50 nm of a substrate having a 3D nanostructure according to an embodiment of the present invention.

[0068] FIG. 10 is a graph showing the EF (Raman Enhancement Factor) value of an MXene SERS chip coated on a flat SiO2 and 3D nanostructure substrate according to one embodiment of the present invention.

[0069] FIG. 11 is a graph showing the Raman Shift at various line width and depth conditions of a substrate having a 3D nanostructure according to an embodiment of the present invention, and the Raman Shift of a pico-based SERS chip formed on a flat SiO2 substrate for comparison.

[0070] Figure 12 is a graph and table comparing Raman shift and intensity values ​​according to substrate type.

[0071] Figure 13 is a SEM image showing the change in MXene coating according to substrate APTES treatment.

[0072] Figure 14 is an SEM image of MXene coated under the same conditions as the Raman shift and peak intensity according to the substrate type when the coverage of MXene on the substrate is approximately 90%.

[0073] Figure 15 is an SEM image of MXene coated under the same conditions as the Raman shift and peak intensity according to the substrate type, when the coverage of MXene on the substrate is approximately 98%.

[0074] Figure 16 is an SEM image of an APTES-treated substrate and an O2 plasma-treated substrate in an MXene aqueous solution of the same concentration.

[0075]

[0076] Hereinafter, the present invention will be described with reference to the attached drawings. However, the present invention can be implemented in various different forms and is therefore not limited to the embodiments described herein. In the drawings, irrelevant parts have been omitted for clarity of description, and similar parts have been designated with similar reference numerals throughout the specification.

[0077] Throughout the specification, when a part is said to be "connected (connected, contacted, or coupled)" to another part, this includes not only cases where it is "directly connected," but also cases where it is "indirectly connected" with another member in between. Furthermore, when a part is said to "include" a component, this does not exclude other components, but rather implies that it may include other components, unless otherwise specifically stated.

[0078] The terminology used herein is merely used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, it should be understood that the terms "comprises" or "has" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0079]

[0080] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0081] A surface-enhanced Raman scattering chip according to one embodiment of the present invention is described.

[0082] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip comprising a substrate; and an MXene layer positioned on the substrate, wherein the MXene layer has a thickness of less than 5 nm.

[0083] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip characterized in that the MXene layer is formed by stacking three or fewer MXene unit layers.

[0084]

[0085] Figure 1 is a schematic diagram showing the outline shape of an MXene SERS Chip formed on a Si / SiO2 substrate according to one embodiment of the present invention.

[0086] The above embodiment is described with reference to Fig. 1.

[0087]

[0088] The above MXene is a special two-dimensional nanomaterial. It is a ceramic material in the form of a thin and strong sheet. It is a new material composed of an atomic-thick layer of carbon or nitrogen bonded to a transition metal. The MXene is obtained by removing elements located between other atomic-layer materials, such as carbon or nitride, as a thin layer. Due to this special structure, it is a unique material that has metallic properties such as conductivity due to the transition metal, but also hydrophilic properties due to the hydroxyl groups or oxygen present at the terminals.

[0089]

[0090] MXene is made from a crystalline material called MAX, which is made of M n+1 AX n It refers to a hexagonal layered carbide or nitride having an empirical formula of .

[0091] In the above, M is a transition metal, A is a group 13 or 14 element, X is carbon or nitrogen, and n has a range of 1 to 4.

[0092]

[0093] The above MXene has various properties and is used in various applications, generally having high electrical and thermal conductivity, high mechanical strength, and chemical stability.

[0094]

[0095] Referring to Figure 1, it can be confirmed that the structure is one in which MXene unit layers are laminated on the substrate.

[0096] It can be confirmed that the MXene unit layers are laminated in numbers of three or less, and the MXene layer is characterized by a thickness of less than 5 nm.

[0097]

[0098] Previously, there was a study on the increase in the Raman Enhancement Factor (EF) value of SERS as the thickness of MXene increased from 5 nm to 120 nm.

[0099] In the case of the above example, unlike the above-mentioned prior study, it is characterized in that the Raman enhancement factor (EF) value of SERS increases as the thickness becomes thinner at a thickness of less than 5 nm.

[0100]

[0101] In addition, the Raman enhancement factor (EF) value of the SERS according to the above embodiment is about 6*10 4 Compared to the above-mentioned previous study, it can be confirmed that the performance is improved by approximately 1.4 times.

[0102]

[0103] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip characterized in that the MXene layer has a thickness of 2 nm or less.

[0104] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip characterized in that the MXene layer is composed of one MXene unit layer.

[0105] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip characterized in that the MXene layer has a coverage of 45% to 85% of MXene constituting the MXene layer.

[0106] Figure 3 shows SEM images of the MXene SERS Chip formed on a flat SiO2 substrate according to one embodiment of the present invention, according to coverage (thickness).

[0107] Figure 4 shows the Raman intensity according to the MXene coverage of the MXene SERS Chip formed on a flat SiO2 substrate according to one embodiment of the present invention.

[0108] The above embodiment is described with reference to FIGS. 3 and 4.

[0109]

[0110] Referring to FIG. 3, it can be confirmed that the thickness of the MXene layer is determined according to the number of MXene unit layers positioned on the substrate.

[0111] For example, one MXene unit layer has a thickness of about 1.6 nm, and when two unit layers are laminated, the thickness is about 3.2 nm.

[0112] If there is one or more of the above MXene unit layers, the coverage of the MXene constituting the MXene layer becomes 100%.

[0113] In addition, even if the MXene unit layer is the same as one, the thickness may vary depending on the coverage of the MXene constituting the MXene layer.

[0114]

[0115] Referring to Figure 4, when the coverage of MXene constituting the MXene layer is in the range of 45% to 85%, the 611 cm -1 and 1361cm -1 In all graphs, it can be seen that it has the best Raman intensity.

[0116]

[0117] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip characterized in that the substrate is a substrate having electrical insulation properties.

[0118] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip characterized in that the substrate having the insulating property is a Si / SiN or Si / SiO2 substrate.

[0119] As an example of the above embodiment, more preferably, there may be a surface-enhanced Raman scattering chip characterized in that the substrate having the insulating property is a Si / SiO2 substrate.

[0120]

[0121] Figure 12 is a graph and table comparing Raman shift and intensity values ​​according to substrate type.

[0122] The above embodiment is described with reference to Fig. 12.

[0123]

[0124] When comparing electrical insulation, the Si substrate shows a resistance value of several Ω, while the SiO2 substrate shows a resistance value of several M Ω. Due to this difference in electrical insulation, the SiO2 substrate shows a difference in amplification effect of up to 10 times compared to the Si substrate.

[0125]

[0126] The above Si / SiN refers to a structure in which a silicon nitride (SiN) layer is coated on a silicon (Si) substrate. The silicon nitride (SiN) is very effective in acting as an insulator and has good electrical insulation properties.

[0127] The above Si / SiO2 refers to a structure in which a silicon dioxide (SiO2) layer is coated on a silicon (Si) substrate. The silicon dioxide (SiO2) has physical properties similar to glass and is very effective in acting as an insulator.

[0128]

[0129] In particular, the Si / SiO2 substrate is used to manufacture various devices, and at this time, the SiO2 layer serves to maintain insulation between devices and prevent electrical connection between devices and the substrate, and can improve the reliability and stability of the devices due to the characteristics of the Si / SiO2 structure.

[0130]

[0131] Referring to Fig. 12, the amplification effect of the surface-enhanced Raman scattering chip can be compared when Si is used as the substrate and when Si / SiN and Si / SiO2 having electrical insulation are used.

[0132] First of all, basically, the substrate must have electrical insulation properties so that the amplification effect of the surface-enhanced Raman scattering chip can be increased. In this case, when compared to a case where a material without electrical insulation properties is used as the substrate, a difference in the amplification effect of up to 10 times can occur.

[0133]

[0134] When comparing electrical insulation, the Si substrate shows a resistance value of several Ω, while the SiO2 substrate shows a resistance value of several M Ω. Due to this difference in electrical insulation, the SiO2 substrate shows a difference in amplification effect of up to 10 times compared to the Si substrate.

[0135]

[0136] Referring to Fig. 12, it can be confirmed that the amplification effect of the surface-enhanced Raman scattering chip is the best when Si / SiO2 is used as the substrate.

[0137] Next, the excellent effects are achieved in the order of when Si / SiN is used as a substrate and when Si is used as a substrate.

[0138]

[0139] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip characterized by further including a 3-(triethoxysilyl)propylamine (3-aminopropyltriethoxysilane) coating layer between the substrate and the MXene layer.

[0140] Figure 13 is a SEM image showing the change in MXene coating according to substrate APTES treatment.

[0141] Figure 16 is an SEM image of an APTES-treated substrate and an O2 plasma-treated substrate in an MXene aqueous solution of the same concentration.

[0142] The above embodiment is described with reference to FIGS. 13 and 16.

[0143]

[0144] In the above APTES treatment, APTES is an abbreviation for 3-aminopropyltriethoxysilane, which is mainly used for surface treatment, and is particularly used to promote bonding between organic and inorganic substances.

[0145]

[0146] Referring to (a) of Fig. 13, it can be confirmed that when APTES treatment is not performed, the MXene layer coated on the substrate is formed unevenly.

[0147] On the other hand, referring to (b) of Fig. 13, when an MXene layer is formed after coating with APTES, it can be confirmed that the MXene layer is coated very uniformly.

[0148] Referring to Fig. 16, a more intuitive comparison can be made between the MXene layers formed on the O2 plasma treated substrate and the APTES treated substrate, with respect to the results according to the concentration of the MXene aqueous solution.

[0149] By uniformly coating the above MXene layer, the uniformity of SERS signal amplification can also be improved. More specifically,

[0150] The yield of MXene is improved through the above APTES treatment, enabling effective coating with a small amount of MXene, thereby forming a more uniform MXene coating layer.

[0151] Although the MXene layer uniformly coated as described above does not directly affect the SERS amplification effect, it can affect the reduction of positional deviation, resulting in an effect of improving the uniformity of SERS signal amplification.

[0152]

[0153] As an example of the above embodiment, a substrate having a 3D nanostructure on which a nano pattern is formed; and an MXene layer positioned on the substrate having the 3D nanostructure on which the nano pattern is formed,

[0154] The above MXene layer may have a surface-enhanced Raman scattering chip characterized by a thickness of less than 5 nm.

[0155] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip characterized in that the 3D nanostructure in which the nano-pattern is formed is a 3D nanostructure in which a trench-shaped nano-pattern is formed.

[0156] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip in which the trench-shaped nano-patterned 3D nanostructure is formed, characterized in that the line width is 20 nm to 50 nm and the depth is 50 nm to 100 nm.

[0157]

[0158] Figure 2 is a schematic diagram showing the schematic shape of an MXene SERS Chip formed on a substrate having a 3D nanostructure according to one embodiment of the present invention.

[0159] The above embodiment is described with reference to Fig. 2.

[0160]

[0161] Referring to Figure 2, it can be confirmed that the substrate is formed in a three-dimensional structure, not a flat structure.

[0162] The above three-dimensional structure is a three-dimensional nanostructure, and a nano-sized pattern may be formed.

[0163] The above nano-sized pattern may be a trench-shaped nano-pattern, in which protruding and concave portions are arranged in a regular pattern, as shown in FIG. 2.

[0164] In the case of the above trench-shaped nano-pattern, the performance of the surface-enhanced Raman scattering chip may vary depending on the line width and depth.

[0165] As in the above example, excellent effects can be obtained in a range of line widths from 20 nm to 50 nm and depths from 50 nm to 100 nm.

[0166] The critical significance of this will be described later in the experimental examples.

[0167]

[0168] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip characterized in that the substrate having the 3D nanostructure on which the nano-pattern is formed is an insulating Si / SiN or Si / SiO2 substrate.

[0169] As an example of the above embodiment, more preferably, there may be a surface-enhanced Raman scattering chip characterized in that the substrate having the 3D nanostructure on which the nano-pattern is formed is an insulating Si / SiO2 substrate.

[0170]

[0171] When comparing electrical insulation, the Si substrate shows a resistance value of several Ω, while the SiO2 substrate shows a resistance value of several M Ω. Due to this difference in electrical insulation, the SiO2 substrate shows a difference in amplification effect of up to 10 times compared to the Si substrate.

[0172]

[0173] The above Si / SiN refers to a structure in which a silicon nitride (SiN) layer is coated on a silicon (Si) substrate. The silicon nitride (SiN) is very effective in acting as an insulator and has good electrical insulation properties.

[0174] The above Si / SiO2 refers to a structure in which a silicon dioxide (SiO2) layer is coated on a silicon (Si) substrate. The silicon dioxide (SiO2) has physical properties similar to glass and is very effective in acting as an insulator.

[0175]

[0176] In particular, the Si / SiO2 substrate is used to manufacture various devices, and at this time, the SiO2 layer serves to maintain insulation between devices and prevent electrical connection between devices and the substrate, and can improve the reliability and stability of the devices due to the characteristics of the Si / SiO2 structure.

[0177]

[0178] Referring to Fig. 12, the amplification effect of the surface-enhanced Raman scattering chip can be compared when Si is used as the substrate and when Si / SiN and Si / SiO2 having electrical insulation are used.

[0179] First of all, basically, the substrate must have electrical insulation properties so that the amplification effect of the surface-enhanced Raman scattering chip can be greater. In this case, when compared to the case where Si, a material that does not have electrical insulation properties, is used as the substrate, a difference in the amplification effect of up to 10 times can occur.

[0180]

[0181] Referring to Fig. 12, it can be confirmed that the amplification effect of the surface-enhanced Raman scattering chip is the best when Si / SiO2 is used as the substrate.

[0182] Next, the excellent effects are achieved in the order of when Si / SiN is used as a substrate and when Si is used as a substrate.

[0183]

[0184] As an example of the above embodiment, there may be a surface-enhanced Raman scattering chip characterized by further including a 3-aminopropyltriethoxysilane coating layer between a substrate having a 3D nanostructure on which the nano-pattern is formed and an MXene layer.

[0185] Referring to (a) of Fig. 13, it can be confirmed that when APTES treatment is not performed, the MXene layer coated on the substrate is formed unevenly.

[0186] On the other hand, referring to (b) of Fig. 13, when an MXene layer is formed after coating with APTES, it can be confirmed that the MXene layer is coated very uniformly.

[0187] Referring to Fig. 16, a more intuitive comparison can be made between the MXene layers formed on the O2 plasma treated substrate and the APTES treated substrate, with respect to the results according to the concentration of the MXene aqueous solution.

[0188] By uniformly coating the above MXene layer, the uniformity of SERS signal amplification can also be improved. More specifically,

[0189] The yield of MXene is improved through the above APTES treatment, enabling effective coating with a small amount of MXene, thereby forming a more uniform MXene coating layer.

[0190] Although the MXene layer uniformly coated as described above does not directly affect the SERS amplification effect, it can affect the reduction of positional deviation, resulting in an effect of improving the uniformity of SERS signal amplification.

[0191]

[0192] A method for manufacturing a surface-enhanced Raman scattering chip according to another embodiment of the present invention is described.

[0193] Since the above-described method for manufacturing a surface-enhanced Raman scattering chip is an invention for a method for manufacturing the above-described surface-enhanced Raman scattering chip, the features of the above-described invention can be applied as is to the surface-enhanced Raman scattering chip invention.

[0194] Therefore, any content that overlaps with the above-described content in the description of the surface-enhanced Raman scattering chip invention will be omitted below.

[0195]

[0196] As an example of the above embodiment, the method comprises the steps of preparing an MXene aqueous solution; and the steps of forming an MXene layer by coating the prepared MXene aqueous solution on a substrate.

[0197] There may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the formed MXene layer has a thickness of less than 5 nm.

[0198] As an example of the above embodiment, the step of preparing the MXene aqueous solution; and the step of forming the MXene layer; between,

[0199] There may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that it further includes a step of forming a 3-(triethoxysilyl)propylamine (3-aminopropyltriethoxysilane) coating layer on a substrate.

[0200] The step of forming the above 3-(triethoxysilyl)propylamine (3-aminopropyltriethoxysilane) coating layer corresponds to the above-described APTES treatment process.

[0201]

[0202] As an example of the above embodiment, there may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the step of preparing the MXene aqueous solution is such that the concentration of the MXene aqueous solution is 5 mg / ml or less.

[0203] As an example of the above embodiment, more preferably, there may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the step of preparing the MXene aqueous solution is such that the concentration of the MXene aqueous solution is 0.25 mg / ml to 1 mg / ml.

[0204]

[0205] Figure 5 shows the Raman intensity according to the MXene coverage of an MXene SERS Chip formed on a substrate having a 3D nanostructure according to an embodiment of the present invention.

[0206] Referring to Figure 4, when the coverage of MXene constituting the MXene layer is in the range of 45% to 85%, the 611 cm -1 and 1361cm -1 In all graphs, it can be seen that it has the best Raman intensity.

[0207] Referring to Figure 5, in the MXene SERS Chip formed on a substrate having a 3D nanostructure, when the coverage of the MXene constituting the MXene layer is in the range of 45% to 85%, the 611 cm -1 and 1361cm -1 In all graphs, it can be seen that it has the best Raman intensity.

[0208]

[0209] And, referring to FIGS. 3 and 6, it can be confirmed that the concentration of the MXene aqueous solution, which allows the coverage of the MXene to be in the range of 45% to 85%, is approximately 0.25 mg / ml to 1 mg / ml, among 5 mg / ml or less.

[0210] Referring to Figure 3, in the case of a flat substrate, when the concentration of the MXene aqueous solution is 0.25 mg / ml to 1 mg / ml, the coverage of the MXene has a range of 45% to 85%.

[0211] Referring to FIG. 6, in the case of a 3D nanostructure (trench structure), it can be confirmed that when the concentration of the MXene aqueous solution is 0.25 mg / ml to 1.5 mg / ml, the coverage of the MXene is in the range of 45% to 85%.

[0212] Referring to FIGS. 4 and 5, it can be confirmed that the Raman intensity is the best in the above-described range.

[0213]

[0214] As an example of the above embodiment, there may be a method for manufacturing a surface-enhanced Raman scattering chip characterized in that the substrate is a 3D nanostructure in which a trench-shaped nano pattern is formed.

[0215] As an example of the above embodiment, the 3D nanostructure formed with the trench-shaped nano pattern is

[0216] There may be a method for manufacturing a surface-enhanced Raman scattering chip characterized by a line width of 20 nm to 50 nm and a depth of 50 nm to 100 nm.

[0217]

[0218] As an example of the above embodiment, there may be a method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the substrate is a Si / SiN or Si / SiO2 substrate having insulating properties.

[0219]

[0220] Manufacturing Example 1. Manufacturing of MXene SERS chip with less than 1 layer.

[0221]

[0222] Step 1. Preparation of MXene aqueous solution (preparation at concentrations ranging from 0.05 to 10 mg / ml)

[0223] The concentration of the MXene aqueous solution is adjusted using the manufactured MXene and deionized water.

[0224]

[0225] 2. Substrate preparation stage

[0226] 1) Substrate type: Flat Si / SiO2 substrate

[0227] 2) Substrate pretreatment

[0228] - Cleaning

[0229] After washing in EtOH for 30 seconds, rinse in Acetone for 30 seconds.

[0230] - Plasma cleaning

[0231] Run for 10 minutes at 100W.

[0232] - APTES surface treatment

[0233] In a mixed solution of 50 ml of acetone and 1 ml of APTES, stir at 350 rpm for 3 minutes.

[0234]

[0235] 3. MXene SERS chip fabrication steps

[0236] Using the MXene spin coating method, at this time, the substrate is 1 cm 2 Load 36 ml of MXene aqueous solution.

[0237] The above Spin coating is performed under the conditions of 3000 rpm, 6 sec, 1 min ramp, room temperature, and 1 hour drying in the air.

[0238]

[0239] 4. Raman measurement step

[0240] 532nm laser (R6G)

[0241] Power: Approximately 4mW

[0242] Integration time: 500ms

[0243] Raman measurements are performed under the above conditions.

[0244]

[0245] Manufacturing Example 2. Fabrication of MXene SERS chip on 3D nanostructure (trench structure) substrate.

[0246]

[0247] 1. Preparation of MXene aqueous solution

[0248] The concentration of the MXene aqueous solution is adjusted using the manufactured MXene and deionized water.

[0249]

[0250] 2. Substrate preparation stage

[0251] 1) Substrate type

[0252] Fabrication of a substrate with a nano-trench (Si / SiO2) structure

[0253] Line width: 20 nm, depth: 50, 70 nm

[0254] Line width: 50 nm, depth: 50, 80, 100 nm

[0255]

[0256] If the above conditions are expressed in line width / depth,

[0257] Nano-Trench (Si / SiO2) structure substrates having line widths / depths of 20 / 50, 20 / 70, 50 / 50, 50 / 80, and 50 / 100, respectively, are manufactured.

[0258]

[0259] 2) Substrate pretreatment

[0260] - Cleaning

[0261] Wash in EtOH for 30 seconds, then rinse in Acetone for 30 seconds.

[0262] - Plasma cleaning

[0263] Run for 10 minutes at 100W.

[0264] - APTES surface treatment

[0265] In a mixed solution of 50 ml of acetone and 1 ml of APTES, stir at 350 rpm for 3 minutes.

[0266]

[0267] 3. MXene spin coating step

[0268] Spin coating is performed using MXene aqueous solutions prepared by mixing MXene and deionized water at different concentrations.

[0269]

[0270] At this time, the substrate is 1 cm 2 Load 36 ml of the above MXene aqueous solution.

[0271] The above Spin coating is performed under the conditions of 3000 rpm, ramp 6 sec, 1 min, room temperature, and drying in the air for 1 hour.

[0272]

[0273] 4. Raman measurement step

[0274] 532nm laser

[0275] Power: Approximately 4mW

[0276] Itegration time: 500ms

[0277]

[0278] Raman measurements are performed under the above conditions.

[0279]

[0280] Experimental Example 1. Raman intensity analysis by condition.

[0281] Figure 4 shows the Raman intensity according to the MXene coverage of the MXene SERS Chip formed on a flat SiO2 substrate according to one embodiment of the present invention.

[0282] Figure 5 shows the Raman intensity according to the MXene coverage of an MXene SERS Chip formed on a substrate having a 3D nanostructure according to an embodiment of the present invention.

[0283] FIG. 7 is a graph showing Raman intensity at different depths (50, 80, 100 nm) for a 40 nm line width of a substrate having a 3D nanostructure according to an embodiment of the present invention.

[0284] FIG. 9 is a graph showing Raman intensity at different line widths (20 nm, 40 nm) for a depth of 50 nm of a substrate having a 3D nanostructure according to an embodiment of the present invention.

[0285] FIG. 10 is a graph showing the EF (Raman Enhancement Factor) value of an MXene SERS chip coated on a flat SiO2 and 3D nanostructure substrate according to one embodiment of the present invention.

[0286] FIG. 11 is a graph showing the Raman Shift at various line width and depth conditions of a substrate having a 3D nanostructure according to an embodiment of the present invention, and the Raman Shift of a pico-based SERS chip formed on a flat SiO2 substrate for comparison.

[0287] Figure 12 is a graph and table comparing Raman shift and intensity values ​​according to substrate type.

[0288] Figure 13 is a SEM image showing the change in MXene coating according to substrate APTES treatment.

[0289]

[0290] Referring to the above Figure 4, when the coverage of the MXene constituting the MXene layer is in the range of 45% to 85%, the 611 cm -1 and 1361cm -1 In all graphs, it can be seen that it has the best Raman intensity.

[0291]

[0292] Referring to the above Figure 5, in the MXene SERS Chip formed on a substrate having a 3D nanostructure, when the coverage of the MXene constituting the MXene layer is in the range of 45% to 85%, the 611 cm -1 and 1361cm -1 In all graphs, it can be seen that it has the best Raman intensity.

[0293]

[0294] Referring to the above Figure 7, the Raman intensity of the MXene SERS chip stacked on a 3D nanostructure substrate having a flat structure and various depth conditions can be compared, and the graph is organized in a table as shown in Table 1 below.

[0295]

[0296] Flat depth 50 nm depth 80 nm depth 100 nm 611 cm -1 4502300290031001361cm -1 250120015001500

[0297]

[0298] Referring to the above Figure 7 and Table 1, it can be confirmed that the best results are obtained when the depth is 80 nm to 100 nm under the condition of a line width of 40 nm.

[0299]

[0300] If the graph of the above figure 9 is organized into a table, it is as shown in Table 2 below.

[0301] 20nm40nm611cm -1 290025001361cm -1 17001500

[0302]

[0303] Referring to the above Figure 9 and Table 2, it can be confirmed that the lower the line width, the greater the amplification effect. More specifically,

[0304] As a result of confirming the SERS amplification effect using the R6G indicator under two conditions of line width of 20 nm and 40 nm after fixing the depth to 50 nm, it can be confirmed that the amplification effect is improved by approximately 15% at the line width of 20 nm.

[0305]

[0306] Referring to the above Fig. 10, the EF (Raman Enhancement Factor) values ​​of the MXene SERS chip coated on the flat SiO2 and 3D nanostructure substrates can be compared. In common, when the coverage of the MXene constituting the MXene layer is in the range of 45% to 85%, the 611 cm -1 In all graphs, it can be seen that it has the best Raman intensity.

[0307]

[0308] The Raman intensity results of the above Fig. 11 can be summarized in Table 3 below.

[0309] FlatSi / SiO2 substrate 3D nanostructure commercial (pico) 40 / 100 / 40 / 80 / 40 / 50 / 20 / 50 / 61 / 11 cm -1 450310029002300290024001361cm -1 25015001500120017001500

[0310]

[0311] Referring to the above Figure 11 and Table 3, it can be confirmed that when a substrate having a 3D nano structure is used, a SERS effect that is up to about 7 times improved can be obtained compared to when a flat substrate is used.

[0312] In addition, it can be confirmed that the deeper the depth of the 3D nanostructure, the more improved the SERS amplification effect can be obtained, and the narrower the line width, the more improved the SERS amplification effect can be obtained.

[0313] In the most preferable case, it can be confirmed that the SERS amplification effect is greatest when the MXene structure coated on the substrate having the 3D nanostructure has a line width of 40 nm and a depth of 100 nm.

[0314]

[0315] Referring to the above Fig. 12, the amplification effect of the surface-enhanced Raman scattering chip can be compared when Si is used as the substrate and when Si / SiN and Si / SiO2 having electrical insulation are used, and it can be confirmed that the case in which the amplification effect of the surface-enhanced Raman scattering chip is the best is when Si / SiO2 is used as the substrate.

[0316] Next, it can be seen that the superior effect is achieved in the order of when Si / SiN is used as a substrate and when Si is used as a substrate.

[0317]

[0318] Referring to (a) of the above Fig. 13, it can be confirmed that when APTES treatment is not performed, the MXene layer coated on the substrate is formed unevenly.

[0319] On the other hand, referring to (b) of Fig. 13, when an MXene layer is formed after coating with APTES, it can be confirmed that the MXene layer is coated very uniformly.

[0320]

[0321] Experimental Example 2. SEM image analysis according to MXene concentration.

[0322] Figure 3 shows SEM images of the MXene SERS Chip formed on a flat SiO2 substrate according to one embodiment of the present invention, according to coverage (thickness).

[0323] FIG. 6 shows an SEM image according to MXene coverage formed on a substrate having an APTES-treated 3D nanostructure according to an embodiment of the present invention.

[0324] FIG. 8 shows SEM images at different depths (50, 80, 100 nm) for a 40 nm line width of a substrate having a 3D nanostructure according to one embodiment of the present invention.

[0325] Figure 14 is an SEM image of MXene coated under the same conditions as the Raman shift and peak intensity according to the substrate type when the coverage of MXene on the substrate is approximately 90%.

[0326] Figure 15 is an SEM image of MXene coated under the same conditions as the Raman shift and peak intensity according to the substrate type, when the coverage of MXene on the substrate is approximately 98%.

[0327] Figure 16 is an SEM image of an APTES-treated substrate and an O2 plasma-treated substrate in an MXene aqueous solution of the same concentration.

[0328]

[0329] Referring to the above Figure 3, in the case of a flat substrate, it can be confirmed that when the concentration of the MXene aqueous solution is 0.25 mg / ml to 1 mg / ml, the coverage of the MXene is in the range of 45% to 85%.

[0330] Referring to the above Figure 6, in the case of a 3D nanostructure (trench structure), it can be confirmed that when the concentration of the MXene aqueous solution is 0.25 mg / ml to 1.5 mg / ml, the coverage of the MXene is in the range of 45% to 85%.

[0331] Referring to the above Figure 8, it can be confirmed that the coverage and shape of the coated MXene layer do not change significantly even as the depth increases.

[0332]

[0333] The above figures 14 and 15 show the Raman intensity at the same coverage on Si, SiN, and SiO2 substrates with different insulating properties.

[0334] Figure 14 shows a comparison of an MXene layer with a coverage of 90% under a thickness condition of less than about 1.6 nm, and Figure 15 shows a comparison of an MXene layer with a coverage of 98-99% under a thickness condition of about 2 nm.

[0335] Referring to the above Figures 14 and 15, it can be confirmed that the trend according to the insulation of the substrate does not change even if the MXene layer becomes thicker.

[0336]

[0337] Referring to the above Figure 16, the results according to the concentration of the MXene aqueous solution can be compared more intuitively for the MXene layer formed on the O2 plasma treated substrate and the APTES treated substrate.

[0338] By uniformly coating the above MXene layer, the uniformity of SERS signal amplification can also be improved. More specifically,

[0339] The yield of MXene is improved through the above APTES treatment, enabling effective coating with a small amount of MXene, thereby forming a more uniform MXene coating layer.

[0340] Although the MXene layer uniformly coated as described above does not directly affect the SERS amplification effect, it can affect the reduction of positional deviation, resulting in an effect of improving the uniformity of SERS signal amplification.

[0341]

[0342] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will readily appreciate that the present invention can be readily modified into other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single entity may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined manner.

[0343] The scope of the present invention is indicated by the claims described below, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

Claims

1. Substrate; and Including an MXene layer positioned on the above substrate, A surface-enhanced Raman scattering chip, characterized in that the MXene layer has a thickness of less than 5 nm.

2. In paragraph 1, A surface-enhanced Raman scattering chip characterized in that the above MXene layer is formed by stacking three or fewer MXene unit layers.

3. In paragraph 1, A surface-enhanced Raman scattering chip characterized in that the MXene layer has a thickness of 2 nm or less.

4. In paragraph 3, A surface-enhanced Raman scattering chip characterized in that the above MXene layer is composed of one MXene unit layer.

5. In the fourth paragraph, the MXene layer, A surface-enhanced Raman scattering chip characterized in that the coverage of MXene constituting the above MXene layer is 45% to 85%.

6. In paragraph 1, A surface-enhanced Raman scattering chip characterized in that the substrate is an electrically insulating substrate.

7. In paragraph 6, A surface-enhanced Raman scattering chip characterized in that the substrate having the above insulating properties is a Si / SiN or Si / SiO2 substrate.

8. In paragraph 1, A surface-enhanced Raman scattering chip further comprising a 3-(triethoxysilyl)propylamine (3-aminopropyltriethoxysilane) coating layer between the substrate and the MXene layer.

9. A substrate having a 3D nanostructure with a nano-pattern formed thereon; and Including an MXene layer positioned on a substrate having a 3D nanostructure on which the above nano pattern is formed, A surface-enhanced Raman scattering chip, characterized in that the MXene layer has a thickness of less than 5 nm.

10. In paragraph 9, The 3D nanostructure formed with the above nano pattern is A surface-enhanced Raman scattering chip characterized by a 3D nanostructure formed with a trench-shaped nano pattern.

11. In paragraph 10, The 3D nanostructure formed with the above trench-shaped nano pattern is A surface-enhanced Raman scattering chip characterized by a line width of 20 nm to 50 nm and a depth of 50 nm to 100 nm.

12. In paragraph 9, The substrate having a 3D nanostructure formed with the above nano pattern is A surface-enhanced Raman scattering chip characterized by a Si / SiN or Si / SiO2 substrate having insulating properties.

13. In paragraph 9, A surface-enhanced Raman scattering chip characterized in that it further includes a 3-aminopropyltriethoxysilane coating layer between a substrate having a 3D nanostructure on which the above nano-pattern is formed and an MXene layer.

14. Step of preparing MXene aqueous solution; and It includes a step of forming an MXene layer by coating the prepared MXene aqueous solution on a substrate, A method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the formed MXene layer has a thickness of less than 5 nm.

15. In paragraph 14, The step of preparing the above MXene aqueous solution; and the step of forming the MXene layer; between them, A method for manufacturing a surface-enhanced Raman scattering chip, characterized in that it further comprises a step of forming a 3-(triethoxysilyl)propylamine (3-aminopropyltriethoxysilane) coating layer on a substrate.

16. In the 14th paragraph, the step of preparing the MXene aqueous solution is as follows: A method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the concentration of the above MXene aqueous solution is 5 mg / ml or less.

17. In the 14th paragraph, the step of preparing the MXene aqueous solution is: A method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the concentration of the above MXene aqueous solution is 0.25 mg / ml to 1 mg / ml.

18. A method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the substrate in claim 14 is a 3D nanostructure having a trench-shaped nano pattern formed therein.

19. In the 18th paragraph, the 3D nanostructure in which the trench-shaped nano pattern is formed is A method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the line width is 20 nm to 50 nm and the depth is 50 nm to 100 nm.

20. In paragraph 14, A method for manufacturing a surface-enhanced Raman scattering chip, characterized in that the substrate is a Si / SiN or Si / SiO2 substrate having insulating properties.

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