Power-on reset circuit, chip, and electronic device

Abstract

The present application belongs to the technical field of integrated circuits. Disclosed are a power-on reset circuit, a chip, and an electronic device. The power-on reset circuit comprises: a reset signal output circuit, which is used for receiving a power supply voltage and generating a first reset signal; a reset signal inversion protection circuit, which is connected to the reset signal output circuit, and is used for receiving the first reset signal and maintaining the level state of the first reset signal; and a glitch filtering circuit, which is connected to the reset signal inversion protection circuit, and is used for receiving the first reset signal and filtering glitches of the first reset signal, wherein the glitch filtering circuit comprises a delay module, a logic processing module and an inverter module, the delay module being used for delaying the first reset signal to output a delay signal, the logic processing unit being used for carrying out logic processing on the first reset signal and the delay signal to generate a logic signal, and the inverter module being used for carrying out inversion processing on the logic signal to generate a first reset signal having no glitches. By means of the present application, glitches on a reset signal can be filtered, thereby avoiding reset abnormalities caused by the glitches.

Description

Power-on reset circuits, chips, and electronic devices

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 15, 2023, with application number 202311199378.4 and application name “Power-on reset circuit, chip and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of integrated circuits, and in particular to a power-on reset circuit, a chip, and an electronic device. Background Art

[0003] In the field of integrated circuit design, the stability of a chip's power-on reset (POR) circuit directly impacts the reliability of the entire chip. Therefore, a stable and reliable power-on reset module is crucial to chip reliability. A power-on reset circuit is typically used to send a reset signal to the digital circuits within the integrated circuit, resetting and initializing them to the designer's desired initial state.

[0004] When the chip's working environment is harsh, its power-on reset signal is prone to level flipping due to factors such as electromagnetic interference and particle ray interference. In addition, the power-on reset signal of high-speed chips such as FPGA chips is more prone to glitches during transmission. The power-on reset circuit of traditional chips lacks corresponding response methods, which can easily cause abnormal chip operation.

[0005] Summary of the Invention

[0006] In view of the above problems, the present application provides a power-on reset circuit, chip and electronic device to solve the above technical problems.

[0007] In a first aspect, the present application provides a power-on reset circuit, comprising:

[0008] A reset signal output circuit, configured to receive a power supply voltage and generate a first reset signal;

[0009] a reset signal inversion protection circuit, connected to the reset signal output circuit, configured to receive the first reset signal and maintain a level state of the first reset signal;

[0010] a glitch filtering circuit, connected to the reset signal flip protection circuit, configured to receive the first reset signal and filter out glitches in the first reset signal;

[0011] Among them, the glitch filtering circuit includes a delay module, a logic processing module and an inversion module. The delay module is used to delay the first reset signal and then output a delayed signal; the logic processing unit is used to perform logic processing on the first reset signal and the delayed signal to generate a logic signal, and the inversion module is used to invert the logic signal to generate the first reset signal without glitch.

[0012] In some embodiments, the reset signal output circuit includes:

[0013] A voltage divider circuit is configured to receive the power supply voltage and divide the power supply voltage to generate a power supply divided voltage;

[0014] A reference voltage output circuit, used for generating a preset reference voltage;

[0015] a comparison output circuit, configured to receive the power supply divided voltage and the reference voltage, and generate the first reset signal of a high level or a low level according to a comparison result of the power supply divided voltage and the reference voltage;

[0016] The voltage divider feedback circuit is configured to receive the first reset signal and modify the voltage divider ratio of the voltage divider circuit according to the first reset signal.

[0017] In some embodiments, the voltage divider circuit includes a first resistance unit, a second resistance unit, and a third resistance unit connected in series, the first resistance unit is further configured to be connected to a power supply to receive a power supply voltage, and the third resistance unit is further configured to be grounded; a voltage divider node is provided between the first resistance unit and the second resistance unit;

[0018] The comparison output circuit includes a comparator, wherein a first input terminal and a second input terminal of the comparator are respectively connected to the reference voltage output circuit and the voltage dividing node to receive the reference voltage and the power supply divided voltage;

[0019] The voltage divider feedback circuit includes a first inverting unit and a first switching unit, wherein the input end of the first inverting unit is connected to the output end of the comparator to invert the first reset signal, and the output end of the first inverting unit is connected to the first switching unit; the first end of the first switching unit is connected to the first inverting unit to control the on and off of the first switching unit according to its output signal, the second end of the first switching unit is respectively connected to the second resistance unit and the third resistance unit, and the third end of the first switching unit is used for grounding.

[0020] In some embodiments, the first switch unit includes a first NMOS transistor, the gate of the first NMOS transistor is connected to the first inverting unit, the drain of the first NMOS transistor is respectively connected to the second resistance unit and the third resistance unit, and the source of the first NMOS transistor is used for grounding.

[0021] In some embodiments, the delay module includes a first delay unit and a second delay unit, the logic processing module includes a first logic processing unit and a second logic processing unit, and the inversion module includes a second inversion unit and a third inversion unit;

[0022] The first delay unit is used to delay the first reset signal for a first time and then output a first delayed signal; the first logic processing unit is used to perform a logical OR operation on the first delayed signal and the first reset signal to generate a first logic signal; and the second inverting unit is used to invert the first logic signal to generate the first reset signal without high-level glitches;

[0023] The second delay unit is connected to the second inverting unit, and is used to delay the first reset signal output by the second inverting unit for a second time and then output a second delayed signal. The second logic processing unit is used to perform a logical AND operation on the second delayed signal and the first reset signal output by the second inverting unit to generate a second logic signal. The third inverting unit is used to invert the second logic signal to generate the first reset signal without low-level glitches.

[0024] In some embodiments, the reset signal flip protection circuit includes a first energy storage unit, a second switch unit, a fourth inverting unit, a third switch unit, a second energy storage unit and a fifth inverting unit;

[0025] The first end of the first energy storage unit is used to connect to a power supply to receive the power supply voltage, and the second end of the first energy storage unit is connected to the second switch unit;

[0026] A first end of the second switch unit is connected to the second logic processing unit to control the on and off of the second switch unit according to the second logic signal, a second end of the second switch unit is connected to the first energy storage unit, and a third end of the second switch unit is connected to the reset signal output circuit and the fourth inverting unit respectively;

[0027] The input end of the fourth inverting unit is connected to the reset signal output circuit and the second switch unit respectively, and the output end of the fourth inverting unit is connected to the third switch unit and the fifth inverting unit respectively;

[0028] The first end of the third switch unit is connected to the third inverting unit to control the on / off of the third switch unit according to the first reset signal output by the third inverting unit, the second end of the third switch unit is connected to the fourth inverting unit and the fifth inverting unit respectively, and the third end of the third switch unit is connected to the second energy storage unit;

[0029] A first end of the second energy storage unit is connected to the third switch unit, and a second end is grounded;

[0030] An input end of the fifth inverting unit is connected to the fourth inverting unit and the third switch unit respectively, and an output end of the fifth inverting unit is connected to the first delay unit and the first logic processing unit.

[0031] In some embodiments, the second switch unit includes a first PMOS transistor, a gate of the first PMOS transistor is connected to the second logic processing unit to receive the second logic signal, a drain of the first PMOS transistor is connected to the first energy storage unit, and a source of the first PMOS transistor is connected to the reset signal output circuit and the fourth inverting unit respectively;

[0032] The third switching unit includes a second NMOS transistor, the gate of the second NMOS transistor is connected to the second inverting unit to receive the first reset signal output by the second inverting unit, the drain of the second NMOS transistor is respectively connected to the fourth inverting unit and the fifth inverting unit, and the source of the second NMOS transistor is connected to the second energy storage unit.

[0033] In some embodiments, the power-on reset circuit further includes:

[0034] a pulse filtering circuit, connected to the third inverting unit, configured to receive the first reset signal output by the third inverting unit and filter out spike pulses of the first reset signal;

[0035] The pulse filtering circuit includes a fourth resistor unit, a first end of the fourth resistor unit is connected to the third inverting unit, and a second end of the fourth resistor unit is grounded.

[0036] In a second aspect, the present application also provides a chip comprising any of the power-on reset circuits described above.

[0037] In a third aspect, the present application also provides an electronic device, comprising a device body and the chip as described above provided in the device body.

[0038] The power-on reset circuit, chip, and electronic device provided in the present application have a power-on reset circuit that generates a first reset signal for power-on reset through a reset signal output circuit, a reset chip flip protection circuit that maintains the level of the first reset signal so that the first reset signal will not flip due to interference from environmental factors, and a glitch filtering circuit that filters out glitches on the first reset signal to obtain a glitch-free first reset signal for power-on reset. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] FIG1 shows a module schematic diagram of a power-on reset circuit provided in an embodiment of the present application.

[0041] FIG2 shows a module schematic diagram of a reset signal output circuit provided in an embodiment of the present application.

[0042] FIG3 shows a schematic structural diagram of a reset signal output circuit provided in an embodiment of the present application.

[0043] FIG4 shows a schematic structural diagram of a glitch filtering circuit provided in an embodiment of the present application.

[0044] FIG5 shows a schematic structural diagram of a reset signal inversion protection circuit provided in an embodiment of the present application.

[0045] FIG6 shows a schematic structural diagram of a power-on reset circuit provided in an embodiment of the present application.

[0046] FIG7 shows a timing diagram of a power-on reset circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0048] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0049] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0050] In the circuit structure provided in the embodiments of the present application, the nodes do not represent actual components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0051] Figure 1 shows a module schematic diagram of a power-on reset circuit provided in an embodiment of the present application. The power-on reset circuit is used to solve the problem of power-on reset signal flipping caused by environmental factors such as high-intensity electromagnetic interference, particle ray interference, etc., and to remove the burrs of the power-on reset signal when burrs appear in the power-on reset signal. As shown in Figure 1, the power-on reset circuit provided in an embodiment of the present application includes a reset signal output circuit, a reset signal flip protection circuit, and a burr filtering circuit.

[0052] The reset signal output circuit is used to receive the power supply voltage and generate a first reset signal. Specifically, the reset signal output circuit generates a first reset signal for a power-on reset operation after sensing that the chip starts to power on. The level of the first reset signal is determined by the power supply voltage. When the power supply voltage reaches a preset voltage threshold, the power-on reset signal is converted from a low level to a high level. The power-on reset signal may or may not contain glitches.

[0053] The reset signal flip protection circuit is connected to the reset signal output circuit, and is used to receive the first reset signal and maintain the level state of the first reset signal. Specifically, when the chip operates in a complex environment, the first reset signal may be abnormally flipped at a high level due to the influence of environmental factors (such as electromagnetic interference, particle ray interference, etc.), thereby affecting the power-on reset of the chip. The reset signal flip protection circuit receives the first reset signal generated by the reset signal output circuit. Even if the first reset signal reaches the threshold of abnormal flip, the level state of the first reset signal can be maintained, thereby avoiding abnormal flip of the first reset circuit. Obviously, there is no difference between the first reset signal output by the reset signal flip protection circuit and the first reset signal output by the reset signal output circuit.

[0054] A glitch filtering circuit is connected to the reset signal flip protection circuit, and is used to receive the first reset signal and filter the glitches of the first reset signal; wherein the glitch filtering circuit includes a delay module, a logic processing module and an inverting module, the delay module is used to delay the first reset signal and then output a delayed signal; the logic processing unit is used to perform logic processing on the first reset signal and the delay signal to generate a logic signal, and the inverting module is used to invert the logic signal to generate a glitch-free first reset signal. Obviously, when the first reset signal output by the reset signal output circuit is glitch-free, the first reset signal output by the glitch filtering circuit is indistinguishable from the first reset signal output by the reset signal output circuit; when the first reset signal output by the reset signal output circuit has glitches, the first reset signal output by the glitch filtering circuit only removes the glitches.

[0055] The power-on reset circuit provided in the embodiment of the present application maintains the level of the first reset signal through the reset chip flip protection circuit, and filters out the glitches on the first reset signal through the glitch filtering circuit by delaying, logical operation and inverting the first reset signal, thereby obtaining a glitch-free first reset signal for power-on reset. The present application solves the problem of abnormal flipping of the chip caused by environmental factors such as electromagnetic interference and particle ray interference, removes the glitches of the chip power-on reset signal, and avoids abnormal reset of the chip caused by glitches.

[0056] In some embodiments, FIG2 shows a module schematic diagram of a reset signal output circuit provided in an embodiment of the present application. As shown in FIG2 , the reset signal output circuit includes:

[0057] The voltage divider circuit is configured to receive the power supply voltage and divide the power supply voltage to generate a power supply divided voltage.

[0058] The reference voltage output circuit is used to generate a preset reference voltage, wherein the specific voltage value of the reference voltage is determined according to factors such as the type of chip and the application scenario. The embodiment of the present application does not require the circuit structure of the reference voltage output circuit, as long as it can be set in the power-on reset module of the chip and can generate the corresponding reference voltage.

[0059] The comparison output circuit is used to receive the power supply divided voltage and the reference voltage, and generate the first reset signal of high level or low level according to the comparison result of the power supply divided voltage and the reference voltage. Specifically, during the chip power-on process, the power supply voltage starts to rise from 0V. Before the power supply divided voltage exceeds the reference voltage, the comparison output circuit always outputs the first reset signal of low level. When the power supply divided voltage exceeds the reference voltage, the comparison output circuit outputs the first reset signal of high level.

[0060] The voltage divider feedback circuit is used to receive the first reset signal and modify the voltage divider ratio of the voltage divider circuit according to the first reset signal. Specifically, if there are glitches in the first reset signal during the chip power-on process, the glitches may cause the chip to be repeatedly reset. The embodiment of the present application changes the voltage divider ratio of the power supply voltage divider in the circuit by setting a voltage divider feedback circuit, thereby avoiding repeated resetting of the first reset signal due to glitches during the power-on process. On the other hand, the embodiment of the present application is also applicable to the power-off reset process of the chip. By setting the voltage divider feedback circuit to change the voltage divider ratio of the power supply voltage divider in the circuit, the threshold value of the change in the level state of the first reset signal during the power-on process and the power-off process can be distinguished.

[0061] In some embodiments, Figure 3 shows a structural schematic diagram of the reset signal output circuit provided in an embodiment of the present application. As shown in Figure 3, the voltage divider circuit includes a first resistance unit R1, a second resistance unit R2 and a third resistance unit R3 connected in series. The first resistance unit R1 is also used to connect to the power supply to receive the power supply voltage, and the third resistance unit R3 is also used for grounding; a voltage divider node is provided between the first resistance unit R1 and the second resistance unit R2.

[0062] The comparison output circuit includes a comparator A1. The first input terminal and the second input terminal of the comparator A1 are respectively connected to the reference voltage output circuit and the voltage divider node to receive the reference voltage and the power supply divided voltage. Comparator A1 outputs a high or low first reset signal based on the comparison result of the two voltage signals received at the input terminal. In the embodiment of the present application, during the power supply voltage power-up process, the power supply divided voltage starts to rise from 0V. At this time, the power supply divided voltage is less than the reference voltage. Comparator A1 outputs a low first reset signal. When the power supply divided voltage exceeds the reference voltage, comparator A1 outputs a high first reset signal.

[0063] The voltage divider feedback circuit includes a first inverting unit N1 and a first switch unit Q1. The input end of the first inverting unit N1 is connected to the output end of the comparator A1 to invert the first reset signal, and the output end of the first inverting unit N1 is connected to the first switch unit Q1. The first end of the first switch unit Q1 is connected to the first inverting unit N1 to control the on and off of the first switch unit Q1 according to its output signal. The second end of the first switch unit Q1 is connected to the second resistor unit R2 and the third resistor unit R3 respectively. The third end of the first switch unit Q1 is used for grounding.

[0064] Optionally, the first inverting unit N1 is an inverter, which is used to invert the input signal, but it should be clear that in the embodiment of the present application, the first inverting unit N1 is not limited to an inverter. In fact, as long as it can be integrated into the chip, any element or circuit structure that can invert the input signal and then output it can be used as the first inverting unit N1. Designers can select a suitable first inverting unit N1 based on cost, chip requirements and other reasons.

[0065] It should be clear that in the embodiment of the present application, the first resistance unit R1, the second resistance unit R2 and the third resistance unit R3 can be a single resistance element or a resistance string.

[0066] In some embodiments, the first switch unit Q1 includes a first NMOS transistor, the gate of the first NMOS transistor Q1 is connected to the first inverting unit N1, the drain of the first NMOS transistor is respectively connected to the second resistor unit R2 and the third resistor unit R3, and the source of the first NMOS transistor is grounded.

[0067] It should be noted that the first switching unit in this article is a first NMOS transistor for illustrative purposes only. Since the source and drain of a transistor can be symmetrical in structure, their source and drain can be structurally the same. That is, the NMOS transistor in the circuit can be replaced by a related circuit of a PMOS transistor to achieve the same function. In addition, the first switching unit in this article can also be a CMOS switch and a diode connected to the gate source of the CMOS switch. In fact, the first switching unit in this article can be any circuit with corresponding switching capabilities that meets the requirements.

[0068] In some embodiments, Figure 4 shows a structural schematic diagram of the glitch filtering circuit provided in an embodiment of the present application. As shown in Figure 4, in the glitch filtering circuit provided in an embodiment of the present application, the delay module includes a first delay unit D1 and a second delay unit D2, the logic processing module includes a first logic processing unit NOR1 and a second logic processing unit NAND1, and the inverting module includes a second inverting unit N2 and a third inverting unit N3.

[0069] The first delay unit D1 is connected to the reset signal flip protection circuit to receive the first reset signal outputted therefrom, and is configured to delay the first reset signal by a first time and then output the first delayed signal. The two input terminals of the first logic processing unit NOR1 are respectively connected to the first delay unit D1 and the reset signal flip protection circuit, and are configured to perform a logical negation operation on the first delayed signal and the first reset signal to generate a first logic signal. The second inverting unit N2 is connected to the output terminal of the first logic processing unit NOR1, and is configured to invert the first logic signal to generate a first reset signal free of high-level glitches. Specifically, the first delay unit D1, the first logic processing unit NOR1, and the second inverting unit N2 are configured to process high-level glitches in the first reset signal, wherein the first time is determined based on the actual requirements of the chip design.

[0070] The second delay unit D2 is connected to the second inverting unit N2 and is configured to delay the first reset signal output by the second inverting unit N2 by a second time and then output a second delayed signal. The two input terminals of the first logic processing unit NAND1 are respectively connected to the second delay unit D2 and the second inverting unit N2 and are configured to perform a logical AND operation on the second delayed signal and the first reset signal output by the second inverting unit N2 to generate a second logic signal. The third inverting unit N3 is connected to the output terminal of the first logic processing unit NAND1 and is configured to invert the second logic signal to generate a first reset signal without low-level glitches. Specifically, the second delay unit D2, the first logic processing unit NAND1, and the third inverting unit N3 are configured to process low-level glitches in the first reset signal. The second time is determined based on the actual requirements of the chip design and can be the same as or different from the first time.

[0071] Optionally, the second inverting unit and the third inverting unit are inverters, but it should be clear that in the embodiments of the present application, the second inverting unit and the third inverting unit are not limited to inverters. In fact, as long as they can be integrated into the chip, any element or circuit structure that can invert the input signal and then output it can be used as the second inverting unit and the third inverting unit. Designers can choose appropriate second inverting units and third inverting units based on cost, chip requirements and other reasons; in addition, the first logic processing unit can be an NOR gate and a corresponding element or circuit with a first-OR-later NOT logic function, the second logic processing unit can be a NAND gate and a corresponding element or circuit with a first-AND-later NOT logic function, the first delay unit and the second delay unit can be set to any delay module or delay circuit, and the embodiments of the present application do not require the specific structure of the delay unit.

[0072] In some embodiments, Figure 5 shows a structural schematic diagram of the reset signal flip protection circuit provided in an embodiment of the present application. As shown in Figure 5, the reset signal flip protection circuit includes a first energy storage unit C1, a second switch unit Q2, a fourth inverting unit N4, a third switch unit Q3, a second energy storage unit C2 and a fifth inverting unit N5.

[0073] A first end of the first energy storage unit C1 is used to connect to a power source to receive a power voltage, and a second end of the first energy storage unit C1 is connected to the second switch unit Q2 .

[0074] A first end of the second switch unit Q2 is connected to the second logic processing unit NAND1 to control the on and off of the second switch unit Q2 according to the second logic signal. A second end of the second switch unit Q2 is connected to the first energy storage unit C1. A third end of the second switch unit Q2 is respectively connected to the reset signal output circuit and the fourth inverting unit N4.

[0075] The input end of the fourth inverting unit N4 is connected to the reset signal output circuit and the second switch unit Q2 respectively, and the output end of the fourth inverting unit N4 is connected to the third switch unit Q3 and the fifth inverting unit N5 respectively.

[0076] The first end of the third switch unit Q3 is connected to the third inverting unit N3 to control the on and off of the third switch unit Q3 according to the first reset signal output by the third inverting unit N2, the second end of the third switch unit Q3 is respectively connected to the fourth inverting unit N4 and the fifth inverting unit N5, and the third end of the third switch unit Q3 is connected to the second energy storage unit C2.

[0077] A first end of the second energy storage unit C2 is connected to the third switch unit Q3, and a second end thereof is grounded;

[0078] The input end of the fifth inverting unit N5 is connected to the fourth inverting unit N4 and the third switch unit Q3 respectively, and the output end of the fifth inverting unit N5 is connected to the first delay unit D1 and the first logic processing unit NOR1.

[0079] Optionally, the first energy storage unit and the second energy storage unit are energy storage capacitors. Specifically, the energy storage capacitors may be conventional capacitors, or may be wiring capacitors, parasitic capacitors, and the like.

[0080] Optionally, the fourth inverting unit and the fifth inverting unit are inverters, but it should be clear that in the embodiments of the present application, the fourth inverting unit and the fifth inverting unit are not limited to inverters. In fact, as long as they can be integrated into the chip, any element or circuit structure that can invert the input signal and then output it can be used as the fourth inverting unit and the fifth inverting unit. Designers can choose appropriate fourth inverting units and fifth inverting units based on cost, chip requirements and other reasons.

[0081] In some embodiments, the second switch unit Q2 includes a first PMOS transistor, a gate of the first PMOS transistor is connected to the second logic processing unit to receive the second logic signal, a drain of the first PMOS transistor is connected to the first energy storage unit C1, and a source of the first PMOS transistor is respectively connected to the reset signal output circuit and the fourth inverting unit N4;

[0082] The third switch unit Q3 includes a second NMOS tube, the gate of the second NMOS tube is connected to the second inverting unit to receive the first reset signal output by the second inverting unit N2, the drain of the second NMOS tube is respectively connected to the fourth inverting unit N4 and the fifth inverting unit N5, and the source of the second NMOS tube is connected to the second energy storage unit C2.

[0083] It should be noted that the second switch unit is a PMOS transistor and the third switch unit is an NMOS transistor in this article for illustrative purposes only. Since the source and drain of a transistor can be symmetrical in structure, their source and drain can be structurally the same. That is, the PMOS transistor in the circuit can be replaced by the relevant circuit of an NMOS transistor to achieve the same function. Conversely, the NMOS transistor in the circuit can be replaced by the relevant circuit of a PMOS transistor to achieve the same function. In addition, the second switch unit and the third switch in this article can also be CMOS switches and diodes connected to the gate and source of the CMOS switches. In fact, the second switch unit and the third switch unit in this article can be any circuit with corresponding switching capabilities that meets the requirements.

[0084] In some embodiments, FIG6 shows a schematic diagram of the structure of a power-on reset circuit provided in an embodiment of the present application. As shown in FIG6 , the power-on reset circuit provided in an embodiment of the present application further includes:

[0085] a pulse filtering circuit, connected to the third inverting unit N3, configured to receive the first reset signal output by the third inverting unit N3, and filter out spike pulses of the first reset signal;

[0086] The pulse filtering circuit includes a fourth resistor unit R4 , a first end of the fourth resistor unit R4 is connected to the third inverting unit N3 , and a second end of the fourth resistor unit R4 is grounded.

[0087] It should be clear that in the embodiment of the present application, the fourth resistance unit can be a single resistance element or a resistance string.

[0088] FIG7 shows a timing diagram of a power-on reset circuit provided in an embodiment of the present application. As shown in FIG6 and FIG7 , the working principle of the power-on reset circuit provided in an embodiment of the present application is as follows:

[0089] For the reset signal output circuit, during the power-on process, the first reset signal is initially at a low level, and outputs a high level after passing through the first inverting unit. The first NMOS tube receives the high level and turns on. At this time, the power supply divided voltage is R2 / (R1+R2); when the power supply divided voltage exceeds the reference voltage, the first reset signal output by the comparator is a high level, and outputs a low level after passing through the first inverting unit. The first NMOS tube receives the low level and is in a dielectric cutoff state. At this time, the power supply divided voltage is (R2+R3) / (R1+R2+R3), where " / " represents a division symbol.

[0090] For the glitch filtering circuit, when the reset signal flip protection circuit outputs a low-level first reset signal, the first reset signal passes through the first delay unit to output a first delayed signal, the first reset signal and the first delayed signal are subjected to a first logic processing unit to perform an OR-NOT logic operation, and then a high-level first logic signal is output. The first logic signal passes through the second inverting unit to output a low-level first reset signal, the first reset signal passes through the second delay unit to output a second delayed signal, the second delayed signal and the first reset signal are subjected to a second logic processing unit to perform an AND-NOT logic operation, and then a high-level second logic signal is output. The second logic signal passes through the third inverting unit to output a low-level first reset signal, which is the reset signal ultimately used for power-on. If the low-level first reset signal output by the reset signal flip protection circuit contains glitches, as shown in FIG7 , the first reset signal is delayed by the second delay unit and a logical AND-NOT operation is performed with the second delayed signal output by the second delay unit to remove the low-level glitches of the first reset signal.

[0091] When the reset signal flip protection circuit outputs a high-level first reset signal, the first reset signal outputs a first delay signal after passing through the first delay unit, the first reset signal and the first delay signal are subjected to a non-OR logic operation by the first logic processing unit to output a low-level first logic signal, and the first logic signal is outputted through the second inverting unit to output a high-level first reset signal.

[0092] The first reset signal outputs a second delayed signal after passing through the second delay unit. The second delayed signal and the first reset signal are subjected to a NOT logical operation by the second logic processing unit, and then a low-level second logic signal is output. The second logic signal is subjected to a third inversion unit, and then a low-level first reset signal is output. The first reset signal is the reset signal ultimately used for power-on. If the reset signal flip protection circuit outputs a high-level first reset signal with glitches, as shown in FIG7 , the first reset signal is delayed by the first delay unit, and a NOT logical operation is performed with the first delay signal output by the first delay unit to filter out the high-level glitches of the first reset signal.

[0093] The burr on the first reset signal is not sufficient to cause the logic operation result of the first reset signal and the first delay signal to be reversed when there is no burr.

[0094] It should be clear that in the embodiment of the present application, the first delay unit, the first logic processing unit and the first inverting unit are used to filter high-level glitches, and the second delay unit, the second logic processing unit and the second inverting unit are used to filter low-level glitches. In the glitch filtering circuit provided in the embodiment of the present application, after the high-level first reset signal passes through the first delay unit, the first logic processing unit and the first inverting unit to filter the glitches, it can still obtain the first reset signal of the same level after passing through the second delay unit, the second logic processing unit and the second inverting unit. Similarly, the low-level first reset signal is still at a low level after passing through the first delay unit, the first logic processing unit and the first inverting unit, so that the second delay unit, the second logic processing unit and the second inverting unit can filter its glitches.

[0095] For the reset signal flip protection circuit, when the reset signal output circuit outputs a low-level first reset signal, the first PMOS tube receives a high-level second logic signal, and the second NMOS tube receives a low-level first reset signal. The first PMOS tube and the second NMOS tube are both in the cut-off state. At this time, the first reset signal is output to the glitch filtering circuit through the fourth inverting unit and the fifth inverting unit.

[0096] When the reset signal output circuit outputs a high-level first reset signal, the first PMOS transistor receives a low-level second logic signal, and the second NMOS transistor receives a high-level first reset signal. The first PMOS transistor and the second NMOS transistor are both in the on state. When the power supply voltage rises to trigger environmental interference such as electromagnetic interference, ion ray interference, etc., causing the high-level first reset signal to flip to a low level, the second logic signal and the first reset signal fed back by the glitch filter signal will also flip, causing the first PMOS transistor and the second NMOS transistor to be in the off state. At this time, the first energy storage unit C1 and the second energy storage unit C2 begin to discharge, and the first PMOS transistor and the second NMOS transistor are turned on by the first energy storage unit C1 and the second energy storage unit C2, respectively. Then, the first energy storage unit C1 can quickly charge the first reset signal flipped to a low level to a high level (the first reset signal at the input end of the fourth inverting unit), and the second energy storage unit C2 can also quickly discharge the first reset signal output by the fourth inverting unit to a low level. Therefore, in the power-on reset circuit provided in the embodiment of the present application, when the first reset signal reaches the flip condition, the positive feedback design can quickly lock the state to resist abnormal flipping of the circuit caused by strong magnetic field interference.

[0097] The present application also provides a chip including the power-on reset circuit described above. An integrated circuit (IC) is also referred to as a chip, and the chip may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.

[0098] An embodiment of the present application further provides an electronic device, which includes a device body and the chip as described above disposed in the device body.

[0099] The above content is a further detailed description of the present application in conjunction with specific implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, they can make several simple deductions or substitutions without departing from the concept of the present application, which should be considered as the scope of protection of the present application.

Claims

1. A power-on reset circuit, characterized in that: include: A reset signal output circuit, used for receiving a power supply voltage and generating a first reset signal; A reset signal flip protection circuit, connected to the reset signal output circuit, configured to receive the first reset signal and maintain a level state of the first reset signal; A glitch filtering circuit, connected to the reset signal flip protection circuit, for receiving the first reset signal and filtering the glitch of the first reset signal; Among them, the glitch filtering circuit includes a delay module, a logic processing module and an inversion module. The delay module is used to output a delayed signal after delaying the first reset signal; the logic processing module is used to perform logic processing on the first reset signal and the delay signal to generate a logic signal, and the inversion module is used to perform inversion processing on the logic signal to generate the first reset signal without glitch.

2. The power-on reset circuit according to claim 1, characterized in that: The reset signal output circuit comprises: A voltage divider circuit, used for receiving the power supply voltage and dividing the power supply voltage to generate a power supply divided voltage; A reference voltage output circuit, used for generating a preset reference voltage; a comparison output circuit, configured to receive the power supply divided voltage and the reference voltage, and generate the first reset signal of a high level or a low level according to a comparison result between the power supply divided voltage and the reference voltage; The voltage-dividing feedback circuit is used to receive the first reset signal and modify the voltage-dividing ratio of the voltage-dividing circuit according to the first reset signal.

3. The power-on reset circuit according to claim 2, characterized in that: The voltage divider circuit comprises a first resistance unit, a second resistance unit and a third resistance unit connected in series, the first resistance unit is also used to connect to a power supply to receive a power supply voltage, and the third resistance unit is also used to be grounded; a voltage divider node is provided between the first resistance unit and the second resistance unit; The comparison output circuit comprises a comparator, wherein a first input terminal and a second input terminal of the comparator are respectively connected to the reference voltage output circuit and the voltage dividing node to receive the reference voltage and the power supply divided voltage; The voltage divider feedback circuit includes a first inverting unit and a first switch unit, wherein the input end of the first inverting unit is connected to the output end of the comparator to invert the first reset signal, and the output end of the first inverting unit is connected to the first switch unit; the first end of the first switch unit is connected to the first inverting unit to control the on and off of the first switch unit according to its output signal, the second end of the first switch unit is respectively connected to the second resistance unit and the third resistance unit, and the third end of the first switch unit is used for grounding.

4. The power-on reset circuit according to claim 3, characterized in that: The first switch unit includes a first NMOS tube, a gate of the first NMOS tube is connected to the first inverting unit, a drain of the first NMOS tube is respectively connected to the second resistance unit and the third resistance unit, and a source of the first NMOS tube is grounded.

5. The power-on reset circuit according to claim 1, wherein: The delay module includes a first delay unit and a second delay unit, the logic processing module includes a first logic processing unit and a second logic processing unit, and the inversion module includes a second inversion unit and a third inversion unit; The first delay unit is used to delay the first reset signal for a first time and then output a first delay signal, the first logic processing unit is used to perform a logic OR operation on the first delay signal and the first reset signal to generate a first logic signal, and the second inversion unit is used to invert the first logic signal to generate the first reset signal without high-level glitches; The second delay unit is connected to the second inverting unit, and is used to delay the first reset signal output by the second inverting unit for a second time and then output a second delay signal. The second logic processing unit is used to perform a logic AND operation on the second delay signal and the first reset signal output by the second inverting unit to generate a second logic signal. The third inverting unit is used to invert the second logic signal to generate the first reset signal without low-level glitches.

6. The power-on reset circuit according to claim 5, characterized in that: The reset signal flip protection circuit comprises a first energy storage unit, a second switch unit, a fourth inverting unit, a third switch unit, a second energy storage unit and a fifth inverting unit; The first end of the first energy storage unit is used to connect to a power source to receive the power supply voltage, and the second end of the first energy storage unit is connected to the second switch unit; The first end of the second switch unit is connected to the second logic processing unit to control the on and off of the second switch unit according to the second logic signal, the second end of the second switch unit is connected to the first energy storage unit, and the third end of the second switch unit is respectively connected to the reset signal output circuit and the fourth inverting unit; The input end of the fourth inverting unit is connected to the reset signal output circuit and the second switch unit respectively, and the output end of the fourth inverting unit is connected to the third switch unit and the fifth inverting unit respectively; The first end of the third switch unit is connected to the third inverting unit to control the on and off of the third switch unit according to the first reset signal output by the third inverting unit, the second end of the third switch unit is respectively connected to the fourth inverting unit and the fifth inverting unit, and the third end of the third switch unit is connected to the second energy storage unit; The first end of the second energy storage unit is connected to the third switch unit, and the second end is grounded; The input end of the fifth inverting unit is connected to the fourth inverting unit and the third switch unit respectively, and the output end of the fifth inverting unit is connected to the first delay unit and the first logic processing unit.

7. The power-on reset circuit according to claim 6, characterized in that: The second switch unit includes a first PMOS tube, the gate of the first PMOS tube is connected to the second logic processing unit to receive the second logic signal, the drain of the first PMOS tube is connected to the first energy storage unit, and the source of the first PMOS tube is respectively connected to the reset signal output circuit and the fourth inverting unit; The third switch unit includes a second NMOS tube, the gate of the second NMOS tube is connected to the second inverting unit to receive the first reset signal output by the second inverting unit, the drain of the second NMOS tube is respectively connected to the fourth inverting unit and the fifth inverting unit, and the source of the second NMOS tube is connected to the second energy storage unit.

8. The power-on reset circuit according to claim 5, characterized in that: The power-on reset circuit also includes: a pulse filtering circuit, connected to the third inverting unit, for receiving the first reset signal output by the third inverting unit, and filtering out a peak pulse of the first reset signal; The pulse filtering circuit includes a fourth resistor unit, a first end of the fourth resistor unit is connected to the third inverting unit, and a second end of the fourth resistor unit is grounded.

9. A chip, characterized in that: The invention comprises a power-on reset circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a device body and the chip as claimed in claim 9 arranged in the device body.

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