Power conversion circuit and power conversion method

Abstract

In order to further reduce the loss of a three-level circuit formed from a multi-gate IGBT and a MOS gate diode, the present invention comprises: a first unit circuit and a fourth unit circuit each of which are formed from a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode with a control terminal connected in anti-parallel to the semiconductor element; and a second unit circuit and a third unit circuit each of which are formed from a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode connected in anti-parallel to the semiconductor element. The first unit circuit, the second unit circuit, the third unit circuit, and the fourth unit circuit are connected in series in the stated order. The positive side terminal of the first unit circuit is connected to a positive power supply line, and the negative side terminal of the fourth unit circuit is connected to a negative power supply line. The intermediate potential between the positive power supply line and the negative power supply line is set as a neutral point terminal, and a connection point between the second unit circuit and the third unit circuit is set as an input / output terminal for one AC phase. The present invention comprises: a first clamp diode with a control terminal the cathode of which is connected to a connection point between the first unit circuit and the second unit circuit and the anode of which is connected to the neutral point terminal; and a second clamp diode with a control terminal the cathode of which is connected to the neutral point terminal and the anode of which is connected to a connection point between the third unit circuit and the fourth unit circuit.

Description

Power conversion circuit and power conversion method

[0001] The present invention relates to a power conversion circuit and a power conversion method that constitute a power conversion device, and is particularly suitable for a power conversion device that is constituted by a power semiconductor element having a diode with a gate control terminal.

[0002] Since their introduction as power semiconductor devices for power conversion equipment, IGBTs have undergone continuous performance improvement, with progress being made in increasing voltage resistance, output power, and loss. However, these performance improvements are approaching their limits.

[0003] Therefore, in order to further improve performance, in recent years, elements such as MOSFETs using so-called wide bandgap semiconductors, which use next-generation semiconductor materials such as SiC (silicon carbide) and GaN (gallium nitride) instead of Si (silicon), which has been used as the element material up to now, have been developed and are gradually becoming more widespread. However, wide bandgap semiconductor elements have higher material costs and manufacturing costs than conventional Si IGBTs, which poses a major challenge to their further widespread use.

[0004] Therefore, the multi-gate IGBT has been devised as a technology to reduce losses in IGBTs without using these expensive materials, and its development is underway. The multi-gate IGBT has an auxiliary gate electrode that controls the carrier concentration inside the IGBT, and by switching the auxiliary gate electrode on and off, it reduces losses when the current is cut off (when the device is turned off).

[0005] Specifically, when the IGBT is on, i.e., when the collector-emitter is in a conductive state, all gate electrodes are turned on to supply sufficient carriers (charges) into the IGBT, lowering the conduction resistance and reducing conduction loss.On the other hand, when the current is turned off, the auxiliary gate electrodes are turned off in advance a certain time before turn-off to reduce the carriers accumulated in the IGBT and reduce turn-off loss.

[0006] The technology for reducing losses using the auxiliary gate electrodes described above can be applied not only to switching elements such as IGBTs, but also to freewheeling diodes in inverter circuits, etc. In the case of these diodes, as with multi-gate IGBTs, it is possible to reduce both conduction loss and switching loss by controlling the carrier concentration depending on the conduction state or switching state.

[0007] To achieve this, a MOS (Metal-Oxide-Semiconductor) gated diode has been devised and is currently under development. A MOS gated diode has a MOS gate electrode that controls the carrier concentration inside the diode, and by switching the MOS gate electrode on and off, it reduces loss when the diode is turned off (during recovery).

[0008] Patent Document 1 discloses an example in which a MOS gate diode capable of gate control is used as a clamp diode, thereby making it possible to reduce losses in the clamp diode. Here, the freewheel diode disclosed in Patent Document 1 is a conventional diode without gate control.

[0009] To drive a MOS gate diode, a gate command for the diode must be given to the diode separately from the gate command for the IGBT. Patent Document 1 discloses a method in which, for a MOS gate diode connected in antiparallel to an IGBT, a gate command for the IGBT generated by a host controller is input to a gate driver, and the gate driver generates a gate command for the diode.

[0010] JP 2018-14880 A JP 2021-90026 A

[0011] The inventors of the present invention have conducted extensive research into further reducing the loss in a three-level circuit using a multi-gate IGBT and a MOS gate diode, and have come to the following findings.

[0012] Patent Document 1 discloses an example in which a gate-controlled MOS gate diode is used as a clamp diode to prevent a large surge current from placing an excessive load on electrical elements in an inverter. It also discloses that the diode is discharged before switching on one branch of the inverter, thereby reducing switching losses in that branch. However, the freewheeling diode is a conventional diode without gate control, and no consideration is given to reducing losses in the freewheeling diode.

[0013] Furthermore, the host controller of a three-level circuit using conventional IGBTs generates drive command signals for four IGBTs. In contrast, to reduce the loss of all elements in a three-level circuit using multi-gate IGBTs and MOS gated diodes, gate commands are required not only for the four series-connected multi-gate IGBTs and MOS gated diodes, but also for the MOS gated diodes used as clamp diodes, which necessitates the output of two additional gate commands from the host controller. Therefore, when changing the IGBTs and diodes that make up a conventional three-level circuit to multi-gate IGBTs and MOS gated diodes, the host controller also needs to be changed.

[0014] Furthermore, a gate driver board for driving the clamp diode must also be added, which increases the size, weight, and cost of the device.

[0015] Therefore, in order to solve the above problems, the present invention aims to further reduce losses in a three-level circuit composed of a multi-gate IGBT and a MOS gate diode, and preferably to provide a low-loss three-level circuit system that is compatible with conventional three-level circuit systems.

[0016] In order to solve the above problems, one of the power conversion circuits for one phase of a representative power conversion device according to the present invention for converting DC and AC mutually comprises a first unit circuit and a fourth unit circuit each composed of a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode with a control terminal connected in anti-parallel to the semiconductor element, and a second unit circuit and a third unit circuit each composed of a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode connected in anti-parallel to the semiconductor element, and the first unit circuit to the fourth unit circuit are connected in series in the order of the first unit circuit, the second unit circuit, the third unit circuit and the fourth unit circuit, The positive terminal of the first unit circuit is connected to a positive power supply line, the negative terminal of the fourth unit circuit is connected to a negative power supply line, the intermediate potential between the potentials of the positive power supply line and the negative power supply line is used as a neutral terminal, the connection point between the second unit circuit and the third unit circuit is used as an input / output terminal for one phase of AC, and the device is provided with a first clamp diode with a control terminal, the cathode of which is connected to the connection point between the first unit circuit and the second unit circuit and the anode of which is connected to the neutral terminal, and a second clamp diode with a control terminal, the cathode of which is connected to the neutral terminal and the anode of which is connected to the connection point between the third unit circuit and the fourth unit circuit. Preferably, the semiconductor device includes a first driver that drives and controls the semiconductor element and the diode with a control terminal that constitute the first unit circuit, a second driver that drives and controls the semiconductor element and the second clamp diode with a control terminal that constitute the second unit circuit, a third driver that drives and controls the semiconductor element and the first clamp diode with a control terminal that constitute the third unit circuit, and a fourth driver that drives and controls the semiconductor element and the diode with a control terminal that constitute the fourth unit circuit. Also, the second driver drives and controls the second clamp diode with a control terminal via an insulating element, and the third driver drives and controls the first clamp diode with a control terminal via an insulating element.

[0017] According to the present invention, by providing gates for all freewheel diodes and clamp diodes corresponding to current paths that generate recovery loss, the recovery loss can be reduced regardless of the current path between the positive or negative terminal and the input / output terminal, and the current path between the neutral terminal and the input / output terminal, including commutation (covering all patterns in which recovery loss occurs in a three-level circuit). Preferably, by applying low-loss multi-gate IGBTs and MOS gated diodes to a three-level circuit without changing the upper controller that controls the three-level circuit, the recovery loss can be reduced regardless of the current path, including commutation, thereby easily achieving low system loss. Furthermore, since no additional gate driver board is required, the device size can be kept the same as that of a conventional system, and multi-gate IGBTs and MOS gated diodes can be installed without design changes. This is expected to shorten the time required for development, design, and replacement work. Other issues, configurations, and advantages will be clarified in the following description of the embodiments.

[0018] Fig. 1 is a diagram showing a circuit for one phase constituting a power conversion device according to a first embodiment of the present invention. Fig. 2 is a diagram showing a timing chart of a gate command of a multi-gate IGBT, a MOS gate diode current, and a load voltage when a current flows from a load toward a main circuit. Fig. 3 is a diagram showing a timing chart of a gate command of a multi-gate IGBT, a MOS gate diode current, and a load voltage when a current flows from a main circuit toward a load. Fig. 4 is a diagram showing a circuit for one phase constituting a power conversion device according to a second embodiment of the present invention. Fig. 5 is a diagram showing a circuit for one phase constituting a power conversion device according to a third embodiment of the present invention.

[0019] Hereinafter, with reference to the drawings, a first to third embodiments of the present invention will be described as embodiments for carrying out the present invention. Note that the present invention is not limited to these embodiments. In addition, in the drawings, the same parts are denoted by the same reference numerals.

[0020] 1 is a diagram showing a circuit for one phase constituting a power conversion device according to a first embodiment of the present invention. The circuit shown in Fig. 1 is one phase of a DC / AC power conversion device that converts DC and AC mutually, that is, a so-called converter / inverter circuit.

[0021] Three power sources, a DC positive power source (+E [V]), a neutral point (0 [V]), and a negative power source (-E [V]), are connected to a DC power source positive terminal 232, a DC power source neutral point terminal 231, and a DC power source negative terminal 233, respectively, and power is converted by operating multi-gate IGBTs 235 to 238 in a predetermined order.

[0022] MOS gate freewheel diodes 201 and 204 are connected in antiparallel to the multi-gate IGBTs 235 and 238, respectively. In addition, MOS gate clamp diodes 205 and 206 are connected as clamp diodes between the neutral point and the emitter of the multi-gate IGBT 235 and between the neutral point and the collector of the multi-gate IGBT 238, respectively.

[0023] Gate command lines 002 to 009 are connected from the host controller 001 to the gate drivers 101 to 104, and gate commands are input from the host controller 001. The signals input to the gate drivers 101 to 104 are transmitted in an insulated manner by an insulating circuit using a photocoupler (not shown) inside the driver, and are amplified by an amplifier circuit or the like.

[0024] The amplified gate signals are output to the main gate voltage output terminals 107, 111, 115 and 119, the auxiliary gate voltage output terminals 108, 112, 116 and 120, and the diode voltage output terminals 109, 113, 117 and 121, respectively, with the auxiliary emitter potential terminals 110, 114, 118 and 122 as references, and control the multi-gate IGBTs 235 to 238, the MOS gate freewheel diodes 201 and 204, and the MOS gate clamp diodes 205 and 206.

[0025] As described above, the multi-gate IGBTs 235 to 238, the MOS gate freewheel diodes 201 and 204, and the MOS gate clamp diodes 205 and 206 have auxiliary gates for reducing loss, and by appropriately controlling these, conduction and switching losses can be reduced.

[0026] That is, in the present invention, including this first embodiment and embodiments 2 and 3 described below, by providing gates to all of the freewheel diodes and clamp diodes corresponding to current paths in which recovery loss occurs, it is possible to achieve a reduction in recovery loss regardless of the path taken by the current path between the positive terminal or negative terminal and the input / output terminal and the current path between the neutral terminal and the input / output terminal, including commutation (covering all patterns in which recovery loss occurs in a three-level circuit).

[0027] Next, the features of the present embodiment 1 will be described. The first feature is that MOS gate diodes are applied to the freewheel diodes 201 and 204 and the clamp diodes 205 and 206, and conventional PN diodes or Schottky barrier diodes without gate electrodes are applied to the freewheel diodes 202 and 203.

[0028] The freewheeling diodes 202 and 203 in the three-level main circuit do not generate recovery loss because no voltage is applied between the anode and cathode when the current is commutated. Therefore, these diodes may be configured as conventional PN diodes or Schottky barrier diodes without MOS gates.

[0029] The second feature is that the gate driver 102 drives the MOS gate clamp diode 206 , and the gate driver 103 drives the MOS gate clamp diode 205 .

[0030] Since the freewheel diodes 202 and 203 do not require gate control, if the MOS gate clamp diodes 205 and 206 are driven by the gate control signal that is no longer required, it becomes possible to control all the MOS gate diodes without increasing the number of gate drivers.

[0031] Furthermore, since the number of gate drivers does not increase, there is no need to increase the number of command signals supplied from the host controller, and there is also the advantage that the host controller for conventional three-level circuit control can be used as is. The reason why the MOS gate clamp diode 206 is driven by the gate driver 102 and the MOS gate clamp diode 205 is driven by the gate driver 103 will be described later.

[0032] Furthermore, in this embodiment 1, a photocoupler 303 and an input buffer circuit 304 are provided between the MOS gate clamp diode 205 and the gate driver 103, and a photocoupler 301 and an input buffer circuit 302 are provided between the MOS gate clamp diode 206 and the gate driver 102, thereby providing insulation between them. The reason for this is to prevent overcurrent from occurring due to the potential difference between the auxiliary emitter terminal 214 and the auxiliary anode terminal 230, and the potential difference between the auxiliary emitter terminal 218 and the auxiliary anode terminal 226.

[0033] Here, the occurrence of an overcurrent will be described using the potential difference between the auxiliary emitter terminal 214 and the auxiliary anode terminal 230 as an example. If the diode gate voltage output terminal 113 and the MOS clamp diode gate terminal 229, and the auxiliary emitter potential terminal 114 and the MOS clamp diode anode terminal 230 were directly connected, the multi-gate IGBTs 235 and 236 would turn on and a positive power supply voltage (+E [V]) would be output to the AC input / output terminal 234. Then, the potential of the auxiliary emitter terminal 214 would be +E [V], while the potential of the auxiliary anode terminal 230 would be clamped to the potential of the DC power supply neutral terminal 231 and become 0 [V], resulting in a potential difference of E [V] between the auxiliary emitter terminal 214 and the auxiliary anode terminal 230. This causes an overcurrent to flow from the auxiliary emitter terminal 214 to the auxiliary anode terminal 230.

[0034] In this way, if the auxiliary emitter terminal and auxiliary anode terminal, which have different potentials, are directly connected, an overcurrent will flow due to the potential difference, so the above-mentioned insulation is used to prevent this overcurrent.On the other hand, the input buffer circuits 302 and 304 are necessary when the outputs of the photocouplers 301 and 303 cannot supply a sufficient voltage to the gate electrodes of the MOS gate diodes.

[0035] The isolation means is not limited to a photocoupler, and other methods such as an isolation transformer may be used. Also, the isolation point may be provided between the gate driver 102 (103) and the multi-gate IGBT 236 (237) as long as the system does not suffer from operational delays caused by the photocoupler and input buffer affecting the operation of the circuit.

[0036] Next, detailed operation of the circuit according to the first embodiment will be described. Hereinafter, "on" and "off" refer to steady states in which the gate voltage is "on" and "off," respectively. Furthermore, "turn-on" and "turn-off" refer to states in which the gate voltage is "changing from off to on" and "changing from on to off," respectively. Here, the "gate" of a multi-gate IGBT refers to the "main gate" unless otherwise specified.

[0037] 2 and 3 are timing charts showing the gate command of the multi-gate IGBT, the current of the MOS gate diode, and the load voltage when current flows from the load to the main circuit and when current flows from the main circuit to the load. Fig. 2 shows the operation mode when current flows from the load (AC input / output terminal 234 in Fig. 1) to the main circuit.

[0038] A1, B1, C1 and D1 are gate commands input to the multi-gate IGBTs 235, 236, 237 and 238, respectively; E1 is a gate command input to the MOS gate freewheel diode 201; and F1 is a gate command input to the MOS gate clamp diode 206.

[0039] Furthermore, G1 indicates the current of the MOS gate freewheel diode 201 (positive in the anode to cathode direction), H1 indicates the current of the MOS gate clamp diode 206 (positive in the anode to cathode direction), and I1 indicates the potential of the AC input / output terminal 234 when the DC power supply neutral terminal 231 is used as a reference.

[0040] At time t1, multi-gate IGBTs 235 (A1 in FIG. 2) and 236 (B1 in FIG. 2) are in the on state, and considering the current direction, current flows from AC input / output terminal 234 shown in FIG. 1 through freewheel diode 202 and MOS gate freewheel diode 201 to DC power supply positive terminal 232. Therefore, the potential of AC input / output terminal 234 (I1 in FIG. 2) becomes a positive potential (+E [V]).

[0041] At time t2, the gate command A1 of the multi-gate IGBT 235 is turned off, but the current path does not change because the current flows through the freewheel diode 202 and the MOS gate freewheel diode 201.

[0042] At time t4, when the multi-gate IGBT 237 (C1 in FIG. 2) is turned on, the current path is commutated from the MOS gate freewheel diode 201 to the multi-gate IGBT 237, and flows through the AC input / output terminal 234, the multi-gate IGBT 237, and the MOS gate clamp diode 206 to the DC power supply neutral terminal 231. At this time, the potential of the AC input / output terminal 234 (I1 in FIG. 2) changes from +E [V] to 0 [V].

[0043] If C1 (multi-gate IGBT 237) is accidentally turned on at time t2 before A1 (multi-gate IGBT 235) is turned off, A1, B1 (multi-gate IGBT 236), and C1 will all be turned on. As a current path, a power supply short-circuit path is formed from the DC power supply positive terminal 232 through the multi-gate IGBT 235, the multi-gate IGBT 236, the multi-gate IGBT 237, and the MOS gate clamp diode 206 to the DC power supply neutral terminal 231, as shown in FIG. This generates an overcurrent and leads to destruction of elements in the short-circuit path.

[0044] To prevent this, A1 is turned off at time t2, and then C1 is turned on at time t4 after the lapse of dead time Td, thereby preventing an overcurrent without forming a short circuit path.

[0045] For the same reason, dead times Td are also provided in the following periods: from time t6 when B1 turns off to time t8 when D1 (multi-gate IGBT 238) turns on; from time t10 when D1 turns off to time t12 when B1 turns on; and from time t14 when C1 turns off to time t16 when A1 turns on.

[0046] At time t4, when the diode current is commutated to another path (another element), a temporary reverse current flows as carriers accumulated inside the diode are discharged, and this reverse current causes recovery loss. At this time, if the carrier concentration inside the diode is high immediately before commutation, the reverse current becomes large, resulting in large recovery loss. To reduce this loss in a MOS-gated diode, E1 (MOS-gated freewheeling diode 201) is turned on from time t3, a period T1 before time t4, to reduce the carrier concentration inside the diode in advance. This reduces recovery loss.

[0047] Here, the period T1 is the time required for the carrier concentration to be sufficiently reduced after the MOS diode is turned on. The minimum time for T1 varies depending on the device characteristics of the multi-gate IGBT. Furthermore, the period T2 is a margin time to prevent E1 from turning off before C1 turns on due to variations in pulse width. The greater the variation in the time from the turn-on command from the upper controller 001 to the application of a positive bias between the gate and emitter of the multi-gate IGBT in the main circuit, the longer the period T2 required.

[0048] At time t6, the gate command B1 of the multi-gate IGBT 236 is turned off, but the current path does not change because the current flows through the multi-gate IGBT 237 and the MOS gate clamp diode 206.

[0049] At time t8, when the multi-gate IGBT 238 is turned on, the current is commutated from the MOS gate clamp diode 206 to the multi-gate IGBT 238, and the current path becomes the path shown in Fig. 1 that passes through the AC input / output terminal 234, the multi-gate IGBT 237, and the multi-gate IGBT 238 and flows into the DC power supply negative terminal 233. At this time, the potential of the AC input / output terminal 234 (I1 in Fig. 2) changes from 0 [V] to -E [V].

[0050] Furthermore, since recovery loss occurs in the MOS gate clamp diode 206, similarly to the MOS gate freewheel diode 201, the recovery loss can be reduced by turning on F1 (MOS gate clamp diode 206) from time t7, which is a period T1 before time t8.

[0051] Thereafter, D1 is turned off (time t10), B1 is turned on (time t12), C1 is turned off (time t14), A1 is turned on (time t16), and then the state returns to that of time t1.

[0052] Between time t10 and time t17, the current path of the main circuit and the potential of the AC input / output terminal 234 fluctuate due to control of the multi-gate IGBT, but since neither the freewheel diode nor the clamp diode generates recovery loss, the gate control of the diodes is always off.

[0053] As described above, the gate command E1 of the MOS gate freewheel diode 201 is turned on after a period Td-T1 from the turn-off of the multi-gate IGBT 235 shown in A1 of FIG. 2, and turned off after a period T1+T2 from this turn-on.

[0054] Therefore, the gate command E1 of the MOS gate freewheel diode 201 can be generated by the gate driver 101, which receives the gate command of the multi-gate IGBT 235. Similarly, the gate command F1 of the MOS gate clamp diode 206 can be generated by the gate driver 102, which receives the gate command of the multi-gate IGBT 236. This is the reason why the MOS gate clamp diode 206 is driven by the gate driver 102, and the MOS gate clamp diode 205 is driven by the gate driver 103.

[0055] 3 shows an operation mode in which current flows out from the main circuit toward the load (AC input / output terminal 234 in FIG. 1). A1, B1, C1, D1, and I1 are the same as those in FIG. 2. E2 indicates the gate command input to the MOS gate freewheel diode 204, F2 indicates the gate command input to the MOS gate clamp diode 205, G2 indicates the current of the MOS gate freewheel diode 204 (positive from the anode to the cathode), and H2 indicates the current of the MOS gate clamp diode 205 (positive from the anode to the cathode).

[0056] At time t1, multi-gate IGBTs 235 (A1 in FIG. 3) and 236 (B1 in FIG. 3) are in the on state, and considering the current direction, current flows from DC power supply positive terminal 232 shown in FIG. 1 through multi-gate IGBT 235 and multi-gate IGBT 236 to AC input / output terminal 234. Therefore, the potential of AC input / output terminal 234 (I1 in FIG. 3) becomes a positive potential (+E [V]).

[0057] Thereafter, A1 turns off (time t2), C1 turns on (time t4), B1 turns off (time t6), and D1 turns on (time t8).

[0058] Between time t1 and time t10, the current path of the main circuit and the potential of the AC input / output terminal 234 fluctuate due to control of the multi-gate IGBT, but since no recovery loss occurs in either the freewheel diode or the clamp diode, the gate control of the diode is always off.

[0059] At time t12, when the multi-gate IGBT 236 (B1 in FIG. 3) is turned on, the current is commutated from the MOS gate freewheel diode 204 to the multi-gate IGBT 236, passes through the DC power supply neutral terminal 231, the MOS gate clamp diode 205, and the multi-gate IGBT 236, and flows out to the AC input / output terminal 234. At this time, as shown by I1 in FIG. 3, the potential of the AC input / output terminal 234 changes from −E [V] to 0 [V].

[0060] At time t14, the multi-gate IGBT 237 (C1 in FIG. 3) is turned off, but the current flows through the MOS gate clamp diode 205 and the multi-gate IGBT 236, so there is no change in the current path.

[0061] At time t16, when the multi-gate IGBT 235 (A1 in FIG. 3) is turned on, the current is commutated from the MOS gate clamp diode 205 to the multi-gate IGBT 235, and flows through the DC power supply positive terminal 232, the multi-gate IGBT 235, and the multi-gate IGBT 236 to the AC input / output terminal 234. At this time, as shown by I1 in FIG. 3, the potential of the AC input / output terminal 234 changes from 0 [V] to +E [V].

[0062] Furthermore, since recovery loss occurs in the MOS gate clamp diode 205, similarly to the MOS gate freewheel diode 201, the recovery loss can be reduced by turning on the MOS gate clamp diode 205 (F2 in FIG. 3) from time t15, which is a period T1 before time t16.

[0063] As described above, the gate command E2 of the MOS gate freewheel diode 204 is turned on after a period Td-T1 from the turn-off of the multi-gate IGBT 238, as shown by D1 in FIG. 3, and turned off after a period T1+T2 from this turn-on.

[0064] Therefore, the gate command E2 of the MOS gate freewheel diode 204 can be generated by the gate driver 104 that receives the gate command of the multi-gate IGBT 238. Similarly, the gate command F2 of the MOS gate clamp diode 205 can be generated by the gate driver 103 that receives the gate command C1 of the multi-gate IGBT 237.

[0065] To summarize the above operation modes, the gate commands for MOS gate clamp diodes 205 and 206 can be generated by gate drivers 103 and 102, respectively, and the gate commands for MOS gate freewheel diodes 201 and 204 can be generated by gate drivers 101 and 104, respectively.

[0066] In addition, the diode gate commands E1 and F1 in Fig. 2 and E2 and F2 in Fig. 3 are all generated using the same logic, so these gate drivers can be commonly applied to both clamp diodes and freewheeling diodes.

[0067] 4 is a diagram showing a circuit for one phase constituting a power conversion device according to a second embodiment of the present invention. Here, components common to those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals.

[0068] A feature of the second embodiment is that independent gate drivers 105 and 106 are provided for the gates of MOS gate clamp diodes 205 and 206. The command signals input to these gate drivers 105 and 106 are branched and taken in from gate commands 006 and 007 and gate commands 004 and 005 from the upper controller 001, respectively.

[0069] Furthermore, the gate command generation logic of the gate driver 105 for the MOS gate clamp diode 205 is the same as the gate command generation logic of the gate driver 103, and the gate command generation logic of the gate driver 106 for the MOS gate clamp diode 206 is the same as the gate command generation logic of the gate driver 102.

[0070] In the first embodiment described above, commands are transmitted via photocouplers 301 and 303 and input buffer circuits 302 and 304 to insulate MOS gate clamp diodes 205 and 206. However, the photocouplers and buffer circuits have an operational delay, and the operation of only the MOS gate clamp diodes is delayed compared to the other elements. For this reason, when applying this to a system that requires highly accurate control of operation timing, it is necessary to eliminate this delay.

[0071] In the second embodiment, gate drivers 105 and 106 each having an internal isolation photocoupler are added for MOS gate clamp diodes 205 and 206, thereby eliminating the isolation photocoupler and buffer circuit and preventing the operation delay caused by them.

[0072] Therefore, it is desirable to apply the first embodiment to a system that places importance on reducing the mounting space for the gate driver, and to apply the second embodiment to a system that requires highly accurate gate control.

[0073] 5 is a diagram showing a circuit for one phase constituting a power conversion device according to a third embodiment of the present invention, in which components common to those in the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 4 are denoted by the same reference numerals.

[0074] The feature of the third embodiment is that all the components in the circuit are the same multi-gate IGBTs and MOS gate diodes. Generally, IGBTs and freewheeling diodes are connected in anti-parallel and housed in the same package. Therefore, if conventional PN diodes were used for the freewheeling diodes 202 and 203 and only diodes were used for the clamping diodes 205 and 206, as in the first embodiment shown in FIG. 1, it would be necessary to obtain or develop new dedicated elements, and it would also be cumbersome to manage multiple types of elements.

[0075] In the third embodiment, all the components are identical, which solves the procurement and management problems described above. To replace all the components with multi-gate IGBTs, the multi-gate IGBTs 239 and 240 shown in FIG. 5 must be kept off at all times. Therefore, for the multi-gate IGBT 239, the main gate terminal 223 and the auxiliary gate 224 must be short-circuited to the auxiliary emitter 226. Similarly, for the multi-gate IGBT 240, the main gate terminal 227 and the auxiliary gate 228 must be short-circuited to the auxiliary emitter 230. Alternatively, a separate power supply must be provided to constantly apply a negative bias to each gate terminal of the multi-gate IGBTs 239 and 240.

[0076] Furthermore, in the present embodiment 3, a gate voltage is input to the MOS gate freewheel diodes 241 and 242. However, as described above, these MOS gate diodes do not generate recovery loss during operation, and therefore the main circuit loss is unchanged compared to the previous embodiments 1 and 2.

[0077] However, in the configuration of the present embodiment 3, the multi-gate IGBT and the MOS gate diode element are common, and the wiring connections to the gate driver are also common to the greatest extent possible, so that it is possible to expect both effects of reducing costs by using the same materials and reducing the rate of work defects during manufacturing.

[0078] Although the first to third embodiments have been described above as modes for carrying out the present invention, the present invention is not limited to these embodiments, and various modifications are possible within the scope of the present invention.

[0079] 001: Upper controller, 002 to 009: Gate command lines, 101 to 106: Gate drivers, 107, 111, 115, 119, 123, 127: Main gate voltage output terminals of IGBT, 108, 112, 116, 120, 124, 128: Auxiliary gate voltage output terminals of IGBT, 109, 113, 117, 121, 125, 129: Diode gate voltage output terminals, 110, 114, 118, 122, 126, 130: Auxiliary emitter potential terminals, 201, 204, 241, 242: MOS gate freewheel diodes, 202, 203: Freewheel diodes, 205, 206: MOS gate clamp diodes diodes, 207, 211, 215, 219, 223, 227: main gate terminals of IGBTs, 208, 212, 216, 220, 224, 228: auxiliary gate terminals of IGBTs, 209, 213, 217, 221, 225, 229: gate terminals of diodes, 210, 214, 218, 222: auxiliary emitter terminals, 226, 230: auxiliary anode terminals, 231: neutral terminal of DC power supply, 232: positive terminal of DC power supply, 233: negative terminal of DC power supply, 234: AC input / output terminal, 235, 236, 237, 238, 239, 240: multi-gate IGBTs, 301, 303: photocouplers, 302, 304: input buffer circuits

Claims

1. A power conversion circuit for one phase of a power conversion device for converting direct current and alternating current mutually, comprising: a first unit circuit and a fourth unit circuit each composed of a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode with a control terminal connected in anti-parallel to the semiconductor element; a second unit circuit and a third unit circuit each composed of a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode connected in anti-parallel to the semiconductor element; the first unit circuit to the fourth unit circuit are connected in series in the order of the first unit circuit, the second unit circuit, the third unit circuit and the fourth unit circuit; a positive terminal of the first unit circuit is connected to a positive power supply line and a negative terminal of the fourth unit circuit is connected to a negative power supply line; an intermediate potential between the positive power supply line and the negative power supply line is set as a neutral terminal; a connection point between the second unit circuit and the third unit circuit is set as an input / output terminal for one phase of alternating current; a first clamp diode with a control terminal, the cathode of which is connected to a connection point between the first unit circuit and the second unit circuit and the anode of which is connected to the neutral terminal; and a second clamp diode with a control terminal, the cathode of which is connected to the neutral terminal and the anode of which is connected to a connection point between the third unit circuit and the fourth unit circuit.

2. A power conversion circuit as claimed in claim 1, comprising: a first driver which drives and controls the semiconductor element and the diode with a control terminal which constitute the first unit circuit; a second driver which drives and controls the semiconductor element and the second clamp diode with a control terminal which constitute the second unit circuit; a third driver which drives and controls the semiconductor element and the first clamp diode with a control terminal which constitute the third unit circuit; and a fourth driver which drives and controls the semiconductor element and the diode with a control terminal which constitute the fourth unit circuit.

3. A power conversion circuit as claimed in claim 2, characterized in that the second driver drives and controls the second clamp diode with a control terminal via an insulating element, and the third driver drives and controls the first clamp diode with a control terminal via an insulating element.

4. A power conversion circuit as claimed in claim 1, comprising: a first driver that drives and controls the semiconductor element and the diode with a control terminal that constitute the first unit circuit; a second driver that drives and controls the semiconductor element that constitutes the second unit circuit; a third driver that drives and controls the semiconductor element that constitutes the third unit circuit; a fourth driver that drives and controls the semiconductor element and the diode with a control terminal that constitutes the fourth unit circuit; a fifth driver that drives and controls the first clamp diode with a control terminal; and a sixth driver that drives and controls the second clamp diode with a control terminal.

5. A power conversion circuit as claimed in claim 4, characterized in that the fifth driver uses the drive command input to the third driver as its own drive command, and the sixth driver uses the drive command input to the second driver as its own drive command.

6. A power conversion circuit according to claim 1, comprising: the diodes of each of the second unit circuit and the third unit circuit are both configured as diodes with control terminals that can be gate-controlled; a semiconductor element having a pair of main terminals and a plurality of control terminals is additionally connected between the connection point between the first unit circuit and the second unit circuit and the neutral terminal in such a manner that a first clamp diode with the control terminal is connected in anti-parallel to the semiconductor element, forming a fifth unit circuit composed of the semiconductor element and the first clamp diode with the control terminal; a semiconductor element having a pair of main terminals and a plurality of control terminals is additionally connected between the neutral terminal and the connection point between the third unit circuit and the fourth unit circuit in such a manner that a second clamp diode with the control terminal is connected in anti-parallel to the semiconductor element, forming a sixth unit circuit composed of the semiconductor element and the second clamp diode with the control terminal; a first driver that drives and controls the semiconductor element and the diode with the control terminal that constitute the first unit circuit; a second driver that drives and controls the semiconductor element and the diode with a control terminal that constitute the second unit circuit; a third driver that drives and controls the semiconductor element and the diode with a control terminal that constitute the third unit circuit; a fourth driver that drives and controls the semiconductor element and the diode with a control terminal that constitute the fourth unit circuit; a fifth driver that drives and controls the diode with a control terminal that constitutes the fifth unit circuit; and a sixth driver that drives and controls the diode with a control terminal that constitutes the sixth unit circuit, wherein each of the semiconductor elements that constitute the fifth unit circuit and the sixth unit circuit is always turned off.

7. A power conversion circuit as claimed in claim 6, characterized in that the gate terminals of the semiconductor elements constituting the fifth unit circuit and the sixth unit circuit are connected to a negative bias, so that each of the semiconductor elements is always off.

8. A power conversion circuit as claimed in claim 6 or 7, characterized in that the fifth driver uses the drive command input to the third driver as its own drive command, and the sixth driver uses the drive command input to the second driver as its own drive command.

9. A power conversion circuit as claimed in any one of claims 1 to 8, characterized in that the semiconductor elements constituting each of the unit circuits are multi-gate IGBTs, and the diode with a control terminal and the first and second clamp diodes with a control terminal are MOS gate diodes.

10. A power conversion method using a power conversion circuit for one phase of a power conversion device that converts direct current and alternating current mutually, comprising: controlling and driving a semiconductor element and a diode with a control terminal that constitute a first unit circuit, the semiconductor element having a pair of main terminals and multiple control terminals, and a diode with a control terminal connected inversely parallel to the semiconductor element, based on a first drive command; controlling and driving a semiconductor element and a diode with a control terminal that constitute a second unit circuit, the semiconductor element having a pair of main terminals and multiple control terminals, and a diode connected inversely parallel to the semiconductor element, based on a second drive command; controlling and driving a semiconductor element and a diode with a control terminal that constitute a third unit circuit, the semiconductor element having a pair of main terminals and multiple control terminals, and a diode connected inversely parallel to the semiconductor element, based on a third drive command; controlling and driving a semiconductor element and a diode with a control terminal that constitute a fourth unit circuit, the semiconductor element having a pair of main terminals and multiple control terminals, and a diode with a control terminal connected inversely parallel to the semiconductor element, based on a fourth drive command; a first clamp diode with a control terminal, the cathode of which is connected to a connection point between the first unit circuit and the second unit circuit and the anode of which is connected to a neutral terminal at an intermediate potential between a positive power supply line to which a positive terminal of the first unit circuit is connected and a negative power supply line to which a negative terminal of the fourth unit circuit is connected, is driven and controlled based on the third drive command; and a second clamp diode with a control terminal, the cathode of which is connected to the neutral terminal and the anode of which is connected to a connection point between the third unit circuit and the fourth unit circuit, is driven and controlled based on the second drive command.

11. A power conversion method according to claim 10, comprising: configuring the diode of the second unit circuit as a diode with a gate-controllable control terminal and controlling its operation based on the second operation command; configuring the diode of the third unit circuit as a diode with a gate-controllable control terminal and controlling its operation based on the third operation command; and connecting a semiconductor element having a pair of main terminals and a plurality of control terminals between a connection point between the first unit circuit and the second unit circuit and the neutral terminal, with the first clamp diode with control terminal being connected in inverse parallel to the semiconductor element, and the first clamp diode with control terminal constituting a fifth unit circuit composed of the semiconductor element and the first clamp diode with control terminal, and controlling the operation of the first clamp diode with control terminal based on the third operation command; a semiconductor element having a pair of main terminals and a plurality of control terminals is additionally connected between the neutral terminal and a connection point between the third unit circuit and the fourth unit circuit in such a manner that a second clamp diode with a control terminal is connected in inverse parallel to the semiconductor element, the second clamp diode with a control terminal constituting a sixth unit circuit constituted by the semiconductor element and the second clamp diode with a control terminal is driven and controlled based on the second drive command, and each of the semiconductor elements constituting the fifth unit circuit and the sixth unit circuit is always turned off.

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