Comparator array comprising a kickback compensation circuit and method to perform kickback compensation

Abstract

The present disclosure relates to an array of comparators (120). The comparators (120) of the array are configured to operate in parallel, one input terminal of each of the comparators (120) being connected to a common ramp generator (110). The array further comprises a kickback compensation circuit (105) for subtracting a kickback compensation value from a digital value output by each of the comparators (120).

Description

[0001] COMPARATOR ARRAY COMPRISING A KICKBACK COMPENSATION CIRCUIT

[0002] AND METHOD TO PERFORM KICKBACK COMPENSATION

[0003] Comparators are used in a plurality of applications such as digital converters , semiconductor memories and PLLs . In particular, they are used in analog-to-digital converters (ADC ) and, therefore may be a component of an image sensor .

[0004] A comparator compares an input voltage with a reference voltage and switches its output to indicate the higher voltage . The point in time of switching may also be referred to a as a "triggering" . In an array of comparators which are configured to operate in parallel , e . g . for a use in a column-parallel image sensor, the reference voltage input terminal of a plurality of comparators may be connected to a common ramp generator . When one of the comparators starts latching an input , there may be a large voltage variation across elements of the comparator . This variation in voltage may result in charges being " kicked back" to the input of the further comparators . The charge may be linearly linked to the si ze of the input di f ferential pair and the load thereof . As a result , an input voltage of the further comparators may change . Hence , the accuracy of the comparators may be reduced . This ef fect af fects the ramp reference for all parallel comparators .

[0005] Generally, attempts are being made to compensate kickback ef- f ects .

[0006] It is an obj ect of the present invention to provide an improved array of comparators . SUMMARY

[0007] According to embodiments , the above obj ect is achieved by the claimed matter according to the independent claims . Further developments are defined in the dependent claims .

[0008] According to embodiments , an array of comparators comprises comparators that are configured to operate in parallel , one input terminal of each of the comparators being connected to a common ramp generator . The array further comprising a kickback compensation circuit for subtracting a kickback compensation value from a digital value output by each of the comparators .

[0009] For example , the compensation circuit may be configured to determine a parameter indicating an order in which the comparators of the array have been triggered, wherein the compensation value for a speci fic digital value depends on the parameter .

[0010] According to embodiments , the compensation circuit is configured to assign the digital values output by the comparators to groups corresponding to a respective one of the digital values , a speci fic compensation value being assigned to each of the groups , wherein the compensation circuit further comprises a subtracting unit for subtracting the speci fic compensation values from the digital values , respectively .

[0011] For example , assigning may comprise determining histogram boundaries based on statistical methods .

[0012] According to further embodiments , determining the histogram boundaries may comprise determining a mean value and a standard deviation of the digital values and computing histogram boundaries using statistical quantiles . For example , assigning may comprise determining an initial histogram comprising H initial bins and reducing the H initial bins to C correction bins , wherein a distribution of the digital values in the C correction bins is more uni form than the distribution of the digital values in the H initial bins .

[0013] For example , H may be a power of 2 .

[0014] According to embodiments , the kickback compensation circuit may comprise a histogram storage for storing the initial histogram and a bin memory for storing the digital values and an identi fier of the corresponding correction bin .

[0015] According to further embodiments , the kickback compensation circuit may comprise an auxil iary memory for storing the digital values and the corresponding kickback compensation values . For example , the auxiliary memory may be further configured to store the initial histogram .

[0016] According to embodiments , an image sensor comprises the array of comparators according to any of the preceding claims .

[0017] An electronic device may comprise the image sensor as described above . For example , the electronic device may be a camera or a smart phone .

[0018] The present disclosure further relates to a method to perform kickback compensation on values generated by an array of comparators configured to operate in parallel . One input terminal of each of the comparators is connected to a common ramp generator . The method may comprise determining, by each of the comparators , a digital value , determining a kickback compensation value for each of the digital values , and subtracting, for each of the digital values , the kickback compensation value from the digital value .

[0019] For example , determining the kickback compensation value may comprise determining a parameter indicating an order in which the comparators of the array have been triggered, wherein the compensation value for a speci fic digital value depends on the parameter .

[0020] According to embodiments , determining the parameter may comprise assigning the digital values output by the comparators to groups corresponding to a respective one of the digital values , a speci fic compensation value being assigned to each of the groups .

[0021] BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this speci fication . The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles . Other embodiments of the invention and many of the intended advantages will be readily appreciated, as they become better understood by reference to the following detailed description . The elements of the drawings are not necessarily to scale relative to each other . Like reference numbers designate corresponding similar parts .

[0023] Fig . 1A is a schematic drawing of an image sensor which may comprise an array of comparators .

[0024] Fig . IB summari zes a method according to embodiments . Fig. 1C summarizes a method according to further embodiments.

[0025] Figs. 2A to 2C illustrate elements of an array of comparators when performing kickback compensation according to embodiments .

[0026] Fig. 2D shows a histogram and an example of a distribution of pixel values.

[0027] Fig. 2E summarizes a method according to embodiments.

[0028] Figs. 3A to 3C illustrate elements of an array of comparators when performing kickback compensation according to further embodiments .

[0029] Fig. 4A shows an example of a histogram of pixel values.

[0030] Fig. 4B illustrates an example of a cumulative histogram.

[0031] Fig. 4C shows an example of binning.

[0032] Fig. 4D shows a further example of binning.

[0033] Figs. 5A to 5C show elements of an array of comparators when performing kickback compensation.

[0034] Fig. 5D summarizes a method according to further embodiments.

[0035] Fig. 6 shows an example of an electronic device according to embodiments .

[0036] DETAILED DESCRIPTION In the following detailed description reference is made to the accompanying drawings , which form a part hereof and in which are illustrated by way of illustration speci fic embodiments in which the invention may be practiced . In this regard, directional terminology such as " top" , "bottom" , " front" , "back" , "over" , "on" , " above" , " leading" , " trailing" etc . is used with reference to the orientation of the Figures being described . Since components of embodiments of the invention can be positioned in a number of di f ferent orientations , the directional terminology is used for purposes of illustration and is in no way limiting . It is to be understood that other embodiments may be utili zed and structural or logical changes may be made without departing from the scope defined by the claims .

[0037] The description of the embodiments is not limiting . In particular, elements of the embodiments described hereinafter may be combined with elements of di f ferent embodiments .

[0038] Fig . 1A shows an example of an image sensor 10 which may employ an array of comparators 120 . For example , the image sensor 10 may comprise an array of pixels 100 which may be arranged in rows and columns . For example , the image sensor 10 may be implemented as a CMOS ("complementary metal oxide semiconductor" ) image sensor . Generally, each of the pixels may comprise a photodiode electrically connected to a plurality of transistors to perform readout of charges generated by incident electromagnetic radiation . The image sensor 10 may further comprise a plurality of row select lines 101 which are connected to pixels 100 of one row . The image sensor 10 further may comprise a plurality of column buses 102 which are connected to columns of pixels 100 . Voltages generated due to incident electromagnetic radiation may be read via the column bus 102 to an analog-to-digital converter (ADC ) 125 . Usually, an image sensor 10 comprises an array of analog-to-digital converters 125 , each of the ADCs being assigned to a corresponding one of the column buses 102 . Each of the ADCs may comprise a comparator 120 which compares the voltage supplied by the column bus 102 with a reference voltage . A digital output is generated by each of the comparators 120 . One input terminal of each of the comparators 120 , i . e . a reference voltage input terminal is connected to a ramp generator 110 . I t is to be noted that the above description of the image sensor 10 is merely by way of illustration . The present disclosure may be applied to any array of comparators 120 connected to a common ramp generator 110 .

[0039] As is illustrated in Fig . 1A, the input terminal of each of the comparators 120 is connected to a common ramp generator 110 . As will be explained in the following, the array of comparators 120 shown e . g . in Fig . 1A comprises a kickback compensation circuit 105 for subtracting a kickback compensation value from a digital value output by each of the comparators 120 . For example , the circuit arrangement of Fig . 1A may further comprise a lookup table 107 which stores appropriate compensation values . These compensation values may be subtracted from the digital value output by each of the comparators .

[0040] Generally, the kickback charge accumulates each time a comparator 120 triggers . As a consequence , comparators 120 which trigger first are af fected least , whereas comparators which trigger last are af fected most by the previous kickbacks . Accordingly, the compensation circuit 105 may be configured to determine a parameter indicating an order in which the comparators of the array have been triggered . The compensation value for a speci fic digital value depends on the parameter or the position within the order and, hence , depends on the digital value itsel f . Further, the kickback charge from a single trigger event is less than one LSB ( least signi ficant bit ) . Therefore , multiple trigger events can be grouped together before a non-negligible amount of charge has been accumulated . As a result , only a rough order of the trigger events needs to be determined . Consequently, time and power may be saved .

[0041] Accordingly, for example , the compensation circuit 105 may be configured to assign the digital values output by the comparators 120 to groups or bins which correspond to a respective one of the digital value . Further, a speci fic compensation value may be assigned to each of the groups or bins .

[0042] As has been explained above , the compensation circuit 105 performs kickback compensation for the digital value output by each of the comparators . Accordingly, a digital compensation is performed . This compensation may be more ef ficient and may be more configurable and may be auto-routed . In particular, one single compensation circuit 105 may be assigned to the array of comparators 120 . As a consequence , the compensation circuit 105 may be smaller than analog compensation devices and may consume less power than analog compensation devices .

[0043] The compensation circuit 105 may perform compensation based on a parameter indicating an order in which the single comparators 120 have triggered . According to embodiments , the order may be determined in multiple ways . The correction of fset which is applied may e . g . be stored in a simple lookup table . Alternatively, a simple interpolation may be performed . Accordingly, compensation may be performed in an easy manner .

[0044] Fig . IB summari zes a method according to embodiments . The method relates to a method to perform kickback compensation on values generated by an array of comparators 120 being a compo- nent of an array of analog-to-digital converters 125, ADCs, the comparators 120 being configured to operate in parallel, one input terminal of each of the comparators 120 being connected to a common ramp generator 110. The method may comprise determining (S100) , by each of the comparators 120, a digital value. The method may further comprise determining (S110) a kickback compensation value for each of the digital values, and subtracting (S120) , for each of the digital values, the kickback compensation value from the digital value.

[0045] For example, determining (Slid) the kickback compensation value may comprise determining (S113) a parameter indicating an order in which the comparators 120 of the array have been triggered, wherein the compensation value for a specific digital value depends on the parameter.

[0046] According to embodiments, determining (S113) the parameter may comprise assigning (S117) the digital values output by the comparators to groups corresponding to a respective one of the digital values. Further, a specific compensation value may be assigned to each of the groups.

[0047] Fig. 1C summarizes a method according to further embodiments. The method may comprise determining (S100) , by each of the comparators 120, a digital value. The buffered digital values may be stored into a large digital RAM ("random access memory") (S105) . In step S107, a processing device, e.g. a finite state machine, FSM, may be used to perform a comparison sort. The sorted result may be stored into a second RAM which may be equally sized. The specific sort algorithm may be arbitrary and may, inter alia, comprise bubble sort, selection sort, insertion sort etc. In step S115, the digital values may be read at each index which is a multiple of N / H, wherein N denotes the number of comparators, e.g. the number of columns of the image sensor 10 , and H denotes the number of bins . These digital values become the bin boundaries . In step S 117 the samples are read from the non-sorted memory and are compared to the bin boundaries . In this way, for each of the digital values a correction bin may be determined and the digital value is assigned to a group . In step S 120 , a kickback compensation value may be subtracted from the digital value . The kickback compensation value may e . g . be taken from the lookup table 107 storing kickback compensation values for each correction bin .

[0048] According to further embodiments , the groups or bins may be determined based on statistics . For example , this may comprise determining the mean value of the distribution and the standard deviation . Moreover, boundaries of a histogram may be computed with expected equal frequencies according to a selected quantile . This will be explained with reference to Figs . 2A to 2C .

[0049] Fig . 2A shows elements of the compensation circuit 105 for performing this compensation . Fig . 2A shows an array of comparators 120 which may be components of corresponding ADCs 125 as has been explained above . The output of each of the comparators may be connected to a buf fer 123 for temporarily storing digital values . The buf fer 123 is connected to a value storage 130 and to a first processing device 135 . For example , during readout of each sample row, the values of all comparators or columns are stored in the value storage 130 . As is illustrated in detail in Fig . 2A, the address of each of the columns may be input to the address input 131 , and the pixel value of the corresponding column may be input to the value input 132 of the value storage 130 . The value storage 130 may have a si ze of N x B, wherein N denotes the number of comparators 120 , e . g . the number of columns of the image sensor . B may denote the sample depth of the pixel values .

[0050] The first processing device 135 may be configured to compute a mean value p . As is general ly known, the mean value may be determined by summing the pixel values and multiplying the sum by 1 / N . The mean value may be stored in the second memory 137 .

[0051] Fig . 2B illustrates components of the compensation circuit 105 when performing calculation of the standard deviation o of the pixel values . To thi s end, for each of the columns , the pixel values are read from the value storage 130 via the value output 133 . The standard deviation is computed according to known methods by the second processing device 128 using the mean value stored in the second memory 137 . For example , the standard deviation may be computed when the next sample row is read from the image sensor .

[0052] Fig . 2C illustrates components of the compensation circuit 105 when performing compensation of the pixel values . The pixel values are read from the value storage 130 for each of the columns i=0 , 1 , ... N . A comparison device 134 forms a component of a third processing device 129 . The comparison device 134 compares the pixel values against the quantile boundaries . For example , the quantile boundaries may be determined according to known methods . The boundaries may correspond to Qn* o + p , wherein Qnis the precomputed nth quantile value for a standard normal distribution .

[0053] As a consequence , a bin ID may be determined . The third processing device 129 further comprises a lookup table 138 which stores correction of fset values in dependence from the bin ID . A subtracting unit 126 may be configured to subtract the cor- rection offset value from the pixel value. A result may be output by the output terminal 127.

[0054] Fig. 2D illustrates the determination of a distribution of pixel values. The left-hand portion of Fig. 2D shows a measured histogram and the gaussian distribution with matching mean and standard deviation. The right-hand portion of Fig. 2D shows a part of a distribution as a result of quantile binning performed on the histogram shown in the left-hand side. As is shown, since the histogram on the left-hand side does not show a Gaussian or normal distribution, the distribution of pixel values to the single bins is not uniform.

[0055] Fig. 2E summarizes a method according to embodiments. As is shown, a digital value may be determined (S200) by each of the comparators. In step S210, the buffered digital values are stored and basic statistical values are collected. For example, during buffer readout, the buffered digital values may be stored into the value storage which is comparatively large. Further, as the values are being read, they are accumulated to get a total sum. In step S220, the mean value p and the standard deviation o are determined. The total sum obtained in step S210 may be multiplied by 1 / N to get the mean value of all samples. Further, the samples may be read from the value storage 130 and the standard deviation may be computed.

[0056] In step S230, the bin boundaries may be computed using statistical quantile. The boundaries may correspond to Qn* o + p, wherein Qnis the precomputed nth quantile value for a standard normal distribution.

[0057] Thereafter, in step S240, the digital values are read from the value storage 130 and compared to the bin boundaries. In this manner it may be determined to which correction bin the digi- tai value belongs . Accordingly, the digital values may be assigned to groups . Then, in step 260 , the kickback compensation value is subtracted from the digital value . For example , the kickback compensation value may be taken from a lookup table 138 which stores the kickback compensation values for each of the correction bins .

[0058] According to further implementations , the binning may be performed using a histogram method . In particular, this method may be referred to as count-based binning . As will be explained in the following, a cumulative histogram may be determined and the correction values will be assigned to each of the resulting bins .

[0059] Fig . 3A shows an example of a configuration comprising an array of comparators 120 and a compensation circuit 105 for performing kickback compensation according to further embodiments . As is shown in Fig . 3A, the compensation circuit 105 may comprise a value storage 140 and a histogram storage 144 . The value storage 140 comprises an address input 141 . Further, the value storage 140 comprises a value input 142 for inputting a pixel value and a value output 143 for outputting a pixel value . The value storage 140 may have a si ze of N x B similar to the value storage 130 explained with reference to Fig . 2A. The histogram storage 144 comprises an address input 145 for inputting an address , a value output 147 for outputting a value and a value input 146 for inputting a value .

[0060] During readout of a sample row, the pixel values are stored in the value storage 140 and the histogram is counted in the histogram storage 144 . For example , when a speci fic pixel value is input to the histogram storage 144 , the pixel value is assigned to an address corresponding to a speci fic histogram bin and the number of entries in the speci f ic histogram bin is in- cremented by 1. The histogram storage 144 has a size of H x log2 N. Log2 N is the number of bits needed to store counts in a range [0,N] . The resulting histogram is a granular histogram. The number of bins may be equal to H = 2?, i.e. a power of 2, such that the MSB ("most significant bits") of the pixel values may be used as the address. For example, the MSB may refer to the top p=log2H bits..

[0061] Thereafter, as is shown in Fig. 3B, e.g. when the next sample, e.g. the next row is read, an accumulated histogram is generated. To this end, a processing circuit 152 which may be implemented as a finite state machine reads out each of the initial bins k=0,...H from the histogram storage 144. The counts counted by the histogram storage 144 are accumulated. The processing circuit 152 increments a correction bin ID, when the next bin boundary is reached. For example, the bin boundary may be determined as an integer multiple of N / C, wherein N denotes the number of comparators, e.g. of columns, and C denotes the number of correction bins. N / C refers to an ideal population of a correction bin.

[0062] The correction bin ID is input to a value input 150 of the bin memory 148. The initial bin number k may be input to the address input 145 of the histogram storage 144 and further to the address input 149 of the bin memory 148. The correction bin ID is then stored in the bin memory 148 with the same address as the address input to the histogram storage 144 (initial bin number) . Accordingly, a map of pixel value to correction bin ID is generated.

[0063] This is further illustrated in Figs. 4A and 4B. Fig. 4A shows an initial histogram assuming that a number of initial bins H is equal to 32. As is shown in Fig. 4A, there is a certain frequency for each of ranges of pixel values. Fig. 4B shows a cumulative histogram. In more detail, the cumulative histogram may be generated by adding an actual histogram bin to a sum of previous histogram bins.

[0064] Cumn=Cumn-1+Histn, wherein Cumndenotes the cumulative frequency of bin n and Histndenotes the frequency of bin n.

[0065] Each time, the cumulative histogram intersects a bin boundary, e.g. a multiple integer of N / C as explained above, e.g. 160 in the case of Fig. 4B, the next correction bin is reached. This is illustrated in Fig. 4B by the horizontal lines. The vertical lines indicate the pixel values at the respective bin boundary. In this way, correction bins having an approximately constant frequency may be generated. This is further illustrated in Fig. 4C for the case of reducing initially 32 bins to 8 correction bins. Fig. 4D shows the case of reducing initially 256 to 8 correction bins.

[0066] Accordingly, the bin memory 148 is indexed by the initial bin k = 0, 1 ... H which refers to specific pixel value intervals and maps this to the stored correction bin ID.

[0067] Fig. 3C shows elements of the compensation circuit 105 when performing pixel correction. For example, the processing illustrated in Fig. 3C may be performed during a second sample readout, e.g. when reading a second row. For each of comparators or columns i = 0, 1, ... N, the pixel values are read from the value storage 140. The pixel values are assigned to corresponding values of the initial bin which are mapped to correction bin IDs in the bin memory 148. Accordingly, the corresponding correction bin ID is read from the bin memory 148 via the value output 151. For each of the correction bin IDs, a corresponding correction factor may be assessed from the lookup table 153. The correction value is fed to the subtracting unit 126. The subtracting unit 126 subtracts the correction value from the pixel value. The corrected output value is output by the output terminal 127.

[0068] According to the implementation using a histogram-based sort, the correction bins may have an approximately uniform size. Determining the correction bins may be performed in an easy manner without performing comparisons. Since a small number of triggers generally does not raise the offset by a whole LSB ("least significant bit") , the use of a coarse histogram is sufficient for performing the sorting.

[0069] Figs. 5A to 5C show an implementation of the compensation circuit 105 according to further embodiments. The compensation circuit 105 illustrated in Fig. 5A comprises a value storage 140 which is similar to the value storage 140 explained with reference to Fig. 3A. According to embodiments explained with reference to Figs. 5A to 5C, the histogram storage 144 and the bin memory 148 may be implemented to reuse the same physical memory, e.g. auxiliary memory 155. The auxiliary memory 155 is sized appropriately in order to hold both counts and sample values for performing the next stage. For example, the size of the auxiliary memory 155 may be H x M, wherein H denotes the number of initial bins and M denotes the maximum of B, i.e. the sample depth, and log2 N. The auxiliary memory 155 comprises an address input 156, a value input 158 and a value output 157.

[0070] As is illustrated in Fig. 5A, the functionality of the auxiliary memory 155 is similar to the functionality of the histogram memory 144 shown in Fig. 3A. Referring to Fig . 5B, before the next sample , e . g . the next row is read, the bin ID may be set to 0 . The histogram values may be read and accumulated in a similar manner as explained above with reference to Fig . 3B . Further, the correction bin ID may be determined from the accumulated value . The functionality is performed by the processing circuit 152 in a similar manner as has been explained with reference to Fig . 3B . Di ffering from embodiments as described with reference to Figs . 3A to 3B, using the correction bin ID, a correction factor is directly determined from the lookup table 153 . The correction factor is stored back into the auxiliary memory 155 . In more detail , the correction factor is stored in dependence from an address of an initial bin k input to the address input 156 .

[0071] The auxiliary memory 155 may be implemented as a dual port memory which may read out values simultaneously with writing new values . As a result of the processing explained with reference to Fig . 5B, the auxiliary memory 155 contains correction factors corresponding to samples belonging to a given initial bin k . According to thi s implementation, the correction bin ID is not stored in the memory . Instead, the correction factor retrieved from the lookup table 153 is stored in the auxiliary memory 155 .

[0072] As is shown in Fig . 5C , thereafter, e . g . during a second sample , e . g . row, readout , the pixel values may be read from the value storage 140 . Then, the corresponding correction factors are read from the auxiliary memory 155 using the MSB as address as has been explained above . The correction factor is subtracted from the pixel value in the subtracting unit 126 . The corrected output value is output via the output terminal 127 . According to embodiments described with reference to Figs . 5A to 5C, the correction factor is directly stored in auxiliary memory 155. Hence, the correction factor does not need to be looked up in this stage.

[0073] According to the implementation described with reference to Figs. 5A to 5C, intermediate results which only are needed temporarily are not stored. Accordingly, instead of the correction bin ID, the correction factor is stored in the auxiliary memory. As a result, power and area may be further saved.

[0074] Fig. 5D summarizes a method according to embodiments. In step S500, a digital value may be determined by each of the comparators 120. In step S510, the buffered digital values may be stored and a histogram of samples may be created. This may comprise storing the buffered digital values into a value storage 140 having a comparatively large size. Simultaneously, a coarse histogram of sampled values (i.e. e.g. 16-64 evenly spaced initial bins) may be collected in the auxiliary memory 155. The auxiliary memory 155 may be a comparatively small digital RAM. A power of 2 may be used for the number of bins. This allows the address of the bin to be determined unambiguously by the MSB of the sample.

[0075] In Step 520, the sample values may be grouped in a number of C uniformly populated groups or correction bins. To this end, the counts inside the histogram are accumulated to create an accumulated histogram. For example, each time the sum passes a value N / C corresponding to an ideal population, the correction bin ID is incremented. Further, the value N / C is subtracted from the sum. The first initial bin, in which a correction bin ID is seen, may determine the lower boundary of the samples which receive the given correction factor. Further, the last initial bin, in which a correction bin ID is seen, may determine the upper boundary of the samples which receive the given correction factor. After each count from the histogram is accumulated, the correction bin ID may be used to select the pre-programmed kick- back compensation value from a lookup table 153 . The kickback compensation value is stored back into the auxiliary memory 155 at the same address the previously accumulated count was read from .

[0076] In step S530 , a correction is performed . Each digital value is read from the value storage 140 . The kickback compensation value is read from the auxiliary memory 155 e . g . using the MSBs of the digital value as the address . Then, the kickback compensation value is subtracted from the digital value .

[0077] Fig . 6 shows an electronic device according to embodiments . The electronic device 20 comprises an image sensor 10 which comprises an array of comparators as described above . For example , the electronic device 20 may be a digital camera or a smart phone comprising a digital camera . The address of each of the pixel values may be asses sed using the MSB of the pixel values . In more detail , as has been explained above , the correction bin may be determined from the pixel value . For example , the pixel value may be given in binary form so that a corresponding address may be easily assessed .

[0078] As has been described, a kickback compensation is performed on the digital value . As a consequence , the implementation is more area- and power-ef ficient than analog solutions . The compensation circuit may be shared among all comparators . As a result , there is no need to provide a compensation circuit for each of the comparators . Further, the compensation circuit comprises simple devices such as memories and adders . For example , the compensation circuit may be implemented in a digital layer which allows a smaller technology node to be used . The described implementation may be runtime configurable . The correction factor lookup is j ust a digital number and as such can be programmed or calibrated at runtime . The described implementation is not constrained by pixel pitch .

[0079] Since the compensation circuit is decoupled from the comparator or column, it may be designed in a layout which i s di f ferent from the comparator or the column . The compensation circuit may be auto-routed on an entirely di f ferent layer or even chip .

[0080] The described methods of grouping the pixel values are merely examples . According to further embodiments , the pixel values may be grouped according to further methods .

[0081] While embodiments of the invention have been described above , it is obvious that further embodiments may be implemented . For example , further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above . Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein .

[0082] LIST OF REFERENCES

[0083] 10 image sensor

[0084] 20 electronic device

[0085] 100 pixel

[0086] 101 row select line

[0087] 102 column bus

[0088] 105 kickback compensation circuit

[0089] 107 lookup table

[0090] 110 ramp generator

[0091] 120 comparator

[0092] 123 buf fer

[0093] 125 analog-to-digital converter

[0094] 126 subtracting unit

[0095] 127 output terminal

[0096] 128 second processing device

[0097] 129 third processing device

[0098] 130 value storage

[0099] 131 address input

[0100] 132 value input

[0101] 133 value output

[0102] 134 comparison device

[0103] 135 first processing device

[0104] 136 first memory

[0105] 137 second memory

[0106] 138 Lookup table

[0107] 139 value memory

[0108] 140 value storage

[0109] 141 address input

[0110] 142 value input

[0111] 143 value output

[0112] 144 histogram storage

[0113] 145 address input

[0114] 146 value input value output bin memory address input value input value output processing circuit lookup table auxiliary memory address input value output value input

Claims

CLAIMS1. An array of comparators (120) , the comparators (120) of the array being configured to operate in parallel, one input terminal of each of the comparators (120) being connected to a common ramp generator (110) , the array further comprising a kickback compensation circuit (105) for subtracting a kickback compensation value from a digital value output by each of the comparators (120) .

2. The array according to claim 1, wherein the compensation circuit (105) is configured to determine a parameter indicating an order in which the comparators (120) of the array have been triggered, wherein the compensation value for a specific digital value depends on the parameter.

3. The array according to claim 2, wherein the compensation circuit (105) is configured to assign the digital values output by the comparators (120) to groups corresponding to a respective one of the digital values, a specific compensation value being assigned to each of the groups, wherein the compensation circuit (105) further comprises a subtracting unit (126) for subtracting the specific compensation values from the digital values, respectively.

4. The array according to claim 3, wherein assigning comprises determining histogram boundaries based on statistical methods .

5. The array according to claim 4, wherein determining the histogram boundaries comprises determining a mean value and a standard deviation of the digital values and computing histogram boundaries using statistical quantiles.

6. The array according to claim 3, wherein assigning comprises determining an initial histogram comprising H initial bins and reducing the H initial bins to C correction bins, wherein a distribution of the digital values in the C correction bins is more uniform than the distribution of the digital values in the H initial bins.

7. The array according to claim 6, wherein H is a power of 2.

8. The array according to claim 6 or 7, wherein the kick- back compensation circuit (105) comprises a histogram storage (144) for storing the initial histogram and a bin memory (148) for storing the digital values and an identifier of the corresponding correction bin.

9. The array according to claim 6 or 7, wherein the kick- back compensation circuit (105) comprises an auxiliary memory (155) for storing the digital values and the corresponding kickback compensation values.

10. The array according to claim 9, wherein the auxiliary memory (155) further is configured to store the initial histogram.

11. An image sensor (10) comprising the array of comparators (120) according to any of the preceding claims.

12. An electronic device (20) comprising the image sensor (10) according to claim 11.

13. The electronic device (20) according to claim 12, being a camera or a smart phone.

14. A method to perform kickback compensation on values generated by an array of comparators (120) , the comparators (120) being configured to operate in parallel, one input terminal of each of the comparators (120) being connected to a common ramp generator (110) , the method comprising determining, by each of the comparators (120) , a digital value; determining a kickback compensation value for each of the digital values; and subtracting, for each of the digital values, the kick- back compensation value from the digital value.

15. The method according to claim 14, wherein determining the kickback compensation value comprises determining a parameter indicating an order in which the comparators (120) of the array have been triggered, wherein the compensation value for a specific digital value depends on the parameter.

16. The method according to claim 15, wherein determining the parameter comprises assigning the digital values output by the comparators (120) to groups corresponding to a respective one of the digital values, a specific compensation value being assigned to each of the groups.

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