Power-on reset circuit for power supply

Abstract

Provided in the present invention is a power-on reset (POR) circuit for a power supply. The POR circuit comprises: a resistor voltage-division network, which is configured to be connected between a power supply voltage AVDD and a grounding node, and is configured to provide a second intermediate voltage for a comparator and provide a first intermediate voltage for an error-free flip auxiliary circuit; the comparator, which is configured to receive the second intermediate voltage from the resistor voltage-division network, receive a reference voltage from a band-gap reference (BGR) circuit and output a first POR output; the error-free flip auxiliary circuit, which is configured to receive the first intermediate voltage from the resistor voltage-division network and output a second POR output; and an output logic circuit, which is configured to receive the first POR output and the second POR output, so as to generate an output voltage.

Description

Power-on reset circuit

[0001] This application claims priority to Chinese Patent Application No. 202311251460.7 filed on September 26, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as part of this application. Technical Field

[0002] The present invention relates to the field of mixed signal system circuit design, and more particularly to a high-precision and low-power power-on reset (POR) circuit. Background Art

[0003] Mixed-signal systems often contain complex digital and analog circuits. For digital circuits, their initial state must be determined during the power-up process to ensure a correct starting point for subsequent operation. A power-on reset (POR) circuit typically generates a step signal from 0 to 1 during power-up to achieve a digital reset. Key technical considerations for POR circuits include: 1) the toggle threshold; 2) the toggle hysteresis voltage; and 3) power consumption and area. Traditional POR circuits generate a step signal by comparing the supply voltage with the threshold of an inverter with a high-resistance load. This approach suffers from inaccurate toggle thresholds due to process variations. Another approach compares the supply voltage with a reference voltage to generate a reset signal. However, this approach has the disadvantage that the bandgap reference (BGR) and comparator require the supply voltage to exceed a certain voltage to function properly. Below this voltage, the POR output may not meet requirements, posing a control risk to the system. Another drawback is that the power-up speed can affect the reference voltage transient, leading to the risk of reset signal glitches.

[0004] Summary of the Invention

[0005] The present invention generates a reset signal by using a comparator to compare the power supply voltage with the precise voltage generated by the BGR, thereby achieving a more accurate flip threshold; potential glitches can be eliminated at any power-on speed through appropriate filtering settings, and reliable operation at lower voltages can be achieved by combining with an inverter-type POR circuit.

[0006] According to one aspect of the present invention, a power-on reset (POR) circuit is provided, comprising: a resistor divider network configured to be connected between a power supply voltage AVDD and a ground node, and configured to provide a second intermediate voltage for a comparator, and a first intermediate voltage for an error-free flip auxiliary circuit; a comparator configured to receive the second intermediate voltage from the resistor divider network and a reference voltage from a bandgap reference source BGR circuit, and output a first POR output; a error-free flip auxiliary circuit configured to receive the first intermediate voltage from the resistor divider network and output a second POR output; and an output logic circuit configured to receive the first POR output and the second POR output to generate an output voltage.

[0007] According to one aspect of the present invention, a power-on reset (POR) circuit is provided, wherein the resistor divider network includes a first resistor R1, a second resistor R2, and a third resistor R3 connected in series, and wherein a first intermediate node between the first resistor R1 and the second resistor R2 provides a first intermediate voltage, and a second intermediate node between the second resistor R2 and the third resistor R3 provides a second intermediate voltage.

[0008] According to an aspect of the present invention, a power-on reset (POR) circuit is provided, wherein the comparator includes a latch configured to latch a comparison result of the second intermediate voltage and a reference voltage and output a first POR output.

[0009] According to one aspect of the present invention, a power-on reset (POR) circuit is provided, wherein the comparator further includes a first transistor N1 and a second transistor N2, a third transistor P1, a fourth transistor P4, a fifth transistor P3, a sixth transistor P4, and a current source Io, wherein the gates of the first transistor N1 and the second transistor N2 are respectively configured to be connected to a second intermediate voltage and a reference voltage, respectively; the sources of the first transistor N1 and the second transistor N2 are connected together and to a ground node through the current source Io; the drain of the first transistor N1 is connected to the drains of the third transistor P1 and the fourth transistor P2, and is connected to the latch The gate of the third transistor P1 is connected to the drain of the third transistor P1, and the source thereof is connected to the power supply voltage AVDD; the gate of the fourth transistor P2 is connected to the drain of the second transistor N2, and the source thereof is connected to the power supply voltage AVDD; the drain of the second transistor N2 is connected to the drains of the fifth transistor P3 and the sixth transistor P4, and is connected to the second input terminal of the latch; the gate of the fifth transistor P3 is connected to the drain of the first transistor N1, and the source thereof is connected to the power supply voltage AVDD; the gate of the sixth transistor P4 is connected to the drain of the sixth transistor P4, and the source thereof is connected to the power supply voltage AVDD.

[0010] According to an aspect of the present invention, a power-on reset (POR) circuit is provided, wherein the comparator further comprises a filter capacitor, and the filter capacitor is configured between the first input terminal and the second input terminal of the latch.

[0011] According to one aspect of the present invention, a power-on reset (POR) circuit is provided, wherein the comparator further includes a filter capacitor, which is configured between the first input terminal of the latch and the power supply voltage AVDD; or the filter capacitor is configured between the second input terminal of the latch and the power supply voltage AVDD.

[0012] According to one aspect of the present invention, a power-on reset (POR) circuit is provided, wherein the error-free flip auxiliary circuit includes a seventh transistor, a fourth resistor, and an inverter, wherein the seventh transistor and the fourth resistor are connected in series between a power supply voltage VADD and a ground node, a first intermediate voltage is provided to the gate of the seventh transistor, and a third intermediate node between the seventh transistor and the fourth resistor is connected to the inverter to generate a second POR output.

[0013] According to an aspect of the present invention, a power-on reset (POR) circuit is provided, wherein the output logic circuit includes an AND gate circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a schematic diagram showing a conventional power-on reset (POR) circuit structure and a flip timing sequence;

[0015] FIG2 is a schematic diagram showing how the flip threshold value varies with process parameters under the structure of a traditional POR circuit;

[0016] FIG3 is a schematic diagram showing another power-on reset (POR) circuit structure and flip timing;

[0017] 4 is a schematic diagram showing simulation results of a power-on reset (POR) circuit according to the structure shown in FIG3 under typical circumstances;

[0018] 5 is a schematic diagram showing a power-on reset (POR) circuit structure according to an embodiment of the present invention; and

[0019] FIG6 is a schematic diagram showing an implementation of a comparator structure with a hysteresis or filtering function according to an embodiment of the present invention;

[0020] 7 is a circuit diagram showing circuit simulation of a power-on reset (POR) circuit according to an embodiment of the present invention and a conventional POR circuit at low voltage; and

[0021] FIG. 8 is a diagram illustrating random scan test results of a flip threshold and a hysteresis voltage of a (POR) circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] Before proceeding with the detailed description below, it may be helpful to set forth the definitions of certain words and phrases used throughout this patent document. The terms "couple," "connect," and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmit," "receive," and "communicate," and their derivatives, encompass both direct and indirect communication. The terms "include," "comprise," and their derivatives, mean including, but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives mean including, included within, interconnected, containing, contained within, connected or connected with, coupled or coupled with, communicate with, cooperate with, intertwine, juxtapose, approach, bound or bound with, have, have an attribute of, have a relationship with, or have a relationship with, etc. The term "controller" refers to any device, system, or portion thereof that controls at least one operation. Such a controller may be implemented using hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one of," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be needed. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0023] Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0024] In this patent document, the application combination of modules and the division level of sub-modules are only used for illustration. Without departing from the scope of this disclosure, the application combination of modules and the division level of sub-modules can have different forms.

[0025] FIG. 1 is a schematic diagram showing a conventional power-on reset (POR) circuit structure and a switching timing sequence.

[0026] As shown in Figure 1, a first resistor R1 and a second resistor R2 are connected in series between the power supply voltage AVDD and the ground node. The intermediate node between the first resistor R1 and the second resistor R2 provides an intermediate voltage Vx to the gate of transistor N1. The drain of transistor N1 is connected to the power supply voltage AVDD, and its source is connected to the ground node through resistor R. In addition, the source of transistor N1 is also connected to the input of an inverter, which inverts the signal to provide an output voltage.

[0027] According to the structure shown in Figure 1, the first resistor R1 and the second resistor R2 proportionally extract the power supply voltage AVDD to generate an intermediate voltage Vx. The inverter structure determines the threshold for POR flipping. When the critical flip occurs, the following equation exists:

[0028] make:

[0029] Thus there is

[0030] In which, VDD th is the flip threshold of POR, which is easily affected by the change of process parameters. Figure 2 is a schematic diagram showing the change of flip threshold with process parameters under the structure of traditional POR circuit. th The variation range is very wide, ranging from approximately 1.37V to 1.72V.

[0031] FIG3 is a schematic diagram showing another power-on reset (POR) circuit structure and a switching timing sequence.

[0032] As shown in Figure 3, a first resistor R1 and a second resistor R2 are connected in series between the power supply voltage AVDD and the ground node. The node between the first resistor R1 and the second resistor R2 provides an intermediate voltage Vx to the + input terminal of the comparator. The - input terminal of the comparator is provided with a reference voltage Vref provided by a bandgap reference source (BGR). The output terminal of the comparator provides the output voltage. In addition, a filter capacitor C is connected in series between the intermediate node and the ground node.

[0033] For the power-on reset (POR) circuit structure shown in FIG3 , its flip threshold is determined by the following formula. The accuracy of the flip threshold is basically determined by the accuracy range of Vref itself.

[0034] However, when the power supply voltage falls below a certain value, the comparator and BGR will not function properly, causing the POR circuit to output an incorrect control level. Figure 4 shows simulation results for a typical power-on reset (POR) circuit based on the structure shown in Figure 3. Referring to Figure 4, an erroneous voltage bump occurs around 0.7V, posing a potential risk of system errors.

[0035] In addition, in order for the circuit to generate a normal reset signal during fast power-up, an additional filter capacitor C needs to be introduced into the resistor divider network. This capacitor C will introduce a first-order low-pass effect into the divider circuit.

[0036] FIG5 is a schematic diagram showing a structure of a power-on reset (POR) circuit according to an embodiment of the present invention.

[0037] To address the inaccurate flip threshold problem of the POR circuit shown in Figure 1 and the risk of erroneous flipping under low voltage conditions in the POR circuit shown in Figure 2, which also requires the introduction of a large filter capacitor in the resistor divider network, resulting in a larger area, the POR circuit according to an embodiment of the present invention utilizes a comparator to compare the power supply voltage with a precise reference voltage generated by a bandgap reference (BGR) to generate a reset signal. This achieves a more precise flip threshold, eliminates potential glitches at any power-up speed through appropriate filtering settings, and, by combining with an inverter-type POR circuit, enables reliable operation at lower voltages. The POR circuit according to an embodiment of the present invention also has the following significant advantages: 1) improved flip threshold control accuracy; 2) elimination of bulging under low voltage conditions; and 3) reduced area and power consumption.

[0038] 5 , a power-on reset (POR) circuit according to an embodiment of the present invention includes a resistor divider network, a comparator with hysteresis and filtering functions, an error-free flip-flop auxiliary circuit, and an output logic circuit.

[0039] The resistor divider network is configured to be connected between the power supply voltage AVDD and the ground node and to provide a second intermediate voltage for the comparator and a first intermediate voltage for the error-free flipping auxiliary circuit. The resistor divider network includes a first resistor R1, a second resistor R2, and a third resistor R3, which are connected in series between the power supply voltage AVDD and the ground node. A first intermediate node between the first resistor R1 and the second resistor R2 provides a first intermediate voltage Vx, and a second intermediate node between the second resistor R2 and the third resistor R3 provides a second intermediate voltage Vy. The first intermediate node is connected to the gate of transistor N1 to provide the first intermediate voltage Vx to the gate of transistor N1. The drain of transistor N1 is connected to the power supply voltage AVDD, and its source is connected to the ground node via resistor R. In addition, the source of transistor N1 is also connected to the input of an inverter, which inverts the signal and provides it to the output logic circuit. The second intermediate node provides the second intermediate voltage Vy to one input terminal (e.g., the + input terminal) of the comparator, and the other input terminal (e.g., the - input terminal) of the comparator is connected to the BGR circuit to receive the reference voltage. The output of the comparator and the output of the inverter are provided to the output logic circuit to output the output voltage Vo through the output logic circuit.

[0040] According to an embodiment of the present invention, the comparator is a comparator with hysteresis or filtering functions, for example, it may be a Schmitt comparator with hysteresis and filtering functions, which includes a latch and a filter.

[0041] According to an embodiment of the present invention, the error-free flip auxiliary circuit includes an error-free flip auxiliary circuit under low voltage, which includes a transistor N1 and a resistor R connected in series, and an inverter receiving a voltage signal from a third intermediate node between the transistor N1 and the resistor R.

[0042] According to an embodiment of the present invention, the output logic circuit includes an AND gate circuit.

[0043] Referring to Figure 5, high flip threshold accuracy is achieved by referencing the BGR to generate a reference voltage, using a resistor divider network to detect the supply voltage, and using a comparator with hysteresis. Furthermore, the inverter-based error-free flip auxiliary circuit exhibits minimal bulge at low voltages. Combined with the output logic circuit, this achieves both precise flip threshold accuracy and error-free flip functionality at low voltages.

[0044] Similar to the resistor divider network shown in Figure 1 which does not contain a filter capacitor, and compared to the structure shown in Figure 3 which requires a larger filter capacitor, the POR circuit according to the embodiment of the present invention combines two POR circuits and shares the same resistor divider network. In addition, the POR circuit according to the embodiment of the present invention adopts a comparator structure with hysteresis or filtering function, so that the resistor divider network in the POR circuit of the embodiment of the present invention does not require a larger filter capacitor. At the same time, since the same resistor divider network is shared, it also brings about greater area and power consumption savings.

[0045] The POR circuit according to the embodiment of the present invention can easily achieve the following improvements through appropriate parameter adjustment and design: 1) precise control of the flip threshold; 2) no risk of erroneous flip under low voltage conditions; 3) comparative advantages in area and power consumption compared to traditional structures.

[0046] FIG. 6 is a schematic diagram illustrating an implementation of a comparator structure with a hysteresis or filtering function according to an embodiment of the present invention.

[0047] Referring to Figure 6, the comparator includes transistors N1 and N2, transistors P1-P4, and a current source Io. The gates of transistors N1 and N2 are configured as INN and INP, respectively, and voltages Vy and Vref are provided to the gates of transistors N1 and N2, respectively. The sources of transistors N1 and N2 are connected together and to a ground node through current source Io. The drain of transistor N1 is connected to the drains of transistors P1 and P2 and to the first input of the latch; the gate of transistor P1 is connected to the drain of transistor P1, and its source is connected to the power supply voltage AVDD; the gate of transistor P2 is connected to the drain of transistor N2, and its source is connected to the power supply voltage AVDD. The drain of transistor N2 is connected to the drains of transistors P3 and P4 and to the second input of the latch; the gate of transistor P3 is connected to the drain of transistor N1, and its source is connected to the power supply voltage AVDD; the gate of transistor P4 is connected to the drain of transistor P4, and its source is connected to the power supply voltage AVDD. The comparator further includes a filter capacitor C1 , wherein the filter capacitor C1 may be configured between the first input terminal and the second input terminal of the latch, or the filter capacitor C1 may also be configured between the second input terminal of the latch and the power supply voltage AVDD.

[0048] Referring to Figure 6, the load of the comparator according to an embodiment of the present invention adopts a positive and negative resistance in parallel, which can achieve a higher feedforward gain and an adjustable hysteresis voltage function. By introducing the filter capacitor C1, the comparator has an adjustable low-pass filtering function. Since the comparator has a high output impedance characteristic, the capacitance value of the filter capacitor can be relatively small.

[0049] Figure 7 is a circuit diagram illustrating circuit simulations of a power-on reset (POR) circuit according to an embodiment of the present invention and a conventional POR circuit at low voltage. Referring to Figure 7 , the bulge (the lower half of Figure 7 ) of the POR circuit according to an embodiment of the present invention at low voltage can be much smaller than that of the conventional structure.

[0050] Figure 8 is a schematic diagram illustrating random scan test results of the flip threshold and hysteresis voltage of a POR circuit according to an embodiment of the present invention. Referring to Figure 8 , simulation results of the POR_2P1 hysteresis window flip point of the POR circuit at 27°C (total_mc1000 points) are shown. The standard deviation of the flip threshold of the POR circuit according to an embodiment of the present invention is approximately 19.8 mV, which is significantly smaller than the 350 mV flip threshold variation range shown in Figure 2 .

[0051] In addition, the (POR) circuit according to the embodiment of the present invention eliminates the larger filter capacitor in the resistor divider network. Instead, it only requires a smaller filter capacitor C1, thereby effectively reducing the chip area.

[0052] Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.

[0053] Any description in the present invention should not be construed as implying that any particular element, step, or function is essential to be included in the scope of the claims. The scope of the patented subject matter is defined solely by the claims.

Claims

1. A power-on reset (POR) circuit, comprising: a resistor divider network configured to be connected between the power supply voltage AVDD and a ground node and configured to provide a second intermediate voltage for the comparator and a first intermediate voltage for the error-free flip auxiliary circuit; a comparator configured to receive the second intermediate voltage from the resistor voltage divider network and the reference voltage from the bandgap reference source BGR circuit, and output a first POR output; a non-error flipping auxiliary circuit configured to receive the first intermediate voltage from the resistor divider network and output a second POR output; as well as The output logic circuit is configured to receive the first POR output and the second POR output to generate an output voltage.

2. The power-on reset (POR) circuit according to claim 1, wherein: The resistor divider network includes a first resistor R1, a second resistor R2 and a third resistor R3 connected in series, and wherein a first intermediate node between the first resistor R1 and the second resistor R2 provides a first intermediate voltage, and a second intermediate node between the second resistor R2 and the third resistor R3 provides a second intermediate voltage.

3. The power-on reset (POR) circuit according to claim 1, wherein: The comparator includes a latch configured to latch a comparison result of the second intermediate voltage and a reference voltage and output a first POR output.

4. The power-on reset (POR) circuit according to claim 3, wherein: The comparator further includes a first transistor N1, a second transistor N2, a third transistor P1, a fourth transistor P4, a fifth transistor P3, a sixth transistor P4 and a current source Io. The gates of the first transistor N1 and the second transistor N2 are respectively configured to be connected to the second intermediate voltage and the reference voltage respectively; the sources of the first transistor N1 and the second transistor N2 are connected together and connected to the ground node through the current source Io; the drain of the first transistor N1 is connected to the drains of the third transistor P1 and the fourth transistor P2, and is connected to the first input terminal of the latch; The gate of the third transistor P1 is connected to the drain of the third transistor P1, and the source thereof is connected to the power supply voltage AVDD; The gate of the fourth transistor P2 is connected to the drain of the second transistor N2, and the source thereof is connected to the power supply voltage AVDD; The drain of the second transistor N2 is connected to the drains of the fifth transistor P3 and the sixth transistor P4, and is connected to the second input terminal of the latch; The gate of the fifth transistor P3 is connected to the drain of the first transistor N1, and the source thereof is connected to the power supply voltage AVDD; The gate of the sixth transistor P4 is connected to the drain of the sixth transistor P4 , and the source thereof is connected to the power supply voltage AVDD.

5. The power-on reset (POR) circuit according to claim 3, wherein: The comparator further includes a filter capacitor configured between the first input terminal and the second input terminal of the latch.

6. The power-on reset (POR) circuit according to claim 3, wherein: The comparator further includes a filter capacitor, wherein the filter capacitor is configured between the first input terminal of the latch and a power supply voltage AVDD; or The filter capacitor is configured between the second input terminal of the latch and a power supply voltage AVDD.

7. The power-on reset (POR) circuit according to claim 1, wherein: The error-free flip auxiliary circuit includes a seventh transistor, a fourth resistor and an inverter. The seventh transistor and the fourth resistor are connected in series between the power supply voltage VADD and the ground node, the first intermediate voltage is provided to the gate of the seventh transistor, and the third intermediate node between the seventh transistor and the fourth resistor is connected to the inverter to generate a second POR output.

8. The power-on reset (POR) circuit according to claim 1, wherein: The output logic circuit includes an AND gate circuit.

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